motorhead/qemu
1
0
Fork 0
mirror of https://github.com/Motorhead1991/qemu.git synced 2025-08-07 17:53:56 -06:00
Code Issues Projects Releases Packages Wiki Activity Actions

Use error_fatal to simplify obvious fatal errors

Browse source 
Done with this Coccinelle semantic patch:

    @@
    type T;
    identifier FUN, RET;
    expression list ARGS;
    expression ERR, EC;
    @@
    (
    -    T RET = FUN(ARGS, &ERR);
    +    T RET = FUN(ARGS, &error_fatal);
    |
    -    RET = FUN(ARGS, &ERR);
    +    RET = FUN(ARGS, &error_fatal);
    |
    -    FUN(ARGS, &ERR);
    +    FUN(ARGS, &error_fatal);
    )
    -    if (ERR != NULL) {
    -        error_report_err(ERR);
    -        exit(EC);
    -    }

This is actually a more elegant version of my initial semantic patch
by courtesy of Eduardo.

It leaves dead Error * variables behind, cleaned up manually.

Cc: qemu-arm@nongnu.org
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
This commit is contained in:
Markus Armbruster 2015-09-11 15:04:45 +02:00
parent 8d780f4392
commit 007b06578a
13 changed files with 35 additions and 174 deletions
Download patch file Download diff file Expand all files Collapse all files

13
hw/arm/exynos4210.c
View file

@ -150,27 +150,18 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem,
for (n = 0; n < EXYNOS4210_NCPUS; n++) {
Object *cpuobj = object_new(object_class_get_name(cpu_oc));
Error *err = NULL;
/* By default A9 CPUs have EL3 enabled. This board does not currently
* support EL3 so the CPU EL3 property is disabled before realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
s->cpu[n] = ARM_CPU(cpuobj);
object_property_set_int(cpuobj, EXYNOS4210_SMP_PRIVATE_BASE_ADDR,
"reset-cbar", &error_abort);
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
}
/*** IRQs ***/

7
hw/arm/highbank.c
View file

@ -279,7 +279,6 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
ObjectClass *oc = cpu_class_by_name(TYPE_ARM_CPU, cpu_model);
Object *cpuobj;
ARMCPU *cpu;
Error *err = NULL;
cpuobj = object_new(object_class_get_name(oc));
cpu = ARM_CPU(cpuobj);
@ -297,11 +296,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id)
object_property_set_int(cpuobj, MPCORE_PERIPHBASE,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_IRQ);
cpu_fiq[n] = qdev_get_gpio_in(DEVICE(cpu), ARM_CPU_FIQ);
}

13
hw/arm/integratorcp.c
View file

@ -533,7 +533,6 @@ static void integratorcp_init(MachineState *machine)
qemu_irq pic[32];
DeviceState *dev, *sic, *icp;
int i;
Error *err = NULL;
if (!cpu_model) {
cpu_model = "arm926";
@ -552,18 +551,10 @@ static void integratorcp_init(MachineState *machine)
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu = ARM_CPU(cpuobj);

20
hw/arm/realview.c
View file

@ -99,33 +99,21 @@ static void realview_init(MachineState *machine,
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(object_class_get_name(cpu_oc));
Error *err = NULL;
/* By default A9,A15 and ARM1176 CPUs have EL3 enabled. This board
* does not currently support EL3 so the CPU EL3 property is disabled
* before realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
if (is_pb && is_mpcore) {
object_property_set_int(cpuobj, periphbase, "reset-cbar", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_int(cpuobj, periphbase, "reset-cbar",
&error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu_irq[n] = qdev_get_gpio_in(DEVICE(cpuobj), ARM_CPU_IRQ);
}

13
hw/arm/versatilepb.c
View file

@ -192,7 +192,6 @@ static void versatile_init(MachineState *machine, int board_id)
int n;
int done_smc = 0;
DriveInfo *dinfo;
Error *err = NULL;
if (!machine->cpu_model) {
machine->cpu_model = "arm926";
@ -211,18 +210,10 @@ static void versatile_init(MachineState *machine, int board_id)
* realization.
*/
if (object_property_find(cpuobj, "has_el3", NULL)) {
object_property_set_bool(cpuobj, false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, false, "has_el3", &error_fatal);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
cpu = ARM_CPU(cpuobj);

7
hw/arm/vexpress.c
View file

@ -211,7 +211,6 @@ static void init_cpus(const char *cpu_model, const char *privdev,
/* Create the actual CPUs */
for (n = 0; n < smp_cpus; n++) {
Object *cpuobj = object_new(object_class_get_name(cpu_oc));
Error *err = NULL;
if (!secure) {
object_property_set_bool(cpuobj, false, "has_el3", NULL);
@ -221,11 +220,7 @@ static void init_cpus(const char *cpu_model, const char *privdev,
object_property_set_int(cpuobj, periphbase,
"reset-cbar", &error_abort);
}
object_property_set_bool(cpuobj, true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(cpuobj, true, "realized", &error_fatal);
}
/* Create the private peripheral devices (including the GIC);

28
hw/arm/xilinx_zynq.c
View file

@ -156,7 +156,6 @@ static void zynq_init(MachineState *machine)
DeviceState *dev;
SysBusDevice *busdev;
qemu_irq pic[64];
Error *err = NULL;
int n;
if (!cpu_model) {
@ -171,29 +170,14 @@ static void zynq_init(MachineState *machine)
* realization.
*/
if (object_property_find(OBJECT(cpu), "has_el3", NULL)) {
object_property_set_bool(OBJECT(cpu), false, "has_el3", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(OBJECT(cpu), false, "has_el3", &error_fatal);
}
object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_bool(OBJECT(cpu), true, "realized", &err);
if (err) {
error_report_err(err);
exit(1);
}
object_property_set_int(OBJECT(cpu), ZYNQ_BOARD_MIDR, "midr",
&error_fatal);
object_property_set_int(OBJECT(cpu), MPCORE_PERIPHBASE, "reset-cbar",
&error_fatal);
object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal);
/* max 2GB ram */
if (ram_size > 0x80000000) {