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target/ppc: Remove PowerPC 601 CPUs
The PowerPC 601 processor is the first generation of processors to implement the PowerPC architecture. It was designed as a bridge processor and also could execute most of the instructions of the previous POWER architecture. It was found on the first Macs and IBM RS/6000 workstations. There is not much interest in keeping the CPU model of this POWER-PowerPC bridge processor. We have the 603 and 604 CPU models of the 60x family which implement the complete PowerPC instruction set. Cc: "Hervé Poussineau" <hpoussin@reactos.org> Cc: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com> Message-Id: <20220203142756.1302515-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
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22 changed files with 13 additions and 1659 deletions
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@ -441,29 +441,9 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
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ret = -3;
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}
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} else {
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target_ulong sr;
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qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
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/* Direct-store segment : absolutely *BUGGY* for now */
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/*
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* Direct-store implies a 32-bit MMU.
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* Check the Segment Register's bus unit ID (BUID).
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*/
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sr = env->sr[eaddr >> 28];
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if ((sr & 0x1FF00000) >> 20 == 0x07f) {
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/*
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* Memory-forced I/O controller interface access
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*
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* If T=1 and BUID=x'07F', the 601 performs a memory
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* access to SR[28-31] LA[4-31], bypassing all protection
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* mechanisms.
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*/
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ctx->raddr = ((sr & 0xF) << 28) | (eaddr & 0x0FFFFFFF);
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ctx->prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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return 0;
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}
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switch (type) {
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case ACCESS_INT:
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/* Integer load/store : only access allowed */
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@ -1539,7 +1519,6 @@ bool ppc_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
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#endif
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case POWERPC_MMU_32B:
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case POWERPC_MMU_601:
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return ppc_hash32_xlate(cpu, eaddr, access_type, raddrp,
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psizep, protp, mmu_idx, guest_visible);
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