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tcg: Merge INDEX_op_rot{l,r}_{i32,i64}

Browse source 
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2025-01-08 10:42:16 -08:00
parent 03568c0d53
commit 005a87e148
7 changed files with 50 additions and 56 deletions
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8
docs/devel/tcg-ops.rst
View file

@ -394,15 +394,15 @@ Shifts/Rotates
- | *t0* = *t1* >> *t2* (signed)
| Unspecified behavior for negative or out-of-range shifts.
* - rotl_i32/i64 *t0*, *t1*, *t2*
* - rotl *t0*, *t1*, *t2*
- | Rotation of *t2* bits to the left
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
| Unspecified behavior for negative or out-of-range shifts.
* - rotr_i32/i64 *t0*, *t1*, *t2*
* - rotr *t0*, *t1*, *t2*
- | Rotation of *t2* bits to the right.
| Unspecified behavior if *t2* < 0 or *t2* >= 32 (resp 64)
| Unspecified behavior for negative or out-of-range shifts.
Misc

6
include/tcg/tcg-opc.h
View file

@ -58,6 +58,8 @@ DEF(or, 1, 2, 0, TCG_OPF_INT)
DEF(orc, 1, 2, 0, TCG_OPF_INT)
DEF(rems, 1, 2, 0, TCG_OPF_INT)
DEF(remu, 1, 2, 0, TCG_OPF_INT)
DEF(rotl, 1, 2, 0, TCG_OPF_INT)
DEF(rotr, 1, 2, 0, TCG_OPF_INT)
DEF(sar, 1, 2, 0, TCG_OPF_INT)
DEF(shl, 1, 2, 0, TCG_OPF_INT)
DEF(shr, 1, 2, 0, TCG_OPF_INT)
@ -77,8 +79,6 @@ DEF(st8_i32, 0, 2, 1, 0)
DEF(st16_i32, 0, 2, 1, 0)
DEF(st_i32, 0, 2, 1, 0)
/* shifts/rotates */
DEF(rotl_i32, 1, 2, 0, 0)
DEF(rotr_i32, 1, 2, 0, 0)
DEF(deposit_i32, 1, 2, 2, 0)
DEF(extract_i32, 1, 1, 2, 0)
DEF(sextract_i32, 1, 1, 2, 0)
@ -115,8 +115,6 @@ DEF(st16_i64, 0, 2, 1, 0)
DEF(st32_i64, 0, 2, 1, 0)
DEF(st_i64, 0, 2, 1, 0)
/* shifts/rotates */
DEF(rotl_i64, 1, 2, 0, 0)
DEF(rotr_i64, 1, 2, 0, 0)
DEF(deposit_i64, 1, 2, 2, 0)
DEF(extract_i64, 1, 1, 2, 0)
DEF(sextract_i64, 1, 1, 2, 0)

20
tcg/optimize.c
View file

@ -464,16 +464,16 @@ static uint64_t do_constant_folding_2(TCGOpcode op, TCGType type,
}
return (int64_t)x >> (y & 63);
case INDEX_op_rotr_i32:
return ror32(x, y & 31);
case INDEX_op_rotr_i64:
case INDEX_op_rotr:
if (type == TCG_TYPE_I32) {
return ror32(x, y & 31);
}
return ror64(x, y & 63);
case INDEX_op_rotl_i32:
return rol32(x, y & 31);
case INDEX_op_rotl_i64:
case INDEX_op_rotl:
if (type == TCG_TYPE_I32) {
return rol32(x, y & 31);
}
return rol64(x, y & 63);
case INDEX_op_not:
@ -3025,8 +3025,8 @@ void tcg_optimize(TCGContext *s)
case INDEX_op_remu:
done = fold_remainder(&ctx, op);
break;
CASE_OP_32_64(rotl):
CASE_OP_32_64(rotr):
case INDEX_op_rotl:
case INDEX_op_rotr:
case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:

48
tcg/tcg-op.c
View file

@ -829,12 +829,12 @@ void tcg_gen_ctpop_i32(TCGv_i32 ret, TCGv_i32 arg1)
void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
tcg_gen_neg_i32(t0, arg2);
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, t0);
tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0);
tcg_temp_free_i32(t0);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@ -854,12 +854,12 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_mov_i32(ret, arg1);
} else if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
} else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_constant_i32(arg2);
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, t0);
} else if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0);
} else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_constant_i32(32 - arg2);
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, t0);
tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, t0);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
TCGv_i32 t1 = tcg_temp_ebb_new_i32();
@ -873,12 +873,12 @@ void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2)
void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_rotr_i32, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rotr_i32, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl_i32, TCG_TYPE_I32, 0)) {
if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rotr, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
tcg_gen_neg_i32(t0, arg2);
tcg_gen_op3_i32(INDEX_op_rotl_i32, ret, arg1, t0);
tcg_gen_op3_i32(INDEX_op_rotl, ret, arg1, t0);
tcg_temp_free_i32(t0);
} else {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
@ -2441,12 +2441,12 @@ void tcg_gen_ctpop_i64(TCGv_i64 ret, TCGv_i64 arg1)
void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
tcg_gen_neg_i64(t0, arg2);
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, t0);
tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0);
tcg_temp_free_i64(t0);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
@ -2466,12 +2466,12 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
/* some cases can be optimized here */
if (arg2 == 0) {
tcg_gen_mov_i64(ret, arg1);
} else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
} else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_constant_i64(arg2);
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, t0);
} else if (tcg_op_supported(INDEX_op_rotr_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0);
} else if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_constant_i64(64 - arg2);
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, t0);
tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, t0);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
TCGv_i64 t1 = tcg_temp_ebb_new_i64();
@ -2485,12 +2485,12 @@ void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2)
void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_rotr_i64, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rotr_i64, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl_i64, TCG_TYPE_I64, 0)) {
if (tcg_op_supported(INDEX_op_rotr, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rotr, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_rotl, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
tcg_gen_neg_i64(t0, arg2);
tcg_gen_op3_i64(INDEX_op_rotl_i64, ret, arg1, t0);
tcg_gen_op3_i64(INDEX_op_rotl, ret, arg1, t0);
tcg_temp_free_i64(t0);
} else {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();

12
tcg/tcg.c
View file

@ -1042,10 +1042,8 @@ static const TCGOutOp * const all_outop[NB_OPS] = {
OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc),
OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems),
OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu),
OUTOP(INDEX_op_rotl_i32, TCGOutOpBinary, outop_rotl),
OUTOP(INDEX_op_rotl_i64, TCGOutOpBinary, outop_rotl),
OUTOP(INDEX_op_rotr_i32, TCGOutOpBinary, outop_rotr),
OUTOP(INDEX_op_rotr_i64, TCGOutOpBinary, outop_rotr),
OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl),
OUTOP(INDEX_op_rotr, TCGOutOpBinary, outop_rotr),
OUTOP(INDEX_op_sar, TCGOutOpBinary, outop_sar),
OUTOP(INDEX_op_shl, TCGOutOpBinary, outop_shl),
OUTOP(INDEX_op_shr, TCGOutOpBinary, outop_shr),
@ -5418,10 +5416,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
case INDEX_op_rotl_i32:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i32:
case INDEX_op_rotr_i64:
case INDEX_op_rotl:
case INDEX_op_rotr:
case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:

8
tcg/tci.c
View file

@ -786,11 +786,11 @@ uintptr_t QEMU_DISABLE_CFI tcg_qemu_tb_exec(CPUArchState *env,
/* Shift/rotate operations (64 bit). */
case INDEX_op_rotl_i64:
case INDEX_op_rotl:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = rol64(regs[r1], regs[r2] & 63);
break;
case INDEX_op_rotr_i64:
case INDEX_op_rotr:
tci_args_rrr(insn, &r0, &r1, &r2);
regs[r0] = ror64(regs[r1], regs[r2] & 63);
break;
@ -1066,13 +1066,13 @@ int print_insn_tci(bfd_vma addr, disassemble_info *info)
case INDEX_op_orc:
case INDEX_op_rems:
case INDEX_op_remu:
case INDEX_op_rotl:
case INDEX_op_rotr:
case INDEX_op_sar:
case INDEX_op_shl:
case INDEX_op_shr:
case INDEX_op_sub:
case INDEX_op_xor:
case INDEX_op_rotl_i64:
case INDEX_op_rotr_i64:
case INDEX_op_clz_i32:
case INDEX_op_clz_i64:
case INDEX_op_ctz_i32:

4
tcg/tci/tcg-target.c.inc
View file

@ -773,7 +773,7 @@ static void tgen_rotl(TCGContext *s, TCGType type,
{
TCGOpcode opc = (type == TCG_TYPE_I32
? INDEX_op_tci_rotl32
: INDEX_op_rotl_i64);
: INDEX_op_rotl);
tcg_out_op_rrr(s, opc, a0, a1, a2);
}
@ -787,7 +787,7 @@ static void tgen_rotr(TCGContext *s, TCGType type,
{
TCGOpcode opc = (type == TCG_TYPE_I32
? INDEX_op_tci_rotr32
: INDEX_op_rotr_i64);
: INDEX_op_rotr);
tcg_out_op_rrr(s, opc, a0, a1, a2);
}