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https://github.com/Klipper3d/klipper.git
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e3905eb241
The F405, F407, and F429 chips are in the same series and almost all code definitions should apply to all chips in that series. Implement the alias and fix defintions in adc.c and Kconfig that were only applying to a subset of that series. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
264 lines
8.6 KiB
C
264 lines
8.6 KiB
C
// Code to setup clocks and gpio on stm32f2/stm32f4
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//
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// Copyright (C) 2019 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/irq.h" // irq_disable
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#include "board/usb_cdc.h" // usb_request_bootloader
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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#define FREQ_PERIPH_DIV (CONFIG_MACH_STM32F401 ? 2 : 4)
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
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#define FREQ_USB 48000000
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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RCC->APB1ENR |= (1<<pos);
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RCC->APB1ENR;
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} else if (periph_base < AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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RCC->APB2ENR |= (1<<pos);
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RCC->APB2ENR;
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} else if (periph_base < AHB2PERIPH_BASE) {
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uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400;
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RCC->AHB1ENR |= (1<<pos);
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RCC->AHB1ENR;
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}
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}
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t periph_base)
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{
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if (periph_base < APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
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return RCC->APB1ENR & (1<<pos);
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} else if (periph_base < AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
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return RCC->APB2ENR & (1<<pos);
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} else if (periph_base < AHB2PERIPH_BASE) {
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uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400;
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return RCC->AHB1ENR & (1<<pos);
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}
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return 0;
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400;
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RCC->AHB1ENR |= 1 << rcc_pos;
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RCC->AHB1ENR;
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}
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
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}
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#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 4096)
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#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT"
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// Handle USB reboot requests
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void
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usb_request_bootloader(void)
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{
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irq_disable();
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if (CONFIG_STM32_FLASH_START_4000) {
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// HID Bootloader
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RCC->APB1ENR |= RCC_APB1ENR_PWREN;
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RCC->APB1ENR;
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PWR->CR |= PWR_CR_DBP;
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// HID Bootloader magic key
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RTC->BKP4R = 0x424C;
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PWR->CR &= ~PWR_CR_DBP;
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} else {
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// System DFU Bootloader
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*(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG;
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}
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NVIC_SystemReset();
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Clock configuration
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static void
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enable_clock_stm32f20x(void)
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{
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#if CONFIG_MACH_STM32F207
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uint32_t pll_base = 1000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure 120Mhz PLL from external crystal (HSE)
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uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
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RCC->CR |= RCC_CR_HSEON;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
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} else {
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// Configure 120Mhz PLL from internal 16Mhz oscillator (HSI)
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uint32_t div = 16000000 / pll_base;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
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}
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RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
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| (0 << RCC_PLLCFGR_PLLP_Pos)
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| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos));
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RCC->CR |= RCC_CR_PLLON;
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#endif
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}
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static void
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enable_clock_stm32f40x(void)
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{
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#if CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F4x5
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uint32_t pll_base = (CONFIG_STM32_CLOCK_REF_25M) ? 1000000 : 2000000;
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uint32_t pllp = (CONFIG_MACH_STM32F401) ? 4 : 2;
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uint32_t pll_freq = CONFIG_CLOCK_FREQ * pllp, pllcfgr;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure 168Mhz PLL from external crystal (HSE)
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uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
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RCC->CR |= RCC_CR_HSEON;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
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} else {
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// Configure 168Mhz PLL from internal 16Mhz oscillator (HSI)
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uint32_t div = 16000000 / pll_base;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
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}
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RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
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| (((pllp >> 1) - 1) << RCC_PLLCFGR_PLLP_Pos)
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| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos));
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RCC->CR |= RCC_CR_PLLON;
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#endif
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}
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static void
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enable_clock_stm32f446(void)
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{
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#if CONFIG_MACH_STM32F446
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uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2, pllcfgr;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure 180Mhz PLL from external crystal (HSE)
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uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
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RCC->CR |= RCC_CR_HSEON;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
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} else {
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// Configure 180Mhz PLL from internal 16Mhz oscillator (HSI)
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uint32_t div = 16000000 / pll_base;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
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}
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RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
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| (0 << RCC_PLLCFGR_PLLP_Pos)
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| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos)
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| (6 << RCC_PLLCFGR_PLLR_Pos));
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RCC->CR |= RCC_CR_PLLON;
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// Enable "over drive"
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enable_pclock(PWR_BASE);
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PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN;
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while (!(PWR->CSR & PWR_CSR_ODRDY))
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;
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PWR->CR = (3 << PWR_CR_VOS_Pos) | PWR_CR_ODEN | PWR_CR_ODSWEN;
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while (!(PWR->CSR & PWR_CSR_ODSWRDY))
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;
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// Enable 48Mhz USB clock
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if (CONFIG_USBSERIAL) {
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uint32_t ref = (CONFIG_STM32_CLOCK_REF_INTERNAL
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? 16000000 : CONFIG_CLOCK_REF_FREQ);
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uint32_t plls_base = 2000000, plls_freq = FREQ_USB * 4;
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RCC->PLLSAICFGR = (
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((ref/plls_base) << RCC_PLLSAICFGR_PLLSAIM_Pos)
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| ((plls_freq/plls_base) << RCC_PLLSAICFGR_PLLSAIN_Pos)
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| (((plls_freq/FREQ_USB)/2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)
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| ((plls_freq/FREQ_USB) << RCC_PLLSAICFGR_PLLSAIQ_Pos));
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RCC->CR |= RCC_CR_PLLSAION;
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while (!(RCC->CR & RCC_CR_PLLSAIRDY))
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;
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RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL;
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}
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#endif
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}
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// Main clock setup called at chip startup
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static void
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clock_setup(void)
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{
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// Configure and enable PLL
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if (CONFIG_MACH_STM32F207)
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enable_clock_stm32f20x();
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else if (CONFIG_MACH_STM32F401 || CONFIG_MACH_STM32F4x5)
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enable_clock_stm32f40x();
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else
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enable_clock_stm32f446();
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// Set flash latency
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FLASH->ACR = (FLASH_ACR_LATENCY_5WS | FLASH_ACR_ICEN | FLASH_ACR_DCEN
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| FLASH_ACR_PRFTEN);
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// Wait for PLL lock
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while (!(RCC->CR & RCC_CR_PLLRDY))
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;
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// Switch system clock to PLL
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if (FREQ_PERIPH_DIV == 2)
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RCC->CFGR = RCC_CFGR_PPRE1_DIV2 | RCC_CFGR_PPRE2_DIV2 | RCC_CFGR_SW_PLL;
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else
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RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL;
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
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;
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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if (CONFIG_USBSERIAL && *(uint64_t*)USB_BOOT_FLAG_ADDR == USB_BOOT_FLAG) {
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*(uint64_t*)USB_BOOT_FLAG_ADDR = 0;
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uint32_t *sysbase = (uint32_t*)0x1fff0000;
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asm volatile("mov sp, %0\n bx %1"
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: : "r"(sysbase[0]), "r"(sysbase[1]));
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}
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// Run SystemInit() and then restore VTOR
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SystemInit();
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SCB->VTOR = (uint32_t)VectorTable;
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clock_setup();
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sched_main();
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}
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