mirror of
https://github.com/Klipper3d/klipper.git
synced 2025-07-19 20:57:55 -06:00
6aec6efcc9
Introduce a CONFIG_USB build symbol that is set whenever CONFIG_USBSERIAL or CONFIG_USBCANBUS is set. Use that symbol during setup so that the USB controller is properly initialized for both usb serial and usb canbus bridge configurations. This fixes the clock configuration for usb canbus bridge mode on stm32f446. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
246 lines
9 KiB
C
246 lines
9 KiB
C
// Code to setup clocks on stm32h7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/armcm_reset.h" // try_request_canboot
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // bootloader_request
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // get_pclock_frequency
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#include "sched.h" // sched_main
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/****************************************************************
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* Clock setup
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****************************************************************/
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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// Map a peripheral address to its enable bits
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struct cline
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lookup_clock_line(uint32_t periph_base)
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{
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if (periph_base >= D3_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB4ENR, .rst=&RCC->AHB4RSTR, .bit=bit};
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} else if (periph_base >= D3_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D3_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB4ENR, .rst=&RCC->APB4RSTR, .bit=bit};
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} else if (periph_base >= D1_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB3ENR, .rst=&RCC->AHB3RSTR, .bit=bit};
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} else if (periph_base >= D1_APB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D1_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB3ENR, .rst=&RCC->APB3RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_AHB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB2ENR, .rst=&RCC->AHB2RSTR, .bit=bit};
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} else if (periph_base >= D2_AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
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} else if (periph_base >= D2_APB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - D2_APB2PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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uint32_t bit = 1 << ((periph_base - D2_APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB1LENR,.rst=&RCC->APB1LRSTR,.bit=bit};
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t pos = ((uint32_t)regs - D3_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB4ENR |= (1<<pos);
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RCC->AHB4ENR;
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Main clock and power setup called at chip startup
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static void
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clock_setup(void)
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{
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// Ensure USB OTG ULPI is not enabled
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CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);
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CLEAR_BIT(RCC->AHB1LPENR, RCC_AHB1LPENR_USB2OTGHSULPILPEN);
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// Set this despite correct defaults.
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// "The software has to program the supply configuration in PWR control
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// register 3" (pg. 259)
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// Only a single write is allowed (pg. 304)
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PWR->CR3 = (PWR->CR3 | PWR_CR3_LDOEN) & ~(PWR_CR3_BYPASS | PWR_CR3_SCUEN);
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while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
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;
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// (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
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// /DIVP1(2) (SYSCLK 480Mhz)
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uint32_t pll_base = 5000000;
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// Only even dividers (DIVP1) are allowed
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uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure PLL from external crystal (HSE)
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY))
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;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSE);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(CONFIG_CLOCK_REF_FREQ/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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} else {
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// Configure PLL from internal 64Mhz oscillator (HSI)
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// HSI frequency of 64Mhz is integer divisible with 4Mhz
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pll_base = 4000000;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSI);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(64000000/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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}
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// Set input frequency range of PLL1 according to pll_base
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// 3 = 8-16Mhz, 2 = 4-8Mhz
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2);
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// Disable unused PLL1 outputs
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0);
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// Enable PLL1Q and set to 100MHz for SPI 1,2,3
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN, RCC_PLLCFGR_DIVQ1EN);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1,
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(pll_freq / FREQ_PERIPH - 1) << RCC_PLL1DIVR_Q1_Pos);
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// This is necessary, default is not 1!
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN);
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// Set multiplier DIVN1 and post divider DIVP1
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// 001 = /2, 010 = not allowed, 0011 = /4 ...
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk,
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(pll_freq/pll_base - 1) << RCC_PLL1DIVR_N1_Pos);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1_Msk,
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(pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLL1DIVR_P1_Pos);
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// Pwr
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS);
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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// Enable VOS0 (overdrive)
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if (CONFIG_CLOCK_FREQ > 400000000) {
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RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
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SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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}
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// Set flash latency according to clock frequency (pg.159)
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uint32_t flash_acr_latency = (CONFIG_CLOCK_FREQ > 450000000) ?
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FLASH_ACR_LATENCY_4WS : FLASH_ACR_LATENCY_2WS;
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY_Msk, flash_acr_latency);
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MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ_Msk, FLASH_ACR_WRHIGHFREQ_1);
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while (!(FLASH->ACR & flash_acr_latency))
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;
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// Set HPRE, D1PPRE, D2PPRE, D2PPRE2, D3PPRE dividers
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// 480MHz / 2 = 240MHz rcc_hclk3
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_D1CFGR_HPRE_3);
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// 240MHz / 2 = 120MHz rcc_pclk3
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_D1CFGR_D1PPRE_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk1
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, RCC_D2CFGR_D2PPRE1_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk2
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, RCC_D2CFGR_D2PPRE2_DIV2);
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// 240MHz / 2 = 120MHz rcc_pclk4
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MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, RCC_D3CFGR_D3PPRE_DIV2);
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// Switch on PLL1
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RCC->CR |= RCC_CR_PLL1ON;
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while (!(RCC->CR & RCC_CR_PLL1RDY))
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;
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// Switch system clock source (SYSCLK) to PLL1
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW_Msk, RCC_CFGR_SW_PLL1);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
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;
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// Configure HSI48 clock for USB
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if (CONFIG_USB) {
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SET_BIT(RCC->CR, RCC_CR_HSI48ON);
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while((RCC->CR & RCC_CR_HSI48RDY) == 0);
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SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);
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SET_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_CRSRST);
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CLEAR_BIT(RCC->APB1HRSTR, RCC_APB1HRSTR_CRSRST);
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CLEAR_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC);
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SET_BIT(CRS->CR, CRS_CR_CEN | CRS_CR_AUTOTRIMEN);
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CLEAR_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL);
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SET_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL);
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}
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}
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/****************************************************************
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* Bootloader
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****************************************************************/
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#define USB_BOOT_FLAG_ADDR (CONFIG_RAM_START + CONFIG_RAM_SIZE - 1024)
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#define USB_BOOT_FLAG 0x55534220424f4f54 // "USB BOOT"
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// Flag that bootloader is desired and reboot
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static void
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usb_reboot_for_dfu_bootloader(void)
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{
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irq_disable();
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*(uint64_t*)USB_BOOT_FLAG_ADDR = USB_BOOT_FLAG;
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NVIC_SystemReset();
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}
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// Check if rebooting into system DFU Bootloader
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static void
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check_usb_dfu_bootloader(void)
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{
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if (!CONFIG_USB || *(uint64_t*)USB_BOOT_FLAG_ADDR != USB_BOOT_FLAG)
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return;
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*(uint64_t*)USB_BOOT_FLAG_ADDR = 0;
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uint32_t *sysbase = (uint32_t*)0x1FF09800;
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asm volatile("mov sp, %0\n bx %1"
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: : "r"(sysbase[0]), "r"(sysbase[1]));
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}
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// Handle reboot requests
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void
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bootloader_request(void)
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{
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try_request_canboot();
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usb_reboot_for_dfu_bootloader();
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}
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/****************************************************************
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* Startup
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****************************************************************/
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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// Run SystemInit() and then restore VTOR
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SystemInit();
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RCC->D1CCIPR = 0x00000000;
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RCC->D2CCIP1R = 0x00000000;
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RCC->D2CCIP2R = 0x00000000;
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RCC->D3CCIPR = 0x00000000;
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SCB->VTOR = (uint32_t)VectorTable;
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check_usb_dfu_bootloader();
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clock_setup();
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sched_main();
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}
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