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lib: Add rp2350 files to pico-sdk

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2024-10-25 14:08:46 -04:00
parent 2ad0b1afc2
commit f00919070e
107 changed files with 128556 additions and 0 deletions
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20
lib/pico-sdk/pico-sdk.patch
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@ -47,3 +47,23 @@ index aff1fc9ae..59c67db19 100644
# note we don't do this by default in this file for backwards comaptibility with user code # note we don't do this by default in this file for backwards comaptibility with user code
# that may include this file, but not use unified syntax. Note that this macro does equivalent # that may include this file, but not use unified syntax. Note that this macro does equivalent
diff --git a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
index 8ae014e04..94d0f178c 100644
--- a/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
+++ b/lib/pico-sdk/rp2350/cmsis_include/RP2350.h
@@ -5933,6 +5933,7 @@ typedef struct { /*!< USB_DPRAM Structure
* @{
*/
+#if 0
#define RESETS_BASE 0x40020000UL
#define PSM_BASE 0x40018000UL
#define CLOCKS_BASE 0x40010000UL
@@ -5986,6 +5987,7 @@ typedef struct { /*!< USB_DPRAM Structure
#define OTP_DATA_RAW_BASE 0x40134000UL
#define TBMAN_BASE 0x40160000UL
#define USB_DPRAM_BASE 0x50100000UL
+#endif
/** @} */ /* End of group Device_Peripheral_peripheralAddr */

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lib/pico-sdk/rp2350/cmsis_include/RP2350.h Normal file
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lib/pico-sdk/rp2350/cmsis_include/system_RP2350.h Normal file
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@ -0,0 +1,65 @@
/*************************************************************************//**
* @file system_RP2040.h
* @brief CMSIS-Core(M) Device Peripheral Access Layer Header File for
* Device RP2040
* @version V1.0.0
* @date 5. May 2021
*****************************************************************************/
/*
* Copyright (c) 2009-2021 Arm Limited. All rights reserved.
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _CMSIS_SYSTEM_RP2040_H
#define _CMSIS_SYSTEM_RP2040_H
#ifdef __cplusplus
extern "C" {
#endif
/**
\brief Exception / Interrupt Handler Function Prototype
*/
typedef void(*VECTOR_TABLE_Type)(void);
/**
\brief System Clock Frequency (Core Clock)
*/
extern uint32_t SystemCoreClock;
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* _CMSIS_SYSTEM_RP2040_H */

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lib/pico-sdk/rp2350/hardware/regs/accessctrl.h Normal file
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316
lib/pico-sdk/rp2350/hardware/regs/adc.h Normal file
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@ -0,0 +1,316 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ADC
// Version : 2
// Bus type : apb
// Description : Control and data interface to SAR ADC
// =============================================================================
#ifndef _HARDWARE_REGS_ADC_H
#define _HARDWARE_REGS_ADC_H
// =============================================================================
// Register : ADC_CS
// Description : ADC Control and Status
#define ADC_CS_OFFSET _u(0x00000000)
#define ADC_CS_BITS _u(0x01fff70f)
#define ADC_CS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_CS_RROBIN
// Description : Round-robin sampling. 1 bit per channel. Set all bits to 0 to
// disable.
// Otherwise, the ADC will cycle through each enabled channel in a
// round-robin fashion.
// The first channel to be sampled will be the one currently
// indicated by AINSEL.
// AINSEL will be updated after each conversion with the newly-
// selected channel.
#define ADC_CS_RROBIN_RESET _u(0x000)
#define ADC_CS_RROBIN_BITS _u(0x01ff0000)
#define ADC_CS_RROBIN_MSB _u(24)
#define ADC_CS_RROBIN_LSB _u(16)
#define ADC_CS_RROBIN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_AINSEL
// Description : Select analog mux input. Updated automatically in round-robin
// mode.
// This is corrected for the package option so only ADC channels
// which are bonded are available, and in the correct order
#define ADC_CS_AINSEL_RESET _u(0x0)
#define ADC_CS_AINSEL_BITS _u(0x0000f000)
#define ADC_CS_AINSEL_MSB _u(15)
#define ADC_CS_AINSEL_LSB _u(12)
#define ADC_CS_AINSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR_STICKY
// Description : Some past ADC conversion encountered an error. Write 1 to
// clear.
#define ADC_CS_ERR_STICKY_RESET _u(0x0)
#define ADC_CS_ERR_STICKY_BITS _u(0x00000400)
#define ADC_CS_ERR_STICKY_MSB _u(10)
#define ADC_CS_ERR_STICKY_LSB _u(10)
#define ADC_CS_ERR_STICKY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_ERR
// Description : The most recent ADC conversion encountered an error; result is
// undefined or noisy.
#define ADC_CS_ERR_RESET _u(0x0)
#define ADC_CS_ERR_BITS _u(0x00000200)
#define ADC_CS_ERR_MSB _u(9)
#define ADC_CS_ERR_LSB _u(9)
#define ADC_CS_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_READY
// Description : 1 if the ADC is ready to start a new conversion. Implies any
// previous conversion has completed.
// 0 whilst conversion in progress.
#define ADC_CS_READY_RESET _u(0x0)
#define ADC_CS_READY_BITS _u(0x00000100)
#define ADC_CS_READY_MSB _u(8)
#define ADC_CS_READY_LSB _u(8)
#define ADC_CS_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_MANY
// Description : Continuously perform conversions whilst this bit is 1. A new
// conversion will start immediately after the previous finishes.
#define ADC_CS_START_MANY_RESET _u(0x0)
#define ADC_CS_START_MANY_BITS _u(0x00000008)
#define ADC_CS_START_MANY_MSB _u(3)
#define ADC_CS_START_MANY_LSB _u(3)
#define ADC_CS_START_MANY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_START_ONCE
// Description : Start a single conversion. Self-clearing. Ignored if start_many
// is asserted.
#define ADC_CS_START_ONCE_RESET _u(0x0)
#define ADC_CS_START_ONCE_BITS _u(0x00000004)
#define ADC_CS_START_ONCE_MSB _u(2)
#define ADC_CS_START_ONCE_LSB _u(2)
#define ADC_CS_START_ONCE_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : ADC_CS_TS_EN
// Description : Power on temperature sensor. 1 - enabled. 0 - disabled.
#define ADC_CS_TS_EN_RESET _u(0x0)
#define ADC_CS_TS_EN_BITS _u(0x00000002)
#define ADC_CS_TS_EN_MSB _u(1)
#define ADC_CS_TS_EN_LSB _u(1)
#define ADC_CS_TS_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_CS_EN
// Description : Power on ADC and enable its clock.
// 1 - enabled. 0 - disabled.
#define ADC_CS_EN_RESET _u(0x0)
#define ADC_CS_EN_BITS _u(0x00000001)
#define ADC_CS_EN_MSB _u(0)
#define ADC_CS_EN_LSB _u(0)
#define ADC_CS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_RESULT
// Description : Result of most recent ADC conversion
#define ADC_RESULT_OFFSET _u(0x00000004)
#define ADC_RESULT_BITS _u(0x00000fff)
#define ADC_RESULT_RESET _u(0x00000000)
#define ADC_RESULT_MSB _u(11)
#define ADC_RESULT_LSB _u(0)
#define ADC_RESULT_ACCESS "RO"
// =============================================================================
// Register : ADC_FCS
// Description : FIFO control and status
#define ADC_FCS_OFFSET _u(0x00000008)
#define ADC_FCS_BITS _u(0x0f0f0f0f)
#define ADC_FCS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FCS_THRESH
// Description : DREQ/IRQ asserted when level >= threshold
#define ADC_FCS_THRESH_RESET _u(0x0)
#define ADC_FCS_THRESH_BITS _u(0x0f000000)
#define ADC_FCS_THRESH_MSB _u(27)
#define ADC_FCS_THRESH_LSB _u(24)
#define ADC_FCS_THRESH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_LEVEL
// Description : The number of conversion results currently waiting in the FIFO
#define ADC_FCS_LEVEL_RESET _u(0x0)
#define ADC_FCS_LEVEL_BITS _u(0x000f0000)
#define ADC_FCS_LEVEL_MSB _u(19)
#define ADC_FCS_LEVEL_LSB _u(16)
#define ADC_FCS_LEVEL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_OVER
// Description : 1 if the FIFO has been overflowed. Write 1 to clear.
#define ADC_FCS_OVER_RESET _u(0x0)
#define ADC_FCS_OVER_BITS _u(0x00000800)
#define ADC_FCS_OVER_MSB _u(11)
#define ADC_FCS_OVER_LSB _u(11)
#define ADC_FCS_OVER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_UNDER
// Description : 1 if the FIFO has been underflowed. Write 1 to clear.
#define ADC_FCS_UNDER_RESET _u(0x0)
#define ADC_FCS_UNDER_BITS _u(0x00000400)
#define ADC_FCS_UNDER_MSB _u(10)
#define ADC_FCS_UNDER_LSB _u(10)
#define ADC_FCS_UNDER_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_FULL
#define ADC_FCS_FULL_RESET _u(0x0)
#define ADC_FCS_FULL_BITS _u(0x00000200)
#define ADC_FCS_FULL_MSB _u(9)
#define ADC_FCS_FULL_LSB _u(9)
#define ADC_FCS_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EMPTY
#define ADC_FCS_EMPTY_RESET _u(0x0)
#define ADC_FCS_EMPTY_BITS _u(0x00000100)
#define ADC_FCS_EMPTY_MSB _u(8)
#define ADC_FCS_EMPTY_LSB _u(8)
#define ADC_FCS_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_DREQ_EN
// Description : If 1: assert DMA requests when FIFO contains data
#define ADC_FCS_DREQ_EN_RESET _u(0x0)
#define ADC_FCS_DREQ_EN_BITS _u(0x00000008)
#define ADC_FCS_DREQ_EN_MSB _u(3)
#define ADC_FCS_DREQ_EN_LSB _u(3)
#define ADC_FCS_DREQ_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_ERR
// Description : If 1: conversion error bit appears in the FIFO alongside the
// result
#define ADC_FCS_ERR_RESET _u(0x0)
#define ADC_FCS_ERR_BITS _u(0x00000004)
#define ADC_FCS_ERR_MSB _u(2)
#define ADC_FCS_ERR_LSB _u(2)
#define ADC_FCS_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_SHIFT
// Description : If 1: FIFO results are right-shifted to be one byte in size.
// Enables DMA to byte buffers.
#define ADC_FCS_SHIFT_RESET _u(0x0)
#define ADC_FCS_SHIFT_BITS _u(0x00000002)
#define ADC_FCS_SHIFT_MSB _u(1)
#define ADC_FCS_SHIFT_LSB _u(1)
#define ADC_FCS_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_FCS_EN
// Description : If 1: write result to the FIFO after each conversion.
#define ADC_FCS_EN_RESET _u(0x0)
#define ADC_FCS_EN_BITS _u(0x00000001)
#define ADC_FCS_EN_MSB _u(0)
#define ADC_FCS_EN_LSB _u(0)
#define ADC_FCS_EN_ACCESS "RW"
// =============================================================================
// Register : ADC_FIFO
// Description : Conversion result FIFO
#define ADC_FIFO_OFFSET _u(0x0000000c)
#define ADC_FIFO_BITS _u(0x00008fff)
#define ADC_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_ERR
// Description : 1 if this particular sample experienced a conversion error.
// Remains in the same location if the sample is shifted.
#define ADC_FIFO_ERR_RESET "-"
#define ADC_FIFO_ERR_BITS _u(0x00008000)
#define ADC_FIFO_ERR_MSB _u(15)
#define ADC_FIFO_ERR_LSB _u(15)
#define ADC_FIFO_ERR_ACCESS "RF"
// -----------------------------------------------------------------------------
// Field : ADC_FIFO_VAL
#define ADC_FIFO_VAL_RESET "-"
#define ADC_FIFO_VAL_BITS _u(0x00000fff)
#define ADC_FIFO_VAL_MSB _u(11)
#define ADC_FIFO_VAL_LSB _u(0)
#define ADC_FIFO_VAL_ACCESS "RF"
// =============================================================================
// Register : ADC_DIV
// Description : Clock divider. If non-zero, CS_START_MANY will start
// conversions
// at regular intervals rather than back-to-back.
// The divider is reset when either of these fields are written.
// Total period is 1 + INT + FRAC / 256
#define ADC_DIV_OFFSET _u(0x00000010)
#define ADC_DIV_BITS _u(0x00ffffff)
#define ADC_DIV_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_DIV_INT
// Description : Integer part of clock divisor.
#define ADC_DIV_INT_RESET _u(0x0000)
#define ADC_DIV_INT_BITS _u(0x00ffff00)
#define ADC_DIV_INT_MSB _u(23)
#define ADC_DIV_INT_LSB _u(8)
#define ADC_DIV_INT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ADC_DIV_FRAC
// Description : Fractional part of clock divisor. First-order delta-sigma.
#define ADC_DIV_FRAC_RESET _u(0x00)
#define ADC_DIV_FRAC_BITS _u(0x000000ff)
#define ADC_DIV_FRAC_MSB _u(7)
#define ADC_DIV_FRAC_LSB _u(0)
#define ADC_DIV_FRAC_ACCESS "RW"
// =============================================================================
// Register : ADC_INTR
// Description : Raw Interrupts
#define ADC_INTR_OFFSET _u(0x00000014)
#define ADC_INTR_BITS _u(0x00000001)
#define ADC_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTR_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTR_FIFO_RESET _u(0x0)
#define ADC_INTR_FIFO_BITS _u(0x00000001)
#define ADC_INTR_FIFO_MSB _u(0)
#define ADC_INTR_FIFO_LSB _u(0)
#define ADC_INTR_FIFO_ACCESS "RO"
// =============================================================================
// Register : ADC_INTE
// Description : Interrupt Enable
#define ADC_INTE_OFFSET _u(0x00000018)
#define ADC_INTE_BITS _u(0x00000001)
#define ADC_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTE_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTE_FIFO_RESET _u(0x0)
#define ADC_INTE_FIFO_BITS _u(0x00000001)
#define ADC_INTE_FIFO_MSB _u(0)
#define ADC_INTE_FIFO_LSB _u(0)
#define ADC_INTE_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTF
// Description : Interrupt Force
#define ADC_INTF_OFFSET _u(0x0000001c)
#define ADC_INTF_BITS _u(0x00000001)
#define ADC_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTF_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTF_FIFO_RESET _u(0x0)
#define ADC_INTF_FIFO_BITS _u(0x00000001)
#define ADC_INTF_FIFO_MSB _u(0)
#define ADC_INTF_FIFO_LSB _u(0)
#define ADC_INTF_FIFO_ACCESS "RW"
// =============================================================================
// Register : ADC_INTS
// Description : Interrupt status after masking & forcing
#define ADC_INTS_OFFSET _u(0x00000020)
#define ADC_INTS_BITS _u(0x00000001)
#define ADC_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ADC_INTS_FIFO
// Description : Triggered when the sample FIFO reaches a certain level.
// This level can be programmed via the FCS_THRESH field.
#define ADC_INTS_FIFO_RESET _u(0x0)
#define ADC_INTS_FIFO_BITS _u(0x00000001)
#define ADC_INTS_FIFO_MSB _u(0)
#define ADC_INTS_FIFO_LSB _u(0)
#define ADC_INTS_FIFO_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_ADC_H

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lib/pico-sdk/rp2350/hardware/regs/addressmap.h Normal file
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@ -0,0 +1,112 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _ADDRESSMAP_H
#define _ADDRESSMAP_H
/**
* \file rp2350/addressmap.h
*/
#include "hardware/platform_defs.h"
// Register address offsets for atomic RMW aliases
#define REG_ALIAS_RW_BITS (_u(0x0) << _u(12))
#define REG_ALIAS_XOR_BITS (_u(0x1) << _u(12))
#define REG_ALIAS_SET_BITS (_u(0x2) << _u(12))
#define REG_ALIAS_CLR_BITS (_u(0x3) << _u(12))
#define ROM_BASE _u(0x00000000)
#define XIP_BASE _u(0x10000000)
#define XIP_SRAM_BASE _u(0x13ffc000)
#define XIP_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_BASE _u(0x14000000)
#define XIP_SRAM_END _u(0x14000000)
#define XIP_NOCACHE_NOALLOC_END _u(0x18000000)
#define XIP_MAINTENANCE_BASE _u(0x18000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_BASE _u(0x1c000000)
#define SRAM0_BASE _u(0x20000000)
#define XIP_NOCACHE_NOALLOC_NOTRANSLATE_END _u(0x20000000)
#define SRAM_BASE _u(0x20000000)
#define SRAM_STRIPED_BASE _u(0x20000000)
#define SRAM4_BASE _u(0x20040000)
#define SRAM8_BASE _u(0x20080000)
#define SRAM_STRIPED_END _u(0x20080000)
#define SRAM_SCRATCH_X_BASE _u(0x20080000)
#define SRAM9_BASE _u(0x20081000)
#define SRAM_SCRATCH_Y_BASE _u(0x20081000)
#define SRAM_END _u(0x20082000)
#define SYSINFO_BASE _u(0x40000000)
#define SYSCFG_BASE _u(0x40008000)
#define CLOCKS_BASE _u(0x40010000)
#define PSM_BASE _u(0x40018000)
#define RESETS_BASE _u(0x40020000)
#define IO_BANK0_BASE _u(0x40028000)
#define IO_QSPI_BASE _u(0x40030000)
#define PADS_BANK0_BASE _u(0x40038000)
#define PADS_QSPI_BASE _u(0x40040000)
#define XOSC_BASE _u(0x40048000)
#define PLL_SYS_BASE _u(0x40050000)
#define PLL_USB_BASE _u(0x40058000)
#define ACCESSCTRL_BASE _u(0x40060000)
#define BUSCTRL_BASE _u(0x40068000)
#define UART0_BASE _u(0x40070000)
#define UART1_BASE _u(0x40078000)
#define SPI0_BASE _u(0x40080000)
#define SPI1_BASE _u(0x40088000)
#define I2C0_BASE _u(0x40090000)
#define I2C1_BASE _u(0x40098000)
#define ADC_BASE _u(0x400a0000)
#define PWM_BASE _u(0x400a8000)
#define TIMER0_BASE _u(0x400b0000)
#define TIMER1_BASE _u(0x400b8000)
#define HSTX_CTRL_BASE _u(0x400c0000)
#define XIP_CTRL_BASE _u(0x400c8000)
#define XIP_QMI_BASE _u(0x400d0000)
#define WATCHDOG_BASE _u(0x400d8000)
#define BOOTRAM_BASE _u(0x400e0000)
#define BOOTRAM_END _u(0x400e0400)
#define ROSC_BASE _u(0x400e8000)
#define TRNG_BASE _u(0x400f0000)
#define SHA256_BASE _u(0x400f8000)
#define POWMAN_BASE _u(0x40100000)
#define TICKS_BASE _u(0x40108000)
#define OTP_BASE _u(0x40120000)
#define OTP_DATA_BASE _u(0x40130000)
#define OTP_DATA_RAW_BASE _u(0x40134000)
#define OTP_DATA_GUARDED_BASE _u(0x40138000)
#define OTP_DATA_RAW_GUARDED_BASE _u(0x4013c000)
#define CORESIGHT_PERIPH_BASE _u(0x40140000)
#define CORESIGHT_ROMTABLE_BASE _u(0x40140000)
#define CORESIGHT_AHB_AP_CORE0_BASE _u(0x40142000)
#define CORESIGHT_AHB_AP_CORE1_BASE _u(0x40144000)
#define CORESIGHT_TIMESTAMP_GEN_BASE _u(0x40146000)
#define CORESIGHT_ATB_FUNNEL_BASE _u(0x40147000)
#define CORESIGHT_TPIU_BASE _u(0x40148000)
#define CORESIGHT_CTI_BASE _u(0x40149000)
#define CORESIGHT_APB_AP_RISCV_BASE _u(0x4014a000)
#define DFT_BASE _u(0x40150000)
#define GLITCH_DETECTOR_BASE _u(0x40158000)
#define TBMAN_BASE _u(0x40160000)
#define DMA_BASE _u(0x50000000)
#define USBCTRL_BASE _u(0x50100000)
#define USBCTRL_DPRAM_BASE _u(0x50100000)
#define USBCTRL_REGS_BASE _u(0x50110000)
#define PIO0_BASE _u(0x50200000)
#define PIO1_BASE _u(0x50300000)
#define PIO2_BASE _u(0x50400000)
#define XIP_AUX_BASE _u(0x50500000)
#define HSTX_FIFO_BASE _u(0x50600000)
#define CORESIGHT_TRACE_BASE _u(0x50700000)
#define SIO_BASE _u(0xd0000000)
#define SIO_NONSEC_BASE _u(0xd0020000)
#define PPB_BASE _u(0xe0000000)
#define PPB_NONSEC_BASE _u(0xe0020000)
#define EPPB_BASE _u(0xe0080000)
#endif // _ADDRESSMAP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BOOTRAM
// Version : 1
// Bus type : apb
// Description : Additional registers mapped adjacent to the bootram, for use
// by the bootrom.
// =============================================================================
#ifndef _HARDWARE_REGS_BOOTRAM_H
#define _HARDWARE_REGS_BOOTRAM_H
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE0
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE0_OFFSET _u(0x00000800)
#define BOOTRAM_WRITE_ONCE0_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE0_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE0_MSB _u(31)
#define BOOTRAM_WRITE_ONCE0_LSB _u(0)
#define BOOTRAM_WRITE_ONCE0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_WRITE_ONCE1
// Description : This registers always ORs writes into its current contents.
// Once a bit is set, it can only be cleared by a reset.
#define BOOTRAM_WRITE_ONCE1_OFFSET _u(0x00000804)
#define BOOTRAM_WRITE_ONCE1_BITS _u(0xffffffff)
#define BOOTRAM_WRITE_ONCE1_RESET _u(0x00000000)
#define BOOTRAM_WRITE_ONCE1_MSB _u(31)
#define BOOTRAM_WRITE_ONCE1_LSB _u(0)
#define BOOTRAM_WRITE_ONCE1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK_STAT
// Description : Bootlock status register. 1=unclaimed, 0=claimed. These locks
// function identically to the SIO spinlocks, but are reserved for
// bootrom use.
#define BOOTRAM_BOOTLOCK_STAT_OFFSET _u(0x00000808)
#define BOOTRAM_BOOTLOCK_STAT_BITS _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_RESET _u(0x000000ff)
#define BOOTRAM_BOOTLOCK_STAT_MSB _u(7)
#define BOOTRAM_BOOTLOCK_STAT_LSB _u(0)
#define BOOTRAM_BOOTLOCK_STAT_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK0
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK0_OFFSET _u(0x0000080c)
#define BOOTRAM_BOOTLOCK0_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK0_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK0_MSB _u(31)
#define BOOTRAM_BOOTLOCK0_LSB _u(0)
#define BOOTRAM_BOOTLOCK0_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK1
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK1_OFFSET _u(0x00000810)
#define BOOTRAM_BOOTLOCK1_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK1_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK1_MSB _u(31)
#define BOOTRAM_BOOTLOCK1_LSB _u(0)
#define BOOTRAM_BOOTLOCK1_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK2
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK2_OFFSET _u(0x00000814)
#define BOOTRAM_BOOTLOCK2_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK2_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK2_MSB _u(31)
#define BOOTRAM_BOOTLOCK2_LSB _u(0)
#define BOOTRAM_BOOTLOCK2_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK3
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK3_OFFSET _u(0x00000818)
#define BOOTRAM_BOOTLOCK3_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK3_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK3_MSB _u(31)
#define BOOTRAM_BOOTLOCK3_LSB _u(0)
#define BOOTRAM_BOOTLOCK3_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK4
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK4_OFFSET _u(0x0000081c)
#define BOOTRAM_BOOTLOCK4_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK4_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK4_MSB _u(31)
#define BOOTRAM_BOOTLOCK4_LSB _u(0)
#define BOOTRAM_BOOTLOCK4_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK5
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK5_OFFSET _u(0x00000820)
#define BOOTRAM_BOOTLOCK5_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK5_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK5_MSB _u(31)
#define BOOTRAM_BOOTLOCK5_LSB _u(0)
#define BOOTRAM_BOOTLOCK5_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK6
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK6_OFFSET _u(0x00000824)
#define BOOTRAM_BOOTLOCK6_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK6_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK6_MSB _u(31)
#define BOOTRAM_BOOTLOCK6_LSB _u(0)
#define BOOTRAM_BOOTLOCK6_ACCESS "RW"
// =============================================================================
// Register : BOOTRAM_BOOTLOCK7
// Description : Read to claim and check. Write to unclaim. The value returned
// on successful claim is 1 << n, and on failed claim is zero.
#define BOOTRAM_BOOTLOCK7_OFFSET _u(0x00000828)
#define BOOTRAM_BOOTLOCK7_BITS _u(0xffffffff)
#define BOOTRAM_BOOTLOCK7_RESET _u(0x00000000)
#define BOOTRAM_BOOTLOCK7_MSB _u(31)
#define BOOTRAM_BOOTLOCK7_LSB _u(0)
#define BOOTRAM_BOOTLOCK7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_BOOTRAM_H

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lib/pico-sdk/rp2350/hardware/regs/busctrl.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : BUSCTRL
// Version : 1
// Bus type : apb
// Description : Register block for busfabric control signals and performance
// counters
// =============================================================================
#ifndef _HARDWARE_REGS_BUSCTRL_H
#define _HARDWARE_REGS_BUSCTRL_H
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY
// Description : Set the priority of each master for bus arbitration.
#define BUSCTRL_BUS_PRIORITY_OFFSET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_BITS _u(0x00001111)
#define BUSCTRL_BUS_PRIORITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_W
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_W_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_W_BITS _u(0x00001000)
#define BUSCTRL_BUS_PRIORITY_DMA_W_MSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_LSB _u(12)
#define BUSCTRL_BUS_PRIORITY_DMA_W_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_DMA_R
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_DMA_R_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_DMA_R_BITS _u(0x00000100)
#define BUSCTRL_BUS_PRIORITY_DMA_R_MSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_LSB _u(8)
#define BUSCTRL_BUS_PRIORITY_DMA_R_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC1
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC1_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC1_BITS _u(0x00000010)
#define BUSCTRL_BUS_PRIORITY_PROC1_MSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_LSB _u(4)
#define BUSCTRL_BUS_PRIORITY_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : BUSCTRL_BUS_PRIORITY_PROC0
// Description : 0 - low priority, 1 - high priority
#define BUSCTRL_BUS_PRIORITY_PROC0_RESET _u(0x0)
#define BUSCTRL_BUS_PRIORITY_PROC0_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_PROC0_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_PROC0_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_BUS_PRIORITY_ACK
// Description : Bus priority acknowledge
// Goes to 1 once all arbiters have registered the new global
// priority levels.
// Arbiters update their local priority when servicing a new
// nonsequential access.
// In normal circumstances this will happen almost immediately.
#define BUSCTRL_BUS_PRIORITY_ACK_OFFSET _u(0x00000004)
#define BUSCTRL_BUS_PRIORITY_ACK_BITS _u(0x00000001)
#define BUSCTRL_BUS_PRIORITY_ACK_RESET _u(0x00000000)
#define BUSCTRL_BUS_PRIORITY_ACK_MSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_LSB _u(0)
#define BUSCTRL_BUS_PRIORITY_ACK_ACCESS "RO"
// =============================================================================
// Register : BUSCTRL_PERFCTR_EN
// Description : Enable the performance counters. If 0, the performance counters
// do not increment. This can be used to precisely start/stop
// event sampling around the profiled section of code.
//
// The performance counters are initially disabled, to save
// energy.
#define BUSCTRL_PERFCTR_EN_OFFSET _u(0x00000008)
#define BUSCTRL_PERFCTR_EN_BITS _u(0x00000001)
#define BUSCTRL_PERFCTR_EN_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR_EN_MSB _u(0)
#define BUSCTRL_PERFCTR_EN_LSB _u(0)
#define BUSCTRL_PERFCTR_EN_ACCESS "RW"
// =============================================================================
// Register : BUSCTRL_PERFCTR0
// Description : Bus fabric performance counter 0
// Busfabric saturating performance counter 0
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL0
#define BUSCTRL_PERFCTR0_OFFSET _u(0x0000000c)
#define BUSCTRL_PERFCTR0_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR0_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR0_MSB _u(23)
#define BUSCTRL_PERFCTR0_LSB _u(0)
#define BUSCTRL_PERFCTR0_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL0
// Description : Bus fabric performance event select for PERFCTR0
// Select an event for PERFCTR0. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL0_OFFSET _u(0x00000010)
#define BUSCTRL_PERFSEL0_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL0_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL0_MSB _u(6)
#define BUSCTRL_PERFSEL0_LSB _u(0)
#define BUSCTRL_PERFSEL0_ACCESS "RW"
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL0_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL0_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL0_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL0_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL0_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL0_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL0_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL0_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL0_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL0_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL0_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL0_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL0_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL0_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL0_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR1
// Description : Bus fabric performance counter 1
// Busfabric saturating performance counter 1
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL1
#define BUSCTRL_PERFCTR1_OFFSET _u(0x00000014)
#define BUSCTRL_PERFCTR1_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR1_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR1_MSB _u(23)
#define BUSCTRL_PERFCTR1_LSB _u(0)
#define BUSCTRL_PERFCTR1_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL1
// Description : Bus fabric performance event select for PERFCTR1
// Select an event for PERFCTR1. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL1_OFFSET _u(0x00000018)
#define BUSCTRL_PERFSEL1_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL1_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL1_MSB _u(6)
#define BUSCTRL_PERFSEL1_LSB _u(0)
#define BUSCTRL_PERFSEL1_ACCESS "RW"
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL1_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL1_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL1_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL1_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL1_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL1_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL1_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL1_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL1_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL1_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL1_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL1_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL1_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL1_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL1_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR2
// Description : Bus fabric performance counter 2
// Busfabric saturating performance counter 2
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL2
#define BUSCTRL_PERFCTR2_OFFSET _u(0x0000001c)
#define BUSCTRL_PERFCTR2_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR2_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR2_MSB _u(23)
#define BUSCTRL_PERFCTR2_LSB _u(0)
#define BUSCTRL_PERFCTR2_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL2
// Description : Bus fabric performance event select for PERFCTR2
// Select an event for PERFCTR2. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL2_OFFSET _u(0x00000020)
#define BUSCTRL_PERFSEL2_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL2_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL2_MSB _u(6)
#define BUSCTRL_PERFSEL2_LSB _u(0)
#define BUSCTRL_PERFSEL2_ACCESS "RW"
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL2_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL2_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL2_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL2_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL2_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL2_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL2_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL2_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL2_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL2_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL2_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL2_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL2_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL2_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL2_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
// Register : BUSCTRL_PERFCTR3
// Description : Bus fabric performance counter 3
// Busfabric saturating performance counter 3
// Count some event signal from the busfabric arbiters, if
// PERFCTR_EN is set.
// Write any value to clear. Select an event to count using
// PERFSEL3
#define BUSCTRL_PERFCTR3_OFFSET _u(0x00000024)
#define BUSCTRL_PERFCTR3_BITS _u(0x00ffffff)
#define BUSCTRL_PERFCTR3_RESET _u(0x00000000)
#define BUSCTRL_PERFCTR3_MSB _u(23)
#define BUSCTRL_PERFCTR3_LSB _u(0)
#define BUSCTRL_PERFCTR3_ACCESS "WC"
// =============================================================================
// Register : BUSCTRL_PERFSEL3
// Description : Bus fabric performance event select for PERFCTR3
// Select an event for PERFCTR3. For each downstream port of the
// main crossbar, four events are available: ACCESS, an access
// took place; ACCESS_CONTESTED, an access took place that
// previously stalled due to contention from other masters;
// STALL_DOWNSTREAM, count cycles where any master stalled due to
// a stall on the downstream bus; STALL_UPSTREAM, count cycles
// where any master stalled for any reason, including contention
// from other masters.
// 0x00 -> siob_proc1_stall_upstream
// 0x01 -> siob_proc1_stall_downstream
// 0x02 -> siob_proc1_access_contested
// 0x03 -> siob_proc1_access
// 0x04 -> siob_proc0_stall_upstream
// 0x05 -> siob_proc0_stall_downstream
// 0x06 -> siob_proc0_access_contested
// 0x07 -> siob_proc0_access
// 0x08 -> apb_stall_upstream
// 0x09 -> apb_stall_downstream
// 0x0a -> apb_access_contested
// 0x0b -> apb_access
// 0x0c -> fastperi_stall_upstream
// 0x0d -> fastperi_stall_downstream
// 0x0e -> fastperi_access_contested
// 0x0f -> fastperi_access
// 0x10 -> sram9_stall_upstream
// 0x11 -> sram9_stall_downstream
// 0x12 -> sram9_access_contested
// 0x13 -> sram9_access
// 0x14 -> sram8_stall_upstream
// 0x15 -> sram8_stall_downstream
// 0x16 -> sram8_access_contested
// 0x17 -> sram8_access
// 0x18 -> sram7_stall_upstream
// 0x19 -> sram7_stall_downstream
// 0x1a -> sram7_access_contested
// 0x1b -> sram7_access
// 0x1c -> sram6_stall_upstream
// 0x1d -> sram6_stall_downstream
// 0x1e -> sram6_access_contested
// 0x1f -> sram6_access
// 0x20 -> sram5_stall_upstream
// 0x21 -> sram5_stall_downstream
// 0x22 -> sram5_access_contested
// 0x23 -> sram5_access
// 0x24 -> sram4_stall_upstream
// 0x25 -> sram4_stall_downstream
// 0x26 -> sram4_access_contested
// 0x27 -> sram4_access
// 0x28 -> sram3_stall_upstream
// 0x29 -> sram3_stall_downstream
// 0x2a -> sram3_access_contested
// 0x2b -> sram3_access
// 0x2c -> sram2_stall_upstream
// 0x2d -> sram2_stall_downstream
// 0x2e -> sram2_access_contested
// 0x2f -> sram2_access
// 0x30 -> sram1_stall_upstream
// 0x31 -> sram1_stall_downstream
// 0x32 -> sram1_access_contested
// 0x33 -> sram1_access
// 0x34 -> sram0_stall_upstream
// 0x35 -> sram0_stall_downstream
// 0x36 -> sram0_access_contested
// 0x37 -> sram0_access
// 0x38 -> xip_main1_stall_upstream
// 0x39 -> xip_main1_stall_downstream
// 0x3a -> xip_main1_access_contested
// 0x3b -> xip_main1_access
// 0x3c -> xip_main0_stall_upstream
// 0x3d -> xip_main0_stall_downstream
// 0x3e -> xip_main0_access_contested
// 0x3f -> xip_main0_access
// 0x40 -> rom_stall_upstream
// 0x41 -> rom_stall_downstream
// 0x42 -> rom_access_contested
// 0x43 -> rom_access
#define BUSCTRL_PERFSEL3_OFFSET _u(0x00000028)
#define BUSCTRL_PERFSEL3_BITS _u(0x0000007f)
#define BUSCTRL_PERFSEL3_RESET _u(0x0000001f)
#define BUSCTRL_PERFSEL3_MSB _u(6)
#define BUSCTRL_PERFSEL3_LSB _u(0)
#define BUSCTRL_PERFSEL3_ACCESS "RW"
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_UPSTREAM _u(0x00)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_STALL_DOWNSTREAM _u(0x01)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS_CONTESTED _u(0x02)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC1_ACCESS _u(0x03)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_UPSTREAM _u(0x04)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_STALL_DOWNSTREAM _u(0x05)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS_CONTESTED _u(0x06)
#define BUSCTRL_PERFSEL3_VALUE_SIOB_PROC0_ACCESS _u(0x07)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_UPSTREAM _u(0x08)
#define BUSCTRL_PERFSEL3_VALUE_APB_STALL_DOWNSTREAM _u(0x09)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS_CONTESTED _u(0x0a)
#define BUSCTRL_PERFSEL3_VALUE_APB_ACCESS _u(0x0b)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_UPSTREAM _u(0x0c)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_STALL_DOWNSTREAM _u(0x0d)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS_CONTESTED _u(0x0e)
#define BUSCTRL_PERFSEL3_VALUE_FASTPERI_ACCESS _u(0x0f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_UPSTREAM _u(0x10)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_STALL_DOWNSTREAM _u(0x11)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS_CONTESTED _u(0x12)
#define BUSCTRL_PERFSEL3_VALUE_SRAM9_ACCESS _u(0x13)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_UPSTREAM _u(0x14)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_STALL_DOWNSTREAM _u(0x15)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS_CONTESTED _u(0x16)
#define BUSCTRL_PERFSEL3_VALUE_SRAM8_ACCESS _u(0x17)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_UPSTREAM _u(0x18)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_STALL_DOWNSTREAM _u(0x19)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS_CONTESTED _u(0x1a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM7_ACCESS _u(0x1b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_UPSTREAM _u(0x1c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_STALL_DOWNSTREAM _u(0x1d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS_CONTESTED _u(0x1e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM6_ACCESS _u(0x1f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_UPSTREAM _u(0x20)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_STALL_DOWNSTREAM _u(0x21)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS_CONTESTED _u(0x22)
#define BUSCTRL_PERFSEL3_VALUE_SRAM5_ACCESS _u(0x23)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_UPSTREAM _u(0x24)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_STALL_DOWNSTREAM _u(0x25)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS_CONTESTED _u(0x26)
#define BUSCTRL_PERFSEL3_VALUE_SRAM4_ACCESS _u(0x27)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_UPSTREAM _u(0x28)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_STALL_DOWNSTREAM _u(0x29)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS_CONTESTED _u(0x2a)
#define BUSCTRL_PERFSEL3_VALUE_SRAM3_ACCESS _u(0x2b)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_UPSTREAM _u(0x2c)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_STALL_DOWNSTREAM _u(0x2d)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS_CONTESTED _u(0x2e)
#define BUSCTRL_PERFSEL3_VALUE_SRAM2_ACCESS _u(0x2f)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_UPSTREAM _u(0x30)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_STALL_DOWNSTREAM _u(0x31)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS_CONTESTED _u(0x32)
#define BUSCTRL_PERFSEL3_VALUE_SRAM1_ACCESS _u(0x33)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_UPSTREAM _u(0x34)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_STALL_DOWNSTREAM _u(0x35)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS_CONTESTED _u(0x36)
#define BUSCTRL_PERFSEL3_VALUE_SRAM0_ACCESS _u(0x37)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_UPSTREAM _u(0x38)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_STALL_DOWNSTREAM _u(0x39)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS_CONTESTED _u(0x3a)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN1_ACCESS _u(0x3b)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_UPSTREAM _u(0x3c)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_STALL_DOWNSTREAM _u(0x3d)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS_CONTESTED _u(0x3e)
#define BUSCTRL_PERFSEL3_VALUE_XIP_MAIN0_ACCESS _u(0x3f)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_UPSTREAM _u(0x40)
#define BUSCTRL_PERFSEL3_VALUE_ROM_STALL_DOWNSTREAM _u(0x41)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS_CONTESTED _u(0x42)
#define BUSCTRL_PERFSEL3_VALUE_ROM_ACCESS _u(0x43)
// =============================================================================
#endif // _HARDWARE_REGS_BUSCTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : CORESIGHT_TRACE
// Version : 1
// Bus type : ahbl
// Description : Coresight block - RP specific registers
// =============================================================================
#ifndef _HARDWARE_REGS_CORESIGHT_TRACE_H
#define _HARDWARE_REGS_CORESIGHT_TRACE_H
// =============================================================================
// Register : CORESIGHT_TRACE_CTRL_STATUS
// Description : Control and status register
#define CORESIGHT_TRACE_CTRL_STATUS_OFFSET _u(0x00000000)
#define CORESIGHT_TRACE_CTRL_STATUS_BITS _u(0x00000003)
#define CORESIGHT_TRACE_CTRL_STATUS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW
// Description : This status flag is set high when trace data has been dropped
// due to the FIFO being full at the point trace data was sampled.
// Write 1 to acknowledge and clear the bit.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_RESET _u(0x0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_BITS _u(0x00000002)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_MSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_LSB _u(1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_OVERFLOW_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH
// Description : Set to 1 to continuously hold the trace FIFO in a flushed state
// and prevent overflow.
//
// Before clearing this flag, configure and start a DMA channel
// with the correct DREQ for the TRACE_CAPTURE_FIFO register.
//
// Clear this flag to begin sampling trace data, and set once
// again once the trace capture buffer is full. You must configure
// the TPIU in order to generate trace packets to be captured, as
// well as components like the ETM further upstream to generate
// the event stream propagated to the TPIU.
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_RESET _u(0x1)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_BITS _u(0x00000001)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_MSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_LSB _u(0)
#define CORESIGHT_TRACE_CTRL_STATUS_TRACE_CAPTURE_FIFO_FLUSH_ACCESS "RW"
// =============================================================================
// Register : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO
// Description : FIFO for trace data captured from the TPIU
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET _u(0x00000004)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA
// Description : Read from an 8 x 32-bit FIFO containing trace data captured
// from the TPIU.
//
// Hardware pushes to the FIFO on rising edges of clk_sys, when
// either of the following is true:
//
// * TPIU TRACECTL output is low (normal trace data)
//
// * TPIU TRACETCL output is high, and TPIU TRACEDATA0 and
// TRACEDATA1 are both low (trigger packet)
//
// These conditions are in accordance with Arm Coresight
// Architecture Spec v3.0 section D3.3.3: Decoding requirements
// for Trace Capture Devices
//
// The data captured into the FIFO is the full 32-bit TRACEDATA
// bus output by the TPIU. Note that the TPIU is a DDR output at
// half of clk_sys, therefore this interface can capture the full
// 32-bit TPIU DDR output bandwidth as it samples once per active
// edge of the TPIU output clock.
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_RESET _u(0x00000000)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_BITS _u(0xffffffff)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_MSB _u(31)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_LSB _u(0)
#define CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_RDATA_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_CORESIGHT_TRACE_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _DREQ_H
#define _DREQ_H
/**
* \file rp2350/dreq.h
*/
#ifdef __ASSEMBLER__
#define DREQ_PIO0_TX0 0
#define DREQ_PIO0_TX1 1
#define DREQ_PIO0_TX2 2
#define DREQ_PIO0_TX3 3
#define DREQ_PIO0_RX0 4
#define DREQ_PIO0_RX1 5
#define DREQ_PIO0_RX2 6
#define DREQ_PIO0_RX3 7
#define DREQ_PIO1_TX0 8
#define DREQ_PIO1_TX1 9
#define DREQ_PIO1_TX2 10
#define DREQ_PIO1_TX3 11
#define DREQ_PIO1_RX0 12
#define DREQ_PIO1_RX1 13
#define DREQ_PIO1_RX2 14
#define DREQ_PIO1_RX3 15
#define DREQ_PIO2_TX0 16
#define DREQ_PIO2_TX1 17
#define DREQ_PIO2_TX2 18
#define DREQ_PIO2_TX3 19
#define DREQ_PIO2_RX0 20
#define DREQ_PIO2_RX1 21
#define DREQ_PIO2_RX2 22
#define DREQ_PIO2_RX3 23
#define DREQ_SPI0_TX 24
#define DREQ_SPI0_RX 25
#define DREQ_SPI1_TX 26
#define DREQ_SPI1_RX 27
#define DREQ_UART0_TX 28
#define DREQ_UART0_RX 29
#define DREQ_UART1_TX 30
#define DREQ_UART1_RX 31
#define DREQ_PWM_WRAP0 32
#define DREQ_PWM_WRAP1 33
#define DREQ_PWM_WRAP2 34
#define DREQ_PWM_WRAP3 35
#define DREQ_PWM_WRAP4 36
#define DREQ_PWM_WRAP5 37
#define DREQ_PWM_WRAP6 38
#define DREQ_PWM_WRAP7 39
#define DREQ_PWM_WRAP8 40
#define DREQ_PWM_WRAP9 41
#define DREQ_PWM_WRAP10 42
#define DREQ_PWM_WRAP11 43
#define DREQ_I2C0_TX 44
#define DREQ_I2C0_RX 45
#define DREQ_I2C1_TX 46
#define DREQ_I2C1_RX 47
#define DREQ_ADC 48
#define DREQ_XIP_STREAM 49
#define DREQ_XIP_QMITX 50
#define DREQ_XIP_QMIRX 51
#define DREQ_HSTX 52
#define DREQ_CORESIGHT 53
#define DREQ_SHA256 54
#define DREQ_DMA_TIMER0 59
#define DREQ_DMA_TIMER1 60
#define DREQ_DMA_TIMER2 61
#define DREQ_DMA_TIMER3 62
#define DREQ_FORCE 63
#else
/**
* \brief DREQ numbers for DMA pacing on RP2350 (used as typedef \ref dreq_num_t)
* \ingroup hardware_dma
*/
typedef enum dreq_num_rp2350 {
DREQ_PIO0_TX0 = 0, ///< Select PIO0's TX FIFO 0 as DREQ
DREQ_PIO0_TX1 = 1, ///< Select PIO0's TX FIFO 1 as DREQ
DREQ_PIO0_TX2 = 2, ///< Select PIO0's TX FIFO 2 as DREQ
DREQ_PIO0_TX3 = 3, ///< Select PIO0's TX FIFO 3 as DREQ
DREQ_PIO0_RX0 = 4, ///< Select PIO0's RX FIFO 0 as DREQ
DREQ_PIO0_RX1 = 5, ///< Select PIO0's RX FIFO 1 as DREQ
DREQ_PIO0_RX2 = 6, ///< Select PIO0's RX FIFO 2 as DREQ
DREQ_PIO0_RX3 = 7, ///< Select PIO0's RX FIFO 3 as DREQ
DREQ_PIO1_TX0 = 8, ///< Select PIO1's TX FIFO 0 as DREQ
DREQ_PIO1_TX1 = 9, ///< Select PIO1's TX FIFO 1 as DREQ
DREQ_PIO1_TX2 = 10, ///< Select PIO1's TX FIFO 2 as DREQ
DREQ_PIO1_TX3 = 11, ///< Select PIO1's TX FIFO 3 as DREQ
DREQ_PIO1_RX0 = 12, ///< Select PIO1's RX FIFO 0 as DREQ
DREQ_PIO1_RX1 = 13, ///< Select PIO1's RX FIFO 1 as DREQ
DREQ_PIO1_RX2 = 14, ///< Select PIO1's RX FIFO 2 as DREQ
DREQ_PIO1_RX3 = 15, ///< Select PIO1's RX FIFO 3 as DREQ
DREQ_PIO2_TX0 = 16, ///< Select PIO2's TX FIFO 0 as DREQ
DREQ_PIO2_TX1 = 17, ///< Select PIO2's TX FIFO 1 as DREQ
DREQ_PIO2_TX2 = 18, ///< Select PIO2's TX FIFO 2 as DREQ
DREQ_PIO2_TX3 = 19, ///< Select PIO2's TX FIFO 3 as DREQ
DREQ_PIO2_RX0 = 20, ///< Select PIO2's RX FIFO 0 as DREQ
DREQ_PIO2_RX1 = 21, ///< Select PIO2's RX FIFO 1 as DREQ
DREQ_PIO2_RX2 = 22, ///< Select PIO2's RX FIFO 2 as DREQ
DREQ_PIO2_RX3 = 23, ///< Select PIO2's RX FIFO 3 as DREQ
DREQ_SPI0_TX = 24, ///< Select SPI0's TX FIFO as DREQ
DREQ_SPI0_RX = 25, ///< Select SPI0's RX FIFO as DREQ
DREQ_SPI1_TX = 26, ///< Select SPI1's TX FIFO as DREQ
DREQ_SPI1_RX = 27, ///< Select SPI1's RX FIFO as DREQ
DREQ_UART0_TX = 28, ///< Select UART0's TX FIFO as DREQ
DREQ_UART0_RX = 29, ///< Select UART0's RX FIFO as DREQ
DREQ_UART1_TX = 30, ///< Select UART1's TX FIFO as DREQ
DREQ_UART1_RX = 31, ///< Select UART1's RX FIFO as DREQ
DREQ_PWM_WRAP0 = 32, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP1 = 33, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_PWM_WRAP2 = 34, ///< Select PWM Counter 2's Wrap Value as DREQ
DREQ_PWM_WRAP3 = 35, ///< Select PWM Counter 3's Wrap Value as DREQ
DREQ_PWM_WRAP4 = 36, ///< Select PWM Counter 4's Wrap Value as DREQ
DREQ_PWM_WRAP5 = 37, ///< Select PWM Counter 5's Wrap Value as DREQ
DREQ_PWM_WRAP6 = 38, ///< Select PWM Counter 6's Wrap Value as DREQ
DREQ_PWM_WRAP7 = 39, ///< Select PWM Counter 7's Wrap Value as DREQ
DREQ_PWM_WRAP8 = 40, ///< Select PWM Counter 8's Wrap Value as DREQ
DREQ_PWM_WRAP9 = 41, ///< Select PWM Counter 9's Wrap Value as DREQ
DREQ_PWM_WRAP10 = 42, ///< Select PWM Counter 0's Wrap Value as DREQ
DREQ_PWM_WRAP11 = 43, ///< Select PWM Counter 1's Wrap Value as DREQ
DREQ_I2C0_TX = 44, ///< Select I2C0's TX FIFO as DREQ
DREQ_I2C0_RX = 45, ///< Select I2C0's RX FIFO as DREQ
DREQ_I2C1_TX = 46, ///< Select I2C1's TX FIFO as DREQ
DREQ_I2C1_RX = 47, ///< Select I2C1's RX FIFO as DREQ
DREQ_ADC = 48, ///< Select the ADC as DREQ
DREQ_XIP_STREAM = 49, ///< Select the XIP Streaming FIFO as DREQ
DREQ_XIP_QMITX = 50, ///< Select XIP_QMITX as DREQ
DREQ_XIP_QMIRX = 51, ///< Select XIP_QMIRX as DREQ
DREQ_HSTX = 52, ///< Select HSTX as DREQ
DREQ_CORESIGHT = 53, ///< Select CORESIGHT as DREQ
DREQ_SHA256 = 54, ///< Select SHA256 as DREQ
DREQ_DMA_TIMER0 = 59, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER1 = 60, ///< Select DMA_TIMER0 as DREQ
DREQ_DMA_TIMER2 = 61, ///< Select DMA_TIMER1 as DREQ
DREQ_DMA_TIMER3 = 62, ///< Select DMA_TIMER3 as DREQ
DREQ_FORCE = 63, ///< Select FORCE as DREQ
DREQ_COUNT
} dreq_num_t;
#endif
#endif // _DREQ_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : GLITCH_DETECTOR
// Version : 1
// Bus type : apb
// Description : Glitch detector controls
// =============================================================================
#ifndef _HARDWARE_REGS_GLITCH_DETECTOR_H
#define _HARDWARE_REGS_GLITCH_DETECTOR_H
// =============================================================================
// Register : GLITCH_DETECTOR_ARM
// Description : Forcibly arm the glitch detectors, if they are not already
// armed by OTP. When armed, any individual detector trigger will
// cause a restart of the switched core power domain's power-on
// reset state machine.
//
// Glitch detector triggers are recorded accumulatively in
// TRIG_STATUS. If the system is reset by a glitch detector
// trigger, this is recorded in POWMAN_CHIP_RESET.
//
// This register is Secure read/write only.
// 0x5bad -> Do not force the glitch detectors to be armed
// 0x0000 -> Force the glitch detectors to be armed. (Any value other than ARM_NO counts as YES)
#define GLITCH_DETECTOR_ARM_OFFSET _u(0x00000000)
#define GLITCH_DETECTOR_ARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_ARM_RESET _u(0x00005bad)
#define GLITCH_DETECTOR_ARM_MSB _u(15)
#define GLITCH_DETECTOR_ARM_LSB _u(0)
#define GLITCH_DETECTOR_ARM_ACCESS "RW"
#define GLITCH_DETECTOR_ARM_VALUE_NO _u(0x5bad)
#define GLITCH_DETECTOR_ARM_VALUE_YES _u(0x0000)
// =============================================================================
// Register : GLITCH_DETECTOR_DISARM
// Description : None
// Forcibly disarm the glitch detectors, if they are armed by OTP.
// Ignored if ARM is YES.
//
// This register is Secure read/write only.
// 0x0000 -> Do not disarm the glitch detectors. (Any value other than DISARM_YES counts as NO)
// 0xdcaf -> Disarm the glitch detectors
#define GLITCH_DETECTOR_DISARM_OFFSET _u(0x00000004)
#define GLITCH_DETECTOR_DISARM_BITS _u(0x0000ffff)
#define GLITCH_DETECTOR_DISARM_RESET _u(0x00000000)
#define GLITCH_DETECTOR_DISARM_MSB _u(15)
#define GLITCH_DETECTOR_DISARM_LSB _u(0)
#define GLITCH_DETECTOR_DISARM_ACCESS "RW"
#define GLITCH_DETECTOR_DISARM_VALUE_NO _u(0x0000)
#define GLITCH_DETECTOR_DISARM_VALUE_YES _u(0xdcaf)
// =============================================================================
// Register : GLITCH_DETECTOR_SENSITIVITY
// Description : Adjust the sensitivity of glitch detectors to values other than
// their OTP-provided defaults.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_SENSITIVITY_OFFSET _u(0x00000008)
#define GLITCH_DETECTOR_SENSITIVITY_BITS _u(0xff00ffff)
#define GLITCH_DETECTOR_SENSITIVITY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DEFAULT
// 0x00 -> Use the default sensitivity configured in OTP for all detectors. (Any value other than DEFAULT_NO counts as YES)
// 0xde -> Do not use the default sensitivity configured in OTP. Instead use the value from this register.
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_RESET _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_BITS _u(0xff000000)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_MSB _u(31)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_LSB _u(24)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_ACCESS "RW"
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_YES _u(0x00)
#define GLITCH_DETECTOR_SENSITIVITY_DEFAULT_VALUE_NO _u(0xde)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3_INV
// Description : Must be the inverse of DET3, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_BITS _u(0x0000c000)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_MSB _u(15)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_LSB _u(14)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2_INV
// Description : Must be the inverse of DET2, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_BITS _u(0x00003000)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_MSB _u(13)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_LSB _u(12)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1_INV
// Description : Must be the inverse of DET1, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_BITS _u(0x00000c00)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_MSB _u(11)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_LSB _u(10)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0_INV
// Description : Must be the inverse of DET0, else the default value is used.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_BITS _u(0x00000300)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_MSB _u(9)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_LSB _u(8)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET3
// Description : Set sensitivity for detector 3. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_BITS _u(0x000000c0)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_MSB _u(7)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_LSB _u(6)
#define GLITCH_DETECTOR_SENSITIVITY_DET3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET2
// Description : Set sensitivity for detector 2. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_BITS _u(0x00000030)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_MSB _u(5)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_LSB _u(4)
#define GLITCH_DETECTOR_SENSITIVITY_DET2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET1
// Description : Set sensitivity for detector 1. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_BITS _u(0x0000000c)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_MSB _u(3)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_LSB _u(2)
#define GLITCH_DETECTOR_SENSITIVITY_DET1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_SENSITIVITY_DET0
// Description : Set sensitivity for detector 0. Higher values are more
// sensitive.
#define GLITCH_DETECTOR_SENSITIVITY_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_BITS _u(0x00000003)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_MSB _u(1)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_LSB _u(0)
#define GLITCH_DETECTOR_SENSITIVITY_DET0_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_LOCK
// Description : None
// Write any nonzero value to disable writes to ARM, DISARM,
// SENSITIVITY and LOCK. This register is Secure read/write only.
#define GLITCH_DETECTOR_LOCK_OFFSET _u(0x0000000c)
#define GLITCH_DETECTOR_LOCK_BITS _u(0x000000ff)
#define GLITCH_DETECTOR_LOCK_RESET _u(0x00000000)
#define GLITCH_DETECTOR_LOCK_MSB _u(7)
#define GLITCH_DETECTOR_LOCK_LSB _u(0)
#define GLITCH_DETECTOR_LOCK_ACCESS "RW"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_STATUS
// Description : Set when a detector output triggers. Write-1-clear.
//
// (May immediately return high if the detector remains in a
// failed state. Detectors can only be cleared by a full reset of
// the switched core power domain.)
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_STATUS_OFFSET _u(0x00000010)
#define GLITCH_DETECTOR_TRIG_STATUS_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET3
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_BITS _u(0x00000008)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_LSB _u(3)
#define GLITCH_DETECTOR_TRIG_STATUS_DET3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET2
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_BITS _u(0x00000004)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_MSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_LSB _u(2)
#define GLITCH_DETECTOR_TRIG_STATUS_DET2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET1
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_BITS _u(0x00000002)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_MSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_LSB _u(1)
#define GLITCH_DETECTOR_TRIG_STATUS_DET1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : GLITCH_DETECTOR_TRIG_STATUS_DET0
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_RESET _u(0x0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_BITS _u(0x00000001)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_MSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_STATUS_DET0_ACCESS "WC"
// =============================================================================
// Register : GLITCH_DETECTOR_TRIG_FORCE
// Description : Simulate the firing of one or more detectors. Writing ones to
// this register will set the matching bits in STATUS_TRIG.
//
// If the glitch detectors are currently armed, writing ones will
// also immediately reset the switched core power domain, and set
// the reset reason latches in POWMAN_CHIP_RESET to indicate a
// glitch detector resets.
//
// This register is Secure read/write only.
#define GLITCH_DETECTOR_TRIG_FORCE_OFFSET _u(0x00000014)
#define GLITCH_DETECTOR_TRIG_FORCE_BITS _u(0x0000000f)
#define GLITCH_DETECTOR_TRIG_FORCE_RESET _u(0x00000000)
#define GLITCH_DETECTOR_TRIG_FORCE_MSB _u(3)
#define GLITCH_DETECTOR_TRIG_FORCE_LSB _u(0)
#define GLITCH_DETECTOR_TRIG_FORCE_ACCESS "SC"
// =============================================================================
#endif // _HARDWARE_REGS_GLITCH_DETECTOR_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_CTRL
// Version : 0
// Bus type : apb
// Description : Control interface to HSTX. For FIFO write access and status,
// see the HSTX_FIFO register block.
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_CTRL_H
#define _HARDWARE_REGS_HSTX_CTRL_H
// =============================================================================
// Register : HSTX_CTRL_CSR
#define HSTX_CTRL_CSR_OFFSET _u(0x00000000)
#define HSTX_CTRL_CSR_BITS _u(0xff1f1f73)
#define HSTX_CTRL_CSR_RESET _u(0x10050600)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKDIV
// Description : Clock period of the generated clock, measured in HSTX clock
// cycles. Can be odd or even. The generated clock advances only
// on cycles where the shift register shifts.
//
// For example, a clkdiv of 5 would generate a complete output
// clock period for every 5 HSTX clocks (or every 10 half-clocks).
//
// A CLKDIV value of 0 is mapped to a period of 16 HSTX clock
// cycles.
#define HSTX_CTRL_CSR_CLKDIV_RESET _u(0x1)
#define HSTX_CTRL_CSR_CLKDIV_BITS _u(0xf0000000)
#define HSTX_CTRL_CSR_CLKDIV_MSB _u(31)
#define HSTX_CTRL_CSR_CLKDIV_LSB _u(28)
#define HSTX_CTRL_CSR_CLKDIV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_CLKPHASE
// Description : Set the initial phase of the generated clock.
//
// A CLKPHASE of 0 means the clock is initially low, and the first
// rising edge occurs after one half period of the generated clock
// (i.e. CLKDIV/2 cycles of clk_hstx). Incrementing CLKPHASE by 1
// will advance the initial clock phase by one half clk_hstx
// period. For example, if CLKDIV=2 and CLKPHASE=1:
//
// * The clock will be initially low
//
// * The first rising edge will be 0.5 clk_hstx cycles after
// asserting first data
//
// * The first falling edge will be 1.5 clk_hstx cycles after
// asserting first data
//
// This configuration would be suitable for serialising at a bit
// rate of clk_hstx with a centre-aligned DDR clock.
//
// When the HSTX is halted by clearing CSR_EN, the clock generator
// will return to its initial phase as configured by the CLKPHASE
// field.
//
// Note CLKPHASE must be strictly less than double the value of
// CLKDIV (one full period), else its operation is undefined.
#define HSTX_CTRL_CSR_CLKPHASE_RESET _u(0x0)
#define HSTX_CTRL_CSR_CLKPHASE_BITS _u(0x0f000000)
#define HSTX_CTRL_CSR_CLKPHASE_MSB _u(27)
#define HSTX_CTRL_CSR_CLKPHASE_LSB _u(24)
#define HSTX_CTRL_CSR_CLKPHASE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_N_SHIFTS
// Description : Number of times to shift the shift register before refilling it
// from the FIFO. (A count of how many times it has been shifted,
// *not* the total shift distance.)
//
// A register value of 0 means shift 32 times.
#define HSTX_CTRL_CSR_N_SHIFTS_RESET _u(0x05)
#define HSTX_CTRL_CSR_N_SHIFTS_BITS _u(0x001f0000)
#define HSTX_CTRL_CSR_N_SHIFTS_MSB _u(20)
#define HSTX_CTRL_CSR_N_SHIFTS_LSB _u(16)
#define HSTX_CTRL_CSR_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_SHIFT
// Description : How many bits to right-rotate the shift register by each cycle.
//
// The use of a rotate rather than a shift allows left shifts to
// be emulated, by subtracting the left-shift amount from 32. It
// also allows data to be repeated, when the product of SHIFT and
// N_SHIFTS is greater than 32.
#define HSTX_CTRL_CSR_SHIFT_RESET _u(0x06)
#define HSTX_CTRL_CSR_SHIFT_BITS _u(0x00001f00)
#define HSTX_CTRL_CSR_SHIFT_MSB _u(12)
#define HSTX_CTRL_CSR_SHIFT_LSB _u(8)
#define HSTX_CTRL_CSR_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_SEL
// Description : Select which PIO to use for coupled mode operation.
#define HSTX_CTRL_CSR_COUPLED_SEL_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_SEL_BITS _u(0x00000060)
#define HSTX_CTRL_CSR_COUPLED_SEL_MSB _u(6)
#define HSTX_CTRL_CSR_COUPLED_SEL_LSB _u(5)
#define HSTX_CTRL_CSR_COUPLED_SEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_COUPLED_MODE
// Description : Enable the PIO-to-HSTX 1:1 connection. The HSTX must be clocked
// *directly* from the system clock (not just from some other
// clock source of the same frequency) for this synchronous
// interface to function correctly.
//
// When COUPLED_MODE is set, BITx_SEL_P and SEL_N indices 24
// through 31 will select bits from the 8-bit PIO-to-HSTX path,
// rather than shifter bits. Indices of 0 through 23 will still
// index the shift register as normal.
//
// The PIO outputs connected to the PIO-to-HSTX bus are those same
// outputs that would appear on the HSTX-capable pins if those
// pins' FUNCSELs were set to PIO instead of HSTX.
//
// For example, if HSTX is on GPIOs 12 through 19, then PIO
// outputs 12 through 19 are connected to the HSTX when coupled
// mode is engaged.
#define HSTX_CTRL_CSR_COUPLED_MODE_RESET _u(0x0)
#define HSTX_CTRL_CSR_COUPLED_MODE_BITS _u(0x00000010)
#define HSTX_CTRL_CSR_COUPLED_MODE_MSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_LSB _u(4)
#define HSTX_CTRL_CSR_COUPLED_MODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EXPAND_EN
// Description : Enable the command expander. When 0, raw FIFO data is passed
// directly to the output shift register. When 1, the command
// expander can perform simple operations such as run length
// decoding on data between the FIFO and the shift register.
//
// Do not change CXPD_EN whilst EN is set. It's safe to set
// CXPD_EN simultaneously with setting EN.
#define HSTX_CTRL_CSR_EXPAND_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EXPAND_EN_BITS _u(0x00000002)
#define HSTX_CTRL_CSR_EXPAND_EN_MSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_LSB _u(1)
#define HSTX_CTRL_CSR_EXPAND_EN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_CSR_EN
// Description : When EN is 1, the HSTX will shift out data as it appears in the
// FIFO. As long as there is data, the HSTX shift register will
// shift once per clock cycle, and the frequency of popping from
// the FIFO is determined by the ratio of SHIFT and SHIFT_THRESH.
//
// When EN is 0, the FIFO is not popped. The shift counter and
// clock generator are also reset to their initial state for as
// long as EN is low. Note the initial phase of the clock
// generator can be configured by the CLKPHASE field.
//
// Once the HSTX is enabled again, and data is pushed to the FIFO,
// the generated clock's first rising edge will be one half-period
// after the first data is launched.
#define HSTX_CTRL_CSR_EN_RESET _u(0x0)
#define HSTX_CTRL_CSR_EN_BITS _u(0x00000001)
#define HSTX_CTRL_CSR_EN_MSB _u(0)
#define HSTX_CTRL_CSR_EN_LSB _u(0)
#define HSTX_CTRL_CSR_EN_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT0
// Description : Data control register for output bit 0
#define HSTX_CTRL_BIT0_OFFSET _u(0x00000004)
#define HSTX_CTRL_BIT0_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT0_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT0_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT0_CLK_MSB _u(17)
#define HSTX_CTRL_BIT0_CLK_LSB _u(17)
#define HSTX_CTRL_BIT0_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT0_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT0_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT0_INV_MSB _u(16)
#define HSTX_CTRL_BIT0_INV_LSB _u(16)
#define HSTX_CTRL_BIT0_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT0_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT0_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT0_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT0_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT0_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT0_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT0_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT0_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT0_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT1
// Description : Data control register for output bit 1
#define HSTX_CTRL_BIT1_OFFSET _u(0x00000008)
#define HSTX_CTRL_BIT1_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT1_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT1_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT1_CLK_MSB _u(17)
#define HSTX_CTRL_BIT1_CLK_LSB _u(17)
#define HSTX_CTRL_BIT1_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT1_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT1_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT1_INV_MSB _u(16)
#define HSTX_CTRL_BIT1_INV_LSB _u(16)
#define HSTX_CTRL_BIT1_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT1_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT1_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT1_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT1_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT1_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT1_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT1_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT1_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT1_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT2
// Description : Data control register for output bit 2
#define HSTX_CTRL_BIT2_OFFSET _u(0x0000000c)
#define HSTX_CTRL_BIT2_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT2_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT2_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT2_CLK_MSB _u(17)
#define HSTX_CTRL_BIT2_CLK_LSB _u(17)
#define HSTX_CTRL_BIT2_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT2_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT2_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT2_INV_MSB _u(16)
#define HSTX_CTRL_BIT2_INV_LSB _u(16)
#define HSTX_CTRL_BIT2_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT2_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT2_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT2_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT2_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT2_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT2_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT2_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT2_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT2_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT3
// Description : Data control register for output bit 3
#define HSTX_CTRL_BIT3_OFFSET _u(0x00000010)
#define HSTX_CTRL_BIT3_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT3_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT3_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT3_CLK_MSB _u(17)
#define HSTX_CTRL_BIT3_CLK_LSB _u(17)
#define HSTX_CTRL_BIT3_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT3_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT3_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT3_INV_MSB _u(16)
#define HSTX_CTRL_BIT3_INV_LSB _u(16)
#define HSTX_CTRL_BIT3_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT3_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT3_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT3_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT3_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT3_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT3_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT3_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT3_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT3_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT4
// Description : Data control register for output bit 4
#define HSTX_CTRL_BIT4_OFFSET _u(0x00000014)
#define HSTX_CTRL_BIT4_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT4_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT4_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT4_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT4_CLK_MSB _u(17)
#define HSTX_CTRL_BIT4_CLK_LSB _u(17)
#define HSTX_CTRL_BIT4_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT4_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT4_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT4_INV_MSB _u(16)
#define HSTX_CTRL_BIT4_INV_LSB _u(16)
#define HSTX_CTRL_BIT4_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT4_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT4_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT4_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT4_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT4_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT4_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT4_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT4_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT4_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT5
// Description : Data control register for output bit 5
#define HSTX_CTRL_BIT5_OFFSET _u(0x00000018)
#define HSTX_CTRL_BIT5_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT5_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT5_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT5_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT5_CLK_MSB _u(17)
#define HSTX_CTRL_BIT5_CLK_LSB _u(17)
#define HSTX_CTRL_BIT5_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT5_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT5_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT5_INV_MSB _u(16)
#define HSTX_CTRL_BIT5_INV_LSB _u(16)
#define HSTX_CTRL_BIT5_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT5_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT5_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT5_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT5_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT5_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT5_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT5_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT5_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT5_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT6
// Description : Data control register for output bit 6
#define HSTX_CTRL_BIT6_OFFSET _u(0x0000001c)
#define HSTX_CTRL_BIT6_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT6_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT6_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT6_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT6_CLK_MSB _u(17)
#define HSTX_CTRL_BIT6_CLK_LSB _u(17)
#define HSTX_CTRL_BIT6_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT6_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT6_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT6_INV_MSB _u(16)
#define HSTX_CTRL_BIT6_INV_LSB _u(16)
#define HSTX_CTRL_BIT6_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT6_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT6_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT6_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT6_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT6_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT6_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT6_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT6_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT6_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_BIT7
// Description : Data control register for output bit 7
#define HSTX_CTRL_BIT7_OFFSET _u(0x00000020)
#define HSTX_CTRL_BIT7_BITS _u(0x00031f1f)
#define HSTX_CTRL_BIT7_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_CLK
// Description : Connect this output to the generated clock, rather than the
// data shift register. SEL_P and SEL_N are ignored if this bit is
// set, but INV can still be set to generate an antiphase clock.
#define HSTX_CTRL_BIT7_CLK_RESET _u(0x0)
#define HSTX_CTRL_BIT7_CLK_BITS _u(0x00020000)
#define HSTX_CTRL_BIT7_CLK_MSB _u(17)
#define HSTX_CTRL_BIT7_CLK_LSB _u(17)
#define HSTX_CTRL_BIT7_CLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_INV
// Description : Invert this data output (logical NOT)
#define HSTX_CTRL_BIT7_INV_RESET _u(0x0)
#define HSTX_CTRL_BIT7_INV_BITS _u(0x00010000)
#define HSTX_CTRL_BIT7_INV_MSB _u(16)
#define HSTX_CTRL_BIT7_INV_LSB _u(16)
#define HSTX_CTRL_BIT7_INV_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_N
// Description : Shift register data bit select for the second half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_N_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_N_BITS _u(0x00001f00)
#define HSTX_CTRL_BIT7_SEL_N_MSB _u(12)
#define HSTX_CTRL_BIT7_SEL_N_LSB _u(8)
#define HSTX_CTRL_BIT7_SEL_N_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_BIT7_SEL_P
// Description : Shift register data bit select for the first half of the HSTX
// clock cycle
#define HSTX_CTRL_BIT7_SEL_P_RESET _u(0x00)
#define HSTX_CTRL_BIT7_SEL_P_BITS _u(0x0000001f)
#define HSTX_CTRL_BIT7_SEL_P_MSB _u(4)
#define HSTX_CTRL_BIT7_SEL_P_LSB _u(0)
#define HSTX_CTRL_BIT7_SEL_P_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_SHIFT
// Description : Configure the optional shifter inside the command expander
#define HSTX_CTRL_EXPAND_SHIFT_OFFSET _u(0x00000024)
#define HSTX_CTRL_EXPAND_SHIFT_BITS _u(0x1f1f1f1f)
#define HSTX_CTRL_EXPAND_SHIFT_RESET _u(0x01000100)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is an
// encoded data command (e.g. TMDS). A register value of 0 means
// shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_BITS _u(0x1f000000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_MSB _u(28)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_LSB _u(24)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is an encoded data command (e.g. TMDS).
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_MSB _u(20)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_LSB _u(16)
#define HSTX_CTRL_EXPAND_SHIFT_ENC_SHIFT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS
// Description : Number of times to consume from the shift register before
// refilling it from the FIFO, when the current command is a raw
// data command. A register value of 0 means shift 32 times.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_RESET _u(0x01)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_MSB _u(12)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_LSB _u(8)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_N_SHIFTS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT
// Description : How many bits to right-rotate the shift register by each time
// data is pushed to the output shifter, when the current command
// is a raw data command.
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_MSB _u(4)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_LSB _u(0)
#define HSTX_CTRL_EXPAND_SHIFT_RAW_SHIFT_ACCESS "RW"
// =============================================================================
// Register : HSTX_CTRL_EXPAND_TMDS
// Description : Configure the optional TMDS encoder inside the command expander
#define HSTX_CTRL_EXPAND_TMDS_OFFSET _u(0x00000028)
#define HSTX_CTRL_EXPAND_TMDS_BITS _u(0x00ffffff)
#define HSTX_CTRL_EXPAND_TMDS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_NBITS
// Description : Number of valid data bits for the lane 2 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_BITS _u(0x00e00000)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_MSB _u(23)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_LSB _u(21)
#define HSTX_CTRL_EXPAND_TMDS_L2_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L2_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 2 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_BITS _u(0x001f0000)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_MSB _u(20)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_LSB _u(16)
#define HSTX_CTRL_EXPAND_TMDS_L2_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_NBITS
// Description : Number of valid data bits for the lane 1 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_BITS _u(0x0000e000)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_MSB _u(15)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_LSB _u(13)
#define HSTX_CTRL_EXPAND_TMDS_L1_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L1_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 1 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_BITS _u(0x00001f00)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_MSB _u(12)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_LSB _u(8)
#define HSTX_CTRL_EXPAND_TMDS_L1_ROT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_NBITS
// Description : Number of valid data bits for the lane 0 TMDS encoder, starting
// from bit 7 of the rotated data. Field values of 0 -> 7 encode
// counts of 1 -> 8 bits.
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_RESET _u(0x0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_BITS _u(0x000000e0)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_MSB _u(7)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_LSB _u(5)
#define HSTX_CTRL_EXPAND_TMDS_L0_NBITS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : HSTX_CTRL_EXPAND_TMDS_L0_ROT
// Description : Right-rotate applied to the current shifter data before the
// lane 0 TMDS encoder.
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_RESET _u(0x00)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_BITS _u(0x0000001f)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_MSB _u(4)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_LSB _u(0)
#define HSTX_CTRL_EXPAND_TMDS_L0_ROT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_CTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : HSTX_FIFO
// Version : 1
// Bus type : ahbl
// Description : FIFO status and write access for HSTX
// =============================================================================
#ifndef _HARDWARE_REGS_HSTX_FIFO_H
#define _HARDWARE_REGS_HSTX_FIFO_H
// =============================================================================
// Register : HSTX_FIFO_STAT
// Description : FIFO status
#define HSTX_FIFO_STAT_OFFSET _u(0x00000000)
#define HSTX_FIFO_STAT_BITS _u(0x000007ff)
#define HSTX_FIFO_STAT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_WOF
// Description : FIFO was written when full. Write 1 to clear.
#define HSTX_FIFO_STAT_WOF_RESET _u(0x0)
#define HSTX_FIFO_STAT_WOF_BITS _u(0x00000400)
#define HSTX_FIFO_STAT_WOF_MSB _u(10)
#define HSTX_FIFO_STAT_WOF_LSB _u(10)
#define HSTX_FIFO_STAT_WOF_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_EMPTY
#define HSTX_FIFO_STAT_EMPTY_RESET "-"
#define HSTX_FIFO_STAT_EMPTY_BITS _u(0x00000200)
#define HSTX_FIFO_STAT_EMPTY_MSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_LSB _u(9)
#define HSTX_FIFO_STAT_EMPTY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_FULL
#define HSTX_FIFO_STAT_FULL_RESET "-"
#define HSTX_FIFO_STAT_FULL_BITS _u(0x00000100)
#define HSTX_FIFO_STAT_FULL_MSB _u(8)
#define HSTX_FIFO_STAT_FULL_LSB _u(8)
#define HSTX_FIFO_STAT_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : HSTX_FIFO_STAT_LEVEL
#define HSTX_FIFO_STAT_LEVEL_RESET _u(0x00)
#define HSTX_FIFO_STAT_LEVEL_BITS _u(0x000000ff)
#define HSTX_FIFO_STAT_LEVEL_MSB _u(7)
#define HSTX_FIFO_STAT_LEVEL_LSB _u(0)
#define HSTX_FIFO_STAT_LEVEL_ACCESS "RO"
// =============================================================================
// Register : HSTX_FIFO_FIFO
// Description : Write access to FIFO
#define HSTX_FIFO_FIFO_OFFSET _u(0x00000004)
#define HSTX_FIFO_FIFO_BITS _u(0xffffffff)
#define HSTX_FIFO_FIFO_RESET _u(0x00000000)
#define HSTX_FIFO_FIFO_MSB _u(31)
#define HSTX_FIFO_FIFO_LSB _u(0)
#define HSTX_FIFO_FIFO_ACCESS "WF"
// =============================================================================
#endif // _HARDWARE_REGS_HSTX_FIFO_H

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lib/pico-sdk/rp2350/hardware/regs/intctrl.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _INTCTRL_H
#define _INTCTRL_H
/**
* \file rp2350/intctrl.h
*/
#ifdef __ASSEMBLER__
#define TIMER0_IRQ_0 0
#define TIMER0_IRQ_1 1
#define TIMER0_IRQ_2 2
#define TIMER0_IRQ_3 3
#define TIMER1_IRQ_0 4
#define TIMER1_IRQ_1 5
#define TIMER1_IRQ_2 6
#define TIMER1_IRQ_3 7
#define PWM_IRQ_WRAP_0 8
#define PWM_IRQ_WRAP_1 9
#define DMA_IRQ_0 10
#define DMA_IRQ_1 11
#define DMA_IRQ_2 12
#define DMA_IRQ_3 13
#define USBCTRL_IRQ 14
#define PIO0_IRQ_0 15
#define PIO0_IRQ_1 16
#define PIO1_IRQ_0 17
#define PIO1_IRQ_1 18
#define PIO2_IRQ_0 19
#define PIO2_IRQ_1 20
#define IO_IRQ_BANK0 21
#define IO_IRQ_BANK0_NS 22
#define IO_IRQ_QSPI 23
#define IO_IRQ_QSPI_NS 24
#define SIO_IRQ_FIFO 25
#define SIO_IRQ_BELL 26
#define SIO_IRQ_FIFO_NS 27
#define SIO_IRQ_BELL_NS 28
#define SIO_IRQ_MTIMECMP 29
#define CLOCKS_IRQ 30
#define SPI0_IRQ 31
#define SPI1_IRQ 32
#define UART0_IRQ 33
#define UART1_IRQ 34
#define ADC_IRQ_FIFO 35
#define I2C0_IRQ 36
#define I2C1_IRQ 37
#define OTP_IRQ 38
#define TRNG_IRQ 39
#define PROC0_IRQ_CTI 40
#define PROC1_IRQ_CTI 41
#define PLL_SYS_IRQ 42
#define PLL_USB_IRQ 43
#define POWMAN_IRQ_POW 44
#define POWMAN_IRQ_TIMER 45
#define SPAREIRQ_IRQ_0 46
#define SPAREIRQ_IRQ_1 47
#define SPAREIRQ_IRQ_2 48
#define SPAREIRQ_IRQ_3 49
#define SPAREIRQ_IRQ_4 50
#define SPAREIRQ_IRQ_5 51
#else
/**
* \brief Interrupt numbers on RP2350 (used as typedef \ref irq_num_t)
* \ingroup hardware_irq
*/
typedef enum irq_num_rp2350 {
TIMER0_IRQ_0 = 0, ///< Select TIMER0's IRQ 0 output
TIMER0_IRQ_1 = 1, ///< Select TIMER0's IRQ 1 output
TIMER0_IRQ_2 = 2, ///< Select TIMER0's IRQ 2 output
TIMER0_IRQ_3 = 3, ///< Select TIMER0's IRQ 3 output
TIMER1_IRQ_0 = 4, ///< Select TIMER1's IRQ 0 output
TIMER1_IRQ_1 = 5, ///< Select TIMER1's IRQ 1 output
TIMER1_IRQ_2 = 6, ///< Select TIMER1's IRQ 2 output
TIMER1_IRQ_3 = 7, ///< Select TIMER1's IRQ 3 output
PWM_IRQ_WRAP_0 = 8, ///< Select PWM's IRQ_WRAP 0 output
PWM_IRQ_WRAP_1 = 9, ///< Select PWM's IRQ_WRAP 1 output
DMA_IRQ_0 = 10, ///< Select DMA's IRQ 0 output
DMA_IRQ_1 = 11, ///< Select DMA's IRQ 1 output
DMA_IRQ_2 = 12, ///< Select DMA's IRQ 2 output
DMA_IRQ_3 = 13, ///< Select DMA's IRQ 3 output
USBCTRL_IRQ = 14, ///< Select USBCTRL's IRQ output
PIO0_IRQ_0 = 15, ///< Select PIO0's IRQ 0 output
PIO0_IRQ_1 = 16, ///< Select PIO0's IRQ 1 output
PIO1_IRQ_0 = 17, ///< Select PIO1's IRQ 0 output
PIO1_IRQ_1 = 18, ///< Select PIO1's IRQ 1 output
PIO2_IRQ_0 = 19, ///< Select PIO2's IRQ 0 output
PIO2_IRQ_1 = 20, ///< Select PIO2's IRQ 1 output
IO_IRQ_BANK0 = 21, ///< Select IO_BANK0's IRQ output
IO_IRQ_BANK0_NS = 22, ///< Select IO_BANK0_NS's IRQ output
IO_IRQ_QSPI = 23, ///< Select IO_QSPI's IRQ output
IO_IRQ_QSPI_NS = 24, ///< Select IO_QSPI_NS's IRQ output
SIO_IRQ_FIFO = 25, ///< Select SIO's IRQ_FIFO output
SIO_IRQ_BELL = 26, ///< Select SIO's IRQ_BELL output
SIO_IRQ_FIFO_NS = 27, ///< Select SIO_NS's IRQ_FIFO output
SIO_IRQ_BELL_NS = 28, ///< Select SIO_NS's IRQ_BELL output
SIO_IRQ_MTIMECMP = 29, ///< Select SIO_IRQ_MTIMECMP's IRQ output
CLOCKS_IRQ = 30, ///< Select CLOCKS's IRQ output
SPI0_IRQ = 31, ///< Select SPI0's IRQ output
SPI1_IRQ = 32, ///< Select SPI1's IRQ output
UART0_IRQ = 33, ///< Select UART0's IRQ output
UART1_IRQ = 34, ///< Select UART1's IRQ output
ADC_IRQ_FIFO = 35, ///< Select ADC's IRQ_FIFO output
I2C0_IRQ = 36, ///< Select I2C0's IRQ output
I2C1_IRQ = 37, ///< Select I2C1's IRQ output
OTP_IRQ = 38, ///< Select OTP's IRQ output
TRNG_IRQ = 39, ///< Select TRNG's IRQ output
PROC0_IRQ_CTI = 40, ///< Select PROC0's IRQ_CTI output
PROC1_IRQ_CTI = 41, ///< Select PROC1's IRQ_CTI output
PLL_SYS_IRQ = 42, ///< Select PLL_SYS's IRQ output
PLL_USB_IRQ = 43, ///< Select PLL_USB's IRQ output
POWMAN_IRQ_POW = 44, ///< Select POWMAN's IRQ_POW output
POWMAN_IRQ_TIMER = 45, ///< Select POWMAN's IRQ_TIMER output
SPARE_IRQ_0 = 46, ///< Select SPARE IRQ 0
SPARE_IRQ_1 = 47, ///< Select SPARE IRQ 1
SPARE_IRQ_2 = 48, ///< Select SPARE IRQ 2
SPARE_IRQ_3 = 49, ///< Select SPARE IRQ 3
SPARE_IRQ_4 = 50, ///< Select SPARE IRQ 4
SPARE_IRQ_5 = 51, ///< Select SPARE IRQ 5
IRQ_COUNT
} irq_num_t;
#endif
#define isr_timer0_0 isr_irq0
#define isr_timer0_1 isr_irq1
#define isr_timer0_2 isr_irq2
#define isr_timer0_3 isr_irq3
#define isr_timer1_0 isr_irq4
#define isr_timer1_1 isr_irq5
#define isr_timer1_2 isr_irq6
#define isr_timer1_3 isr_irq7
#define isr_pwm_wrap_0 isr_irq8
#define isr_pwm_wrap_1 isr_irq9
#define isr_dma_0 isr_irq10
#define isr_dma_1 isr_irq11
#define isr_dma_2 isr_irq12
#define isr_dma_3 isr_irq13
#define isr_usbctrl isr_irq14
#define isr_pio0_0 isr_irq15
#define isr_pio0_1 isr_irq16
#define isr_pio1_0 isr_irq17
#define isr_pio1_1 isr_irq18
#define isr_pio2_0 isr_irq19
#define isr_pio2_1 isr_irq20
#define isr_io_bank0 isr_irq21
#define isr_io_bank0_ns isr_irq22
#define isr_io_qspi isr_irq23
#define isr_io_qspi_ns isr_irq24
#define isr_sio_fifo isr_irq25
#define isr_sio_bell isr_irq26
#define isr_sio_fifo_ns isr_irq27
#define isr_sio_bell_ns isr_irq28
#define isr_sio_mtimecmp isr_irq29
#define isr_clocks isr_irq30
#define isr_spi0 isr_irq31
#define isr_spi1 isr_irq32
#define isr_uart0 isr_irq33
#define isr_uart1 isr_irq34
#define isr_adc_fifo isr_irq35
#define isr_i2c0 isr_irq36
#define isr_i2c1 isr_irq37
#define isr_otp isr_irq38
#define isr_trng isr_irq39
#define isr_proc0_cti isr_irq40
#define isr_proc1_cti isr_irq41
#define isr_pll_sys isr_irq42
#define isr_pll_usb isr_irq43
#define isr_powman_pow isr_irq44
#define isr_powman_timer isr_irq45
#define isr_spare_0 isr_irq46
#define isr_spare_1 isr_irq47
#define isr_spare_2 isr_irq48
#define isr_spare_3 isr_irq49
#define isr_spare_4 isr_irq50
#define isr_spare_5 isr_irq51
#endif // _INTCTRL_H

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lib/pico-sdk/rp2350/hardware/regs/io_qspi.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/m33.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : M33_EPPB
// Version : 1
// Bus type : apb
// Description : Cortex-M33 EPPB vendor register block for RP2350
// =============================================================================
#ifndef _HARDWARE_REGS_M33_EPPB_H
#define _HARDWARE_REGS_M33_EPPB_H
// =============================================================================
// Register : M33_EPPB_NMI_MASK0
// Description : NMI mask for IRQs 0 through 31. This register is core-local,
// and is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK0_OFFSET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_BITS _u(0xffffffff)
#define M33_EPPB_NMI_MASK0_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK0_MSB _u(31)
#define M33_EPPB_NMI_MASK0_LSB _u(0)
#define M33_EPPB_NMI_MASK0_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_NMI_MASK1
// Description : NMI mask for IRQs 0 though 51. This register is core-local, and
// is reset by a processor warm reset.
#define M33_EPPB_NMI_MASK1_OFFSET _u(0x00000004)
#define M33_EPPB_NMI_MASK1_BITS _u(0x000fffff)
#define M33_EPPB_NMI_MASK1_RESET _u(0x00000000)
#define M33_EPPB_NMI_MASK1_MSB _u(19)
#define M33_EPPB_NMI_MASK1_LSB _u(0)
#define M33_EPPB_NMI_MASK1_ACCESS "RW"
// =============================================================================
// Register : M33_EPPB_SLEEPCTRL
// Description : Nonstandard sleep control register
#define M33_EPPB_SLEEPCTRL_OFFSET _u(0x00000008)
#define M33_EPPB_SLEEPCTRL_BITS _u(0x00000007)
#define M33_EPPB_SLEEPCTRL_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENACK
// Description : Status signal from the processor's interrupt controller.
// Changes to WICENREQ are eventually reflected in WICENACK.
#define M33_EPPB_SLEEPCTRL_WICENACK_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_WICENACK_BITS _u(0x00000004)
#define M33_EPPB_SLEEPCTRL_WICENACK_MSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_LSB _u(2)
#define M33_EPPB_SLEEPCTRL_WICENACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_WICENREQ
// Description : Request that the next processor deep sleep is a WIC sleep.
// After setting this bit, before sleeping, poll WICENACK to
// ensure the processor interrupt controller has acknowledged the
// change.
#define M33_EPPB_SLEEPCTRL_WICENREQ_RESET _u(0x1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_BITS _u(0x00000002)
#define M33_EPPB_SLEEPCTRL_WICENREQ_MSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_LSB _u(1)
#define M33_EPPB_SLEEPCTRL_WICENREQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : M33_EPPB_SLEEPCTRL_LIGHT_SLEEP
// Description : By default, any processor sleep will deassert the system-level
// clock request. Reenabling the clocks incurs 5 cycles of
// additional latency on wakeup.
//
// Setting LIGHT_SLEEP to 1 keeps the clock request asserted
// during a normal sleep (Arm SCR.SLEEPDEEP = 0), for faster
// wakeup. Processor deep sleep (Arm SCR.SLEEPDEEP = 1) is not
// affected, and will always deassert the system-level clock
// request.
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_RESET _u(0x0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_BITS _u(0x00000001)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_MSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_LSB _u(0)
#define M33_EPPB_SLEEPCTRL_LIGHT_SLEEP_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_M33_EPPB_H

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lib/pico-sdk/rp2350/hardware/regs/otp_data.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/pads_bank0.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/pads_qspi.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PADS_QSPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PADS_QSPI_H
#define _HARDWARE_REGS_PADS_QSPI_H
// =============================================================================
// Register : PADS_QSPI_VOLTAGE_SELECT
// Description : Voltage select. Per bank control
// 0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
// 0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
#define PADS_QSPI_VOLTAGE_SELECT_OFFSET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_BITS _u(0x00000001)
#define PADS_QSPI_VOLTAGE_SELECT_RESET _u(0x00000000)
#define PADS_QSPI_VOLTAGE_SELECT_MSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_LSB _u(0)
#define PADS_QSPI_VOLTAGE_SELECT_ACCESS "RW"
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SCLK
#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SCLK_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SCLK_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD0
#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD0_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD0_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD1
#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
#define PADS_QSPI_GPIO_QSPI_SD1_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD1_RESET _u(0x00000156)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD1_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD2
#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
#define PADS_QSPI_GPIO_QSPI_SD2_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD2_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD2_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SD3
#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
#define PADS_QSPI_GPIO_QSPI_SD3_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SD3_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SD3_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
// =============================================================================
// Register : PADS_QSPI_GPIO_QSPI_SS
#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
#define PADS_QSPI_GPIO_QSPI_SS_BITS _u(0x000001ff)
#define PADS_QSPI_GPIO_QSPI_SS_RESET _u(0x0000015a)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_ISO
// Description : Pad isolation control. Remove this once the pad is configured
// by software.
#define PADS_QSPI_GPIO_QSPI_SS_ISO_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_BITS _u(0x00000100)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_MSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_LSB _u(8)
#define PADS_QSPI_GPIO_QSPI_SS_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_OD
// Description : Output disable. Has priority over output enable from
// peripherals
#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS _u(0x00000080)
#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB _u(7)
#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_IE
// Description : Input enable
#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS _u(0x00000040)
#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB _u(6)
#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_DRIVE
// Description : Drive strength.
// 0x0 -> 2mA
// 0x1 -> 4mA
// 0x2 -> 8mA
// 0x3 -> 12mA
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS _u(0x00000030)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB _u(5)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB _u(4)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS "RW"
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA _u(0x2)
#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PUE
// Description : Pull up enable
#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS _u(0x00000008)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB _u(3)
#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_PDE
// Description : Pull down enable
#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS _u(0x00000004)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB _u(2)
#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
// Description : Enable schmitt trigger
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET _u(0x1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS _u(0x00000002)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB _u(1)
#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
// Description : Slew rate control. 1 = Fast, 0 = Slow
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET _u(0x0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS _u(0x00000001)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB _u(0)
#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_PADS_QSPI_H

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lib/pico-sdk/rp2350/hardware/regs/pll.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PLL
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PLL_H
#define _HARDWARE_REGS_PLL_H
// =============================================================================
// Register : PLL_CS
// Description : Control and Status
// GENERAL CONSTRAINTS:
// Reference clock frequency min=5MHz, max=800MHz
// Feedback divider min=16, max=320
// VCO frequency min=750MHz, max=1600MHz
#define PLL_CS_OFFSET _u(0x00000000)
#define PLL_CS_BITS _u(0xc000013f)
#define PLL_CS_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK
// Description : PLL is locked
#define PLL_CS_LOCK_RESET _u(0x0)
#define PLL_CS_LOCK_BITS _u(0x80000000)
#define PLL_CS_LOCK_MSB _u(31)
#define PLL_CS_LOCK_LSB _u(31)
#define PLL_CS_LOCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PLL_CS_LOCK_N
// Description : PLL is not locked
// Ideally this is cleared when PLL lock is seen and this should
// never normally be set
#define PLL_CS_LOCK_N_RESET _u(0x0)
#define PLL_CS_LOCK_N_BITS _u(0x40000000)
#define PLL_CS_LOCK_N_MSB _u(30)
#define PLL_CS_LOCK_N_LSB _u(30)
#define PLL_CS_LOCK_N_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : PLL_CS_BYPASS
// Description : Passes the reference clock to the output instead of the divided
// VCO. The VCO continues to run so the user can switch between
// the reference clock and the divided VCO but the output will
// glitch when doing so.
#define PLL_CS_BYPASS_RESET _u(0x0)
#define PLL_CS_BYPASS_BITS _u(0x00000100)
#define PLL_CS_BYPASS_MSB _u(8)
#define PLL_CS_BYPASS_LSB _u(8)
#define PLL_CS_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_CS_REFDIV
// Description : Divides the PLL input reference clock.
// Behaviour is undefined for div=0.
// PLL output will be unpredictable during refdiv changes, wait
// for lock=1 before using it.
#define PLL_CS_REFDIV_RESET _u(0x01)
#define PLL_CS_REFDIV_BITS _u(0x0000003f)
#define PLL_CS_REFDIV_MSB _u(5)
#define PLL_CS_REFDIV_LSB _u(0)
#define PLL_CS_REFDIV_ACCESS "RW"
// =============================================================================
// Register : PLL_PWR
// Description : Controls the PLL power modes.
#define PLL_PWR_OFFSET _u(0x00000004)
#define PLL_PWR_BITS _u(0x0000002d)
#define PLL_PWR_RESET _u(0x0000002d)
// -----------------------------------------------------------------------------
// Field : PLL_PWR_VCOPD
// Description : PLL VCO powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_VCOPD_RESET _u(0x1)
#define PLL_PWR_VCOPD_BITS _u(0x00000020)
#define PLL_PWR_VCOPD_MSB _u(5)
#define PLL_PWR_VCOPD_LSB _u(5)
#define PLL_PWR_VCOPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_POSTDIVPD
// Description : PLL post divider powerdown
// To save power set high when PLL output not required or
// bypass=1.
#define PLL_PWR_POSTDIVPD_RESET _u(0x1)
#define PLL_PWR_POSTDIVPD_BITS _u(0x00000008)
#define PLL_PWR_POSTDIVPD_MSB _u(3)
#define PLL_PWR_POSTDIVPD_LSB _u(3)
#define PLL_PWR_POSTDIVPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_DSMPD
// Description : PLL DSM powerdown
// Nothing is achieved by setting this low.
#define PLL_PWR_DSMPD_RESET _u(0x1)
#define PLL_PWR_DSMPD_BITS _u(0x00000004)
#define PLL_PWR_DSMPD_MSB _u(2)
#define PLL_PWR_DSMPD_LSB _u(2)
#define PLL_PWR_DSMPD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PWR_PD
// Description : PLL powerdown
// To save power set high when PLL output not required.
#define PLL_PWR_PD_RESET _u(0x1)
#define PLL_PWR_PD_BITS _u(0x00000001)
#define PLL_PWR_PD_MSB _u(0)
#define PLL_PWR_PD_LSB _u(0)
#define PLL_PWR_PD_ACCESS "RW"
// =============================================================================
// Register : PLL_FBDIV_INT
// Description : Feedback divisor
// (note: this PLL does not support fractional division)
// see ctrl reg description for constraints
#define PLL_FBDIV_INT_OFFSET _u(0x00000008)
#define PLL_FBDIV_INT_BITS _u(0x00000fff)
#define PLL_FBDIV_INT_RESET _u(0x00000000)
#define PLL_FBDIV_INT_MSB _u(11)
#define PLL_FBDIV_INT_LSB _u(0)
#define PLL_FBDIV_INT_ACCESS "RW"
// =============================================================================
// Register : PLL_PRIM
// Description : Controls the PLL post dividers for the primary output
// (note: this PLL does not have a secondary output)
// the primary output is driven from VCO divided by
// postdiv1*postdiv2
#define PLL_PRIM_OFFSET _u(0x0000000c)
#define PLL_PRIM_BITS _u(0x00077000)
#define PLL_PRIM_RESET _u(0x00077000)
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV1
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV1_RESET _u(0x7)
#define PLL_PRIM_POSTDIV1_BITS _u(0x00070000)
#define PLL_PRIM_POSTDIV1_MSB _u(18)
#define PLL_PRIM_POSTDIV1_LSB _u(16)
#define PLL_PRIM_POSTDIV1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PLL_PRIM_POSTDIV2
// Description : divide by 1-7
#define PLL_PRIM_POSTDIV2_RESET _u(0x7)
#define PLL_PRIM_POSTDIV2_BITS _u(0x00007000)
#define PLL_PRIM_POSTDIV2_MSB _u(14)
#define PLL_PRIM_POSTDIV2_LSB _u(12)
#define PLL_PRIM_POSTDIV2_ACCESS "RW"
// =============================================================================
// Register : PLL_INTR
// Description : Raw Interrupts
#define PLL_INTR_OFFSET _u(0x00000010)
#define PLL_INTR_BITS _u(0x00000001)
#define PLL_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTR_LOCK_N_STICKY
#define PLL_INTR_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTR_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTR_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTR_LOCK_N_STICKY_ACCESS "WC"
// =============================================================================
// Register : PLL_INTE
// Description : Interrupt Enable
#define PLL_INTE_OFFSET _u(0x00000014)
#define PLL_INTE_BITS _u(0x00000001)
#define PLL_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTE_LOCK_N_STICKY
#define PLL_INTE_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTE_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTE_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTE_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTF
// Description : Interrupt Force
#define PLL_INTF_OFFSET _u(0x00000018)
#define PLL_INTF_BITS _u(0x00000001)
#define PLL_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTF_LOCK_N_STICKY
#define PLL_INTF_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTF_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTF_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTF_LOCK_N_STICKY_ACCESS "RW"
// =============================================================================
// Register : PLL_INTS
// Description : Interrupt status after masking & forcing
#define PLL_INTS_OFFSET _u(0x0000001c)
#define PLL_INTS_BITS _u(0x00000001)
#define PLL_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PLL_INTS_LOCK_N_STICKY
#define PLL_INTS_LOCK_N_STICKY_RESET _u(0x0)
#define PLL_INTS_LOCK_N_STICKY_BITS _u(0x00000001)
#define PLL_INTS_LOCK_N_STICKY_MSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_LSB _u(0)
#define PLL_INTS_LOCK_N_STICKY_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PLL_H

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lib/pico-sdk/rp2350/hardware/regs/powman.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : PSM
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_PSM_H
#define _HARDWARE_REGS_PSM_H
// =============================================================================
// Register : PSM_FRCE_ON
// Description : Force block out of reset (i.e. power it on)
#define PSM_FRCE_ON_OFFSET _u(0x00000000)
#define PSM_FRCE_ON_BITS _u(0x01ffffff)
#define PSM_FRCE_ON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC1
#define PSM_FRCE_ON_PROC1_RESET _u(0x0)
#define PSM_FRCE_ON_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_ON_PROC1_MSB _u(24)
#define PSM_FRCE_ON_PROC1_LSB _u(24)
#define PSM_FRCE_ON_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC0
#define PSM_FRCE_ON_PROC0_RESET _u(0x0)
#define PSM_FRCE_ON_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_ON_PROC0_MSB _u(23)
#define PSM_FRCE_ON_PROC0_LSB _u(23)
#define PSM_FRCE_ON_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ACCESSCTRL
#define PSM_FRCE_ON_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_ON_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_ON_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_ON_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SIO
#define PSM_FRCE_ON_SIO_RESET _u(0x0)
#define PSM_FRCE_ON_SIO_BITS _u(0x00200000)
#define PSM_FRCE_ON_SIO_MSB _u(21)
#define PSM_FRCE_ON_SIO_LSB _u(21)
#define PSM_FRCE_ON_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XIP
#define PSM_FRCE_ON_XIP_RESET _u(0x0)
#define PSM_FRCE_ON_XIP_BITS _u(0x00100000)
#define PSM_FRCE_ON_XIP_MSB _u(20)
#define PSM_FRCE_ON_XIP_LSB _u(20)
#define PSM_FRCE_ON_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM9
#define PSM_FRCE_ON_SRAM9_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_ON_SRAM9_MSB _u(19)
#define PSM_FRCE_ON_SRAM9_LSB _u(19)
#define PSM_FRCE_ON_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM8
#define PSM_FRCE_ON_SRAM8_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_ON_SRAM8_MSB _u(18)
#define PSM_FRCE_ON_SRAM8_LSB _u(18)
#define PSM_FRCE_ON_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM7
#define PSM_FRCE_ON_SRAM7_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_ON_SRAM7_MSB _u(17)
#define PSM_FRCE_ON_SRAM7_LSB _u(17)
#define PSM_FRCE_ON_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM6
#define PSM_FRCE_ON_SRAM6_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_ON_SRAM6_MSB _u(16)
#define PSM_FRCE_ON_SRAM6_LSB _u(16)
#define PSM_FRCE_ON_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM5
#define PSM_FRCE_ON_SRAM5_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_ON_SRAM5_MSB _u(15)
#define PSM_FRCE_ON_SRAM5_LSB _u(15)
#define PSM_FRCE_ON_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM4
#define PSM_FRCE_ON_SRAM4_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_ON_SRAM4_MSB _u(14)
#define PSM_FRCE_ON_SRAM4_LSB _u(14)
#define PSM_FRCE_ON_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM3
#define PSM_FRCE_ON_SRAM3_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_ON_SRAM3_MSB _u(13)
#define PSM_FRCE_ON_SRAM3_LSB _u(13)
#define PSM_FRCE_ON_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM2
#define PSM_FRCE_ON_SRAM2_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_ON_SRAM2_MSB _u(12)
#define PSM_FRCE_ON_SRAM2_LSB _u(12)
#define PSM_FRCE_ON_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM1
#define PSM_FRCE_ON_SRAM1_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_ON_SRAM1_MSB _u(11)
#define PSM_FRCE_ON_SRAM1_LSB _u(11)
#define PSM_FRCE_ON_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_SRAM0
#define PSM_FRCE_ON_SRAM0_RESET _u(0x0)
#define PSM_FRCE_ON_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_ON_SRAM0_MSB _u(10)
#define PSM_FRCE_ON_SRAM0_LSB _u(10)
#define PSM_FRCE_ON_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BOOTRAM
#define PSM_FRCE_ON_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_ON_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_ON_BOOTRAM_MSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_LSB _u(9)
#define PSM_FRCE_ON_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROM
#define PSM_FRCE_ON_ROM_RESET _u(0x0)
#define PSM_FRCE_ON_ROM_BITS _u(0x00000100)
#define PSM_FRCE_ON_ROM_MSB _u(8)
#define PSM_FRCE_ON_ROM_LSB _u(8)
#define PSM_FRCE_ON_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_BUSFABRIC
#define PSM_FRCE_ON_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_ON_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_ON_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_ON_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PSM_READY
#define PSM_FRCE_ON_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_ON_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_ON_PSM_READY_MSB _u(6)
#define PSM_FRCE_ON_PSM_READY_LSB _u(6)
#define PSM_FRCE_ON_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_CLOCKS
#define PSM_FRCE_ON_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_ON_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_ON_CLOCKS_MSB _u(5)
#define PSM_FRCE_ON_CLOCKS_LSB _u(5)
#define PSM_FRCE_ON_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_RESETS
#define PSM_FRCE_ON_RESETS_RESET _u(0x0)
#define PSM_FRCE_ON_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_ON_RESETS_MSB _u(4)
#define PSM_FRCE_ON_RESETS_LSB _u(4)
#define PSM_FRCE_ON_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_XOSC
#define PSM_FRCE_ON_XOSC_RESET _u(0x0)
#define PSM_FRCE_ON_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_ON_XOSC_MSB _u(3)
#define PSM_FRCE_ON_XOSC_LSB _u(3)
#define PSM_FRCE_ON_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_ROSC
#define PSM_FRCE_ON_ROSC_RESET _u(0x0)
#define PSM_FRCE_ON_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_ON_ROSC_MSB _u(2)
#define PSM_FRCE_ON_ROSC_LSB _u(2)
#define PSM_FRCE_ON_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_OTP
#define PSM_FRCE_ON_OTP_RESET _u(0x0)
#define PSM_FRCE_ON_OTP_BITS _u(0x00000002)
#define PSM_FRCE_ON_OTP_MSB _u(1)
#define PSM_FRCE_ON_OTP_LSB _u(1)
#define PSM_FRCE_ON_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_ON_PROC_COLD
#define PSM_FRCE_ON_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_ON_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_ON_PROC_COLD_MSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_LSB _u(0)
#define PSM_FRCE_ON_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_FRCE_OFF
// Description : Force into reset (i.e. power it off)
#define PSM_FRCE_OFF_OFFSET _u(0x00000004)
#define PSM_FRCE_OFF_BITS _u(0x01ffffff)
#define PSM_FRCE_OFF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC1
#define PSM_FRCE_OFF_PROC1_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC1_BITS _u(0x01000000)
#define PSM_FRCE_OFF_PROC1_MSB _u(24)
#define PSM_FRCE_OFF_PROC1_LSB _u(24)
#define PSM_FRCE_OFF_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC0
#define PSM_FRCE_OFF_PROC0_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC0_BITS _u(0x00800000)
#define PSM_FRCE_OFF_PROC0_MSB _u(23)
#define PSM_FRCE_OFF_PROC0_LSB _u(23)
#define PSM_FRCE_OFF_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ACCESSCTRL
#define PSM_FRCE_OFF_ACCESSCTRL_RESET _u(0x0)
#define PSM_FRCE_OFF_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_FRCE_OFF_ACCESSCTRL_MSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_LSB _u(22)
#define PSM_FRCE_OFF_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SIO
#define PSM_FRCE_OFF_SIO_RESET _u(0x0)
#define PSM_FRCE_OFF_SIO_BITS _u(0x00200000)
#define PSM_FRCE_OFF_SIO_MSB _u(21)
#define PSM_FRCE_OFF_SIO_LSB _u(21)
#define PSM_FRCE_OFF_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XIP
#define PSM_FRCE_OFF_XIP_RESET _u(0x0)
#define PSM_FRCE_OFF_XIP_BITS _u(0x00100000)
#define PSM_FRCE_OFF_XIP_MSB _u(20)
#define PSM_FRCE_OFF_XIP_LSB _u(20)
#define PSM_FRCE_OFF_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM9
#define PSM_FRCE_OFF_SRAM9_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM9_BITS _u(0x00080000)
#define PSM_FRCE_OFF_SRAM9_MSB _u(19)
#define PSM_FRCE_OFF_SRAM9_LSB _u(19)
#define PSM_FRCE_OFF_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM8
#define PSM_FRCE_OFF_SRAM8_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM8_BITS _u(0x00040000)
#define PSM_FRCE_OFF_SRAM8_MSB _u(18)
#define PSM_FRCE_OFF_SRAM8_LSB _u(18)
#define PSM_FRCE_OFF_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM7
#define PSM_FRCE_OFF_SRAM7_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM7_BITS _u(0x00020000)
#define PSM_FRCE_OFF_SRAM7_MSB _u(17)
#define PSM_FRCE_OFF_SRAM7_LSB _u(17)
#define PSM_FRCE_OFF_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM6
#define PSM_FRCE_OFF_SRAM6_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM6_BITS _u(0x00010000)
#define PSM_FRCE_OFF_SRAM6_MSB _u(16)
#define PSM_FRCE_OFF_SRAM6_LSB _u(16)
#define PSM_FRCE_OFF_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM5
#define PSM_FRCE_OFF_SRAM5_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM5_BITS _u(0x00008000)
#define PSM_FRCE_OFF_SRAM5_MSB _u(15)
#define PSM_FRCE_OFF_SRAM5_LSB _u(15)
#define PSM_FRCE_OFF_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM4
#define PSM_FRCE_OFF_SRAM4_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM4_BITS _u(0x00004000)
#define PSM_FRCE_OFF_SRAM4_MSB _u(14)
#define PSM_FRCE_OFF_SRAM4_LSB _u(14)
#define PSM_FRCE_OFF_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM3
#define PSM_FRCE_OFF_SRAM3_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM3_BITS _u(0x00002000)
#define PSM_FRCE_OFF_SRAM3_MSB _u(13)
#define PSM_FRCE_OFF_SRAM3_LSB _u(13)
#define PSM_FRCE_OFF_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM2
#define PSM_FRCE_OFF_SRAM2_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM2_BITS _u(0x00001000)
#define PSM_FRCE_OFF_SRAM2_MSB _u(12)
#define PSM_FRCE_OFF_SRAM2_LSB _u(12)
#define PSM_FRCE_OFF_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM1
#define PSM_FRCE_OFF_SRAM1_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM1_BITS _u(0x00000800)
#define PSM_FRCE_OFF_SRAM1_MSB _u(11)
#define PSM_FRCE_OFF_SRAM1_LSB _u(11)
#define PSM_FRCE_OFF_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_SRAM0
#define PSM_FRCE_OFF_SRAM0_RESET _u(0x0)
#define PSM_FRCE_OFF_SRAM0_BITS _u(0x00000400)
#define PSM_FRCE_OFF_SRAM0_MSB _u(10)
#define PSM_FRCE_OFF_SRAM0_LSB _u(10)
#define PSM_FRCE_OFF_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BOOTRAM
#define PSM_FRCE_OFF_BOOTRAM_RESET _u(0x0)
#define PSM_FRCE_OFF_BOOTRAM_BITS _u(0x00000200)
#define PSM_FRCE_OFF_BOOTRAM_MSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_LSB _u(9)
#define PSM_FRCE_OFF_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROM
#define PSM_FRCE_OFF_ROM_RESET _u(0x0)
#define PSM_FRCE_OFF_ROM_BITS _u(0x00000100)
#define PSM_FRCE_OFF_ROM_MSB _u(8)
#define PSM_FRCE_OFF_ROM_LSB _u(8)
#define PSM_FRCE_OFF_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_BUSFABRIC
#define PSM_FRCE_OFF_BUSFABRIC_RESET _u(0x0)
#define PSM_FRCE_OFF_BUSFABRIC_BITS _u(0x00000080)
#define PSM_FRCE_OFF_BUSFABRIC_MSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_LSB _u(7)
#define PSM_FRCE_OFF_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PSM_READY
#define PSM_FRCE_OFF_PSM_READY_RESET _u(0x0)
#define PSM_FRCE_OFF_PSM_READY_BITS _u(0x00000040)
#define PSM_FRCE_OFF_PSM_READY_MSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_LSB _u(6)
#define PSM_FRCE_OFF_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_CLOCKS
#define PSM_FRCE_OFF_CLOCKS_RESET _u(0x0)
#define PSM_FRCE_OFF_CLOCKS_BITS _u(0x00000020)
#define PSM_FRCE_OFF_CLOCKS_MSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_LSB _u(5)
#define PSM_FRCE_OFF_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_RESETS
#define PSM_FRCE_OFF_RESETS_RESET _u(0x0)
#define PSM_FRCE_OFF_RESETS_BITS _u(0x00000010)
#define PSM_FRCE_OFF_RESETS_MSB _u(4)
#define PSM_FRCE_OFF_RESETS_LSB _u(4)
#define PSM_FRCE_OFF_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_XOSC
#define PSM_FRCE_OFF_XOSC_RESET _u(0x0)
#define PSM_FRCE_OFF_XOSC_BITS _u(0x00000008)
#define PSM_FRCE_OFF_XOSC_MSB _u(3)
#define PSM_FRCE_OFF_XOSC_LSB _u(3)
#define PSM_FRCE_OFF_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_ROSC
#define PSM_FRCE_OFF_ROSC_RESET _u(0x0)
#define PSM_FRCE_OFF_ROSC_BITS _u(0x00000004)
#define PSM_FRCE_OFF_ROSC_MSB _u(2)
#define PSM_FRCE_OFF_ROSC_LSB _u(2)
#define PSM_FRCE_OFF_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_OTP
#define PSM_FRCE_OFF_OTP_RESET _u(0x0)
#define PSM_FRCE_OFF_OTP_BITS _u(0x00000002)
#define PSM_FRCE_OFF_OTP_MSB _u(1)
#define PSM_FRCE_OFF_OTP_LSB _u(1)
#define PSM_FRCE_OFF_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_FRCE_OFF_PROC_COLD
#define PSM_FRCE_OFF_PROC_COLD_RESET _u(0x0)
#define PSM_FRCE_OFF_PROC_COLD_BITS _u(0x00000001)
#define PSM_FRCE_OFF_PROC_COLD_MSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_LSB _u(0)
#define PSM_FRCE_OFF_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_WDSEL
// Description : Set to 1 if the watchdog should reset this
#define PSM_WDSEL_OFFSET _u(0x00000008)
#define PSM_WDSEL_BITS _u(0x01ffffff)
#define PSM_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC1
#define PSM_WDSEL_PROC1_RESET _u(0x0)
#define PSM_WDSEL_PROC1_BITS _u(0x01000000)
#define PSM_WDSEL_PROC1_MSB _u(24)
#define PSM_WDSEL_PROC1_LSB _u(24)
#define PSM_WDSEL_PROC1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC0
#define PSM_WDSEL_PROC0_RESET _u(0x0)
#define PSM_WDSEL_PROC0_BITS _u(0x00800000)
#define PSM_WDSEL_PROC0_MSB _u(23)
#define PSM_WDSEL_PROC0_LSB _u(23)
#define PSM_WDSEL_PROC0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ACCESSCTRL
#define PSM_WDSEL_ACCESSCTRL_RESET _u(0x0)
#define PSM_WDSEL_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_WDSEL_ACCESSCTRL_MSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_LSB _u(22)
#define PSM_WDSEL_ACCESSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SIO
#define PSM_WDSEL_SIO_RESET _u(0x0)
#define PSM_WDSEL_SIO_BITS _u(0x00200000)
#define PSM_WDSEL_SIO_MSB _u(21)
#define PSM_WDSEL_SIO_LSB _u(21)
#define PSM_WDSEL_SIO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XIP
#define PSM_WDSEL_XIP_RESET _u(0x0)
#define PSM_WDSEL_XIP_BITS _u(0x00100000)
#define PSM_WDSEL_XIP_MSB _u(20)
#define PSM_WDSEL_XIP_LSB _u(20)
#define PSM_WDSEL_XIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM9
#define PSM_WDSEL_SRAM9_RESET _u(0x0)
#define PSM_WDSEL_SRAM9_BITS _u(0x00080000)
#define PSM_WDSEL_SRAM9_MSB _u(19)
#define PSM_WDSEL_SRAM9_LSB _u(19)
#define PSM_WDSEL_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM8
#define PSM_WDSEL_SRAM8_RESET _u(0x0)
#define PSM_WDSEL_SRAM8_BITS _u(0x00040000)
#define PSM_WDSEL_SRAM8_MSB _u(18)
#define PSM_WDSEL_SRAM8_LSB _u(18)
#define PSM_WDSEL_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM7
#define PSM_WDSEL_SRAM7_RESET _u(0x0)
#define PSM_WDSEL_SRAM7_BITS _u(0x00020000)
#define PSM_WDSEL_SRAM7_MSB _u(17)
#define PSM_WDSEL_SRAM7_LSB _u(17)
#define PSM_WDSEL_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM6
#define PSM_WDSEL_SRAM6_RESET _u(0x0)
#define PSM_WDSEL_SRAM6_BITS _u(0x00010000)
#define PSM_WDSEL_SRAM6_MSB _u(16)
#define PSM_WDSEL_SRAM6_LSB _u(16)
#define PSM_WDSEL_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM5
#define PSM_WDSEL_SRAM5_RESET _u(0x0)
#define PSM_WDSEL_SRAM5_BITS _u(0x00008000)
#define PSM_WDSEL_SRAM5_MSB _u(15)
#define PSM_WDSEL_SRAM5_LSB _u(15)
#define PSM_WDSEL_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM4
#define PSM_WDSEL_SRAM4_RESET _u(0x0)
#define PSM_WDSEL_SRAM4_BITS _u(0x00004000)
#define PSM_WDSEL_SRAM4_MSB _u(14)
#define PSM_WDSEL_SRAM4_LSB _u(14)
#define PSM_WDSEL_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM3
#define PSM_WDSEL_SRAM3_RESET _u(0x0)
#define PSM_WDSEL_SRAM3_BITS _u(0x00002000)
#define PSM_WDSEL_SRAM3_MSB _u(13)
#define PSM_WDSEL_SRAM3_LSB _u(13)
#define PSM_WDSEL_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM2
#define PSM_WDSEL_SRAM2_RESET _u(0x0)
#define PSM_WDSEL_SRAM2_BITS _u(0x00001000)
#define PSM_WDSEL_SRAM2_MSB _u(12)
#define PSM_WDSEL_SRAM2_LSB _u(12)
#define PSM_WDSEL_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM1
#define PSM_WDSEL_SRAM1_RESET _u(0x0)
#define PSM_WDSEL_SRAM1_BITS _u(0x00000800)
#define PSM_WDSEL_SRAM1_MSB _u(11)
#define PSM_WDSEL_SRAM1_LSB _u(11)
#define PSM_WDSEL_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_SRAM0
#define PSM_WDSEL_SRAM0_RESET _u(0x0)
#define PSM_WDSEL_SRAM0_BITS _u(0x00000400)
#define PSM_WDSEL_SRAM0_MSB _u(10)
#define PSM_WDSEL_SRAM0_LSB _u(10)
#define PSM_WDSEL_SRAM0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BOOTRAM
#define PSM_WDSEL_BOOTRAM_RESET _u(0x0)
#define PSM_WDSEL_BOOTRAM_BITS _u(0x00000200)
#define PSM_WDSEL_BOOTRAM_MSB _u(9)
#define PSM_WDSEL_BOOTRAM_LSB _u(9)
#define PSM_WDSEL_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROM
#define PSM_WDSEL_ROM_RESET _u(0x0)
#define PSM_WDSEL_ROM_BITS _u(0x00000100)
#define PSM_WDSEL_ROM_MSB _u(8)
#define PSM_WDSEL_ROM_LSB _u(8)
#define PSM_WDSEL_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_BUSFABRIC
#define PSM_WDSEL_BUSFABRIC_RESET _u(0x0)
#define PSM_WDSEL_BUSFABRIC_BITS _u(0x00000080)
#define PSM_WDSEL_BUSFABRIC_MSB _u(7)
#define PSM_WDSEL_BUSFABRIC_LSB _u(7)
#define PSM_WDSEL_BUSFABRIC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PSM_READY
#define PSM_WDSEL_PSM_READY_RESET _u(0x0)
#define PSM_WDSEL_PSM_READY_BITS _u(0x00000040)
#define PSM_WDSEL_PSM_READY_MSB _u(6)
#define PSM_WDSEL_PSM_READY_LSB _u(6)
#define PSM_WDSEL_PSM_READY_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_CLOCKS
#define PSM_WDSEL_CLOCKS_RESET _u(0x0)
#define PSM_WDSEL_CLOCKS_BITS _u(0x00000020)
#define PSM_WDSEL_CLOCKS_MSB _u(5)
#define PSM_WDSEL_CLOCKS_LSB _u(5)
#define PSM_WDSEL_CLOCKS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_RESETS
#define PSM_WDSEL_RESETS_RESET _u(0x0)
#define PSM_WDSEL_RESETS_BITS _u(0x00000010)
#define PSM_WDSEL_RESETS_MSB _u(4)
#define PSM_WDSEL_RESETS_LSB _u(4)
#define PSM_WDSEL_RESETS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_XOSC
#define PSM_WDSEL_XOSC_RESET _u(0x0)
#define PSM_WDSEL_XOSC_BITS _u(0x00000008)
#define PSM_WDSEL_XOSC_MSB _u(3)
#define PSM_WDSEL_XOSC_LSB _u(3)
#define PSM_WDSEL_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_ROSC
#define PSM_WDSEL_ROSC_RESET _u(0x0)
#define PSM_WDSEL_ROSC_BITS _u(0x00000004)
#define PSM_WDSEL_ROSC_MSB _u(2)
#define PSM_WDSEL_ROSC_LSB _u(2)
#define PSM_WDSEL_ROSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_OTP
#define PSM_WDSEL_OTP_RESET _u(0x0)
#define PSM_WDSEL_OTP_BITS _u(0x00000002)
#define PSM_WDSEL_OTP_MSB _u(1)
#define PSM_WDSEL_OTP_LSB _u(1)
#define PSM_WDSEL_OTP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : PSM_WDSEL_PROC_COLD
#define PSM_WDSEL_PROC_COLD_RESET _u(0x0)
#define PSM_WDSEL_PROC_COLD_BITS _u(0x00000001)
#define PSM_WDSEL_PROC_COLD_MSB _u(0)
#define PSM_WDSEL_PROC_COLD_LSB _u(0)
#define PSM_WDSEL_PROC_COLD_ACCESS "RW"
// =============================================================================
// Register : PSM_DONE
// Description : Is the subsystem ready?
#define PSM_DONE_OFFSET _u(0x0000000c)
#define PSM_DONE_BITS _u(0x01ffffff)
#define PSM_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC1
#define PSM_DONE_PROC1_RESET _u(0x0)
#define PSM_DONE_PROC1_BITS _u(0x01000000)
#define PSM_DONE_PROC1_MSB _u(24)
#define PSM_DONE_PROC1_LSB _u(24)
#define PSM_DONE_PROC1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC0
#define PSM_DONE_PROC0_RESET _u(0x0)
#define PSM_DONE_PROC0_BITS _u(0x00800000)
#define PSM_DONE_PROC0_MSB _u(23)
#define PSM_DONE_PROC0_LSB _u(23)
#define PSM_DONE_PROC0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ACCESSCTRL
#define PSM_DONE_ACCESSCTRL_RESET _u(0x0)
#define PSM_DONE_ACCESSCTRL_BITS _u(0x00400000)
#define PSM_DONE_ACCESSCTRL_MSB _u(22)
#define PSM_DONE_ACCESSCTRL_LSB _u(22)
#define PSM_DONE_ACCESSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SIO
#define PSM_DONE_SIO_RESET _u(0x0)
#define PSM_DONE_SIO_BITS _u(0x00200000)
#define PSM_DONE_SIO_MSB _u(21)
#define PSM_DONE_SIO_LSB _u(21)
#define PSM_DONE_SIO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XIP
#define PSM_DONE_XIP_RESET _u(0x0)
#define PSM_DONE_XIP_BITS _u(0x00100000)
#define PSM_DONE_XIP_MSB _u(20)
#define PSM_DONE_XIP_LSB _u(20)
#define PSM_DONE_XIP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM9
#define PSM_DONE_SRAM9_RESET _u(0x0)
#define PSM_DONE_SRAM9_BITS _u(0x00080000)
#define PSM_DONE_SRAM9_MSB _u(19)
#define PSM_DONE_SRAM9_LSB _u(19)
#define PSM_DONE_SRAM9_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM8
#define PSM_DONE_SRAM8_RESET _u(0x0)
#define PSM_DONE_SRAM8_BITS _u(0x00040000)
#define PSM_DONE_SRAM8_MSB _u(18)
#define PSM_DONE_SRAM8_LSB _u(18)
#define PSM_DONE_SRAM8_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM7
#define PSM_DONE_SRAM7_RESET _u(0x0)
#define PSM_DONE_SRAM7_BITS _u(0x00020000)
#define PSM_DONE_SRAM7_MSB _u(17)
#define PSM_DONE_SRAM7_LSB _u(17)
#define PSM_DONE_SRAM7_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM6
#define PSM_DONE_SRAM6_RESET _u(0x0)
#define PSM_DONE_SRAM6_BITS _u(0x00010000)
#define PSM_DONE_SRAM6_MSB _u(16)
#define PSM_DONE_SRAM6_LSB _u(16)
#define PSM_DONE_SRAM6_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM5
#define PSM_DONE_SRAM5_RESET _u(0x0)
#define PSM_DONE_SRAM5_BITS _u(0x00008000)
#define PSM_DONE_SRAM5_MSB _u(15)
#define PSM_DONE_SRAM5_LSB _u(15)
#define PSM_DONE_SRAM5_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM4
#define PSM_DONE_SRAM4_RESET _u(0x0)
#define PSM_DONE_SRAM4_BITS _u(0x00004000)
#define PSM_DONE_SRAM4_MSB _u(14)
#define PSM_DONE_SRAM4_LSB _u(14)
#define PSM_DONE_SRAM4_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM3
#define PSM_DONE_SRAM3_RESET _u(0x0)
#define PSM_DONE_SRAM3_BITS _u(0x00002000)
#define PSM_DONE_SRAM3_MSB _u(13)
#define PSM_DONE_SRAM3_LSB _u(13)
#define PSM_DONE_SRAM3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM2
#define PSM_DONE_SRAM2_RESET _u(0x0)
#define PSM_DONE_SRAM2_BITS _u(0x00001000)
#define PSM_DONE_SRAM2_MSB _u(12)
#define PSM_DONE_SRAM2_LSB _u(12)
#define PSM_DONE_SRAM2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM1
#define PSM_DONE_SRAM1_RESET _u(0x0)
#define PSM_DONE_SRAM1_BITS _u(0x00000800)
#define PSM_DONE_SRAM1_MSB _u(11)
#define PSM_DONE_SRAM1_LSB _u(11)
#define PSM_DONE_SRAM1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_SRAM0
#define PSM_DONE_SRAM0_RESET _u(0x0)
#define PSM_DONE_SRAM0_BITS _u(0x00000400)
#define PSM_DONE_SRAM0_MSB _u(10)
#define PSM_DONE_SRAM0_LSB _u(10)
#define PSM_DONE_SRAM0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BOOTRAM
#define PSM_DONE_BOOTRAM_RESET _u(0x0)
#define PSM_DONE_BOOTRAM_BITS _u(0x00000200)
#define PSM_DONE_BOOTRAM_MSB _u(9)
#define PSM_DONE_BOOTRAM_LSB _u(9)
#define PSM_DONE_BOOTRAM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROM
#define PSM_DONE_ROM_RESET _u(0x0)
#define PSM_DONE_ROM_BITS _u(0x00000100)
#define PSM_DONE_ROM_MSB _u(8)
#define PSM_DONE_ROM_LSB _u(8)
#define PSM_DONE_ROM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_BUSFABRIC
#define PSM_DONE_BUSFABRIC_RESET _u(0x0)
#define PSM_DONE_BUSFABRIC_BITS _u(0x00000080)
#define PSM_DONE_BUSFABRIC_MSB _u(7)
#define PSM_DONE_BUSFABRIC_LSB _u(7)
#define PSM_DONE_BUSFABRIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PSM_READY
#define PSM_DONE_PSM_READY_RESET _u(0x0)
#define PSM_DONE_PSM_READY_BITS _u(0x00000040)
#define PSM_DONE_PSM_READY_MSB _u(6)
#define PSM_DONE_PSM_READY_LSB _u(6)
#define PSM_DONE_PSM_READY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_CLOCKS
#define PSM_DONE_CLOCKS_RESET _u(0x0)
#define PSM_DONE_CLOCKS_BITS _u(0x00000020)
#define PSM_DONE_CLOCKS_MSB _u(5)
#define PSM_DONE_CLOCKS_LSB _u(5)
#define PSM_DONE_CLOCKS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_RESETS
#define PSM_DONE_RESETS_RESET _u(0x0)
#define PSM_DONE_RESETS_BITS _u(0x00000010)
#define PSM_DONE_RESETS_MSB _u(4)
#define PSM_DONE_RESETS_LSB _u(4)
#define PSM_DONE_RESETS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_XOSC
#define PSM_DONE_XOSC_RESET _u(0x0)
#define PSM_DONE_XOSC_BITS _u(0x00000008)
#define PSM_DONE_XOSC_MSB _u(3)
#define PSM_DONE_XOSC_LSB _u(3)
#define PSM_DONE_XOSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_ROSC
#define PSM_DONE_ROSC_RESET _u(0x0)
#define PSM_DONE_ROSC_BITS _u(0x00000004)
#define PSM_DONE_ROSC_MSB _u(2)
#define PSM_DONE_ROSC_LSB _u(2)
#define PSM_DONE_ROSC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_OTP
#define PSM_DONE_OTP_RESET _u(0x0)
#define PSM_DONE_OTP_BITS _u(0x00000002)
#define PSM_DONE_OTP_MSB _u(1)
#define PSM_DONE_OTP_LSB _u(1)
#define PSM_DONE_OTP_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : PSM_DONE_PROC_COLD
#define PSM_DONE_PROC_COLD_RESET _u(0x0)
#define PSM_DONE_PROC_COLD_BITS _u(0x00000001)
#define PSM_DONE_PROC_COLD_MSB _u(0)
#define PSM_DONE_PROC_COLD_LSB _u(0)
#define PSM_DONE_PROC_COLD_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_PSM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RESETS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RESETS_H
#define _HARDWARE_REGS_RESETS_H
// =============================================================================
// Register : RESETS_RESET
#define RESETS_RESET_OFFSET _u(0x00000000)
#define RESETS_RESET_BITS _u(0x1fffffff)
#define RESETS_RESET_RESET _u(0x1fffffff)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_USBCTRL
#define RESETS_RESET_USBCTRL_RESET _u(0x1)
#define RESETS_RESET_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_USBCTRL_MSB _u(28)
#define RESETS_RESET_USBCTRL_LSB _u(28)
#define RESETS_RESET_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART1
#define RESETS_RESET_UART1_RESET _u(0x1)
#define RESETS_RESET_UART1_BITS _u(0x08000000)
#define RESETS_RESET_UART1_MSB _u(27)
#define RESETS_RESET_UART1_LSB _u(27)
#define RESETS_RESET_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_UART0
#define RESETS_RESET_UART0_RESET _u(0x1)
#define RESETS_RESET_UART0_BITS _u(0x04000000)
#define RESETS_RESET_UART0_MSB _u(26)
#define RESETS_RESET_UART0_LSB _u(26)
#define RESETS_RESET_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TRNG
#define RESETS_RESET_TRNG_RESET _u(0x1)
#define RESETS_RESET_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_TRNG_MSB _u(25)
#define RESETS_RESET_TRNG_LSB _u(25)
#define RESETS_RESET_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER1
#define RESETS_RESET_TIMER1_RESET _u(0x1)
#define RESETS_RESET_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_TIMER1_MSB _u(24)
#define RESETS_RESET_TIMER1_LSB _u(24)
#define RESETS_RESET_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TIMER0
#define RESETS_RESET_TIMER0_RESET _u(0x1)
#define RESETS_RESET_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_TIMER0_MSB _u(23)
#define RESETS_RESET_TIMER0_LSB _u(23)
#define RESETS_RESET_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_TBMAN
#define RESETS_RESET_TBMAN_RESET _u(0x1)
#define RESETS_RESET_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_TBMAN_MSB _u(22)
#define RESETS_RESET_TBMAN_LSB _u(22)
#define RESETS_RESET_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSINFO
#define RESETS_RESET_SYSINFO_RESET _u(0x1)
#define RESETS_RESET_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_SYSINFO_MSB _u(21)
#define RESETS_RESET_SYSINFO_LSB _u(21)
#define RESETS_RESET_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SYSCFG
#define RESETS_RESET_SYSCFG_RESET _u(0x1)
#define RESETS_RESET_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_SYSCFG_MSB _u(20)
#define RESETS_RESET_SYSCFG_LSB _u(20)
#define RESETS_RESET_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI1
#define RESETS_RESET_SPI1_RESET _u(0x1)
#define RESETS_RESET_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_SPI1_MSB _u(19)
#define RESETS_RESET_SPI1_LSB _u(19)
#define RESETS_RESET_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SPI0
#define RESETS_RESET_SPI0_RESET _u(0x1)
#define RESETS_RESET_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_SPI0_MSB _u(18)
#define RESETS_RESET_SPI0_LSB _u(18)
#define RESETS_RESET_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_SHA256
#define RESETS_RESET_SHA256_RESET _u(0x1)
#define RESETS_RESET_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_SHA256_MSB _u(17)
#define RESETS_RESET_SHA256_LSB _u(17)
#define RESETS_RESET_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PWM
#define RESETS_RESET_PWM_RESET _u(0x1)
#define RESETS_RESET_PWM_BITS _u(0x00010000)
#define RESETS_RESET_PWM_MSB _u(16)
#define RESETS_RESET_PWM_LSB _u(16)
#define RESETS_RESET_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_USB
#define RESETS_RESET_PLL_USB_RESET _u(0x1)
#define RESETS_RESET_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_PLL_USB_MSB _u(15)
#define RESETS_RESET_PLL_USB_LSB _u(15)
#define RESETS_RESET_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PLL_SYS
#define RESETS_RESET_PLL_SYS_RESET _u(0x1)
#define RESETS_RESET_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_PLL_SYS_MSB _u(14)
#define RESETS_RESET_PLL_SYS_LSB _u(14)
#define RESETS_RESET_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO2
#define RESETS_RESET_PIO2_RESET _u(0x1)
#define RESETS_RESET_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_PIO2_MSB _u(13)
#define RESETS_RESET_PIO2_LSB _u(13)
#define RESETS_RESET_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO1
#define RESETS_RESET_PIO1_RESET _u(0x1)
#define RESETS_RESET_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_PIO1_MSB _u(12)
#define RESETS_RESET_PIO1_LSB _u(12)
#define RESETS_RESET_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PIO0
#define RESETS_RESET_PIO0_RESET _u(0x1)
#define RESETS_RESET_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_PIO0_MSB _u(11)
#define RESETS_RESET_PIO0_LSB _u(11)
#define RESETS_RESET_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_QSPI
#define RESETS_RESET_PADS_QSPI_RESET _u(0x1)
#define RESETS_RESET_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_PADS_BANK0
#define RESETS_RESET_PADS_BANK0_RESET _u(0x1)
#define RESETS_RESET_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_JTAG
#define RESETS_RESET_JTAG_RESET _u(0x1)
#define RESETS_RESET_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_JTAG_MSB _u(8)
#define RESETS_RESET_JTAG_LSB _u(8)
#define RESETS_RESET_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_QSPI
#define RESETS_RESET_IO_QSPI_RESET _u(0x1)
#define RESETS_RESET_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_IO_QSPI_MSB _u(7)
#define RESETS_RESET_IO_QSPI_LSB _u(7)
#define RESETS_RESET_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_IO_BANK0
#define RESETS_RESET_IO_BANK0_RESET _u(0x1)
#define RESETS_RESET_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_IO_BANK0_MSB _u(6)
#define RESETS_RESET_IO_BANK0_LSB _u(6)
#define RESETS_RESET_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C1
#define RESETS_RESET_I2C1_RESET _u(0x1)
#define RESETS_RESET_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_I2C1_MSB _u(5)
#define RESETS_RESET_I2C1_LSB _u(5)
#define RESETS_RESET_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_I2C0
#define RESETS_RESET_I2C0_RESET _u(0x1)
#define RESETS_RESET_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_I2C0_MSB _u(4)
#define RESETS_RESET_I2C0_LSB _u(4)
#define RESETS_RESET_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_HSTX
#define RESETS_RESET_HSTX_RESET _u(0x1)
#define RESETS_RESET_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_HSTX_MSB _u(3)
#define RESETS_RESET_HSTX_LSB _u(3)
#define RESETS_RESET_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DMA
#define RESETS_RESET_DMA_RESET _u(0x1)
#define RESETS_RESET_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DMA_MSB _u(2)
#define RESETS_RESET_DMA_LSB _u(2)
#define RESETS_RESET_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_BUSCTRL
#define RESETS_RESET_BUSCTRL_RESET _u(0x1)
#define RESETS_RESET_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_BUSCTRL_MSB _u(1)
#define RESETS_RESET_BUSCTRL_LSB _u(1)
#define RESETS_RESET_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_ADC
#define RESETS_RESET_ADC_RESET _u(0x1)
#define RESETS_RESET_ADC_BITS _u(0x00000001)
#define RESETS_RESET_ADC_MSB _u(0)
#define RESETS_RESET_ADC_LSB _u(0)
#define RESETS_RESET_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_WDSEL
#define RESETS_WDSEL_OFFSET _u(0x00000004)
#define RESETS_WDSEL_BITS _u(0x1fffffff)
#define RESETS_WDSEL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_USBCTRL
#define RESETS_WDSEL_USBCTRL_RESET _u(0x0)
#define RESETS_WDSEL_USBCTRL_BITS _u(0x10000000)
#define RESETS_WDSEL_USBCTRL_MSB _u(28)
#define RESETS_WDSEL_USBCTRL_LSB _u(28)
#define RESETS_WDSEL_USBCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART1
#define RESETS_WDSEL_UART1_RESET _u(0x0)
#define RESETS_WDSEL_UART1_BITS _u(0x08000000)
#define RESETS_WDSEL_UART1_MSB _u(27)
#define RESETS_WDSEL_UART1_LSB _u(27)
#define RESETS_WDSEL_UART1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_UART0
#define RESETS_WDSEL_UART0_RESET _u(0x0)
#define RESETS_WDSEL_UART0_BITS _u(0x04000000)
#define RESETS_WDSEL_UART0_MSB _u(26)
#define RESETS_WDSEL_UART0_LSB _u(26)
#define RESETS_WDSEL_UART0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TRNG
#define RESETS_WDSEL_TRNG_RESET _u(0x0)
#define RESETS_WDSEL_TRNG_BITS _u(0x02000000)
#define RESETS_WDSEL_TRNG_MSB _u(25)
#define RESETS_WDSEL_TRNG_LSB _u(25)
#define RESETS_WDSEL_TRNG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER1
#define RESETS_WDSEL_TIMER1_RESET _u(0x0)
#define RESETS_WDSEL_TIMER1_BITS _u(0x01000000)
#define RESETS_WDSEL_TIMER1_MSB _u(24)
#define RESETS_WDSEL_TIMER1_LSB _u(24)
#define RESETS_WDSEL_TIMER1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TIMER0
#define RESETS_WDSEL_TIMER0_RESET _u(0x0)
#define RESETS_WDSEL_TIMER0_BITS _u(0x00800000)
#define RESETS_WDSEL_TIMER0_MSB _u(23)
#define RESETS_WDSEL_TIMER0_LSB _u(23)
#define RESETS_WDSEL_TIMER0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_TBMAN
#define RESETS_WDSEL_TBMAN_RESET _u(0x0)
#define RESETS_WDSEL_TBMAN_BITS _u(0x00400000)
#define RESETS_WDSEL_TBMAN_MSB _u(22)
#define RESETS_WDSEL_TBMAN_LSB _u(22)
#define RESETS_WDSEL_TBMAN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSINFO
#define RESETS_WDSEL_SYSINFO_RESET _u(0x0)
#define RESETS_WDSEL_SYSINFO_BITS _u(0x00200000)
#define RESETS_WDSEL_SYSINFO_MSB _u(21)
#define RESETS_WDSEL_SYSINFO_LSB _u(21)
#define RESETS_WDSEL_SYSINFO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SYSCFG
#define RESETS_WDSEL_SYSCFG_RESET _u(0x0)
#define RESETS_WDSEL_SYSCFG_BITS _u(0x00100000)
#define RESETS_WDSEL_SYSCFG_MSB _u(20)
#define RESETS_WDSEL_SYSCFG_LSB _u(20)
#define RESETS_WDSEL_SYSCFG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI1
#define RESETS_WDSEL_SPI1_RESET _u(0x0)
#define RESETS_WDSEL_SPI1_BITS _u(0x00080000)
#define RESETS_WDSEL_SPI1_MSB _u(19)
#define RESETS_WDSEL_SPI1_LSB _u(19)
#define RESETS_WDSEL_SPI1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SPI0
#define RESETS_WDSEL_SPI0_RESET _u(0x0)
#define RESETS_WDSEL_SPI0_BITS _u(0x00040000)
#define RESETS_WDSEL_SPI0_MSB _u(18)
#define RESETS_WDSEL_SPI0_LSB _u(18)
#define RESETS_WDSEL_SPI0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_SHA256
#define RESETS_WDSEL_SHA256_RESET _u(0x0)
#define RESETS_WDSEL_SHA256_BITS _u(0x00020000)
#define RESETS_WDSEL_SHA256_MSB _u(17)
#define RESETS_WDSEL_SHA256_LSB _u(17)
#define RESETS_WDSEL_SHA256_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PWM
#define RESETS_WDSEL_PWM_RESET _u(0x0)
#define RESETS_WDSEL_PWM_BITS _u(0x00010000)
#define RESETS_WDSEL_PWM_MSB _u(16)
#define RESETS_WDSEL_PWM_LSB _u(16)
#define RESETS_WDSEL_PWM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_USB
#define RESETS_WDSEL_PLL_USB_RESET _u(0x0)
#define RESETS_WDSEL_PLL_USB_BITS _u(0x00008000)
#define RESETS_WDSEL_PLL_USB_MSB _u(15)
#define RESETS_WDSEL_PLL_USB_LSB _u(15)
#define RESETS_WDSEL_PLL_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PLL_SYS
#define RESETS_WDSEL_PLL_SYS_RESET _u(0x0)
#define RESETS_WDSEL_PLL_SYS_BITS _u(0x00004000)
#define RESETS_WDSEL_PLL_SYS_MSB _u(14)
#define RESETS_WDSEL_PLL_SYS_LSB _u(14)
#define RESETS_WDSEL_PLL_SYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO2
#define RESETS_WDSEL_PIO2_RESET _u(0x0)
#define RESETS_WDSEL_PIO2_BITS _u(0x00002000)
#define RESETS_WDSEL_PIO2_MSB _u(13)
#define RESETS_WDSEL_PIO2_LSB _u(13)
#define RESETS_WDSEL_PIO2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO1
#define RESETS_WDSEL_PIO1_RESET _u(0x0)
#define RESETS_WDSEL_PIO1_BITS _u(0x00001000)
#define RESETS_WDSEL_PIO1_MSB _u(12)
#define RESETS_WDSEL_PIO1_LSB _u(12)
#define RESETS_WDSEL_PIO1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PIO0
#define RESETS_WDSEL_PIO0_RESET _u(0x0)
#define RESETS_WDSEL_PIO0_BITS _u(0x00000800)
#define RESETS_WDSEL_PIO0_MSB _u(11)
#define RESETS_WDSEL_PIO0_LSB _u(11)
#define RESETS_WDSEL_PIO0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_QSPI
#define RESETS_WDSEL_PADS_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_WDSEL_PADS_QSPI_MSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_LSB _u(10)
#define RESETS_WDSEL_PADS_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_PADS_BANK0
#define RESETS_WDSEL_PADS_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_WDSEL_PADS_BANK0_MSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_LSB _u(9)
#define RESETS_WDSEL_PADS_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_JTAG
#define RESETS_WDSEL_JTAG_RESET _u(0x0)
#define RESETS_WDSEL_JTAG_BITS _u(0x00000100)
#define RESETS_WDSEL_JTAG_MSB _u(8)
#define RESETS_WDSEL_JTAG_LSB _u(8)
#define RESETS_WDSEL_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_QSPI
#define RESETS_WDSEL_IO_QSPI_RESET _u(0x0)
#define RESETS_WDSEL_IO_QSPI_BITS _u(0x00000080)
#define RESETS_WDSEL_IO_QSPI_MSB _u(7)
#define RESETS_WDSEL_IO_QSPI_LSB _u(7)
#define RESETS_WDSEL_IO_QSPI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_IO_BANK0
#define RESETS_WDSEL_IO_BANK0_RESET _u(0x0)
#define RESETS_WDSEL_IO_BANK0_BITS _u(0x00000040)
#define RESETS_WDSEL_IO_BANK0_MSB _u(6)
#define RESETS_WDSEL_IO_BANK0_LSB _u(6)
#define RESETS_WDSEL_IO_BANK0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C1
#define RESETS_WDSEL_I2C1_RESET _u(0x0)
#define RESETS_WDSEL_I2C1_BITS _u(0x00000020)
#define RESETS_WDSEL_I2C1_MSB _u(5)
#define RESETS_WDSEL_I2C1_LSB _u(5)
#define RESETS_WDSEL_I2C1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_I2C0
#define RESETS_WDSEL_I2C0_RESET _u(0x0)
#define RESETS_WDSEL_I2C0_BITS _u(0x00000010)
#define RESETS_WDSEL_I2C0_MSB _u(4)
#define RESETS_WDSEL_I2C0_LSB _u(4)
#define RESETS_WDSEL_I2C0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_HSTX
#define RESETS_WDSEL_HSTX_RESET _u(0x0)
#define RESETS_WDSEL_HSTX_BITS _u(0x00000008)
#define RESETS_WDSEL_HSTX_MSB _u(3)
#define RESETS_WDSEL_HSTX_LSB _u(3)
#define RESETS_WDSEL_HSTX_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_DMA
#define RESETS_WDSEL_DMA_RESET _u(0x0)
#define RESETS_WDSEL_DMA_BITS _u(0x00000004)
#define RESETS_WDSEL_DMA_MSB _u(2)
#define RESETS_WDSEL_DMA_LSB _u(2)
#define RESETS_WDSEL_DMA_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_BUSCTRL
#define RESETS_WDSEL_BUSCTRL_RESET _u(0x0)
#define RESETS_WDSEL_BUSCTRL_BITS _u(0x00000002)
#define RESETS_WDSEL_BUSCTRL_MSB _u(1)
#define RESETS_WDSEL_BUSCTRL_LSB _u(1)
#define RESETS_WDSEL_BUSCTRL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RESETS_WDSEL_ADC
#define RESETS_WDSEL_ADC_RESET _u(0x0)
#define RESETS_WDSEL_ADC_BITS _u(0x00000001)
#define RESETS_WDSEL_ADC_MSB _u(0)
#define RESETS_WDSEL_ADC_LSB _u(0)
#define RESETS_WDSEL_ADC_ACCESS "RW"
// =============================================================================
// Register : RESETS_RESET_DONE
#define RESETS_RESET_DONE_OFFSET _u(0x00000008)
#define RESETS_RESET_DONE_BITS _u(0x1fffffff)
#define RESETS_RESET_DONE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_USBCTRL
#define RESETS_RESET_DONE_USBCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_USBCTRL_BITS _u(0x10000000)
#define RESETS_RESET_DONE_USBCTRL_MSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_LSB _u(28)
#define RESETS_RESET_DONE_USBCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART1
#define RESETS_RESET_DONE_UART1_RESET _u(0x0)
#define RESETS_RESET_DONE_UART1_BITS _u(0x08000000)
#define RESETS_RESET_DONE_UART1_MSB _u(27)
#define RESETS_RESET_DONE_UART1_LSB _u(27)
#define RESETS_RESET_DONE_UART1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_UART0
#define RESETS_RESET_DONE_UART0_RESET _u(0x0)
#define RESETS_RESET_DONE_UART0_BITS _u(0x04000000)
#define RESETS_RESET_DONE_UART0_MSB _u(26)
#define RESETS_RESET_DONE_UART0_LSB _u(26)
#define RESETS_RESET_DONE_UART0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TRNG
#define RESETS_RESET_DONE_TRNG_RESET _u(0x0)
#define RESETS_RESET_DONE_TRNG_BITS _u(0x02000000)
#define RESETS_RESET_DONE_TRNG_MSB _u(25)
#define RESETS_RESET_DONE_TRNG_LSB _u(25)
#define RESETS_RESET_DONE_TRNG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER1
#define RESETS_RESET_DONE_TIMER1_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER1_BITS _u(0x01000000)
#define RESETS_RESET_DONE_TIMER1_MSB _u(24)
#define RESETS_RESET_DONE_TIMER1_LSB _u(24)
#define RESETS_RESET_DONE_TIMER1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TIMER0
#define RESETS_RESET_DONE_TIMER0_RESET _u(0x0)
#define RESETS_RESET_DONE_TIMER0_BITS _u(0x00800000)
#define RESETS_RESET_DONE_TIMER0_MSB _u(23)
#define RESETS_RESET_DONE_TIMER0_LSB _u(23)
#define RESETS_RESET_DONE_TIMER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_TBMAN
#define RESETS_RESET_DONE_TBMAN_RESET _u(0x0)
#define RESETS_RESET_DONE_TBMAN_BITS _u(0x00400000)
#define RESETS_RESET_DONE_TBMAN_MSB _u(22)
#define RESETS_RESET_DONE_TBMAN_LSB _u(22)
#define RESETS_RESET_DONE_TBMAN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSINFO
#define RESETS_RESET_DONE_SYSINFO_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSINFO_BITS _u(0x00200000)
#define RESETS_RESET_DONE_SYSINFO_MSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_LSB _u(21)
#define RESETS_RESET_DONE_SYSINFO_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SYSCFG
#define RESETS_RESET_DONE_SYSCFG_RESET _u(0x0)
#define RESETS_RESET_DONE_SYSCFG_BITS _u(0x00100000)
#define RESETS_RESET_DONE_SYSCFG_MSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_LSB _u(20)
#define RESETS_RESET_DONE_SYSCFG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI1
#define RESETS_RESET_DONE_SPI1_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI1_BITS _u(0x00080000)
#define RESETS_RESET_DONE_SPI1_MSB _u(19)
#define RESETS_RESET_DONE_SPI1_LSB _u(19)
#define RESETS_RESET_DONE_SPI1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SPI0
#define RESETS_RESET_DONE_SPI0_RESET _u(0x0)
#define RESETS_RESET_DONE_SPI0_BITS _u(0x00040000)
#define RESETS_RESET_DONE_SPI0_MSB _u(18)
#define RESETS_RESET_DONE_SPI0_LSB _u(18)
#define RESETS_RESET_DONE_SPI0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_SHA256
#define RESETS_RESET_DONE_SHA256_RESET _u(0x0)
#define RESETS_RESET_DONE_SHA256_BITS _u(0x00020000)
#define RESETS_RESET_DONE_SHA256_MSB _u(17)
#define RESETS_RESET_DONE_SHA256_LSB _u(17)
#define RESETS_RESET_DONE_SHA256_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PWM
#define RESETS_RESET_DONE_PWM_RESET _u(0x0)
#define RESETS_RESET_DONE_PWM_BITS _u(0x00010000)
#define RESETS_RESET_DONE_PWM_MSB _u(16)
#define RESETS_RESET_DONE_PWM_LSB _u(16)
#define RESETS_RESET_DONE_PWM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_USB
#define RESETS_RESET_DONE_PLL_USB_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_USB_BITS _u(0x00008000)
#define RESETS_RESET_DONE_PLL_USB_MSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_LSB _u(15)
#define RESETS_RESET_DONE_PLL_USB_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PLL_SYS
#define RESETS_RESET_DONE_PLL_SYS_RESET _u(0x0)
#define RESETS_RESET_DONE_PLL_SYS_BITS _u(0x00004000)
#define RESETS_RESET_DONE_PLL_SYS_MSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_LSB _u(14)
#define RESETS_RESET_DONE_PLL_SYS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO2
#define RESETS_RESET_DONE_PIO2_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO2_BITS _u(0x00002000)
#define RESETS_RESET_DONE_PIO2_MSB _u(13)
#define RESETS_RESET_DONE_PIO2_LSB _u(13)
#define RESETS_RESET_DONE_PIO2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO1
#define RESETS_RESET_DONE_PIO1_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO1_BITS _u(0x00001000)
#define RESETS_RESET_DONE_PIO1_MSB _u(12)
#define RESETS_RESET_DONE_PIO1_LSB _u(12)
#define RESETS_RESET_DONE_PIO1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PIO0
#define RESETS_RESET_DONE_PIO0_RESET _u(0x0)
#define RESETS_RESET_DONE_PIO0_BITS _u(0x00000800)
#define RESETS_RESET_DONE_PIO0_MSB _u(11)
#define RESETS_RESET_DONE_PIO0_LSB _u(11)
#define RESETS_RESET_DONE_PIO0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_QSPI
#define RESETS_RESET_DONE_PADS_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_QSPI_BITS _u(0x00000400)
#define RESETS_RESET_DONE_PADS_QSPI_MSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_LSB _u(10)
#define RESETS_RESET_DONE_PADS_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_PADS_BANK0
#define RESETS_RESET_DONE_PADS_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_PADS_BANK0_BITS _u(0x00000200)
#define RESETS_RESET_DONE_PADS_BANK0_MSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_LSB _u(9)
#define RESETS_RESET_DONE_PADS_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_JTAG
#define RESETS_RESET_DONE_JTAG_RESET _u(0x0)
#define RESETS_RESET_DONE_JTAG_BITS _u(0x00000100)
#define RESETS_RESET_DONE_JTAG_MSB _u(8)
#define RESETS_RESET_DONE_JTAG_LSB _u(8)
#define RESETS_RESET_DONE_JTAG_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_QSPI
#define RESETS_RESET_DONE_IO_QSPI_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_QSPI_BITS _u(0x00000080)
#define RESETS_RESET_DONE_IO_QSPI_MSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_LSB _u(7)
#define RESETS_RESET_DONE_IO_QSPI_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_IO_BANK0
#define RESETS_RESET_DONE_IO_BANK0_RESET _u(0x0)
#define RESETS_RESET_DONE_IO_BANK0_BITS _u(0x00000040)
#define RESETS_RESET_DONE_IO_BANK0_MSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_LSB _u(6)
#define RESETS_RESET_DONE_IO_BANK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C1
#define RESETS_RESET_DONE_I2C1_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C1_BITS _u(0x00000020)
#define RESETS_RESET_DONE_I2C1_MSB _u(5)
#define RESETS_RESET_DONE_I2C1_LSB _u(5)
#define RESETS_RESET_DONE_I2C1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_I2C0
#define RESETS_RESET_DONE_I2C0_RESET _u(0x0)
#define RESETS_RESET_DONE_I2C0_BITS _u(0x00000010)
#define RESETS_RESET_DONE_I2C0_MSB _u(4)
#define RESETS_RESET_DONE_I2C0_LSB _u(4)
#define RESETS_RESET_DONE_I2C0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_HSTX
#define RESETS_RESET_DONE_HSTX_RESET _u(0x0)
#define RESETS_RESET_DONE_HSTX_BITS _u(0x00000008)
#define RESETS_RESET_DONE_HSTX_MSB _u(3)
#define RESETS_RESET_DONE_HSTX_LSB _u(3)
#define RESETS_RESET_DONE_HSTX_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_DMA
#define RESETS_RESET_DONE_DMA_RESET _u(0x0)
#define RESETS_RESET_DONE_DMA_BITS _u(0x00000004)
#define RESETS_RESET_DONE_DMA_MSB _u(2)
#define RESETS_RESET_DONE_DMA_LSB _u(2)
#define RESETS_RESET_DONE_DMA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_BUSCTRL
#define RESETS_RESET_DONE_BUSCTRL_RESET _u(0x0)
#define RESETS_RESET_DONE_BUSCTRL_BITS _u(0x00000002)
#define RESETS_RESET_DONE_BUSCTRL_MSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_LSB _u(1)
#define RESETS_RESET_DONE_BUSCTRL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RESETS_RESET_DONE_ADC
#define RESETS_RESET_DONE_ADC_RESET _u(0x0)
#define RESETS_RESET_DONE_ADC_BITS _u(0x00000001)
#define RESETS_RESET_DONE_ADC_MSB _u(0)
#define RESETS_RESET_DONE_ADC_LSB _u(0)
#define RESETS_RESET_DONE_ADC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RESETS_H

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lib/pico-sdk/rp2350/hardware/regs/riscv_dm.h Normal file
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lib/pico-sdk/rp2350/hardware/regs/rosc.h Normal file
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@ -0,0 +1,345 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : ROSC
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_ROSC_H
#define _HARDWARE_REGS_ROSC_H
// =============================================================================
// Register : ROSC_CTRL
// Description : Ring Oscillator control
#define ROSC_CTRL_OFFSET _u(0x00000000)
#define ROSC_CTRL_BITS _u(0x00ffffff)
#define ROSC_CTRL_RESET _u(0x00000aa0)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_ENABLE
// Description : On power-up this field is initialised to ENABLE
// The system clock must be switched to another source before
// setting this field to DISABLE otherwise the chip will lock up
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will enable the
// oscillator.
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define ROSC_CTRL_ENABLE_RESET "-"
#define ROSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define ROSC_CTRL_ENABLE_MSB _u(23)
#define ROSC_CTRL_ENABLE_LSB _u(12)
#define ROSC_CTRL_ENABLE_ACCESS "RW"
#define ROSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define ROSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : ROSC_CTRL_FREQ_RANGE
// Description : Controls the number of delay stages in the ROSC ring
// LOW uses stages 0 to 7
// MEDIUM uses stages 2 to 7
// HIGH uses stages 4 to 7
// TOOHIGH uses stages 6 to 7 and should not be used because its
// frequency exceeds design specifications
// The clock output will not glitch when changing the range up one
// step at a time
// The clock output will glitch when changing the range down
// Note: the values here are gray coded which is why HIGH comes
// before TOOHIGH
// 0xfa4 -> LOW
// 0xfa5 -> MEDIUM
// 0xfa7 -> HIGH
// 0xfa6 -> TOOHIGH
#define ROSC_CTRL_FREQ_RANGE_RESET _u(0xaa0)
#define ROSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define ROSC_CTRL_FREQ_RANGE_MSB _u(11)
#define ROSC_CTRL_FREQ_RANGE_LSB _u(0)
#define ROSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define ROSC_CTRL_FREQ_RANGE_VALUE_LOW _u(0xfa4)
#define ROSC_CTRL_FREQ_RANGE_VALUE_MEDIUM _u(0xfa5)
#define ROSC_CTRL_FREQ_RANGE_VALUE_HIGH _u(0xfa7)
#define ROSC_CTRL_FREQ_RANGE_VALUE_TOOHIGH _u(0xfa6)
// =============================================================================
// Register : ROSC_FREQA
// Description : The FREQA & FREQB registers control the frequency by
// controlling the drive strength of each stage
// The drive strength has 4 levels determined by the number of
// bits set
// Increasing the number of bits set increases the drive strength
// and increases the oscillation frequency
// 0 bits set is the default drive strength
// 1 bit set doubles the drive strength
// 2 bits set triples drive strength
// 3 bits set quadruples drive strength
// For frequency randomisation set both DS0_RANDOM=1 &
// DS1_RANDOM=1
#define ROSC_FREQA_OFFSET _u(0x00000004)
#define ROSC_FREQA_BITS _u(0xffff77ff)
#define ROSC_FREQA_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQA_PASSWD_RESET _u(0x0000)
#define ROSC_FREQA_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQA_PASSWD_MSB _u(31)
#define ROSC_FREQA_PASSWD_LSB _u(16)
#define ROSC_FREQA_PASSWD_ACCESS "RW"
#define ROSC_FREQA_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS3
// Description : Stage 3 drive strength
#define ROSC_FREQA_DS3_RESET _u(0x0)
#define ROSC_FREQA_DS3_BITS _u(0x00007000)
#define ROSC_FREQA_DS3_MSB _u(14)
#define ROSC_FREQA_DS3_LSB _u(12)
#define ROSC_FREQA_DS3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS2
// Description : Stage 2 drive strength
#define ROSC_FREQA_DS2_RESET _u(0x0)
#define ROSC_FREQA_DS2_BITS _u(0x00000700)
#define ROSC_FREQA_DS2_MSB _u(10)
#define ROSC_FREQA_DS2_LSB _u(8)
#define ROSC_FREQA_DS2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1_RANDOM
// Description : Randomises the stage 1 drive strength
#define ROSC_FREQA_DS1_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS1_RANDOM_BITS _u(0x00000080)
#define ROSC_FREQA_DS1_RANDOM_MSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_LSB _u(7)
#define ROSC_FREQA_DS1_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS1
// Description : Stage 1 drive strength
#define ROSC_FREQA_DS1_RESET _u(0x0)
#define ROSC_FREQA_DS1_BITS _u(0x00000070)
#define ROSC_FREQA_DS1_MSB _u(6)
#define ROSC_FREQA_DS1_LSB _u(4)
#define ROSC_FREQA_DS1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0_RANDOM
// Description : Randomises the stage 0 drive strength
#define ROSC_FREQA_DS0_RANDOM_RESET _u(0x0)
#define ROSC_FREQA_DS0_RANDOM_BITS _u(0x00000008)
#define ROSC_FREQA_DS0_RANDOM_MSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_LSB _u(3)
#define ROSC_FREQA_DS0_RANDOM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQA_DS0
// Description : Stage 0 drive strength
#define ROSC_FREQA_DS0_RESET _u(0x0)
#define ROSC_FREQA_DS0_BITS _u(0x00000007)
#define ROSC_FREQA_DS0_MSB _u(2)
#define ROSC_FREQA_DS0_LSB _u(0)
#define ROSC_FREQA_DS0_ACCESS "RW"
// =============================================================================
// Register : ROSC_FREQB
// Description : For a detailed description see freqa register
#define ROSC_FREQB_OFFSET _u(0x00000008)
#define ROSC_FREQB_BITS _u(0xffff7777)
#define ROSC_FREQB_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_PASSWD
// Description : Set to 0x9696 to apply the settings
// Any other value in this field will set all drive strengths to 0
// 0x9696 -> PASS
#define ROSC_FREQB_PASSWD_RESET _u(0x0000)
#define ROSC_FREQB_PASSWD_BITS _u(0xffff0000)
#define ROSC_FREQB_PASSWD_MSB _u(31)
#define ROSC_FREQB_PASSWD_LSB _u(16)
#define ROSC_FREQB_PASSWD_ACCESS "RW"
#define ROSC_FREQB_PASSWD_VALUE_PASS _u(0x9696)
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS7
// Description : Stage 7 drive strength
#define ROSC_FREQB_DS7_RESET _u(0x0)
#define ROSC_FREQB_DS7_BITS _u(0x00007000)
#define ROSC_FREQB_DS7_MSB _u(14)
#define ROSC_FREQB_DS7_LSB _u(12)
#define ROSC_FREQB_DS7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS6
// Description : Stage 6 drive strength
#define ROSC_FREQB_DS6_RESET _u(0x0)
#define ROSC_FREQB_DS6_BITS _u(0x00000700)
#define ROSC_FREQB_DS6_MSB _u(10)
#define ROSC_FREQB_DS6_LSB _u(8)
#define ROSC_FREQB_DS6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS5
// Description : Stage 5 drive strength
#define ROSC_FREQB_DS5_RESET _u(0x0)
#define ROSC_FREQB_DS5_BITS _u(0x00000070)
#define ROSC_FREQB_DS5_MSB _u(6)
#define ROSC_FREQB_DS5_LSB _u(4)
#define ROSC_FREQB_DS5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_FREQB_DS4
// Description : Stage 4 drive strength
#define ROSC_FREQB_DS4_RESET _u(0x0)
#define ROSC_FREQB_DS4_BITS _u(0x00000007)
#define ROSC_FREQB_DS4_MSB _u(2)
#define ROSC_FREQB_DS4_LSB _u(0)
#define ROSC_FREQB_DS4_ACCESS "RW"
// =============================================================================
// Register : ROSC_RANDOM
// Description : Loads a value to the LFSR randomiser
#define ROSC_RANDOM_OFFSET _u(0x0000000c)
#define ROSC_RANDOM_BITS _u(0xffffffff)
#define ROSC_RANDOM_RESET _u(0x3f04b16d)
// -----------------------------------------------------------------------------
// Field : ROSC_RANDOM_SEED
#define ROSC_RANDOM_SEED_RESET _u(0x3f04b16d)
#define ROSC_RANDOM_SEED_BITS _u(0xffffffff)
#define ROSC_RANDOM_SEED_MSB _u(31)
#define ROSC_RANDOM_SEED_LSB _u(0)
#define ROSC_RANDOM_SEED_ACCESS "RW"
// =============================================================================
// Register : ROSC_DORMANT
// Description : Ring Oscillator pause control
// This is used to save power by pausing the ROSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define ROSC_DORMANT_OFFSET _u(0x00000010)
#define ROSC_DORMANT_BITS _u(0xffffffff)
#define ROSC_DORMANT_RESET "-"
#define ROSC_DORMANT_MSB _u(31)
#define ROSC_DORMANT_LSB _u(0)
#define ROSC_DORMANT_ACCESS "RW"
#define ROSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define ROSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : ROSC_DIV
// Description : Controls the output divider
// set to 0xaa00 + div where
// div = 0 divides by 128
// div = 1-127 divides by div
// any other value sets div=128
// this register resets to div=32
// 0xaa00 -> PASS
#define ROSC_DIV_OFFSET _u(0x00000014)
#define ROSC_DIV_BITS _u(0x0000ffff)
#define ROSC_DIV_RESET "-"
#define ROSC_DIV_MSB _u(15)
#define ROSC_DIV_LSB _u(0)
#define ROSC_DIV_ACCESS "RW"
#define ROSC_DIV_VALUE_PASS _u(0xaa00)
// =============================================================================
// Register : ROSC_PHASE
// Description : Controls the phase shifted output
#define ROSC_PHASE_OFFSET _u(0x00000018)
#define ROSC_PHASE_BITS _u(0x00000fff)
#define ROSC_PHASE_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_PASSWD
// Description : set to 0xaa
// any other value enables the output with shift=0
#define ROSC_PHASE_PASSWD_RESET _u(0x00)
#define ROSC_PHASE_PASSWD_BITS _u(0x00000ff0)
#define ROSC_PHASE_PASSWD_MSB _u(11)
#define ROSC_PHASE_PASSWD_LSB _u(4)
#define ROSC_PHASE_PASSWD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_ENABLE
// Description : enable the phase-shifted output
// this can be changed on-the-fly
#define ROSC_PHASE_ENABLE_RESET _u(0x1)
#define ROSC_PHASE_ENABLE_BITS _u(0x00000008)
#define ROSC_PHASE_ENABLE_MSB _u(3)
#define ROSC_PHASE_ENABLE_LSB _u(3)
#define ROSC_PHASE_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_FLIP
// Description : invert the phase-shifted output
// this is ignored when div=1
#define ROSC_PHASE_FLIP_RESET _u(0x0)
#define ROSC_PHASE_FLIP_BITS _u(0x00000004)
#define ROSC_PHASE_FLIP_MSB _u(2)
#define ROSC_PHASE_FLIP_LSB _u(2)
#define ROSC_PHASE_FLIP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : ROSC_PHASE_SHIFT
// Description : phase shift the phase-shifted output by SHIFT input clocks
// this can be changed on-the-fly
// must be set to 0 before setting div=1
#define ROSC_PHASE_SHIFT_RESET _u(0x0)
#define ROSC_PHASE_SHIFT_BITS _u(0x00000003)
#define ROSC_PHASE_SHIFT_MSB _u(1)
#define ROSC_PHASE_SHIFT_LSB _u(0)
#define ROSC_PHASE_SHIFT_ACCESS "RW"
// =============================================================================
// Register : ROSC_STATUS
// Description : Ring Oscillator Status
#define ROSC_STATUS_OFFSET _u(0x0000001c)
#define ROSC_STATUS_BITS _u(0x81011000)
#define ROSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define ROSC_STATUS_STABLE_RESET _u(0x0)
#define ROSC_STATUS_STABLE_BITS _u(0x80000000)
#define ROSC_STATUS_STABLE_MSB _u(31)
#define ROSC_STATUS_STABLE_LSB _u(31)
#define ROSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
#define ROSC_STATUS_BADWRITE_RESET _u(0x0)
#define ROSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define ROSC_STATUS_BADWRITE_MSB _u(24)
#define ROSC_STATUS_BADWRITE_LSB _u(24)
#define ROSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_DIV_RUNNING
// Description : post-divider is running
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_DIV_RUNNING_RESET "-"
#define ROSC_STATUS_DIV_RUNNING_BITS _u(0x00010000)
#define ROSC_STATUS_DIV_RUNNING_MSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_LSB _u(16)
#define ROSC_STATUS_DIV_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : ROSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable
// this resets to 0 but transitions to 1 during chip startup
#define ROSC_STATUS_ENABLED_RESET "-"
#define ROSC_STATUS_ENABLED_BITS _u(0x00001000)
#define ROSC_STATUS_ENABLED_MSB _u(12)
#define ROSC_STATUS_ENABLED_LSB _u(12)
#define ROSC_STATUS_ENABLED_ACCESS "RO"
// =============================================================================
// Register : ROSC_RANDOMBIT
// Description : This just reads the state of the oscillator output so
// randomness is compromised if the ring oscillator is stopped or
// run at a harmonic of the bus frequency
#define ROSC_RANDOMBIT_OFFSET _u(0x00000020)
#define ROSC_RANDOMBIT_BITS _u(0x00000001)
#define ROSC_RANDOMBIT_RESET _u(0x00000001)
#define ROSC_RANDOMBIT_MSB _u(0)
#define ROSC_RANDOMBIT_LSB _u(0)
#define ROSC_RANDOMBIT_ACCESS "RO"
// =============================================================================
// Register : ROSC_COUNT
// Description : A down counter running at the ROSC frequency which counts to
// zero and stops.
// To start the counter write a non-zero value.
// Can be used for short software pauses when setting up time
// sensitive hardware.
#define ROSC_COUNT_OFFSET _u(0x00000024)
#define ROSC_COUNT_BITS _u(0x0000ffff)
#define ROSC_COUNT_RESET _u(0x00000000)
#define ROSC_COUNT_MSB _u(15)
#define ROSC_COUNT_LSB _u(0)
#define ROSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_ROSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : RP_AP
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_RP_AP_H
#define _HARDWARE_REGS_RP_AP_H
// =============================================================================
// Register : RP_AP_CTRL
// Description : This register is primarily used for DFT but can also be used to
// overcome some power up problems. However, it should not be used
// to force power up of domains. Use DBG_POW_OVRD for that.
#define RP_AP_CTRL_OFFSET _u(0x00000000)
#define RP_AP_CTRL_BITS _u(0xc000007f)
#define RP_AP_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_RESCUE_RESTART
// Description : Allows debug of boot problems by restarting the chip with
// minimal boot code execution. Write to 1 to put the chip in
// reset then write to 0 to restart the chip with the rescue flag
// set. The rescue flag is in the POWMAN_CHIP_RESET register and
// is read by boot code. The rescue flag is cleared by writing 0
// to POWMAN_CHIP_RESET_RESCUE_FLAG or by resetting the chip by
// any means other than RESCUE_RESTART.
#define RP_AP_CTRL_RESCUE_RESTART_RESET _u(0x0)
#define RP_AP_CTRL_RESCUE_RESTART_BITS _u(0x80000000)
#define RP_AP_CTRL_RESCUE_RESTART_MSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_LSB _u(31)
#define RP_AP_CTRL_RESCUE_RESTART_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_SPARE
// Description : Unused
#define RP_AP_CTRL_SPARE_RESET _u(0x0)
#define RP_AP_CTRL_SPARE_BITS _u(0x40000000)
#define RP_AP_CTRL_SPARE_MSB _u(30)
#define RP_AP_CTRL_SPARE_LSB _u(30)
#define RP_AP_CTRL_SPARE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_DBG_FRCE_GPIO_LPCK
// Description : Allows chip start-up when the Low Power Oscillator (LPOSC) is
// inoperative or malfunctioning and also allows the initial power
// sequencing rate to be adjusted. Write to 1 to force the LPOSC
// output to be driven from a GPIO (gpio20 on 80-pin package,
// gpio34 on the 60-pin package). If the LPOSC is inoperative or
// malfunctioning it may also be necessary to set the
// LPOSC_STABLE_FRCE bit in this register. The user must provide a
// clock on the GPIO. For normal operation use a clock running at
// around 32kHz. Adjusting the frequency will speed up or slow
// down the initial power-up sequence.
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_RESET _u(0x0)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_BITS _u(0x00000040)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_MSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_LSB _u(6)
#define RP_AP_CTRL_DBG_FRCE_GPIO_LPCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_LPOSC_STABLE_FRCE
// Description : Allows the chip to start-up even though the Low Power
// Oscillator (LPOSC) is failing to set its stable flag. Initial
// power sequencing is clocked by LPOSC at around 32kHz but does
// not start until the LPOSC declares itself to be stable. If the
// LPOSC is otherwise working correctly the chip will boot when
// this bit is set. If the LPOSC is not working then
// DBG_FRCE_GPIO_LPCK must be set and an external clock provided.
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_RESET _u(0x0)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_BITS _u(0x00000020)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_MSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_LSB _u(5)
#define RP_AP_CTRL_LPOSC_STABLE_FRCE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_ISO_OFF
// Description : Holds the isolation gates between power domains in the open
// state. This is intended to hold the gates open for DFT and
// power manager debug. It is not intended to force the isolation
// gates open. Use the overrides in DBG_POW_OVRD to force the
// isolation gates open or closed.
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_BITS _u(0x00000010)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_MSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_LSB _u(4)
#define RP_AP_CTRL_POWMAN_DFT_ISO_OFF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DFT_PWRON
// Description : Holds the power switches on for all domains. This is intended
// to keep the power on for DFT and debug, rather than for
// switching the power on. The power switches are not sequenced
// and the sudden demand for current could cause the always-on
// power domain to brown out. This register is in the always-on
// domain therefore chaos could ensue. It is recommended to use
// the DBG_POW_OVRD controls instead.
#define RP_AP_CTRL_POWMAN_DFT_PWRON_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_BITS _u(0x00000008)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_MSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_LSB _u(3)
#define RP_AP_CTRL_POWMAN_DFT_PWRON_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_POWMAN_DBGMODE
// Description : This prevents the power manager from powering down and
// resetting the switched-core power domain. It is intended for
// DFT and for debugging the power manager after the chip has
// booted. It cannot be used to force initial power on because it
// simultaneously deasserts the reset.
#define RP_AP_CTRL_POWMAN_DBGMODE_RESET _u(0x0)
#define RP_AP_CTRL_POWMAN_DBGMODE_BITS _u(0x00000004)
#define RP_AP_CTRL_POWMAN_DBGMODE_MSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_LSB _u(2)
#define RP_AP_CTRL_POWMAN_DBGMODE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_FUNCSEL
// Description : Multiplexes the JTAG ports onto GPIO0-3
#define RP_AP_CTRL_JTAG_FUNCSEL_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_FUNCSEL_BITS _u(0x00000002)
#define RP_AP_CTRL_JTAG_FUNCSEL_MSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_LSB _u(1)
#define RP_AP_CTRL_JTAG_FUNCSEL_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_CTRL_JTAG_TRSTN
// Description : Resets the JTAG module. Active low.
#define RP_AP_CTRL_JTAG_TRSTN_RESET _u(0x0)
#define RP_AP_CTRL_JTAG_TRSTN_BITS _u(0x00000001)
#define RP_AP_CTRL_JTAG_TRSTN_MSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_LSB _u(0)
#define RP_AP_CTRL_JTAG_TRSTN_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBGKEY
// Description : Serial key load interface (write-only)
#define RP_AP_DBGKEY_OFFSET _u(0x00000004)
#define RP_AP_DBGKEY_BITS _u(0x00000007)
#define RP_AP_DBGKEY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_RESET
// Description : Reset (before sending a new key)
#define RP_AP_DBGKEY_RESET_RESET _u(0x0)
#define RP_AP_DBGKEY_RESET_BITS _u(0x00000004)
#define RP_AP_DBGKEY_RESET_MSB _u(2)
#define RP_AP_DBGKEY_RESET_LSB _u(2)
#define RP_AP_DBGKEY_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_PUSH
#define RP_AP_DBGKEY_PUSH_RESET _u(0x0)
#define RP_AP_DBGKEY_PUSH_BITS _u(0x00000002)
#define RP_AP_DBGKEY_PUSH_MSB _u(1)
#define RP_AP_DBGKEY_PUSH_LSB _u(1)
#define RP_AP_DBGKEY_PUSH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBGKEY_DATA
#define RP_AP_DBGKEY_DATA_RESET _u(0x0)
#define RP_AP_DBGKEY_DATA_BITS _u(0x00000001)
#define RP_AP_DBGKEY_DATA_MSB _u(0)
#define RP_AP_DBGKEY_DATA_LSB _u(0)
#define RP_AP_DBGKEY_DATA_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SWCORE
// Description : This register indicates the state of the power sequencer for
// the switched-core domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
// Bits 9-11 describe the states of the power manager clocks which
// change as clock generators in the switched-core become
// available following switched-core power up.
// This bus can be sent to GPIO for debug. See
// DBG_POW_OUTPUT_TO_GPIO in the DBG_POW_OVRD register.
#define RP_AP_DBG_POW_STATE_SWCORE_OFFSET _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK
// Description : Indicates the source of the power manager clock. On switched-
// core power up the clock switches from the LPOSC to clk_ref and
// this flag will be set. clk_ref will be running from the ROSC
// initially but will switch to XOSC when it comes available. On
// switched-core power down the clock switches to LPOSC and this
// flag will be cleared.
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_BITS _u(0x00000800)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_MSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_LSB _u(11)
#define RP_AP_DBG_POW_STATE_SWCORE_USING_FAST_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK
// Description : Indicates the switched-core power sequencer is waiting for the
// power manager clock to update. On switched-core power up the
// clock switches from the LPOSC to clk_ref. clk_ref will be
// running from the ROSC initially but will switch to XOSC when it
// comes available. On switched-core power down the clock switches
// to LPOSC.
// If the switched-core power up sequence stalls with this flag
// active then it means clk_ref is not running which indicates a
// problem with the ROSC. If that happens then set
// DBG_POW_RESTART_FROM_XOSC in the DBG_POW_OVRD register to avoid
// using the ROSC.
// If the switched-core power down sequence stalls with this flag
// active then it means LPOSC is not running. The solution is to
// not stop LPOSC when the switched-core power domain is powered.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_BITS _u(0x00000400)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_MSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_LSB _u(10)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_POWCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK
// Description : Indicates that the switched-core power sequencer is waiting for
// the AON-Timer to update. On switched-core power-up there is
// nothing to be done. The AON-Timer continues to run from the
// LPOSC so this flag will not be set. Software decides whether to
// switch the AON-Timer clock to XOSC (via clk_ref). On switched-
// core power-down the sequencer will switch the AON-Timer back to
// LPOSC if software switched it to XOSC. During the switchover
// the WAITING_TIMCK flag will be set. If the switched-core power
// down sequence stalls with this flag active then the only
// recourse is to reset the chip and change software to not select
// XOSC as the AON-Timer source.
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_BITS _u(0x00000200)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_MSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_LSB _u(9)
#define RP_AP_DBG_POW_STATE_SWCORE_WAITING_TIMCK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SWCORE_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SWCORE_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SWCORE_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SWCORE_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SWCORE_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SWCORE_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SWCORE_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_XIP
// Description : This register indicates the state of the power sequencer for
// the XIP domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_XIP_OFFSET _u(0x0000000c)
#define RP_AP_DBG_POW_STATE_XIP_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_XIP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_XIP_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_XIP_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_XIP_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_XIP_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_XIP_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_XIP_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_XIP_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_XIP_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM0
// Description : This register indicates the state of the power sequencer for
// the SRAM0 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM0_OFFSET _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM0_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM0_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM0_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM0_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM0_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM0_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM0_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_STATE_SRAM1
// Description : This register indicates the state of the power sequencer for
// the SRAM1 domain.
// The sequencer timing is managed by the POWMAN_SEQ_* registers.
// See the header file for those registers for more information on
// the timing.
// Power up of the domain commences by clearing bit 0 (IS_PD) then
// bits 1-8 are set in sequence. Bit 8 (IS_PU) indicates the
// sequence is complete.
// Power down of the domain commences by clearing bit 8 (IS_PU)
// then bits 7-1 are cleared in sequence. Bit 0 (IS_PU) is then
// set to indicate the sequence is complete.
#define RP_AP_DBG_POW_STATE_SRAM1_OFFSET _u(0x00000014)
#define RP_AP_DBG_POW_STATE_SRAM1_BITS _u(0x000001ff)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PU
// Description : Indicates the power somain is fully powered up.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_BITS _u(0x00000100)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_MSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_LSB _u(8)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PU_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ
// Description : Indicates the state of the reset to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_BITS _u(0x00000080)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_MSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_LSB _u(7)
#define RP_AP_DBG_POW_STATE_SRAM1_RESET_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK
// Description : Indicates the state of the enable to the power domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_BITS _u(0x00000040)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_MSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_LSB _u(6)
#define RP_AP_DBG_POW_STATE_SRAM1_ENAB_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ
// Description : Indicates the state of the isolation control to the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_BITS _u(0x00000020)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_MSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_LSB _u(5)
#define RP_AP_DBG_POW_STATE_SRAM1_ISOLATE_FROM_SEQ_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK
// Description : Indicates the state of the large power switches for the power
// domain.
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_BITS _u(0x00000010)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_MSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_LSB _u(4)
#define RP_AP_DBG_POW_STATE_SRAM1_LARGE_ACK_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2
// Description : The small switches are split into 3 chains. In the power up
// sequence they are switched on separately to allow management of
// the VDD rise time. In the power down sequence they switch off
// simultaneously with the large power switches.
// This bit indicates the state of the last element in small power
// switch chain 2.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_BITS _u(0x00000008)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_MSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_LSB _u(3)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1
// Description : This bit indicates the state of the last element in small power
// switch chain 1.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_BITS _u(0x00000004)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_MSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_LSB _u(2)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0
// Description : This bit indicates the state of the last element in small power
// switch chain 0.
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_BITS _u(0x00000002)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_MSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_LSB _u(1)
#define RP_AP_DBG_POW_STATE_SRAM1_SMALL_ACK0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_STATE_SRAM1_IS_PD
// Description : Indicates the power somain is fully powered down.
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_RESET _u(0x0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_BITS _u(0x00000001)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_MSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_LSB _u(0)
#define RP_AP_DBG_POW_STATE_SRAM1_IS_PD_ACCESS "RO"
// =============================================================================
// Register : RP_AP_DBG_POW_OVRD
// Description : This register allows external control of the power sequencer
// outputs for all the switched power domains. If any of the power
// sequencers stall at any stage then force power up operation of
// all domains by running this sequence:
// - set DBG_POW_OVRD = 0x3b to force small power switches on,
// large power switches off, resets on and isolation on
// - allow time for the domain power supplies to reach full rail
// - set DBG_POW_OVRD = 0x3b to force large power switches on
// - set DBG_POW_OVRD = 0x37 to remove isolation
// - set DBG_POW_OVRD = 0x17 to remove resets
#define RP_AP_DBG_POW_OVRD_OFFSET _u(0x00000018)
#define RP_AP_DBG_POW_OVRD_BITS _u(0x0000007f)
#define RP_AP_DBG_POW_OVRD_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC
// Description : By default the system begins boot as soon as a clock is
// available from the ROSC, then it switches to the XOSC when it
// is available. This is done because the XOSC takes several ms to
// start up. If there is a problem with the ROSC then the default
// behaviour can be changed to not use the ROSC and wait for XOSC.
// However, this requires a mask change to modify the reset value
// of the Power Manager START_FROM_XOSC register. To allow
// experimentation the default can be temporarily changed by
// setting this register bit to 1. After setting this bit the core
// must be reset by a Coresight dprst or a rescue reset (see
// RESCUE_RESTART in the RP_AP_CTRL register above). A power-on
// reset, brown-out reset or RUN pin reset will reset this control
// and revert to the default behaviour.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_BITS _u(0x00000040)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_MSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_LSB _u(6)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESTART_FROM_XOSC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_RESET
// Description : When DBG_POW_OVRD_RESET=1 this register bit controls the resets
// for all domains. 1 = reset. 0 = not reset.
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_BITS _u(0x00000020)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_MSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_LSB _u(5)
#define RP_AP_DBG_POW_OVRD_DBG_POW_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET
// Description : Enables DBG_POW_RESET to control the resets for the power
// manager and the switched-core. Essentially that is everythjing
// except the Coresight 2-wire interface and the RP_AP registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_BITS _u(0x00000010)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_MSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_LSB _u(4)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_RESET_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_ISO
// Description : When DBG_POW_OVRD_ISO=1 this register bit controls the
// isolation gates for all domains. 1 = isolated. 0 = not
// isolated.
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_BITS _u(0x00000008)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_MSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_LSB _u(3)
#define RP_AP_DBG_POW_OVRD_DBG_POW_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO
// Description : Enables DBG_POW_ISO to control the isolation gates between
// domains.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_BITS _u(0x00000004)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_MSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_LSB _u(2)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_ISO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ
// Description : Turn on the large power switches for all domains. This should
// not be done until sufficient time has been allowed for the
// small switches to bring the supplies up. Switching the large
// switches on too soon risks browning out the always-on domain
// and corrupting these very registers.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_BITS _u(0x00000002)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_MSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_LSB _u(1)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_LARGE_REQ_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ
// Description : Turn on the small power switches for all domains. This switches
// on chain 0 for each domain and switches off chains 2 & 3 and
// the large power switch chain. This will bring the power up for
// all domains without browning out the always-on power domain.
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_RESET _u(0x0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_BITS _u(0x00000001)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_MSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_LSB _u(0)
#define RP_AP_DBG_POW_OVRD_DBG_POW_OVRD_SMALL_REQ_ACCESS "RW"
// =============================================================================
// Register : RP_AP_DBG_POW_OUTPUT_TO_GPIO
// Description : Send some, or all, bits of DBG_POW_STATE_SWCORE to gpios.
// Bit 0 sends bit 0 of DBG_POW_STATE_SWCORE to GPIO 34
// Bit 1 sends bit 1 of DBG_POW_STATE_SWCORE to GPIO 35
// Bit 2 sends bit 2 of DBG_POW_STATE_SWCORE to GPIO 36
// .
// .
// Bit 11 sends bit 11 of DBG_POW_STATE_SWCORE to GPIO 45
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_OFFSET _u(0x0000001c)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_RESET _u(0x000)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_BITS _u(0x00000fff)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_MSB _u(11)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_LSB _u(0)
#define RP_AP_DBG_POW_OUTPUT_TO_GPIO_ENABLE_ACCESS "RW"
// =============================================================================
// Register : RP_AP_IDR
// Description : Standard Coresight ID Register
#define RP_AP_IDR_OFFSET _u(0x00000dfc)
#define RP_AP_IDR_BITS _u(0xffffffff)
#define RP_AP_IDR_RESET "-"
#define RP_AP_IDR_MSB _u(31)
#define RP_AP_IDR_LSB _u(0)
#define RP_AP_IDR_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_RP_AP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SHA256
// Version : 1
// Bus type : apb
// Description : SHA-256 hash function implementation
// =============================================================================
#ifndef _HARDWARE_REGS_SHA256_H
#define _HARDWARE_REGS_SHA256_H
// =============================================================================
// Register : SHA256_CSR
// Description : Control and status register
#define SHA256_CSR_OFFSET _u(0x00000000)
#define SHA256_CSR_BITS _u(0x00001317)
#define SHA256_CSR_RESET _u(0x00001206)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_BSWAP
// Description : Enable byte swapping of 32-bit values at the point they are
// committed to the SHA message scheduler.
//
// This block's bus interface assembles byte/halfword data into
// message words in little-endian order, so that DMAing the same
// buffer with different transfer sizes always gives the same
// result on a little-endian system like RP2350.
//
// However, when marshalling bytes into blocks, SHA expects that
// the first byte is the *most significant* in each message word.
// To resolve this, once the bus interface has accumulated 32 bits
// of data (either a word write, two halfword writes in little-
// endian order, or four byte writes in little-endian order) the
// final value can be byte-swapped before passing to the actual
// SHA core.
//
// This feature is enabled by default because using the SHA core
// to checksum byte buffers is expected to be more common than
// having preformatted SHA message words lying around.
#define SHA256_CSR_BSWAP_RESET _u(0x1)
#define SHA256_CSR_BSWAP_BITS _u(0x00001000)
#define SHA256_CSR_BSWAP_MSB _u(12)
#define SHA256_CSR_BSWAP_LSB _u(12)
#define SHA256_CSR_BSWAP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_DMA_SIZE
// Description : Configure DREQ logic for the correct DMA data size. Must be
// configured before the DMA channel is triggered.
//
// The SHA-256 core's DREQ logic requests one entire block of data
// at once, since there is no FIFO, and data goes straight into
// the core's message schedule and digest hardware. Therefore,
// when transferring data with DMA, CSR_DMA_SIZE must be
// configured in advance so that the correct number of transfers
// can be requested per block.
// 0x0 -> 8bit
// 0x1 -> 16bit
// 0x2 -> 32bit
#define SHA256_CSR_DMA_SIZE_RESET _u(0x2)
#define SHA256_CSR_DMA_SIZE_BITS _u(0x00000300)
#define SHA256_CSR_DMA_SIZE_MSB _u(9)
#define SHA256_CSR_DMA_SIZE_LSB _u(8)
#define SHA256_CSR_DMA_SIZE_ACCESS "RW"
#define SHA256_CSR_DMA_SIZE_VALUE_8BIT _u(0x0)
#define SHA256_CSR_DMA_SIZE_VALUE_16BIT _u(0x1)
#define SHA256_CSR_DMA_SIZE_VALUE_32BIT _u(0x2)
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_ERR_WDATA_NOT_RDY
// Description : Set when a write occurs whilst the SHA-256 core is not ready
// for data (WDATA_RDY is low). Write one to clear.
#define SHA256_CSR_ERR_WDATA_NOT_RDY_RESET _u(0x0)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_BITS _u(0x00000010)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_MSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_LSB _u(4)
#define SHA256_CSR_ERR_WDATA_NOT_RDY_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_SUM_VLD
// Description : If 1, the SHA-256 checksum presented in registers SUM0 through
// SUM7 is currently valid.
//
// Goes low when WDATA is first written, then returns high once 16
// words have been written and the digest of the current 512-bit
// block has subsequently completed.
#define SHA256_CSR_SUM_VLD_RESET _u(0x1)
#define SHA256_CSR_SUM_VLD_BITS _u(0x00000004)
#define SHA256_CSR_SUM_VLD_MSB _u(2)
#define SHA256_CSR_SUM_VLD_LSB _u(2)
#define SHA256_CSR_SUM_VLD_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_WDATA_RDY
// Description : If 1, the SHA-256 core is ready to accept more data through the
// WDATA register.
//
// After writing 16 words, this flag will go low for 57 cycles
// whilst the core completes its digest.
#define SHA256_CSR_WDATA_RDY_RESET _u(0x1)
#define SHA256_CSR_WDATA_RDY_BITS _u(0x00000002)
#define SHA256_CSR_WDATA_RDY_MSB _u(1)
#define SHA256_CSR_WDATA_RDY_LSB _u(1)
#define SHA256_CSR_WDATA_RDY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SHA256_CSR_START
// Description : Write 1 to prepare the SHA-256 core for a new checksum.
//
// The SUMx registers are initialised to the proper values
// (fractional bits of square roots of first 8 primes) and
// internal counters are cleared. This immediately forces
// WDATA_RDY and SUM_VLD high.
//
// START must be written before initiating a DMA transfer to the
// SHA-256 core, because the core will always request 16 transfers
// at a time (1 512-bit block). Additionally, the DMA channel
// should be configured for a multiple of 16 32-bit transfers.
#define SHA256_CSR_START_RESET _u(0x0)
#define SHA256_CSR_START_BITS _u(0x00000001)
#define SHA256_CSR_START_MSB _u(0)
#define SHA256_CSR_START_LSB _u(0)
#define SHA256_CSR_START_ACCESS "SC"
// =============================================================================
// Register : SHA256_WDATA
// Description : Write data register
// After pulsing START and writing 16 words of data to this
// register, WDATA_RDY will go low and the SHA-256 core will
// complete the digest of the current 512-bit block.
//
// Software is responsible for ensuring the data is correctly
// padded and terminated to a whole number of 512-bit blocks.
//
// After this, WDATA_RDY will return high, and more data can be
// written (if any).
//
// This register supports word, halfword and byte writes, so that
// DMA from non-word-aligned buffers can be supported. The total
// amount of data per block remains the same (16 words, 32
// halfwords or 64 bytes) and byte/halfword transfers must not be
// mixed within a block.
#define SHA256_WDATA_OFFSET _u(0x00000004)
#define SHA256_WDATA_BITS _u(0xffffffff)
#define SHA256_WDATA_RESET _u(0x00000000)
#define SHA256_WDATA_MSB _u(31)
#define SHA256_WDATA_LSB _u(0)
#define SHA256_WDATA_ACCESS "WF"
// =============================================================================
// Register : SHA256_SUM0
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM0_OFFSET _u(0x00000008)
#define SHA256_SUM0_BITS _u(0xffffffff)
#define SHA256_SUM0_RESET _u(0x00000000)
#define SHA256_SUM0_MSB _u(31)
#define SHA256_SUM0_LSB _u(0)
#define SHA256_SUM0_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM1
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM1_OFFSET _u(0x0000000c)
#define SHA256_SUM1_BITS _u(0xffffffff)
#define SHA256_SUM1_RESET _u(0x00000000)
#define SHA256_SUM1_MSB _u(31)
#define SHA256_SUM1_LSB _u(0)
#define SHA256_SUM1_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM2
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM2_OFFSET _u(0x00000010)
#define SHA256_SUM2_BITS _u(0xffffffff)
#define SHA256_SUM2_RESET _u(0x00000000)
#define SHA256_SUM2_MSB _u(31)
#define SHA256_SUM2_LSB _u(0)
#define SHA256_SUM2_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM3
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM3_OFFSET _u(0x00000014)
#define SHA256_SUM3_BITS _u(0xffffffff)
#define SHA256_SUM3_RESET _u(0x00000000)
#define SHA256_SUM3_MSB _u(31)
#define SHA256_SUM3_LSB _u(0)
#define SHA256_SUM3_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM4
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM4_OFFSET _u(0x00000018)
#define SHA256_SUM4_BITS _u(0xffffffff)
#define SHA256_SUM4_RESET _u(0x00000000)
#define SHA256_SUM4_MSB _u(31)
#define SHA256_SUM4_LSB _u(0)
#define SHA256_SUM4_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM5
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM5_OFFSET _u(0x0000001c)
#define SHA256_SUM5_BITS _u(0xffffffff)
#define SHA256_SUM5_RESET _u(0x00000000)
#define SHA256_SUM5_MSB _u(31)
#define SHA256_SUM5_LSB _u(0)
#define SHA256_SUM5_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM6
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM6_OFFSET _u(0x00000020)
#define SHA256_SUM6_BITS _u(0xffffffff)
#define SHA256_SUM6_RESET _u(0x00000000)
#define SHA256_SUM6_MSB _u(31)
#define SHA256_SUM6_LSB _u(0)
#define SHA256_SUM6_ACCESS "RO"
// =============================================================================
// Register : SHA256_SUM7
// Description : 256-bit checksum result. Contents are undefined when
// CSR_SUM_VLD is 0.
#define SHA256_SUM7_OFFSET _u(0x00000024)
#define SHA256_SUM7_BITS _u(0xffffffff)
#define SHA256_SUM7_RESET _u(0x00000000)
#define SHA256_SUM7_MSB _u(31)
#define SHA256_SUM7_LSB _u(0)
#define SHA256_SUM7_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SHA256_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SPI
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SPI_H
#define _HARDWARE_REGS_SPI_H
// =============================================================================
// Register : SPI_SSPCR0
// Description : Control register 0, SSPCR0 on page 3-4
#define SPI_SSPCR0_OFFSET _u(0x00000000)
#define SPI_SSPCR0_BITS _u(0x0000ffff)
#define SPI_SSPCR0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SCR
// Description : Serial clock rate. The value SCR is used to generate the
// transmit and receive bit rate of the PrimeCell SSP. The bit
// rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even
// value from 2-254, programmed through the SSPCPSR register and
// SCR is a value from 0-255.
#define SPI_SSPCR0_SCR_RESET _u(0x00)
#define SPI_SSPCR0_SCR_BITS _u(0x0000ff00)
#define SPI_SSPCR0_SCR_MSB _u(15)
#define SPI_SSPCR0_SCR_LSB _u(8)
#define SPI_SSPCR0_SCR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPH
// Description : SSPCLKOUT phase, applicable to Motorola SPI frame format only.
// See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPH_RESET _u(0x0)
#define SPI_SSPCR0_SPH_BITS _u(0x00000080)
#define SPI_SSPCR0_SPH_MSB _u(7)
#define SPI_SSPCR0_SPH_LSB _u(7)
#define SPI_SSPCR0_SPH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_SPO
// Description : SSPCLKOUT polarity, applicable to Motorola SPI frame format
// only. See Motorola SPI frame format on page 2-10.
#define SPI_SSPCR0_SPO_RESET _u(0x0)
#define SPI_SSPCR0_SPO_BITS _u(0x00000040)
#define SPI_SSPCR0_SPO_MSB _u(6)
#define SPI_SSPCR0_SPO_LSB _u(6)
#define SPI_SSPCR0_SPO_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_FRF
// Description : Frame format: 00 Motorola SPI frame format. 01 TI synchronous
// serial frame format. 10 National Microwire frame format. 11
// Reserved, undefined operation.
#define SPI_SSPCR0_FRF_RESET _u(0x0)
#define SPI_SSPCR0_FRF_BITS _u(0x00000030)
#define SPI_SSPCR0_FRF_MSB _u(5)
#define SPI_SSPCR0_FRF_LSB _u(4)
#define SPI_SSPCR0_FRF_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR0_DSS
// Description : Data Size Select: 0000 Reserved, undefined operation. 0001
// Reserved, undefined operation. 0010 Reserved, undefined
// operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data.
// 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data.
// 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
#define SPI_SSPCR0_DSS_RESET _u(0x0)
#define SPI_SSPCR0_DSS_BITS _u(0x0000000f)
#define SPI_SSPCR0_DSS_MSB _u(3)
#define SPI_SSPCR0_DSS_LSB _u(0)
#define SPI_SSPCR0_DSS_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPCR1
// Description : Control register 1, SSPCR1 on page 3-5
#define SPI_SSPCR1_OFFSET _u(0x00000004)
#define SPI_SSPCR1_BITS _u(0x0000000f)
#define SPI_SSPCR1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SOD
// Description : Slave-mode output disable. This bit is relevant only in the
// slave mode, MS=1. In multiple-slave systems, it is possible for
// an PrimeCell SSP master to broadcast a message to all slaves in
// the system while ensuring that only one slave drives data onto
// its serial output line. In such systems the RXD lines from
// multiple slaves could be tied together. To operate in such
// systems, the SOD bit can be set if the PrimeCell SSP slave is
// not supposed to drive the SSPTXD line: 0 SSP can drive the
// SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
// output in slave mode.
#define SPI_SSPCR1_SOD_RESET _u(0x0)
#define SPI_SSPCR1_SOD_BITS _u(0x00000008)
#define SPI_SSPCR1_SOD_MSB _u(3)
#define SPI_SSPCR1_SOD_LSB _u(3)
#define SPI_SSPCR1_SOD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_MS
// Description : Master or slave mode select. This bit can be modified only when
// the PrimeCell SSP is disabled, SSE=0: 0 Device configured as
// master, default. 1 Device configured as slave.
#define SPI_SSPCR1_MS_RESET _u(0x0)
#define SPI_SSPCR1_MS_BITS _u(0x00000004)
#define SPI_SSPCR1_MS_MSB _u(2)
#define SPI_SSPCR1_MS_LSB _u(2)
#define SPI_SSPCR1_MS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_SSE
// Description : Synchronous serial port enable: 0 SSP operation disabled. 1 SSP
// operation enabled.
#define SPI_SSPCR1_SSE_RESET _u(0x0)
#define SPI_SSPCR1_SSE_BITS _u(0x00000002)
#define SPI_SSPCR1_SSE_MSB _u(1)
#define SPI_SSPCR1_SSE_LSB _u(1)
#define SPI_SSPCR1_SSE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPCR1_LBM
// Description : Loop back mode: 0 Normal serial port operation enabled. 1
// Output of transmit serial shifter is connected to input of
// receive serial shifter internally.
#define SPI_SSPCR1_LBM_RESET _u(0x0)
#define SPI_SSPCR1_LBM_BITS _u(0x00000001)
#define SPI_SSPCR1_LBM_MSB _u(0)
#define SPI_SSPCR1_LBM_LSB _u(0)
#define SPI_SSPCR1_LBM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPDR
// Description : Data register, SSPDR on page 3-6
#define SPI_SSPDR_OFFSET _u(0x00000008)
#define SPI_SSPDR_BITS _u(0x0000ffff)
#define SPI_SSPDR_RESET "-"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDR_DATA
// Description : Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO.
// You must right-justify data when the PrimeCell SSP is
// programmed for a data size that is less than 16 bits. Unused
// bits at the top are ignored by transmit logic. The receive
// logic automatically right-justifies.
#define SPI_SSPDR_DATA_RESET "-"
#define SPI_SSPDR_DATA_BITS _u(0x0000ffff)
#define SPI_SSPDR_DATA_MSB _u(15)
#define SPI_SSPDR_DATA_LSB _u(0)
#define SPI_SSPDR_DATA_ACCESS "RWF"
// =============================================================================
// Register : SPI_SSPSR
// Description : Status register, SSPSR on page 3-7
#define SPI_SSPSR_OFFSET _u(0x0000000c)
#define SPI_SSPSR_BITS _u(0x0000001f)
#define SPI_SSPSR_RESET _u(0x00000003)
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_BSY
// Description : PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently
// transmitting and/or receiving a frame or the transmit FIFO is
// not empty.
#define SPI_SSPSR_BSY_RESET _u(0x0)
#define SPI_SSPSR_BSY_BITS _u(0x00000010)
#define SPI_SSPSR_BSY_MSB _u(4)
#define SPI_SSPSR_BSY_LSB _u(4)
#define SPI_SSPSR_BSY_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RFF
// Description : Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive
// FIFO is full.
#define SPI_SSPSR_RFF_RESET _u(0x0)
#define SPI_SSPSR_RFF_BITS _u(0x00000008)
#define SPI_SSPSR_RFF_MSB _u(3)
#define SPI_SSPSR_RFF_LSB _u(3)
#define SPI_SSPSR_RFF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_RNE
// Description : Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive
// FIFO is not empty.
#define SPI_SSPSR_RNE_RESET _u(0x0)
#define SPI_SSPSR_RNE_BITS _u(0x00000004)
#define SPI_SSPSR_RNE_MSB _u(2)
#define SPI_SSPSR_RNE_LSB _u(2)
#define SPI_SSPSR_RNE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TNF
// Description : Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit
// FIFO is not full.
#define SPI_SSPSR_TNF_RESET _u(0x1)
#define SPI_SSPSR_TNF_BITS _u(0x00000002)
#define SPI_SSPSR_TNF_MSB _u(1)
#define SPI_SSPSR_TNF_LSB _u(1)
#define SPI_SSPSR_TNF_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPSR_TFE
// Description : Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1
// Transmit FIFO is empty.
#define SPI_SSPSR_TFE_RESET _u(0x1)
#define SPI_SSPSR_TFE_BITS _u(0x00000001)
#define SPI_SSPSR_TFE_MSB _u(0)
#define SPI_SSPSR_TFE_LSB _u(0)
#define SPI_SSPSR_TFE_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPCPSR
// Description : Clock prescale register, SSPCPSR on page 3-8
#define SPI_SSPCPSR_OFFSET _u(0x00000010)
#define SPI_SSPCPSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPCPSR_CPSDVSR
// Description : Clock prescale divisor. Must be an even number from 2-254,
// depending on the frequency of SSPCLK. The least significant bit
// always returns zero on reads.
#define SPI_SSPCPSR_CPSDVSR_RESET _u(0x00)
#define SPI_SSPCPSR_CPSDVSR_BITS _u(0x000000ff)
#define SPI_SSPCPSR_CPSDVSR_MSB _u(7)
#define SPI_SSPCPSR_CPSDVSR_LSB _u(0)
#define SPI_SSPCPSR_CPSDVSR_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPIMSC
// Description : Interrupt mask set or clear register, SSPIMSC on page 3-9
#define SPI_SSPIMSC_OFFSET _u(0x00000014)
#define SPI_SSPIMSC_BITS _u(0x0000000f)
#define SPI_SSPIMSC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_TXIM
// Description : Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or
// less condition interrupt is masked. 1 Transmit FIFO half empty
// or less condition interrupt is not masked.
#define SPI_SSPIMSC_TXIM_RESET _u(0x0)
#define SPI_SSPIMSC_TXIM_BITS _u(0x00000008)
#define SPI_SSPIMSC_TXIM_MSB _u(3)
#define SPI_SSPIMSC_TXIM_LSB _u(3)
#define SPI_SSPIMSC_TXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RXIM
// Description : Receive FIFO interrupt mask: 0 Receive FIFO half full or less
// condition interrupt is masked. 1 Receive FIFO half full or less
// condition interrupt is not masked.
#define SPI_SSPIMSC_RXIM_RESET _u(0x0)
#define SPI_SSPIMSC_RXIM_BITS _u(0x00000004)
#define SPI_SSPIMSC_RXIM_MSB _u(2)
#define SPI_SSPIMSC_RXIM_LSB _u(2)
#define SPI_SSPIMSC_RXIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RTIM
// Description : Receive timeout interrupt mask: 0 Receive FIFO not empty and no
// read prior to timeout period interrupt is masked. 1 Receive
// FIFO not empty and no read prior to timeout period interrupt is
// not masked.
#define SPI_SSPIMSC_RTIM_RESET _u(0x0)
#define SPI_SSPIMSC_RTIM_BITS _u(0x00000002)
#define SPI_SSPIMSC_RTIM_MSB _u(1)
#define SPI_SSPIMSC_RTIM_LSB _u(1)
#define SPI_SSPIMSC_RTIM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPIMSC_RORIM
// Description : Receive overrun interrupt mask: 0 Receive FIFO written to while
// full condition interrupt is masked. 1 Receive FIFO written to
// while full condition interrupt is not masked.
#define SPI_SSPIMSC_RORIM_RESET _u(0x0)
#define SPI_SSPIMSC_RORIM_BITS _u(0x00000001)
#define SPI_SSPIMSC_RORIM_MSB _u(0)
#define SPI_SSPIMSC_RORIM_LSB _u(0)
#define SPI_SSPIMSC_RORIM_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPRIS
// Description : Raw interrupt status register, SSPRIS on page 3-10
#define SPI_SSPRIS_OFFSET _u(0x00000018)
#define SPI_SSPRIS_BITS _u(0x0000000f)
#define SPI_SSPRIS_RESET _u(0x00000008)
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_TXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPTXINTR interrupt
#define SPI_SSPRIS_TXRIS_RESET _u(0x1)
#define SPI_SSPRIS_TXRIS_BITS _u(0x00000008)
#define SPI_SSPRIS_TXRIS_MSB _u(3)
#define SPI_SSPRIS_TXRIS_LSB _u(3)
#define SPI_SSPRIS_TXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RXRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRXINTR interrupt
#define SPI_SSPRIS_RXRIS_RESET _u(0x0)
#define SPI_SSPRIS_RXRIS_BITS _u(0x00000004)
#define SPI_SSPRIS_RXRIS_MSB _u(2)
#define SPI_SSPRIS_RXRIS_LSB _u(2)
#define SPI_SSPRIS_RXRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RTRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRTINTR interrupt
#define SPI_SSPRIS_RTRIS_RESET _u(0x0)
#define SPI_SSPRIS_RTRIS_BITS _u(0x00000002)
#define SPI_SSPRIS_RTRIS_MSB _u(1)
#define SPI_SSPRIS_RTRIS_LSB _u(1)
#define SPI_SSPRIS_RTRIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPRIS_RORRIS
// Description : Gives the raw interrupt state, prior to masking, of the
// SSPRORINTR interrupt
#define SPI_SSPRIS_RORRIS_RESET _u(0x0)
#define SPI_SSPRIS_RORRIS_BITS _u(0x00000001)
#define SPI_SSPRIS_RORRIS_MSB _u(0)
#define SPI_SSPRIS_RORRIS_LSB _u(0)
#define SPI_SSPRIS_RORRIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPMIS
// Description : Masked interrupt status register, SSPMIS on page 3-11
#define SPI_SSPMIS_OFFSET _u(0x0000001c)
#define SPI_SSPMIS_BITS _u(0x0000000f)
#define SPI_SSPMIS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_TXMIS
// Description : Gives the transmit FIFO masked interrupt state, after masking,
// of the SSPTXINTR interrupt
#define SPI_SSPMIS_TXMIS_RESET _u(0x0)
#define SPI_SSPMIS_TXMIS_BITS _u(0x00000008)
#define SPI_SSPMIS_TXMIS_MSB _u(3)
#define SPI_SSPMIS_TXMIS_LSB _u(3)
#define SPI_SSPMIS_TXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RXMIS
// Description : Gives the receive FIFO masked interrupt state, after masking,
// of the SSPRXINTR interrupt
#define SPI_SSPMIS_RXMIS_RESET _u(0x0)
#define SPI_SSPMIS_RXMIS_BITS _u(0x00000004)
#define SPI_SSPMIS_RXMIS_MSB _u(2)
#define SPI_SSPMIS_RXMIS_LSB _u(2)
#define SPI_SSPMIS_RXMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RTMIS
// Description : Gives the receive timeout masked interrupt state, after
// masking, of the SSPRTINTR interrupt
#define SPI_SSPMIS_RTMIS_RESET _u(0x0)
#define SPI_SSPMIS_RTMIS_BITS _u(0x00000002)
#define SPI_SSPMIS_RTMIS_MSB _u(1)
#define SPI_SSPMIS_RTMIS_LSB _u(1)
#define SPI_SSPMIS_RTMIS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPMIS_RORMIS
// Description : Gives the receive over run masked interrupt status, after
// masking, of the SSPRORINTR interrupt
#define SPI_SSPMIS_RORMIS_RESET _u(0x0)
#define SPI_SSPMIS_RORMIS_BITS _u(0x00000001)
#define SPI_SSPMIS_RORMIS_MSB _u(0)
#define SPI_SSPMIS_RORMIS_LSB _u(0)
#define SPI_SSPMIS_RORMIS_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPICR
// Description : Interrupt clear register, SSPICR on page 3-11
#define SPI_SSPICR_OFFSET _u(0x00000020)
#define SPI_SSPICR_BITS _u(0x00000003)
#define SPI_SSPICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RTIC
// Description : Clears the SSPRTINTR interrupt
#define SPI_SSPICR_RTIC_RESET _u(0x0)
#define SPI_SSPICR_RTIC_BITS _u(0x00000002)
#define SPI_SSPICR_RTIC_MSB _u(1)
#define SPI_SSPICR_RTIC_LSB _u(1)
#define SPI_SSPICR_RTIC_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : SPI_SSPICR_RORIC
// Description : Clears the SSPRORINTR interrupt
#define SPI_SSPICR_RORIC_RESET _u(0x0)
#define SPI_SSPICR_RORIC_BITS _u(0x00000001)
#define SPI_SSPICR_RORIC_MSB _u(0)
#define SPI_SSPICR_RORIC_LSB _u(0)
#define SPI_SSPICR_RORIC_ACCESS "WC"
// =============================================================================
// Register : SPI_SSPDMACR
// Description : DMA control register, SSPDMACR on page 3-12
#define SPI_SSPDMACR_OFFSET _u(0x00000024)
#define SPI_SSPDMACR_BITS _u(0x00000003)
#define SPI_SSPDMACR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_TXDMAE
// Description : Transmit DMA Enable. If this bit is set to 1, DMA for the
// transmit FIFO is enabled.
#define SPI_SSPDMACR_TXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_TXDMAE_BITS _u(0x00000002)
#define SPI_SSPDMACR_TXDMAE_MSB _u(1)
#define SPI_SSPDMACR_TXDMAE_LSB _u(1)
#define SPI_SSPDMACR_TXDMAE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SPI_SSPDMACR_RXDMAE
// Description : Receive DMA Enable. If this bit is set to 1, DMA for the
// receive FIFO is enabled.
#define SPI_SSPDMACR_RXDMAE_RESET _u(0x0)
#define SPI_SSPDMACR_RXDMAE_BITS _u(0x00000001)
#define SPI_SSPDMACR_RXDMAE_MSB _u(0)
#define SPI_SSPDMACR_RXDMAE_LSB _u(0)
#define SPI_SSPDMACR_RXDMAE_ACCESS "RW"
// =============================================================================
// Register : SPI_SSPPERIPHID0
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID0_OFFSET _u(0x00000fe0)
#define SPI_SSPPERIPHID0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_RESET _u(0x00000022)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID0_PARTNUMBER0
// Description : These bits read back as 0x22
#define SPI_SSPPERIPHID0_PARTNUMBER0_RESET _u(0x22)
#define SPI_SSPPERIPHID0_PARTNUMBER0_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID0_PARTNUMBER0_MSB _u(7)
#define SPI_SSPPERIPHID0_PARTNUMBER0_LSB _u(0)
#define SPI_SSPPERIPHID0_PARTNUMBER0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID1
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID1_OFFSET _u(0x00000fe4)
#define SPI_SSPPERIPHID1_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID1_RESET _u(0x00000010)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_DESIGNER0
// Description : These bits read back as 0x1
#define SPI_SSPPERIPHID1_DESIGNER0_RESET _u(0x1)
#define SPI_SSPPERIPHID1_DESIGNER0_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID1_DESIGNER0_MSB _u(7)
#define SPI_SSPPERIPHID1_DESIGNER0_LSB _u(4)
#define SPI_SSPPERIPHID1_DESIGNER0_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID1_PARTNUMBER1
// Description : These bits read back as 0x0
#define SPI_SSPPERIPHID1_PARTNUMBER1_RESET _u(0x0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID1_PARTNUMBER1_MSB _u(3)
#define SPI_SSPPERIPHID1_PARTNUMBER1_LSB _u(0)
#define SPI_SSPPERIPHID1_PARTNUMBER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID2
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID2_OFFSET _u(0x00000fe8)
#define SPI_SSPPERIPHID2_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID2_RESET _u(0x00000034)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_REVISION
// Description : These bits return the peripheral revision
#define SPI_SSPPERIPHID2_REVISION_RESET _u(0x3)
#define SPI_SSPPERIPHID2_REVISION_BITS _u(0x000000f0)
#define SPI_SSPPERIPHID2_REVISION_MSB _u(7)
#define SPI_SSPPERIPHID2_REVISION_LSB _u(4)
#define SPI_SSPPERIPHID2_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID2_DESIGNER1
// Description : These bits read back as 0x4
#define SPI_SSPPERIPHID2_DESIGNER1_RESET _u(0x4)
#define SPI_SSPPERIPHID2_DESIGNER1_BITS _u(0x0000000f)
#define SPI_SSPPERIPHID2_DESIGNER1_MSB _u(3)
#define SPI_SSPPERIPHID2_DESIGNER1_LSB _u(0)
#define SPI_SSPPERIPHID2_DESIGNER1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPERIPHID3
// Description : Peripheral identification registers, SSPPeriphID0-3 on page
// 3-13
#define SPI_SSPPERIPHID3_OFFSET _u(0x00000fec)
#define SPI_SSPPERIPHID3_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPERIPHID3_CONFIGURATION
// Description : These bits read back as 0x00
#define SPI_SSPPERIPHID3_CONFIGURATION_RESET _u(0x00)
#define SPI_SSPPERIPHID3_CONFIGURATION_BITS _u(0x000000ff)
#define SPI_SSPPERIPHID3_CONFIGURATION_MSB _u(7)
#define SPI_SSPPERIPHID3_CONFIGURATION_LSB _u(0)
#define SPI_SSPPERIPHID3_CONFIGURATION_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID0
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID0_OFFSET _u(0x00000ff0)
#define SPI_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_RESET _u(0x0000000d)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID0_SSPPCELLID0
// Description : These bits read back as 0x0D
#define SPI_SSPPCELLID0_SSPPCELLID0_RESET _u(0x0d)
#define SPI_SSPPCELLID0_SSPPCELLID0_BITS _u(0x000000ff)
#define SPI_SSPPCELLID0_SSPPCELLID0_MSB _u(7)
#define SPI_SSPPCELLID0_SSPPCELLID0_LSB _u(0)
#define SPI_SSPPCELLID0_SSPPCELLID0_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID1
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID1_OFFSET _u(0x00000ff4)
#define SPI_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_RESET _u(0x000000f0)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID1_SSPPCELLID1
// Description : These bits read back as 0xF0
#define SPI_SSPPCELLID1_SSPPCELLID1_RESET _u(0xf0)
#define SPI_SSPPCELLID1_SSPPCELLID1_BITS _u(0x000000ff)
#define SPI_SSPPCELLID1_SSPPCELLID1_MSB _u(7)
#define SPI_SSPPCELLID1_SSPPCELLID1_LSB _u(0)
#define SPI_SSPPCELLID1_SSPPCELLID1_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID2
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID2_OFFSET _u(0x00000ff8)
#define SPI_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_RESET _u(0x00000005)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID2_SSPPCELLID2
// Description : These bits read back as 0x05
#define SPI_SSPPCELLID2_SSPPCELLID2_RESET _u(0x05)
#define SPI_SSPPCELLID2_SSPPCELLID2_BITS _u(0x000000ff)
#define SPI_SSPPCELLID2_SSPPCELLID2_MSB _u(7)
#define SPI_SSPPCELLID2_SSPPCELLID2_LSB _u(0)
#define SPI_SSPPCELLID2_SSPPCELLID2_ACCESS "RO"
// =============================================================================
// Register : SPI_SSPPCELLID3
// Description : PrimeCell identification registers, SSPPCellID0-3 on page 3-16
#define SPI_SSPPCELLID3_OFFSET _u(0x00000ffc)
#define SPI_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_RESET _u(0x000000b1)
// -----------------------------------------------------------------------------
// Field : SPI_SSPPCELLID3_SSPPCELLID3
// Description : These bits read back as 0xB1
#define SPI_SSPPCELLID3_SSPPCELLID3_RESET _u(0xb1)
#define SPI_SSPPCELLID3_SSPPCELLID3_BITS _u(0x000000ff)
#define SPI_SSPPCELLID3_SSPPCELLID3_MSB _u(7)
#define SPI_SSPPCELLID3_SSPPCELLID3_LSB _u(0)
#define SPI_SSPPCELLID3_SSPPCELLID3_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SPI_H

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lib/pico-sdk/rp2350/hardware/regs/syscfg.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSCFG
// Version : 1
// Bus type : apb
// Description : Register block for various chip control signals
// =============================================================================
#ifndef _HARDWARE_REGS_SYSCFG_H
#define _HARDWARE_REGS_SYSCFG_H
// =============================================================================
// Register : SYSCFG_PROC_CONFIG
// Description : Configuration for processors
#define SYSCFG_PROC_CONFIG_OFFSET _u(0x00000000)
#define SYSCFG_PROC_CONFIG_BITS _u(0x00000003)
#define SYSCFG_PROC_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC1_HALTED
// Description : Indication that proc1 has halted
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_BITS _u(0x00000002)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_MSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_LSB _u(1)
#define SYSCFG_PROC_CONFIG_PROC1_HALTED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_CONFIG_PROC0_HALTED
// Description : Indication that proc0 has halted
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_RESET _u(0x0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_BITS _u(0x00000001)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_MSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_LSB _u(0)
#define SYSCFG_PROC_CONFIG_PROC0_HALTED_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 0...31.
#define SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET _u(0x00000004)
#define SYSCFG_PROC_IN_SYNC_BYPASS_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_RESET _u(0x00000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_BITS _u(0xffffffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_PROC_IN_SYNC_BYPASS_HI
// Description : For each bit, if 1, bypass the input synchronizer between that
// GPIO
// and the GPIO input register in the SIO. The input synchronizers
// should
// generally be unbypassed, to avoid injecting metastabilities
// into processors.
// If you're feeling brave, you can bypass to save two cycles of
// input
// latency. This register applies to GPIO 32...47. USB GPIO 56..57
// QSPI GPIO 58..63
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET _u(0x00000008)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_BITS _u(0xff00ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_BITS _u(0xf0000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_MSB _u(31)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_LSB _u(28)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SD_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_BITS _u(0x08000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_MSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_LSB _u(27)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_CSN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_BITS _u(0x04000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_MSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_LSB _u(26)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_QSPI_SCK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_BITS _u(0x02000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_MSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_LSB _u(25)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_RESET _u(0x0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_BITS _u(0x01000000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_MSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_LSB _u(24)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_USB_DP_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_RESET _u(0x0000)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_BITS _u(0x0000ffff)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_MSB _u(15)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_LSB _u(0)
#define SYSCFG_PROC_IN_SYNC_BYPASS_HI_GPIO_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_DBGFORCE
// Description : Directly control the chip SWD debug port
#define SYSCFG_DBGFORCE_OFFSET _u(0x0000000c)
#define SYSCFG_DBGFORCE_BITS _u(0x0000000f)
#define SYSCFG_DBGFORCE_RESET _u(0x00000006)
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_ATTACH
// Description : Attach chip debug port to syscfg controls, and disconnect it
// from external SWD pads.
#define SYSCFG_DBGFORCE_ATTACH_RESET _u(0x0)
#define SYSCFG_DBGFORCE_ATTACH_BITS _u(0x00000008)
#define SYSCFG_DBGFORCE_ATTACH_MSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_LSB _u(3)
#define SYSCFG_DBGFORCE_ATTACH_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWCLK
// Description : Directly drive SWCLK, if ATTACH is set
#define SYSCFG_DBGFORCE_SWCLK_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWCLK_BITS _u(0x00000004)
#define SYSCFG_DBGFORCE_SWCLK_MSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_LSB _u(2)
#define SYSCFG_DBGFORCE_SWCLK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDI
// Description : Directly drive SWDIO input, if ATTACH is set
#define SYSCFG_DBGFORCE_SWDI_RESET _u(0x1)
#define SYSCFG_DBGFORCE_SWDI_BITS _u(0x00000002)
#define SYSCFG_DBGFORCE_SWDI_MSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_LSB _u(1)
#define SYSCFG_DBGFORCE_SWDI_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_DBGFORCE_SWDO
// Description : Observe the value of SWDIO output.
#define SYSCFG_DBGFORCE_SWDO_RESET "-"
#define SYSCFG_DBGFORCE_SWDO_BITS _u(0x00000001)
#define SYSCFG_DBGFORCE_SWDO_MSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_LSB _u(0)
#define SYSCFG_DBGFORCE_SWDO_ACCESS "RO"
// =============================================================================
// Register : SYSCFG_MEMPOWERDOWN
// Description : Control PD pins to memories.
// Set high to put memories to a low power state. In this state
// the memories will retain contents but not be accessible
// Use with caution
#define SYSCFG_MEMPOWERDOWN_OFFSET _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_BITS _u(0x00001fff)
#define SYSCFG_MEMPOWERDOWN_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_BOOTRAM
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_BITS _u(0x00001000)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_MSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_LSB _u(12)
#define SYSCFG_MEMPOWERDOWN_BOOTRAM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_ROM
#define SYSCFG_MEMPOWERDOWN_ROM_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_ROM_BITS _u(0x00000800)
#define SYSCFG_MEMPOWERDOWN_ROM_MSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_LSB _u(11)
#define SYSCFG_MEMPOWERDOWN_ROM_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_USB
#define SYSCFG_MEMPOWERDOWN_USB_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_USB_BITS _u(0x00000400)
#define SYSCFG_MEMPOWERDOWN_USB_MSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_LSB _u(10)
#define SYSCFG_MEMPOWERDOWN_USB_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM9
#define SYSCFG_MEMPOWERDOWN_SRAM9_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM9_BITS _u(0x00000200)
#define SYSCFG_MEMPOWERDOWN_SRAM9_MSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_LSB _u(9)
#define SYSCFG_MEMPOWERDOWN_SRAM9_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM8
#define SYSCFG_MEMPOWERDOWN_SRAM8_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM8_BITS _u(0x00000100)
#define SYSCFG_MEMPOWERDOWN_SRAM8_MSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_LSB _u(8)
#define SYSCFG_MEMPOWERDOWN_SRAM8_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM7
#define SYSCFG_MEMPOWERDOWN_SRAM7_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM7_BITS _u(0x00000080)
#define SYSCFG_MEMPOWERDOWN_SRAM7_MSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_LSB _u(7)
#define SYSCFG_MEMPOWERDOWN_SRAM7_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM6
#define SYSCFG_MEMPOWERDOWN_SRAM6_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM6_BITS _u(0x00000040)
#define SYSCFG_MEMPOWERDOWN_SRAM6_MSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_LSB _u(6)
#define SYSCFG_MEMPOWERDOWN_SRAM6_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM5
#define SYSCFG_MEMPOWERDOWN_SRAM5_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM5_BITS _u(0x00000020)
#define SYSCFG_MEMPOWERDOWN_SRAM5_MSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_LSB _u(5)
#define SYSCFG_MEMPOWERDOWN_SRAM5_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM4
#define SYSCFG_MEMPOWERDOWN_SRAM4_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM4_BITS _u(0x00000010)
#define SYSCFG_MEMPOWERDOWN_SRAM4_MSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_LSB _u(4)
#define SYSCFG_MEMPOWERDOWN_SRAM4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM3
#define SYSCFG_MEMPOWERDOWN_SRAM3_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM3_BITS _u(0x00000008)
#define SYSCFG_MEMPOWERDOWN_SRAM3_MSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_LSB _u(3)
#define SYSCFG_MEMPOWERDOWN_SRAM3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM2
#define SYSCFG_MEMPOWERDOWN_SRAM2_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM2_BITS _u(0x00000004)
#define SYSCFG_MEMPOWERDOWN_SRAM2_MSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_LSB _u(2)
#define SYSCFG_MEMPOWERDOWN_SRAM2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM1
#define SYSCFG_MEMPOWERDOWN_SRAM1_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM1_BITS _u(0x00000002)
#define SYSCFG_MEMPOWERDOWN_SRAM1_MSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_LSB _u(1)
#define SYSCFG_MEMPOWERDOWN_SRAM1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : SYSCFG_MEMPOWERDOWN_SRAM0
#define SYSCFG_MEMPOWERDOWN_SRAM0_RESET _u(0x0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_BITS _u(0x00000001)
#define SYSCFG_MEMPOWERDOWN_SRAM0_MSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_LSB _u(0)
#define SYSCFG_MEMPOWERDOWN_SRAM0_ACCESS "RW"
// =============================================================================
// Register : SYSCFG_AUXCTRL
// Description : Auxiliary system control register
// * Bits 7:2: Reserved
//
// * Bit 1: When clear, the LPOSC output is XORed into the TRNG
// ROSC output as an additional, uncorrelated entropy source. When
// set, this behaviour is disabled.
//
// * Bit 0: Force POWMAN clock to switch to LPOSC, by asserting
// its WDRESET input. This must be set before initiating a
// watchdog reset of the RSM from a stage that includes CLOCKS, if
// POWMAN is running from clk_ref at the point that the watchdog
// reset takes place. Otherwise, the short pulse generated on
// clk_ref by the reset of the CLOCKS block may affect POWMAN
// register state.
#define SYSCFG_AUXCTRL_OFFSET _u(0x00000014)
#define SYSCFG_AUXCTRL_BITS _u(0x000000ff)
#define SYSCFG_AUXCTRL_RESET _u(0x00000000)
#define SYSCFG_AUXCTRL_MSB _u(7)
#define SYSCFG_AUXCTRL_LSB _u(0)
#define SYSCFG_AUXCTRL_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_SYSCFG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : SYSINFO
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_SYSINFO_H
#define _HARDWARE_REGS_SYSINFO_H
// =============================================================================
// Register : SYSINFO_CHIP_ID
// Description : JEDEC JEP-106 compliant chip identifier.
#define SYSINFO_CHIP_ID_OFFSET _u(0x00000000)
#define SYSINFO_CHIP_ID_BITS _u(0xffffffff)
#define SYSINFO_CHIP_ID_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_REVISION
#define SYSINFO_CHIP_ID_REVISION_RESET "-"
#define SYSINFO_CHIP_ID_REVISION_BITS _u(0xf0000000)
#define SYSINFO_CHIP_ID_REVISION_MSB _u(31)
#define SYSINFO_CHIP_ID_REVISION_LSB _u(28)
#define SYSINFO_CHIP_ID_REVISION_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_PART
#define SYSINFO_CHIP_ID_PART_RESET "-"
#define SYSINFO_CHIP_ID_PART_BITS _u(0x0ffff000)
#define SYSINFO_CHIP_ID_PART_MSB _u(27)
#define SYSINFO_CHIP_ID_PART_LSB _u(12)
#define SYSINFO_CHIP_ID_PART_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_MANUFACTURER
#define SYSINFO_CHIP_ID_MANUFACTURER_RESET "-"
#define SYSINFO_CHIP_ID_MANUFACTURER_BITS _u(0x00000ffe)
#define SYSINFO_CHIP_ID_MANUFACTURER_MSB _u(11)
#define SYSINFO_CHIP_ID_MANUFACTURER_LSB _u(1)
#define SYSINFO_CHIP_ID_MANUFACTURER_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_CHIP_ID_STOP_BIT
#define SYSINFO_CHIP_ID_STOP_BIT_RESET _u(0x1)
#define SYSINFO_CHIP_ID_STOP_BIT_BITS _u(0x00000001)
#define SYSINFO_CHIP_ID_STOP_BIT_MSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_LSB _u(0)
#define SYSINFO_CHIP_ID_STOP_BIT_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PACKAGE_SEL
#define SYSINFO_PACKAGE_SEL_OFFSET _u(0x00000004)
#define SYSINFO_PACKAGE_SEL_BITS _u(0x00000001)
#define SYSINFO_PACKAGE_SEL_RESET _u(0x00000000)
#define SYSINFO_PACKAGE_SEL_MSB _u(0)
#define SYSINFO_PACKAGE_SEL_LSB _u(0)
#define SYSINFO_PACKAGE_SEL_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_PLATFORM
// Description : Platform register. Allows software to know what environment it
// is running in during pre-production development. Post-
// production, the PLATFORM is always ASIC, non-SIM.
#define SYSINFO_PLATFORM_OFFSET _u(0x00000008)
#define SYSINFO_PLATFORM_BITS _u(0x0000001f)
#define SYSINFO_PLATFORM_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_GATESIM
#define SYSINFO_PLATFORM_GATESIM_RESET "-"
#define SYSINFO_PLATFORM_GATESIM_BITS _u(0x00000010)
#define SYSINFO_PLATFORM_GATESIM_MSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_LSB _u(4)
#define SYSINFO_PLATFORM_GATESIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_BATCHSIM
#define SYSINFO_PLATFORM_BATCHSIM_RESET "-"
#define SYSINFO_PLATFORM_BATCHSIM_BITS _u(0x00000008)
#define SYSINFO_PLATFORM_BATCHSIM_MSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_LSB _u(3)
#define SYSINFO_PLATFORM_BATCHSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_HDLSIM
#define SYSINFO_PLATFORM_HDLSIM_RESET "-"
#define SYSINFO_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define SYSINFO_PLATFORM_HDLSIM_MSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_LSB _u(2)
#define SYSINFO_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_ASIC
#define SYSINFO_PLATFORM_ASIC_RESET "-"
#define SYSINFO_PLATFORM_ASIC_BITS _u(0x00000002)
#define SYSINFO_PLATFORM_ASIC_MSB _u(1)
#define SYSINFO_PLATFORM_ASIC_LSB _u(1)
#define SYSINFO_PLATFORM_ASIC_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : SYSINFO_PLATFORM_FPGA
#define SYSINFO_PLATFORM_FPGA_RESET "-"
#define SYSINFO_PLATFORM_FPGA_BITS _u(0x00000001)
#define SYSINFO_PLATFORM_FPGA_MSB _u(0)
#define SYSINFO_PLATFORM_FPGA_LSB _u(0)
#define SYSINFO_PLATFORM_FPGA_ACCESS "RO"
// =============================================================================
// Register : SYSINFO_GITREF_RP2350
// Description : Git hash of the chip source. Used to identify chip version.
#define SYSINFO_GITREF_RP2350_OFFSET _u(0x00000014)
#define SYSINFO_GITREF_RP2350_BITS _u(0xffffffff)
#define SYSINFO_GITREF_RP2350_RESET "-"
#define SYSINFO_GITREF_RP2350_MSB _u(31)
#define SYSINFO_GITREF_RP2350_LSB _u(0)
#define SYSINFO_GITREF_RP2350_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_SYSINFO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TBMAN
// Version : 1
// Bus type : apb
// Description : For managing simulation testbenches
// =============================================================================
#ifndef _HARDWARE_REGS_TBMAN_H
#define _HARDWARE_REGS_TBMAN_H
// =============================================================================
// Register : TBMAN_PLATFORM
// Description : Indicates the type of platform in use
#define TBMAN_PLATFORM_OFFSET _u(0x00000000)
#define TBMAN_PLATFORM_BITS _u(0x00000007)
#define TBMAN_PLATFORM_RESET _u(0x00000001)
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_HDLSIM
// Description : Indicates the platform is a simulation
#define TBMAN_PLATFORM_HDLSIM_RESET _u(0x0)
#define TBMAN_PLATFORM_HDLSIM_BITS _u(0x00000004)
#define TBMAN_PLATFORM_HDLSIM_MSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_LSB _u(2)
#define TBMAN_PLATFORM_HDLSIM_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_FPGA
// Description : Indicates the platform is an FPGA
#define TBMAN_PLATFORM_FPGA_RESET _u(0x0)
#define TBMAN_PLATFORM_FPGA_BITS _u(0x00000002)
#define TBMAN_PLATFORM_FPGA_MSB _u(1)
#define TBMAN_PLATFORM_FPGA_LSB _u(1)
#define TBMAN_PLATFORM_FPGA_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TBMAN_PLATFORM_ASIC
// Description : Indicates the platform is an ASIC
#define TBMAN_PLATFORM_ASIC_RESET _u(0x1)
#define TBMAN_PLATFORM_ASIC_BITS _u(0x00000001)
#define TBMAN_PLATFORM_ASIC_MSB _u(0)
#define TBMAN_PLATFORM_ASIC_LSB _u(0)
#define TBMAN_PLATFORM_ASIC_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TBMAN_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TICKS
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_TICKS_H
#define _HARDWARE_REGS_TICKS_H
// =============================================================================
// Register : TICKS_PROC0_CTRL
// Description : Controls the tick generator
#define TICKS_PROC0_CTRL_OFFSET _u(0x00000000)
#define TICKS_PROC0_CTRL_BITS _u(0x00000003)
#define TICKS_PROC0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC0_CTRL_RUNNING_RESET "-"
#define TICKS_PROC0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC0_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC0_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC0_CYCLES_OFFSET _u(0x00000004)
#define TICKS_PROC0_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC0_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC0_CYCLES_MSB _u(8)
#define TICKS_PROC0_CYCLES_LSB _u(0)
#define TICKS_PROC0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC0_COUNT_OFFSET _u(0x00000008)
#define TICKS_PROC0_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC0_COUNT_RESET "-"
#define TICKS_PROC0_COUNT_MSB _u(8)
#define TICKS_PROC0_COUNT_LSB _u(0)
#define TICKS_PROC0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_PROC1_CTRL
// Description : Controls the tick generator
#define TICKS_PROC1_CTRL_OFFSET _u(0x0000000c)
#define TICKS_PROC1_CTRL_BITS _u(0x00000003)
#define TICKS_PROC1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_PROC1_CTRL_RUNNING_RESET "-"
#define TICKS_PROC1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_PROC1_CTRL_RUNNING_MSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_LSB _u(1)
#define TICKS_PROC1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_PROC1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_PROC1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_PROC1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_PROC1_CTRL_ENABLE_MSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_LSB _u(0)
#define TICKS_PROC1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_PROC1_CYCLES_OFFSET _u(0x00000010)
#define TICKS_PROC1_CYCLES_BITS _u(0x000001ff)
#define TICKS_PROC1_CYCLES_RESET _u(0x00000000)
#define TICKS_PROC1_CYCLES_MSB _u(8)
#define TICKS_PROC1_CYCLES_LSB _u(0)
#define TICKS_PROC1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_PROC1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_PROC1_COUNT_OFFSET _u(0x00000014)
#define TICKS_PROC1_COUNT_BITS _u(0x000001ff)
#define TICKS_PROC1_COUNT_RESET "-"
#define TICKS_PROC1_COUNT_MSB _u(8)
#define TICKS_PROC1_COUNT_LSB _u(0)
#define TICKS_PROC1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER0_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER0_CTRL_OFFSET _u(0x00000018)
#define TICKS_TIMER0_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER0_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER0_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER0_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER0_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER0_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER0_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER0_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER0_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER0_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER0_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER0_CYCLES_OFFSET _u(0x0000001c)
#define TICKS_TIMER0_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER0_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER0_CYCLES_MSB _u(8)
#define TICKS_TIMER0_CYCLES_LSB _u(0)
#define TICKS_TIMER0_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER0_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER0_COUNT_OFFSET _u(0x00000020)
#define TICKS_TIMER0_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER0_COUNT_RESET "-"
#define TICKS_TIMER0_COUNT_MSB _u(8)
#define TICKS_TIMER0_COUNT_LSB _u(0)
#define TICKS_TIMER0_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_TIMER1_CTRL
// Description : Controls the tick generator
#define TICKS_TIMER1_CTRL_OFFSET _u(0x00000024)
#define TICKS_TIMER1_CTRL_BITS _u(0x00000003)
#define TICKS_TIMER1_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_TIMER1_CTRL_RUNNING_RESET "-"
#define TICKS_TIMER1_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_TIMER1_CTRL_RUNNING_MSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_LSB _u(1)
#define TICKS_TIMER1_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_TIMER1_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_TIMER1_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_TIMER1_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_TIMER1_CTRL_ENABLE_MSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_LSB _u(0)
#define TICKS_TIMER1_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_TIMER1_CYCLES_OFFSET _u(0x00000028)
#define TICKS_TIMER1_CYCLES_BITS _u(0x000001ff)
#define TICKS_TIMER1_CYCLES_RESET _u(0x00000000)
#define TICKS_TIMER1_CYCLES_MSB _u(8)
#define TICKS_TIMER1_CYCLES_LSB _u(0)
#define TICKS_TIMER1_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_TIMER1_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_TIMER1_COUNT_OFFSET _u(0x0000002c)
#define TICKS_TIMER1_COUNT_BITS _u(0x000001ff)
#define TICKS_TIMER1_COUNT_RESET "-"
#define TICKS_TIMER1_COUNT_MSB _u(8)
#define TICKS_TIMER1_COUNT_LSB _u(0)
#define TICKS_TIMER1_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_WATCHDOG_CTRL
// Description : Controls the tick generator
#define TICKS_WATCHDOG_CTRL_OFFSET _u(0x00000030)
#define TICKS_WATCHDOG_CTRL_BITS _u(0x00000003)
#define TICKS_WATCHDOG_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_WATCHDOG_CTRL_RUNNING_RESET "-"
#define TICKS_WATCHDOG_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_WATCHDOG_CTRL_RUNNING_MSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_LSB _u(1)
#define TICKS_WATCHDOG_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_WATCHDOG_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_WATCHDOG_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_WATCHDOG_CTRL_ENABLE_MSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_LSB _u(0)
#define TICKS_WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_WATCHDOG_CYCLES_OFFSET _u(0x00000034)
#define TICKS_WATCHDOG_CYCLES_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_CYCLES_RESET _u(0x00000000)
#define TICKS_WATCHDOG_CYCLES_MSB _u(8)
#define TICKS_WATCHDOG_CYCLES_LSB _u(0)
#define TICKS_WATCHDOG_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_WATCHDOG_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_WATCHDOG_COUNT_OFFSET _u(0x00000038)
#define TICKS_WATCHDOG_COUNT_BITS _u(0x000001ff)
#define TICKS_WATCHDOG_COUNT_RESET "-"
#define TICKS_WATCHDOG_COUNT_MSB _u(8)
#define TICKS_WATCHDOG_COUNT_LSB _u(0)
#define TICKS_WATCHDOG_COUNT_ACCESS "RO"
// =============================================================================
// Register : TICKS_RISCV_CTRL
// Description : Controls the tick generator
#define TICKS_RISCV_CTRL_OFFSET _u(0x0000003c)
#define TICKS_RISCV_CTRL_BITS _u(0x00000003)
#define TICKS_RISCV_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_RUNNING
// Description : Is the tick generator running?
#define TICKS_RISCV_CTRL_RUNNING_RESET "-"
#define TICKS_RISCV_CTRL_RUNNING_BITS _u(0x00000002)
#define TICKS_RISCV_CTRL_RUNNING_MSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_LSB _u(1)
#define TICKS_RISCV_CTRL_RUNNING_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TICKS_RISCV_CTRL_ENABLE
// Description : start / stop tick generation
#define TICKS_RISCV_CTRL_ENABLE_RESET _u(0x0)
#define TICKS_RISCV_CTRL_ENABLE_BITS _u(0x00000001)
#define TICKS_RISCV_CTRL_ENABLE_MSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_LSB _u(0)
#define TICKS_RISCV_CTRL_ENABLE_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_CYCLES
// Description : None
// Total number of clk_tick cycles before the next tick.
#define TICKS_RISCV_CYCLES_OFFSET _u(0x00000040)
#define TICKS_RISCV_CYCLES_BITS _u(0x000001ff)
#define TICKS_RISCV_CYCLES_RESET _u(0x00000000)
#define TICKS_RISCV_CYCLES_MSB _u(8)
#define TICKS_RISCV_CYCLES_LSB _u(0)
#define TICKS_RISCV_CYCLES_ACCESS "RW"
// =============================================================================
// Register : TICKS_RISCV_COUNT
// Description : None
// Count down timer: the remaining number clk_tick cycles before
// the next tick is generated.
#define TICKS_RISCV_COUNT_OFFSET _u(0x00000044)
#define TICKS_RISCV_COUNT_BITS _u(0x000001ff)
#define TICKS_RISCV_COUNT_RESET "-"
#define TICKS_RISCV_COUNT_MSB _u(8)
#define TICKS_RISCV_COUNT_LSB _u(0)
#define TICKS_RISCV_COUNT_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TICKS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TIMER
// Version : 1
// Bus type : apb
// Description : Controls time and alarms
//
// time is a 64 bit value indicating the time since power-on
//
// timeh is the top 32 bits of time & timel is the bottom 32
// bits to change time write to timelw before timehw to read
// time read from timelr before timehr
//
// An alarm is set by setting alarm_enable and writing to the
// corresponding alarm register When an alarm is pending, the
// corresponding alarm_running signal will be high An alarm can
// be cancelled before it has finished by clearing the
// alarm_enable When an alarm fires, the corresponding
// alarm_irq is set and alarm_running is cleared To clear the
// interrupt write a 1 to the corresponding alarm_irq The timer
// can be locked to prevent writing
// =============================================================================
#ifndef _HARDWARE_REGS_TIMER_H
#define _HARDWARE_REGS_TIMER_H
// =============================================================================
// Register : TIMER_TIMEHW
// Description : Write to bits 63:32 of time always write timelw before timehw
#define TIMER_TIMEHW_OFFSET _u(0x00000000)
#define TIMER_TIMEHW_BITS _u(0xffffffff)
#define TIMER_TIMEHW_RESET _u(0x00000000)
#define TIMER_TIMEHW_MSB _u(31)
#define TIMER_TIMEHW_LSB _u(0)
#define TIMER_TIMEHW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMELW
// Description : Write to bits 31:0 of time writes do not get copied to time
// until timehw is written
#define TIMER_TIMELW_OFFSET _u(0x00000004)
#define TIMER_TIMELW_BITS _u(0xffffffff)
#define TIMER_TIMELW_RESET _u(0x00000000)
#define TIMER_TIMELW_MSB _u(31)
#define TIMER_TIMELW_LSB _u(0)
#define TIMER_TIMELW_ACCESS "WF"
// =============================================================================
// Register : TIMER_TIMEHR
// Description : Read from bits 63:32 of time always read timelr before timehr
#define TIMER_TIMEHR_OFFSET _u(0x00000008)
#define TIMER_TIMEHR_BITS _u(0xffffffff)
#define TIMER_TIMEHR_RESET _u(0x00000000)
#define TIMER_TIMEHR_MSB _u(31)
#define TIMER_TIMEHR_LSB _u(0)
#define TIMER_TIMEHR_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMELR
// Description : Read from bits 31:0 of time
#define TIMER_TIMELR_OFFSET _u(0x0000000c)
#define TIMER_TIMELR_BITS _u(0xffffffff)
#define TIMER_TIMELR_RESET _u(0x00000000)
#define TIMER_TIMELR_MSB _u(31)
#define TIMER_TIMELR_LSB _u(0)
#define TIMER_TIMELR_ACCESS "RO"
// =============================================================================
// Register : TIMER_ALARM0
// Description : Arm alarm 0, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM0 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM0_OFFSET _u(0x00000010)
#define TIMER_ALARM0_BITS _u(0xffffffff)
#define TIMER_ALARM0_RESET _u(0x00000000)
#define TIMER_ALARM0_MSB _u(31)
#define TIMER_ALARM0_LSB _u(0)
#define TIMER_ALARM0_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM1
// Description : Arm alarm 1, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM1 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM1_OFFSET _u(0x00000014)
#define TIMER_ALARM1_BITS _u(0xffffffff)
#define TIMER_ALARM1_RESET _u(0x00000000)
#define TIMER_ALARM1_MSB _u(31)
#define TIMER_ALARM1_LSB _u(0)
#define TIMER_ALARM1_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM2
// Description : Arm alarm 2, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM2 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM2_OFFSET _u(0x00000018)
#define TIMER_ALARM2_BITS _u(0xffffffff)
#define TIMER_ALARM2_RESET _u(0x00000000)
#define TIMER_ALARM2_MSB _u(31)
#define TIMER_ALARM2_LSB _u(0)
#define TIMER_ALARM2_ACCESS "RW"
// =============================================================================
// Register : TIMER_ALARM3
// Description : Arm alarm 3, and configure the time it will fire. Once armed,
// the alarm fires when TIMER_ALARM3 == TIMELR. The alarm will
// disarm itself once it fires, and can be disarmed early using
// the ARMED status register.
#define TIMER_ALARM3_OFFSET _u(0x0000001c)
#define TIMER_ALARM3_BITS _u(0xffffffff)
#define TIMER_ALARM3_RESET _u(0x00000000)
#define TIMER_ALARM3_MSB _u(31)
#define TIMER_ALARM3_LSB _u(0)
#define TIMER_ALARM3_ACCESS "RW"
// =============================================================================
// Register : TIMER_ARMED
// Description : Indicates the armed/disarmed status of each alarm. A write to
// the corresponding ALARMx register arms the alarm. Alarms
// automatically disarm upon firing, but writing ones here will
// disarm immediately without waiting to fire.
#define TIMER_ARMED_OFFSET _u(0x00000020)
#define TIMER_ARMED_BITS _u(0x0000000f)
#define TIMER_ARMED_RESET _u(0x00000000)
#define TIMER_ARMED_MSB _u(3)
#define TIMER_ARMED_LSB _u(0)
#define TIMER_ARMED_ACCESS "WC"
// =============================================================================
// Register : TIMER_TIMERAWH
// Description : Raw read from bits 63:32 of time (no side effects)
#define TIMER_TIMERAWH_OFFSET _u(0x00000024)
#define TIMER_TIMERAWH_BITS _u(0xffffffff)
#define TIMER_TIMERAWH_RESET _u(0x00000000)
#define TIMER_TIMERAWH_MSB _u(31)
#define TIMER_TIMERAWH_LSB _u(0)
#define TIMER_TIMERAWH_ACCESS "RO"
// =============================================================================
// Register : TIMER_TIMERAWL
// Description : Raw read from bits 31:0 of time (no side effects)
#define TIMER_TIMERAWL_OFFSET _u(0x00000028)
#define TIMER_TIMERAWL_BITS _u(0xffffffff)
#define TIMER_TIMERAWL_RESET _u(0x00000000)
#define TIMER_TIMERAWL_MSB _u(31)
#define TIMER_TIMERAWL_LSB _u(0)
#define TIMER_TIMERAWL_ACCESS "RO"
// =============================================================================
// Register : TIMER_DBGPAUSE
// Description : Set bits high to enable pause when the corresponding debug
// ports are active
#define TIMER_DBGPAUSE_OFFSET _u(0x0000002c)
#define TIMER_DBGPAUSE_BITS _u(0x00000006)
#define TIMER_DBGPAUSE_RESET _u(0x00000007)
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG1
// Description : Pause when processor 1 is in debug mode
#define TIMER_DBGPAUSE_DBG1_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG1_BITS _u(0x00000004)
#define TIMER_DBGPAUSE_DBG1_MSB _u(2)
#define TIMER_DBGPAUSE_DBG1_LSB _u(2)
#define TIMER_DBGPAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_DBGPAUSE_DBG0
// Description : Pause when processor 0 is in debug mode
#define TIMER_DBGPAUSE_DBG0_RESET _u(0x1)
#define TIMER_DBGPAUSE_DBG0_BITS _u(0x00000002)
#define TIMER_DBGPAUSE_DBG0_MSB _u(1)
#define TIMER_DBGPAUSE_DBG0_LSB _u(1)
#define TIMER_DBGPAUSE_DBG0_ACCESS "RW"
// =============================================================================
// Register : TIMER_PAUSE
// Description : Set high to pause the timer
#define TIMER_PAUSE_OFFSET _u(0x00000030)
#define TIMER_PAUSE_BITS _u(0x00000001)
#define TIMER_PAUSE_RESET _u(0x00000000)
#define TIMER_PAUSE_MSB _u(0)
#define TIMER_PAUSE_LSB _u(0)
#define TIMER_PAUSE_ACCESS "RW"
// =============================================================================
// Register : TIMER_LOCKED
// Description : Set locked bit to disable write access to timer Once set,
// cannot be cleared (without a reset)
#define TIMER_LOCKED_OFFSET _u(0x00000034)
#define TIMER_LOCKED_BITS _u(0x00000001)
#define TIMER_LOCKED_RESET _u(0x00000000)
#define TIMER_LOCKED_MSB _u(0)
#define TIMER_LOCKED_LSB _u(0)
#define TIMER_LOCKED_ACCESS "RW"
// =============================================================================
// Register : TIMER_SOURCE
// Description : Selects the source for the timer. Defaults to the normal tick
// configured in the ticks block (typically configured to 1
// microsecond). Writing to 1 will ignore the tick and count
// clk_sys cycles instead.
#define TIMER_SOURCE_OFFSET _u(0x00000038)
#define TIMER_SOURCE_BITS _u(0x00000001)
#define TIMER_SOURCE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_SOURCE_CLK_SYS
// 0x0 -> TICK
// 0x1 -> CLK_SYS
#define TIMER_SOURCE_CLK_SYS_RESET _u(0x0)
#define TIMER_SOURCE_CLK_SYS_BITS _u(0x00000001)
#define TIMER_SOURCE_CLK_SYS_MSB _u(0)
#define TIMER_SOURCE_CLK_SYS_LSB _u(0)
#define TIMER_SOURCE_CLK_SYS_ACCESS "RW"
#define TIMER_SOURCE_CLK_SYS_VALUE_TICK _u(0x0)
#define TIMER_SOURCE_CLK_SYS_VALUE_CLK_SYS _u(0x1)
// =============================================================================
// Register : TIMER_INTR
// Description : Raw Interrupts
#define TIMER_INTR_OFFSET _u(0x0000003c)
#define TIMER_INTR_BITS _u(0x0000000f)
#define TIMER_INTR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_3
#define TIMER_INTR_ALARM_3_RESET _u(0x0)
#define TIMER_INTR_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTR_ALARM_3_MSB _u(3)
#define TIMER_INTR_ALARM_3_LSB _u(3)
#define TIMER_INTR_ALARM_3_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_2
#define TIMER_INTR_ALARM_2_RESET _u(0x0)
#define TIMER_INTR_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTR_ALARM_2_MSB _u(2)
#define TIMER_INTR_ALARM_2_LSB _u(2)
#define TIMER_INTR_ALARM_2_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_1
#define TIMER_INTR_ALARM_1_RESET _u(0x0)
#define TIMER_INTR_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTR_ALARM_1_MSB _u(1)
#define TIMER_INTR_ALARM_1_LSB _u(1)
#define TIMER_INTR_ALARM_1_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : TIMER_INTR_ALARM_0
#define TIMER_INTR_ALARM_0_RESET _u(0x0)
#define TIMER_INTR_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTR_ALARM_0_MSB _u(0)
#define TIMER_INTR_ALARM_0_LSB _u(0)
#define TIMER_INTR_ALARM_0_ACCESS "WC"
// =============================================================================
// Register : TIMER_INTE
// Description : Interrupt Enable
#define TIMER_INTE_OFFSET _u(0x00000040)
#define TIMER_INTE_BITS _u(0x0000000f)
#define TIMER_INTE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_3
#define TIMER_INTE_ALARM_3_RESET _u(0x0)
#define TIMER_INTE_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTE_ALARM_3_MSB _u(3)
#define TIMER_INTE_ALARM_3_LSB _u(3)
#define TIMER_INTE_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_2
#define TIMER_INTE_ALARM_2_RESET _u(0x0)
#define TIMER_INTE_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTE_ALARM_2_MSB _u(2)
#define TIMER_INTE_ALARM_2_LSB _u(2)
#define TIMER_INTE_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_1
#define TIMER_INTE_ALARM_1_RESET _u(0x0)
#define TIMER_INTE_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTE_ALARM_1_MSB _u(1)
#define TIMER_INTE_ALARM_1_LSB _u(1)
#define TIMER_INTE_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTE_ALARM_0
#define TIMER_INTE_ALARM_0_RESET _u(0x0)
#define TIMER_INTE_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTE_ALARM_0_MSB _u(0)
#define TIMER_INTE_ALARM_0_LSB _u(0)
#define TIMER_INTE_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTF
// Description : Interrupt Force
#define TIMER_INTF_OFFSET _u(0x00000044)
#define TIMER_INTF_BITS _u(0x0000000f)
#define TIMER_INTF_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_3
#define TIMER_INTF_ALARM_3_RESET _u(0x0)
#define TIMER_INTF_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTF_ALARM_3_MSB _u(3)
#define TIMER_INTF_ALARM_3_LSB _u(3)
#define TIMER_INTF_ALARM_3_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_2
#define TIMER_INTF_ALARM_2_RESET _u(0x0)
#define TIMER_INTF_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTF_ALARM_2_MSB _u(2)
#define TIMER_INTF_ALARM_2_LSB _u(2)
#define TIMER_INTF_ALARM_2_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_1
#define TIMER_INTF_ALARM_1_RESET _u(0x0)
#define TIMER_INTF_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTF_ALARM_1_MSB _u(1)
#define TIMER_INTF_ALARM_1_LSB _u(1)
#define TIMER_INTF_ALARM_1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TIMER_INTF_ALARM_0
#define TIMER_INTF_ALARM_0_RESET _u(0x0)
#define TIMER_INTF_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTF_ALARM_0_MSB _u(0)
#define TIMER_INTF_ALARM_0_LSB _u(0)
#define TIMER_INTF_ALARM_0_ACCESS "RW"
// =============================================================================
// Register : TIMER_INTS
// Description : Interrupt status after masking & forcing
#define TIMER_INTS_OFFSET _u(0x00000048)
#define TIMER_INTS_BITS _u(0x0000000f)
#define TIMER_INTS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_3
#define TIMER_INTS_ALARM_3_RESET _u(0x0)
#define TIMER_INTS_ALARM_3_BITS _u(0x00000008)
#define TIMER_INTS_ALARM_3_MSB _u(3)
#define TIMER_INTS_ALARM_3_LSB _u(3)
#define TIMER_INTS_ALARM_3_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_2
#define TIMER_INTS_ALARM_2_RESET _u(0x0)
#define TIMER_INTS_ALARM_2_BITS _u(0x00000004)
#define TIMER_INTS_ALARM_2_MSB _u(2)
#define TIMER_INTS_ALARM_2_LSB _u(2)
#define TIMER_INTS_ALARM_2_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_1
#define TIMER_INTS_ALARM_1_RESET _u(0x0)
#define TIMER_INTS_ALARM_1_BITS _u(0x00000002)
#define TIMER_INTS_ALARM_1_MSB _u(1)
#define TIMER_INTS_ALARM_1_LSB _u(1)
#define TIMER_INTS_ALARM_1_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TIMER_INTS_ALARM_0
#define TIMER_INTS_ALARM_0_RESET _u(0x0)
#define TIMER_INTS_ALARM_0_BITS _u(0x00000001)
#define TIMER_INTS_ALARM_0_MSB _u(0)
#define TIMER_INTS_ALARM_0_LSB _u(0)
#define TIMER_INTS_ALARM_0_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TIMER_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : TRNG
// Version : 1
// Bus type : apb
// Description : ARM TrustZone RNG register block
// =============================================================================
#ifndef _HARDWARE_REGS_TRNG_H
#define _HARDWARE_REGS_TRNG_H
// =============================================================================
// Register : TRNG_RNG_IMR
// Description : Interrupt masking.
#define TRNG_RNG_IMR_OFFSET _u(0x00000100)
#define TRNG_RNG_IMR_BITS _u(0xffffffff)
#define TRNG_RNG_IMR_RESET _u(0x0000000f)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_RESERVED
// Description : RESERVED
#define TRNG_RNG_IMR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_IMR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_IMR_RESERVED_MSB _u(31)
#define TRNG_RNG_IMR_RESERVED_LSB _u(4)
#define TRNG_RNG_IMR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_VN_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_BITS _u(0x00000008)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_MSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_LSB _u(3)
#define TRNG_RNG_IMR_VN_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_CRNGT_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_BITS _u(0x00000004)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_MSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_LSB _u(2)
#define TRNG_RNG_IMR_CRNGT_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_BITS _u(0x00000002)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_MSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_LSB _u(1)
#define TRNG_RNG_IMR_AUTOCORR_ERR_INT_MASK_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_IMR_EHR_VALID_INT_MASK
// Description : 1'b1-mask interrupt, no interrupt will be generated. See
// RNG_ISR for an explanation on this interrupt.
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_RESET _u(0x1)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_BITS _u(0x00000001)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_MSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_LSB _u(0)
#define TRNG_RNG_IMR_EHR_VALID_INT_MASK_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_ISR
// Description : RNG status register. If corresponding RNG_IMR bit is unmasked,
// an interrupt will be generated.
#define TRNG_RNG_ISR_OFFSET _u(0x00000104)
#define TRNG_RNG_ISR_BITS _u(0xffffffff)
#define TRNG_RNG_ISR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ISR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ISR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ISR_RESERVED_MSB _u(31)
#define TRNG_RNG_ISR_RESERVED_LSB _u(4)
#define TRNG_RNG_ISR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_VN_ERR
// Description : 1'b1 indicates Von Neuman error. Error in von Neuman occurs if
// 32 consecutive collected bits are identical, ZERO or ONE.
#define TRNG_RNG_ISR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ISR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ISR_VN_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_CRNGT_ERR
// Description : 1'b1 indicates CRNGT in the RNG test failed. Failure occurs
// when two consecutive blocks of 16 collected bits are equal.
#define TRNG_RNG_ISR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ISR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ISR_CRNGT_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_AUTOCORR_ERR
// Description : 1'b1 indicates Autocorrelation test failed four times in a row.
// When set, RNG cease from functioning until next reset.
#define TRNG_RNG_ISR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ISR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ISR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ISR_AUTOCORR_ERR_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ISR_EHR_VALID
// Description : 1'b1 indicates that 192 bits have been collected in the RNG,
// and are ready to be read.
#define TRNG_RNG_ISR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ISR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ISR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ISR_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_ICR
// Description : Interrupt/status bit clear Register.
#define TRNG_RNG_ICR_OFFSET _u(0x00000108)
#define TRNG_RNG_ICR_BITS _u(0xffffffff)
#define TRNG_RNG_ICR_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_RESERVED
// Description : RESERVED
#define TRNG_RNG_ICR_RESERVED_RESET _u(0x0000000)
#define TRNG_RNG_ICR_RESERVED_BITS _u(0xfffffff0)
#define TRNG_RNG_ICR_RESERVED_MSB _u(31)
#define TRNG_RNG_ICR_RESERVED_LSB _u(4)
#define TRNG_RNG_ICR_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_VN_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_VN_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_VN_ERR_BITS _u(0x00000008)
#define TRNG_RNG_ICR_VN_ERR_MSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_LSB _u(3)
#define TRNG_RNG_ICR_VN_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_CRNGT_ERR
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_CRNGT_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_CRNGT_ERR_BITS _u(0x00000004)
#define TRNG_RNG_ICR_CRNGT_ERR_MSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_LSB _u(2)
#define TRNG_RNG_ICR_CRNGT_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_AUTOCORR_ERR
// Description : Cannot be cleared by SW! Only RNG reset clears this bit.
#define TRNG_RNG_ICR_AUTOCORR_ERR_RESET _u(0x0)
#define TRNG_RNG_ICR_AUTOCORR_ERR_BITS _u(0x00000002)
#define TRNG_RNG_ICR_AUTOCORR_ERR_MSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_LSB _u(1)
#define TRNG_RNG_ICR_AUTOCORR_ERR_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_ICR_EHR_VALID
// Description : Write 1'b1 - clear corresponding bit in RNG_ISR.
#define TRNG_RNG_ICR_EHR_VALID_RESET _u(0x0)
#define TRNG_RNG_ICR_EHR_VALID_BITS _u(0x00000001)
#define TRNG_RNG_ICR_EHR_VALID_MSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_LSB _u(0)
#define TRNG_RNG_ICR_EHR_VALID_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_CONFIG
// Description : Selecting the inverter-chain length.
#define TRNG_TRNG_CONFIG_OFFSET _u(0x0000010c)
#define TRNG_TRNG_CONFIG_BITS _u(0xffffffff)
#define TRNG_TRNG_CONFIG_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RESERVED
// Description : RESERVED
#define TRNG_TRNG_CONFIG_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_CONFIG_RESERVED_BITS _u(0xfffffffc)
#define TRNG_TRNG_CONFIG_RESERVED_MSB _u(31)
#define TRNG_TRNG_CONFIG_RESERVED_LSB _u(2)
#define TRNG_TRNG_CONFIG_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_CONFIG_RND_SRC_SEL
// Description : Selects the number of inverters (out of four possible
// selections) in the ring oscillator (the entropy source).
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_RESET _u(0x0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_BITS _u(0x00000003)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_MSB _u(1)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_LSB _u(0)
#define TRNG_TRNG_CONFIG_RND_SRC_SEL_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_VALID
// Description : 192 bit collection indication.
#define TRNG_TRNG_VALID_OFFSET _u(0x00000110)
#define TRNG_TRNG_VALID_BITS _u(0xffffffff)
#define TRNG_TRNG_VALID_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_RESERVED
// Description : RESERVED
#define TRNG_TRNG_VALID_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_VALID_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_VALID_RESERVED_MSB _u(31)
#define TRNG_TRNG_VALID_RESERVED_LSB _u(1)
#define TRNG_TRNG_VALID_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_VALID_EHR_VALID
// Description : 1'b1 indicates that collection of bits in the RNG is completed,
// and data can be read from EHR_DATA register.
#define TRNG_TRNG_VALID_EHR_VALID_RESET _u(0x0)
#define TRNG_TRNG_VALID_EHR_VALID_BITS _u(0x00000001)
#define TRNG_TRNG_VALID_EHR_VALID_MSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_LSB _u(0)
#define TRNG_TRNG_VALID_EHR_VALID_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA0
// Description : RNG collected bits.
// Bits [31:0] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA0_OFFSET _u(0x00000114)
#define TRNG_EHR_DATA0_BITS _u(0xffffffff)
#define TRNG_EHR_DATA0_RESET _u(0x00000000)
#define TRNG_EHR_DATA0_MSB _u(31)
#define TRNG_EHR_DATA0_LSB _u(0)
#define TRNG_EHR_DATA0_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA1
// Description : RNG collected bits.
// Bits [63:32] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA1_OFFSET _u(0x00000118)
#define TRNG_EHR_DATA1_BITS _u(0xffffffff)
#define TRNG_EHR_DATA1_RESET _u(0x00000000)
#define TRNG_EHR_DATA1_MSB _u(31)
#define TRNG_EHR_DATA1_LSB _u(0)
#define TRNG_EHR_DATA1_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA2
// Description : RNG collected bits.
// Bits [95:64] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA2_OFFSET _u(0x0000011c)
#define TRNG_EHR_DATA2_BITS _u(0xffffffff)
#define TRNG_EHR_DATA2_RESET _u(0x00000000)
#define TRNG_EHR_DATA2_MSB _u(31)
#define TRNG_EHR_DATA2_LSB _u(0)
#define TRNG_EHR_DATA2_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA3
// Description : RNG collected bits.
// Bits [127:96] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA3_OFFSET _u(0x00000120)
#define TRNG_EHR_DATA3_BITS _u(0xffffffff)
#define TRNG_EHR_DATA3_RESET _u(0x00000000)
#define TRNG_EHR_DATA3_MSB _u(31)
#define TRNG_EHR_DATA3_LSB _u(0)
#define TRNG_EHR_DATA3_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA4
// Description : RNG collected bits.
// Bits [159:128] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA4_OFFSET _u(0x00000124)
#define TRNG_EHR_DATA4_BITS _u(0xffffffff)
#define TRNG_EHR_DATA4_RESET _u(0x00000000)
#define TRNG_EHR_DATA4_MSB _u(31)
#define TRNG_EHR_DATA4_LSB _u(0)
#define TRNG_EHR_DATA4_ACCESS "RO"
// =============================================================================
// Register : TRNG_EHR_DATA5
// Description : RNG collected bits.
// Bits [191:160] of Entropy Holding Register (EHR) - RNG output
// register
#define TRNG_EHR_DATA5_OFFSET _u(0x00000128)
#define TRNG_EHR_DATA5_BITS _u(0xffffffff)
#define TRNG_EHR_DATA5_RESET _u(0x00000000)
#define TRNG_EHR_DATA5_MSB _u(31)
#define TRNG_EHR_DATA5_LSB _u(0)
#define TRNG_EHR_DATA5_ACCESS "RO"
// =============================================================================
// Register : TRNG_RND_SOURCE_ENABLE
// Description : Enable signal for the random source.
#define TRNG_RND_SOURCE_ENABLE_OFFSET _u(0x0000012c)
#define TRNG_RND_SOURCE_ENABLE_BITS _u(0xffffffff)
#define TRNG_RND_SOURCE_ENABLE_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RESERVED
// Description : RESERVED
#define TRNG_RND_SOURCE_ENABLE_RESERVED_RESET _u(0x00000000)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_MSB _u(31)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_LSB _u(1)
#define TRNG_RND_SOURCE_ENABLE_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RND_SOURCE_ENABLE_RND_SRC_EN
// Description : * 1'b1 - entropy source is enabled. *1'b0 - entropy source is
// disabled
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_RESET _u(0x0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_BITS _u(0x00000001)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_MSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_LSB _u(0)
#define TRNG_RND_SOURCE_ENABLE_RND_SRC_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_SAMPLE_CNT1
// Description : Counts clocks between sampling of random bit.
#define TRNG_SAMPLE_CNT1_OFFSET _u(0x00000130)
#define TRNG_SAMPLE_CNT1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_RESET _u(0x0000ffff)
// -----------------------------------------------------------------------------
// Field : TRNG_SAMPLE_CNT1_SAMPLE_CNTR1
// Description : Sets the number of rng_clk cycles between two consecutive ring
// oscillator samples. Note! If the Von-Neuman is bypassed, the
// minimum value for sample counter must not be less then decimal
// seventeen
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_RESET _u(0x0000ffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_BITS _u(0xffffffff)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_MSB _u(31)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_LSB _u(0)
#define TRNG_SAMPLE_CNT1_SAMPLE_CNTR1_ACCESS "RW"
// =============================================================================
// Register : TRNG_AUTOCORR_STATISTIC
// Description : Statistic about Autocorrelation test activations.
#define TRNG_AUTOCORR_STATISTIC_OFFSET _u(0x00000134)
#define TRNG_AUTOCORR_STATISTIC_BITS _u(0xffffffff)
#define TRNG_AUTOCORR_STATISTIC_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_RESERVED
// Description : RESERVED
#define TRNG_AUTOCORR_STATISTIC_RESERVED_RESET _u(0x000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_BITS _u(0xffc00000)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_MSB _u(31)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_LSB _u(22)
#define TRNG_AUTOCORR_STATISTIC_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS
// Description : Count each time an autocorrelation test fails. Any write to the
// register reset the counter. Stop collecting statistic if one of
// the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_RESET _u(0x00)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_BITS _u(0x003fc000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_MSB _u(21)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_LSB _u(14)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_FAILS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS
// Description : Count each time an autocorrelation test starts. Any write to
// the register reset the counter. Stop collecting statistic if
// one of the counters reached the limit.
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_RESET _u(0x0000)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_BITS _u(0x00003fff)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_MSB _u(13)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_LSB _u(0)
#define TRNG_AUTOCORR_STATISTIC_AUTOCORR_TRYS_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_DEBUG_CONTROL
// Description : Debug register.
#define TRNG_TRNG_DEBUG_CONTROL_OFFSET _u(0x00000138)
#define TRNG_TRNG_DEBUG_CONTROL_BITS _u(0x0000000f)
#define TRNG_TRNG_DEBUG_CONTROL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS
// Description : When set, the autocorrelation test in the TRNG module is
// bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_BITS _u(0x00000008)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_MSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_LSB _u(3)
#define TRNG_TRNG_DEBUG_CONTROL_AUTO_CORRELATE_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS
// Description : When set, the CRNGT test in the RNG is bypassed.
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_BITS _u(0x00000004)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_MSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_LSB _u(2)
#define TRNG_TRNG_DEBUG_CONTROL_TRNG_CRNGT_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS
// Description : When set, the Von-Neuman balancer is bypassed (including the 32
// consecutive bits test).
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_BITS _u(0x00000002)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_MSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_LSB _u(1)
#define TRNG_TRNG_DEBUG_CONTROL_VNC_BYPASS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_DEBUG_CONTROL_RESERVED
// Description : N/A
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_RESET _u(0x0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_BITS _u(0x00000001)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_MSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_LSB _u(0)
#define TRNG_TRNG_DEBUG_CONTROL_RESERVED_ACCESS "RO"
// =============================================================================
// Register : TRNG_TRNG_SW_RESET
// Description : Generate internal SW reset within the RNG block.
#define TRNG_TRNG_SW_RESET_OFFSET _u(0x00000140)
#define TRNG_TRNG_SW_RESET_BITS _u(0xffffffff)
#define TRNG_TRNG_SW_RESET_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_RESERVED
// Description : RESERVED
#define TRNG_TRNG_SW_RESET_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_SW_RESET_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_SW_RESET_RESERVED_MSB _u(31)
#define TRNG_TRNG_SW_RESET_RESERVED_LSB _u(1)
#define TRNG_TRNG_SW_RESET_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_SW_RESET_TRNG_SW_RESET
// Description : Writing 1'b1 to this register causes an internal RNG reset.
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_RESET _u(0x0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_BITS _u(0x00000001)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_MSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_LSB _u(0)
#define TRNG_TRNG_SW_RESET_TRNG_SW_RESET_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_DEBUG_EN_INPUT
// Description : Enable the RNG debug mode
#define TRNG_RNG_DEBUG_EN_INPUT_OFFSET _u(0x000001b4)
#define TRNG_RNG_DEBUG_EN_INPUT_BITS _u(0xffffffff)
#define TRNG_RNG_DEBUG_EN_INPUT_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RESERVED
// Description : RESERVED
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_RESET _u(0x00000000)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_MSB _u(31)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_LSB _u(1)
#define TRNG_RNG_DEBUG_EN_INPUT_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN
// Description : * 1'b1 - debug mode is enabled. *1'b0 - debug mode is disabled
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_RESET _u(0x0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_BITS _u(0x00000001)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_MSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_LSB _u(0)
#define TRNG_RNG_DEBUG_EN_INPUT_RNG_DEBUG_EN_ACCESS "RW"
// =============================================================================
// Register : TRNG_TRNG_BUSY
// Description : RNG Busy indication.
#define TRNG_TRNG_BUSY_OFFSET _u(0x000001b8)
#define TRNG_TRNG_BUSY_BITS _u(0xffffffff)
#define TRNG_TRNG_BUSY_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_RESERVED
// Description : RESERVED
#define TRNG_TRNG_BUSY_RESERVED_RESET _u(0x00000000)
#define TRNG_TRNG_BUSY_RESERVED_BITS _u(0xfffffffe)
#define TRNG_TRNG_BUSY_RESERVED_MSB _u(31)
#define TRNG_TRNG_BUSY_RESERVED_LSB _u(1)
#define TRNG_TRNG_BUSY_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_TRNG_BUSY_TRNG_BUSY
// Description : Reflects rng_busy status.
#define TRNG_TRNG_BUSY_TRNG_BUSY_RESET _u(0x0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_BITS _u(0x00000001)
#define TRNG_TRNG_BUSY_TRNG_BUSY_MSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_LSB _u(0)
#define TRNG_TRNG_BUSY_TRNG_BUSY_ACCESS "RO"
// =============================================================================
// Register : TRNG_RST_BITS_COUNTER
// Description : Reset the counter of collected bits in the RNG.
#define TRNG_RST_BITS_COUNTER_OFFSET _u(0x000001bc)
#define TRNG_RST_BITS_COUNTER_BITS _u(0xffffffff)
#define TRNG_RST_BITS_COUNTER_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RESERVED
// Description : RESERVED
#define TRNG_RST_BITS_COUNTER_RESERVED_RESET _u(0x00000000)
#define TRNG_RST_BITS_COUNTER_RESERVED_BITS _u(0xfffffffe)
#define TRNG_RST_BITS_COUNTER_RESERVED_MSB _u(31)
#define TRNG_RST_BITS_COUNTER_RESERVED_LSB _u(1)
#define TRNG_RST_BITS_COUNTER_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER
// Description : Writing any value to this address will reset the bits counter
// and RNG valid registers. RND_SORCE_ENABLE register must be
// unset in order for the reset to take place.
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_RESET _u(0x0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_BITS _u(0x00000001)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_MSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_LSB _u(0)
#define TRNG_RST_BITS_COUNTER_RST_BITS_COUNTER_ACCESS "RW"
// =============================================================================
// Register : TRNG_RNG_VERSION
// Description : Displays the version settings of the TRNG.
#define TRNG_RNG_VERSION_OFFSET _u(0x000001c0)
#define TRNG_RNG_VERSION_BITS _u(0xffffffff)
#define TRNG_RNG_VERSION_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESERVED
// Description : RESERVED
#define TRNG_RNG_VERSION_RESERVED_RESET _u(0x000000)
#define TRNG_RNG_VERSION_RESERVED_BITS _u(0xffffff00)
#define TRNG_RNG_VERSION_RESERVED_MSB _u(31)
#define TRNG_RNG_VERSION_RESERVED_LSB _u(8)
#define TRNG_RNG_VERSION_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RNG_USE_5_SBOXES
// Description : * 1'b1 - 5 SBOX AES. *1'b0 - 20 SBOX AES
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_RESET _u(0x0)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_BITS _u(0x00000080)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_MSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_LSB _u(7)
#define TRNG_RNG_VERSION_RNG_USE_5_SBOXES_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_RESEEDING_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_BITS _u(0x00000040)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_MSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_LSB _u(6)
#define TRNG_RNG_VERSION_RESEEDING_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_KAT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_KAT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_KAT_EXISTS_BITS _u(0x00000020)
#define TRNG_RNG_VERSION_KAT_EXISTS_MSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_LSB _u(5)
#define TRNG_RNG_VERSION_KAT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_PRNG_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_PRNG_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_PRNG_EXISTS_BITS _u(0x00000010)
#define TRNG_RNG_VERSION_PRNG_EXISTS_MSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_LSB _u(4)
#define TRNG_RNG_VERSION_PRNG_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_RESET _u(0x0)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_BITS _u(0x00000008)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_MSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_LSB _u(3)
#define TRNG_RNG_VERSION_TRNG_TESTS_BYPASS_EN_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_AUTOCORR_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_BITS _u(0x00000004)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_MSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_LSB _u(2)
#define TRNG_RNG_VERSION_AUTOCORR_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_CRNGT_EXISTS
// Description : * 1'b1 - Exists. *1'b0 - Does not exist
#define TRNG_RNG_VERSION_CRNGT_EXISTS_RESET _u(0x0)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_BITS _u(0x00000002)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_MSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_LSB _u(1)
#define TRNG_RNG_VERSION_CRNGT_EXISTS_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_VERSION_EHR_WIDTH_192
// Description : * 1'b1 - 192-bit EHR. *1'b0 - 128-bit EHR
#define TRNG_RNG_VERSION_EHR_WIDTH_192_RESET _u(0x0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_BITS _u(0x00000001)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_MSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_LSB _u(0)
#define TRNG_RNG_VERSION_EHR_WIDTH_192_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_0
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_0_OFFSET _u(0x000001e0)
#define TRNG_RNG_BIST_CNTR_0_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_0_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_0_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_0_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_0_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_1
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_1_OFFSET _u(0x000001e4)
#define TRNG_RNG_BIST_CNTR_1_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_1_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_1_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_1_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_1_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
// Register : TRNG_RNG_BIST_CNTR_2
// Description : Collected BIST results.
#define TRNG_RNG_BIST_CNTR_2_OFFSET _u(0x000001e8)
#define TRNG_RNG_BIST_CNTR_2_BITS _u(0xffffffff)
#define TRNG_RNG_BIST_CNTR_2_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_RESERVED
// Description : RESERVED
#define TRNG_RNG_BIST_CNTR_2_RESERVED_RESET _u(0x000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_BITS _u(0xffc00000)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_MSB _u(31)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_LSB _u(22)
#define TRNG_RNG_BIST_CNTR_2_RESERVED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL
// Description : Reflects the results of RNG BIST counter.
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_RESET _u(0x000000)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_BITS _u(0x003fffff)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_MSB _u(21)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_LSB _u(0)
#define TRNG_RNG_BIST_CNTR_2_ROSC_CNTR_VAL_ACCESS "RO"
// =============================================================================
#endif // _HARDWARE_REGS_TRNG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : WATCHDOG
// Version : 1
// Bus type : apb
// =============================================================================
#ifndef _HARDWARE_REGS_WATCHDOG_H
#define _HARDWARE_REGS_WATCHDOG_H
// =============================================================================
// Register : WATCHDOG_CTRL
// Description : Watchdog control
// The rst_wdsel register determines which subsystems are reset
// when the watchdog is triggered.
// The watchdog can be triggered in software.
#define WATCHDOG_CTRL_OFFSET _u(0x00000000)
#define WATCHDOG_CTRL_BITS _u(0xc7ffffff)
#define WATCHDOG_CTRL_RESET _u(0x07000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TRIGGER
// Description : Trigger a watchdog reset
#define WATCHDOG_CTRL_TRIGGER_RESET _u(0x0)
#define WATCHDOG_CTRL_TRIGGER_BITS _u(0x80000000)
#define WATCHDOG_CTRL_TRIGGER_MSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_LSB _u(31)
#define WATCHDOG_CTRL_TRIGGER_ACCESS "SC"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_ENABLE
// Description : When not enabled the watchdog timer is paused
#define WATCHDOG_CTRL_ENABLE_RESET _u(0x0)
#define WATCHDOG_CTRL_ENABLE_BITS _u(0x40000000)
#define WATCHDOG_CTRL_ENABLE_MSB _u(30)
#define WATCHDOG_CTRL_ENABLE_LSB _u(30)
#define WATCHDOG_CTRL_ENABLE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG1
// Description : Pause the watchdog timer when processor 1 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG1_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG1_BITS _u(0x04000000)
#define WATCHDOG_CTRL_PAUSE_DBG1_MSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_LSB _u(26)
#define WATCHDOG_CTRL_PAUSE_DBG1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_DBG0
// Description : Pause the watchdog timer when processor 0 is in debug mode
#define WATCHDOG_CTRL_PAUSE_DBG0_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_DBG0_BITS _u(0x02000000)
#define WATCHDOG_CTRL_PAUSE_DBG0_MSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_LSB _u(25)
#define WATCHDOG_CTRL_PAUSE_DBG0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_PAUSE_JTAG
// Description : Pause the watchdog timer when JTAG is accessing the bus fabric
#define WATCHDOG_CTRL_PAUSE_JTAG_RESET _u(0x1)
#define WATCHDOG_CTRL_PAUSE_JTAG_BITS _u(0x01000000)
#define WATCHDOG_CTRL_PAUSE_JTAG_MSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_LSB _u(24)
#define WATCHDOG_CTRL_PAUSE_JTAG_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_CTRL_TIME
// Description : Indicates the time in usec before a watchdog reset will be
// triggered
#define WATCHDOG_CTRL_TIME_RESET _u(0x000000)
#define WATCHDOG_CTRL_TIME_BITS _u(0x00ffffff)
#define WATCHDOG_CTRL_TIME_MSB _u(23)
#define WATCHDOG_CTRL_TIME_LSB _u(0)
#define WATCHDOG_CTRL_TIME_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_LOAD
// Description : Load the watchdog timer. The maximum setting is 0xffffff which
// corresponds to approximately 16 seconds.
#define WATCHDOG_LOAD_OFFSET _u(0x00000004)
#define WATCHDOG_LOAD_BITS _u(0x00ffffff)
#define WATCHDOG_LOAD_RESET _u(0x00000000)
#define WATCHDOG_LOAD_MSB _u(23)
#define WATCHDOG_LOAD_LSB _u(0)
#define WATCHDOG_LOAD_ACCESS "WF"
// =============================================================================
// Register : WATCHDOG_REASON
// Description : Logs the reason for the last reset. Both bits are zero for the
// case of a hardware reset.
//
// Additionally, as of RP2350, a debugger warm reset of either
// core (SYSRESETREQ or hartreset) will also clear the watchdog
// reason register, so that software loaded under the debugger
// following a watchdog timeout will not continue to see the
// timeout condition.
#define WATCHDOG_REASON_OFFSET _u(0x00000008)
#define WATCHDOG_REASON_BITS _u(0x00000003)
#define WATCHDOG_REASON_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_FORCE
#define WATCHDOG_REASON_FORCE_RESET _u(0x0)
#define WATCHDOG_REASON_FORCE_BITS _u(0x00000002)
#define WATCHDOG_REASON_FORCE_MSB _u(1)
#define WATCHDOG_REASON_FORCE_LSB _u(1)
#define WATCHDOG_REASON_FORCE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : WATCHDOG_REASON_TIMER
#define WATCHDOG_REASON_TIMER_RESET _u(0x0)
#define WATCHDOG_REASON_TIMER_BITS _u(0x00000001)
#define WATCHDOG_REASON_TIMER_MSB _u(0)
#define WATCHDOG_REASON_TIMER_LSB _u(0)
#define WATCHDOG_REASON_TIMER_ACCESS "RO"
// =============================================================================
// Register : WATCHDOG_SCRATCH0
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH0_OFFSET _u(0x0000000c)
#define WATCHDOG_SCRATCH0_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH0_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH0_MSB _u(31)
#define WATCHDOG_SCRATCH0_LSB _u(0)
#define WATCHDOG_SCRATCH0_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH1
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH1_OFFSET _u(0x00000010)
#define WATCHDOG_SCRATCH1_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH1_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH1_MSB _u(31)
#define WATCHDOG_SCRATCH1_LSB _u(0)
#define WATCHDOG_SCRATCH1_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH2
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH2_OFFSET _u(0x00000014)
#define WATCHDOG_SCRATCH2_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH2_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH2_MSB _u(31)
#define WATCHDOG_SCRATCH2_LSB _u(0)
#define WATCHDOG_SCRATCH2_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH3
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH3_OFFSET _u(0x00000018)
#define WATCHDOG_SCRATCH3_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH3_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH3_MSB _u(31)
#define WATCHDOG_SCRATCH3_LSB _u(0)
#define WATCHDOG_SCRATCH3_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH4
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH4_OFFSET _u(0x0000001c)
#define WATCHDOG_SCRATCH4_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH4_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH4_MSB _u(31)
#define WATCHDOG_SCRATCH4_LSB _u(0)
#define WATCHDOG_SCRATCH4_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH5
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH5_OFFSET _u(0x00000020)
#define WATCHDOG_SCRATCH5_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH5_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH5_MSB _u(31)
#define WATCHDOG_SCRATCH5_LSB _u(0)
#define WATCHDOG_SCRATCH5_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH6
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH6_OFFSET _u(0x00000024)
#define WATCHDOG_SCRATCH6_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH6_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH6_MSB _u(31)
#define WATCHDOG_SCRATCH6_LSB _u(0)
#define WATCHDOG_SCRATCH6_ACCESS "RW"
// =============================================================================
// Register : WATCHDOG_SCRATCH7
// Description : Scratch register. Information persists through soft reset of
// the chip.
#define WATCHDOG_SCRATCH7_OFFSET _u(0x00000028)
#define WATCHDOG_SCRATCH7_BITS _u(0xffffffff)
#define WATCHDOG_SCRATCH7_RESET _u(0x00000000)
#define WATCHDOG_SCRATCH7_MSB _u(31)
#define WATCHDOG_SCRATCH7_LSB _u(0)
#define WATCHDOG_SCRATCH7_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_WATCHDOG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP
// Version : 1
// Bus type : ahb
// Description : QSPI flash execute-in-place block
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_H
#define _HARDWARE_REGS_XIP_H
// =============================================================================
// Register : XIP_CTRL
// Description : Cache control register. Read-only from a Non-secure context.
#define XIP_CTRL_OFFSET _u(0x00000000)
#define XIP_CTRL_BITS _u(0x00000ffb)
#define XIP_CTRL_RESET _u(0x00000083)
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M1
// Description : If 1, enable writes to XIP memory window 1 (addresses
// 0x11000000 through 0x11ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 1.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M1_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M1_BITS _u(0x00000800)
#define XIP_CTRL_WRITABLE_M1_MSB _u(11)
#define XIP_CTRL_WRITABLE_M1_LSB _u(11)
#define XIP_CTRL_WRITABLE_M1_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_WRITABLE_M0
// Description : If 1, enable writes to XIP memory window 0 (addresses
// 0x10000000 through 0x10ffffff, and their uncached mirrors). If
// 0, this region is read-only.
//
// XIP memory is *read-only by default*. This bit must be set to
// enable writes if a RAM device is attached on QSPI chip select
// 0.
//
// The default read-only behaviour avoids two issues with writing
// to a read-only QSPI device (e.g. flash). First, a write will
// initially appear to succeed due to caching, but the data will
// eventually be lost when the written line is evicted, causing
// unpredictable behaviour.
//
// Second, when a written line is evicted, it will cause a write
// command to be issued to the flash, which can break the flash
// out of its continuous read mode. After this point, flash reads
// will return garbage. This is a security concern, as it allows
// Non-secure software to break Secure flash reads if it has
// permission to write to any flash address.
//
// Note the read-only behaviour is implemented by downgrading
// writes to reads, so writes will still cause allocation of an
// address, but have no other effect.
#define XIP_CTRL_WRITABLE_M0_RESET _u(0x0)
#define XIP_CTRL_WRITABLE_M0_BITS _u(0x00000400)
#define XIP_CTRL_WRITABLE_M0_MSB _u(10)
#define XIP_CTRL_WRITABLE_M0_LSB _u(10)
#define XIP_CTRL_WRITABLE_M0_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_SPLIT_WAYS
// Description : When 1, route all cached+Secure accesses to way 0 of the cache,
// and route all cached+Non-secure accesses to way 1 of the cache.
//
// This partitions the cache into two half-sized direct-mapped
// regions, such that Non-secure code can not observe cache line
// state changes caused by Secure execution.
//
// A full cache flush is required when changing the value of
// SPLIT_WAYS. The flush should be performed whilst SPLIT_WAYS is
// 0, so that both cache ways are accessible for invalidation.
#define XIP_CTRL_SPLIT_WAYS_RESET _u(0x0)
#define XIP_CTRL_SPLIT_WAYS_BITS _u(0x00000200)
#define XIP_CTRL_SPLIT_WAYS_MSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_LSB _u(9)
#define XIP_CTRL_SPLIT_WAYS_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_MAINT_NONSEC
// Description : When 0, Non-secure accesses to the cache maintenance address
// window (addr[27] == 1, addr[26] == 0) will generate a bus
// error. When 1, Non-secure accesses can perform cache
// maintenance operations by writing to the cache maintenance
// address window.
//
// Cache maintenance operations may be used to corrupt Secure data
// by invalidating cache lines inappropriately, or map Secure
// content into a Non-secure region by pinning cache lines.
// Therefore this bit should generally be set to 0, unless Secure
// code is not using the cache.
//
// Care should also be taken to clear the cache data memory and
// tag memory before granting maintenance operations to Non-secure
// code.
#define XIP_CTRL_MAINT_NONSEC_RESET _u(0x0)
#define XIP_CTRL_MAINT_NONSEC_BITS _u(0x00000100)
#define XIP_CTRL_MAINT_NONSEC_MSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_LSB _u(8)
#define XIP_CTRL_MAINT_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_NONSEC
// Description : When 1, Non-secure accesses to the uncached, untranslated
// window (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_RESET _u(0x1)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_BITS _u(0x00000080)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_MSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_LSB _u(7)
#define XIP_CTRL_NO_UNTRANSLATED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNTRANSLATED_SEC
// Description : When 1, Secure accesses to the uncached, untranslated window
// (addr[27:26] == 3) will generate a bus error.
#define XIP_CTRL_NO_UNTRANSLATED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_BITS _u(0x00000040)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_MSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_LSB _u(6)
#define XIP_CTRL_NO_UNTRANSLATED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_NONSEC
// Description : When 1, Non-secure accesses to the uncached window (addr[27:26]
// == 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_NONSEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_NONSEC_BITS _u(0x00000020)
#define XIP_CTRL_NO_UNCACHED_NONSEC_MSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_LSB _u(5)
#define XIP_CTRL_NO_UNCACHED_NONSEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_NO_UNCACHED_SEC
// Description : When 1, Secure accesses to the uncached window (addr[27:26] ==
// 1) will generate a bus error. This may reduce the number of
// SAU/MPU/PMP regions required to protect flash contents.
//
// Note this does not disable access to the uncached, untranslated
// window -- see NO_UNTRANSLATED_SEC.
#define XIP_CTRL_NO_UNCACHED_SEC_RESET _u(0x0)
#define XIP_CTRL_NO_UNCACHED_SEC_BITS _u(0x00000010)
#define XIP_CTRL_NO_UNCACHED_SEC_MSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_LSB _u(4)
#define XIP_CTRL_NO_UNCACHED_SEC_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_POWER_DOWN
// Description : When 1, the cache memories are powered down. They retain state,
// but can not be accessed. This reduces static power dissipation.
// Writing 1 to this bit forces CTRL_EN_SECURE and
// CTRL_EN_NONSECURE to 0, i.e. the cache cannot be enabled when
// powered down.
#define XIP_CTRL_POWER_DOWN_RESET _u(0x0)
#define XIP_CTRL_POWER_DOWN_BITS _u(0x00000008)
#define XIP_CTRL_POWER_DOWN_MSB _u(3)
#define XIP_CTRL_POWER_DOWN_LSB _u(3)
#define XIP_CTRL_POWER_DOWN_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_NONSECURE
// Description : When 1, enable the cache for Non-secure accesses. When enabled,
// Non-secure XIP accesses to the cached (addr[26] == 0) window
// will query the cache, and QSPI accesses are performed only if
// the requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
#define XIP_CTRL_EN_NONSECURE_RESET _u(0x1)
#define XIP_CTRL_EN_NONSECURE_BITS _u(0x00000002)
#define XIP_CTRL_EN_NONSECURE_MSB _u(1)
#define XIP_CTRL_EN_NONSECURE_LSB _u(1)
#define XIP_CTRL_EN_NONSECURE_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XIP_CTRL_EN_SECURE
// Description : When 1, enable the cache for Secure accesses. When enabled,
// Secure XIP accesses to the cached (addr[26] == 0) window will
// query the cache, and QSPI accesses are performed only if the
// requested data is not present. When disabled, Secure access
// ignore the cache contents, and always access the QSPI
// interface.
//
// Accesses to the uncached (addr[26] == 1) window will never
// query the cache, irrespective of this bit.
//
// There is no cache-as-SRAM address window. Cache lines are
// allocated for SRAM-like use by individually pinning them, and
// keeping the cache enabled.
#define XIP_CTRL_EN_SECURE_RESET _u(0x1)
#define XIP_CTRL_EN_SECURE_BITS _u(0x00000001)
#define XIP_CTRL_EN_SECURE_MSB _u(0)
#define XIP_CTRL_EN_SECURE_LSB _u(0)
#define XIP_CTRL_EN_SECURE_ACCESS "RW"
// =============================================================================
// Register : XIP_STAT
#define XIP_STAT_OFFSET _u(0x00000008)
#define XIP_STAT_BITS _u(0x00000006)
#define XIP_STAT_RESET _u(0x00000002)
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_FULL
// Description : When 1, indicates the XIP streaming FIFO is completely full.
// The streaming FIFO is 2 entries deep, so the full and empty
// flag allow its level to be ascertained.
#define XIP_STAT_FIFO_FULL_RESET _u(0x0)
#define XIP_STAT_FIFO_FULL_BITS _u(0x00000004)
#define XIP_STAT_FIFO_FULL_MSB _u(2)
#define XIP_STAT_FIFO_FULL_LSB _u(2)
#define XIP_STAT_FIFO_FULL_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XIP_STAT_FIFO_EMPTY
// Description : When 1, indicates the XIP streaming FIFO is completely empty.
#define XIP_STAT_FIFO_EMPTY_RESET _u(0x1)
#define XIP_STAT_FIFO_EMPTY_BITS _u(0x00000002)
#define XIP_STAT_FIFO_EMPTY_MSB _u(1)
#define XIP_STAT_FIFO_EMPTY_LSB _u(1)
#define XIP_STAT_FIFO_EMPTY_ACCESS "RO"
// =============================================================================
// Register : XIP_CTR_HIT
// Description : Cache Hit counter
// A 32 bit saturating counter that increments upon each cache
// hit,
// i.e. when an XIP access is serviced directly from cached data.
// Write any value to clear.
#define XIP_CTR_HIT_OFFSET _u(0x0000000c)
#define XIP_CTR_HIT_BITS _u(0xffffffff)
#define XIP_CTR_HIT_RESET _u(0x00000000)
#define XIP_CTR_HIT_MSB _u(31)
#define XIP_CTR_HIT_LSB _u(0)
#define XIP_CTR_HIT_ACCESS "WC"
// =============================================================================
// Register : XIP_CTR_ACC
// Description : Cache Access counter
// A 32 bit saturating counter that increments upon each XIP
// access,
// whether the cache is hit or not. This includes noncacheable
// accesses.
// Write any value to clear.
#define XIP_CTR_ACC_OFFSET _u(0x00000010)
#define XIP_CTR_ACC_BITS _u(0xffffffff)
#define XIP_CTR_ACC_RESET _u(0x00000000)
#define XIP_CTR_ACC_MSB _u(31)
#define XIP_CTR_ACC_LSB _u(0)
#define XIP_CTR_ACC_ACCESS "WC"
// =============================================================================
// Register : XIP_STREAM_ADDR
// Description : FIFO stream address
// The address of the next word to be streamed from flash to the
// streaming FIFO.
// Increments automatically after each flash access.
// Write the initial access address here before starting a
// streaming read.
#define XIP_STREAM_ADDR_OFFSET _u(0x00000014)
#define XIP_STREAM_ADDR_BITS _u(0xfffffffc)
#define XIP_STREAM_ADDR_RESET _u(0x00000000)
#define XIP_STREAM_ADDR_MSB _u(31)
#define XIP_STREAM_ADDR_LSB _u(2)
#define XIP_STREAM_ADDR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_CTR
// Description : FIFO stream control
// Write a nonzero value to start a streaming read. This will then
// progress in the background, using flash idle cycles to transfer
// a linear data block from flash to the streaming FIFO.
// Decrements automatically (1 at a time) as the stream
// progresses, and halts on reaching 0.
// Write 0 to halt an in-progress stream, and discard any in-
// flight
// read, so that a new stream can immediately be started (after
// draining the FIFO and reinitialising STREAM_ADDR)
#define XIP_STREAM_CTR_OFFSET _u(0x00000018)
#define XIP_STREAM_CTR_BITS _u(0x003fffff)
#define XIP_STREAM_CTR_RESET _u(0x00000000)
#define XIP_STREAM_CTR_MSB _u(21)
#define XIP_STREAM_CTR_LSB _u(0)
#define XIP_STREAM_CTR_ACCESS "RW"
// =============================================================================
// Register : XIP_STREAM_FIFO
// Description : FIFO stream data
// Streamed data is buffered here, for retrieval by the system
// DMA.
// This FIFO can also be accessed via the XIP_AUX slave, to avoid
// exposing
// the DMA to bus stalls caused by other XIP traffic.
#define XIP_STREAM_FIFO_OFFSET _u(0x0000001c)
#define XIP_STREAM_FIFO_BITS _u(0xffffffff)
#define XIP_STREAM_FIFO_RESET _u(0x00000000)
#define XIP_STREAM_FIFO_MSB _u(31)
#define XIP_STREAM_FIFO_LSB _u(0)
#define XIP_STREAM_FIFO_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XIP_AUX
// Version : 1
// Bus type : ahb
// Description : Auxiliary DMA access to XIP FIFOs, via fast AHB bus access
// =============================================================================
#ifndef _HARDWARE_REGS_XIP_AUX_H
#define _HARDWARE_REGS_XIP_AUX_H
// =============================================================================
// Register : XIP_AUX_STREAM
// Description : Read the XIP stream FIFO (fast bus access to
// XIP_CTRL_STREAM_FIFO)
#define XIP_AUX_STREAM_OFFSET _u(0x00000000)
#define XIP_AUX_STREAM_BITS _u(0xffffffff)
#define XIP_AUX_STREAM_RESET _u(0x00000000)
#define XIP_AUX_STREAM_MSB _u(31)
#define XIP_AUX_STREAM_LSB _u(0)
#define XIP_AUX_STREAM_ACCESS "RF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_TX
// Description : Write to the QMI direct-mode TX FIFO (fast bus access to
// QMI_DIRECT_TX)
#define XIP_AUX_QMI_DIRECT_TX_OFFSET _u(0x00000004)
#define XIP_AUX_QMI_DIRECT_TX_BITS _u(0x001fffff)
#define XIP_AUX_QMI_DIRECT_TX_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_NOPUSH
// Description : Inhibit the RX FIFO push that would correspond to this TX FIFO
// entry.
//
// Useful to avoid garbage appearing in the RX FIFO when pushing
// the command at the beginning of a SPI transfer.
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_BITS _u(0x00100000)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_MSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_LSB _u(20)
#define XIP_AUX_QMI_DIRECT_TX_NOPUSH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_OE
// Description : Output enable (active-high). For single width (SPI), this field
// is ignored, and SD0 is always set to output, with SD1 always
// set to input.
//
// For dual and quad width (DSPI/QSPI), this sets whether the
// relevant SDx pads are set to output whilst transferring this
// FIFO record. In this case the command/address should have OE
// set, and the data transfer should have OE set or clear
// depending on the direction of the transfer.
#define XIP_AUX_QMI_DIRECT_TX_OE_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_OE_BITS _u(0x00080000)
#define XIP_AUX_QMI_DIRECT_TX_OE_MSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_LSB _u(19)
#define XIP_AUX_QMI_DIRECT_TX_OE_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DWIDTH
// Description : Data width. If 0, hardware will transmit the 8 LSBs of the
// DIRECT_TX DATA field, and return an 8-bit value in the 8 LSBs
// of DIRECT_RX. If 1, the full 16-bit width is used. 8-bit and
// 16-bit transfers can be mixed freely.
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_BITS _u(0x00040000)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_MSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_LSB _u(18)
#define XIP_AUX_QMI_DIRECT_TX_DWIDTH_ACCESS "WF"
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_IWIDTH
// Description : Configure whether this FIFO record is transferred with
// single/dual/quad interface width (0/1/2). Different widths can
// be mixed freely.
// 0x0 -> Single width
// 0x1 -> Dual width
// 0x2 -> Quad width
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_RESET _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_BITS _u(0x00030000)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_MSB _u(17)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_LSB _u(16)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_ACCESS "WF"
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_S _u(0x0)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_D _u(0x1)
#define XIP_AUX_QMI_DIRECT_TX_IWIDTH_VALUE_Q _u(0x2)
// -----------------------------------------------------------------------------
// Field : XIP_AUX_QMI_DIRECT_TX_DATA
// Description : Data pushed here will be clocked out falling edges of SCK (or
// before the very first rising edge of SCK, if this is the first
// pulse). For each byte clocked out, the interface will
// simultaneously sample one byte, on rising edges of SCK, and
// push this to the DIRECT_RX FIFO.
//
// For 16-bit data, the least-significant byte is transmitted
// first.
#define XIP_AUX_QMI_DIRECT_TX_DATA_RESET _u(0x0000)
#define XIP_AUX_QMI_DIRECT_TX_DATA_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_TX_DATA_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_TX_DATA_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_TX_DATA_ACCESS "WF"
// =============================================================================
// Register : XIP_AUX_QMI_DIRECT_RX
// Description : Read from the QMI direct-mode RX FIFO (fast bus access to
// QMI_DIRECT_RX)
// With each byte clocked out on the serial interface, one byte
// will simultaneously be clocked in, and will appear in this
// FIFO. The serial interface will stall when this FIFO is full,
// to avoid dropping data.
//
// When 16-bit data is pushed into the TX FIFO, the corresponding
// RX FIFO push will also contain 16 bits of data. The least-
// significant byte is the first one received.
#define XIP_AUX_QMI_DIRECT_RX_OFFSET _u(0x00000008)
#define XIP_AUX_QMI_DIRECT_RX_BITS _u(0x0000ffff)
#define XIP_AUX_QMI_DIRECT_RX_RESET _u(0x00000000)
#define XIP_AUX_QMI_DIRECT_RX_MSB _u(15)
#define XIP_AUX_QMI_DIRECT_RX_LSB _u(0)
#define XIP_AUX_QMI_DIRECT_RX_ACCESS "RF"
// =============================================================================
#endif // _HARDWARE_REGS_XIP_AUX_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// =============================================================================
// Register block : XOSC
// Version : 1
// Bus type : apb
// Description : Controls the crystal oscillator
// =============================================================================
#ifndef _HARDWARE_REGS_XOSC_H
#define _HARDWARE_REGS_XOSC_H
// =============================================================================
// Register : XOSC_CTRL
// Description : Crystal Oscillator Control
#define XOSC_CTRL_OFFSET _u(0x00000000)
#define XOSC_CTRL_BITS _u(0x00ffffff)
#define XOSC_CTRL_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_ENABLE
// Description : On power-up this field is initialised to DISABLE and the chip
// runs from the ROSC.
// If the chip has subsequently been programmed to run from the
// XOSC then setting this field to DISABLE may lock-up the chip.
// If this is a concern then run the clk_ref from the ROSC and
// enable the clk_sys RESUS feature.
// The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_ENABLED
// 0xd1e -> DISABLE
// 0xfab -> ENABLE
#define XOSC_CTRL_ENABLE_RESET "-"
#define XOSC_CTRL_ENABLE_BITS _u(0x00fff000)
#define XOSC_CTRL_ENABLE_MSB _u(23)
#define XOSC_CTRL_ENABLE_LSB _u(12)
#define XOSC_CTRL_ENABLE_ACCESS "RW"
#define XOSC_CTRL_ENABLE_VALUE_DISABLE _u(0xd1e)
#define XOSC_CTRL_ENABLE_VALUE_ENABLE _u(0xfab)
// -----------------------------------------------------------------------------
// Field : XOSC_CTRL_FREQ_RANGE
// Description : The 12-bit code is intended to give some protection against
// accidental writes. An invalid setting will retain the previous
// value. The actual value being used can be read from
// STATUS_FREQ_RANGE
// 0xaa0 -> 1_15MHZ
// 0xaa1 -> 10_30MHZ
// 0xaa2 -> 25_60MHZ
// 0xaa3 -> 40_100MHZ
#define XOSC_CTRL_FREQ_RANGE_RESET "-"
#define XOSC_CTRL_FREQ_RANGE_BITS _u(0x00000fff)
#define XOSC_CTRL_FREQ_RANGE_MSB _u(11)
#define XOSC_CTRL_FREQ_RANGE_LSB _u(0)
#define XOSC_CTRL_FREQ_RANGE_ACCESS "RW"
#define XOSC_CTRL_FREQ_RANGE_VALUE_1_15MHZ _u(0xaa0)
#define XOSC_CTRL_FREQ_RANGE_VALUE_10_30MHZ _u(0xaa1)
#define XOSC_CTRL_FREQ_RANGE_VALUE_25_60MHZ _u(0xaa2)
#define XOSC_CTRL_FREQ_RANGE_VALUE_40_100MHZ _u(0xaa3)
// =============================================================================
// Register : XOSC_STATUS
// Description : Crystal Oscillator Status
#define XOSC_STATUS_OFFSET _u(0x00000004)
#define XOSC_STATUS_BITS _u(0x81001003)
#define XOSC_STATUS_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_STABLE
// Description : Oscillator is running and stable
#define XOSC_STATUS_STABLE_RESET _u(0x0)
#define XOSC_STATUS_STABLE_BITS _u(0x80000000)
#define XOSC_STATUS_STABLE_MSB _u(31)
#define XOSC_STATUS_STABLE_LSB _u(31)
#define XOSC_STATUS_STABLE_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_BADWRITE
// Description : An invalid value has been written to CTRL_ENABLE or
// CTRL_FREQ_RANGE or DORMANT
#define XOSC_STATUS_BADWRITE_RESET _u(0x0)
#define XOSC_STATUS_BADWRITE_BITS _u(0x01000000)
#define XOSC_STATUS_BADWRITE_MSB _u(24)
#define XOSC_STATUS_BADWRITE_LSB _u(24)
#define XOSC_STATUS_BADWRITE_ACCESS "WC"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_ENABLED
// Description : Oscillator is enabled but not necessarily running and stable,
// resets to 0
#define XOSC_STATUS_ENABLED_RESET "-"
#define XOSC_STATUS_ENABLED_BITS _u(0x00001000)
#define XOSC_STATUS_ENABLED_MSB _u(12)
#define XOSC_STATUS_ENABLED_LSB _u(12)
#define XOSC_STATUS_ENABLED_ACCESS "RO"
// -----------------------------------------------------------------------------
// Field : XOSC_STATUS_FREQ_RANGE
// Description : The current frequency range setting
// 0x0 -> 1_15MHZ
// 0x1 -> 10_30MHZ
// 0x2 -> 25_60MHZ
// 0x3 -> 40_100MHZ
#define XOSC_STATUS_FREQ_RANGE_RESET "-"
#define XOSC_STATUS_FREQ_RANGE_BITS _u(0x00000003)
#define XOSC_STATUS_FREQ_RANGE_MSB _u(1)
#define XOSC_STATUS_FREQ_RANGE_LSB _u(0)
#define XOSC_STATUS_FREQ_RANGE_ACCESS "RO"
#define XOSC_STATUS_FREQ_RANGE_VALUE_1_15MHZ _u(0x0)
#define XOSC_STATUS_FREQ_RANGE_VALUE_10_30MHZ _u(0x1)
#define XOSC_STATUS_FREQ_RANGE_VALUE_25_60MHZ _u(0x2)
#define XOSC_STATUS_FREQ_RANGE_VALUE_40_100MHZ _u(0x3)
// =============================================================================
// Register : XOSC_DORMANT
// Description : Crystal Oscillator pause control
// This is used to save power by pausing the XOSC
// On power-up this field is initialised to WAKE
// An invalid write will also select WAKE
// Warning: stop the PLLs before selecting dormant mode
// Warning: setup the irq before selecting dormant mode
// 0x636f6d61 -> dormant
// 0x77616b65 -> WAKE
#define XOSC_DORMANT_OFFSET _u(0x00000008)
#define XOSC_DORMANT_BITS _u(0xffffffff)
#define XOSC_DORMANT_RESET "-"
#define XOSC_DORMANT_MSB _u(31)
#define XOSC_DORMANT_LSB _u(0)
#define XOSC_DORMANT_ACCESS "RW"
#define XOSC_DORMANT_VALUE_DORMANT _u(0x636f6d61)
#define XOSC_DORMANT_VALUE_WAKE _u(0x77616b65)
// =============================================================================
// Register : XOSC_STARTUP
// Description : Controls the startup delay
#define XOSC_STARTUP_OFFSET _u(0x0000000c)
#define XOSC_STARTUP_BITS _u(0x00103fff)
#define XOSC_STARTUP_RESET _u(0x00000000)
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_X4
// Description : Multiplies the startup_delay by 4, just in case. The reset
// value is controlled by a mask-programmable tiecell and is
// provided in case we are booting from XOSC and the default
// startup delay is insufficient. The reset value is 0x0.
#define XOSC_STARTUP_X4_RESET "-"
#define XOSC_STARTUP_X4_BITS _u(0x00100000)
#define XOSC_STARTUP_X4_MSB _u(20)
#define XOSC_STARTUP_X4_LSB _u(20)
#define XOSC_STARTUP_X4_ACCESS "RW"
// -----------------------------------------------------------------------------
// Field : XOSC_STARTUP_DELAY
// Description : in multiples of 256*xtal_period. The reset value of 0xc4
// corresponds to approx 50 000 cycles.
#define XOSC_STARTUP_DELAY_RESET "-"
#define XOSC_STARTUP_DELAY_BITS _u(0x00003fff)
#define XOSC_STARTUP_DELAY_MSB _u(13)
#define XOSC_STARTUP_DELAY_LSB _u(0)
#define XOSC_STARTUP_DELAY_ACCESS "RW"
// =============================================================================
// Register : XOSC_COUNT
// Description : A down counter running at the xosc frequency which counts to
// zero and stops.
// Can be used for short software pauses when setting up time
// sensitive hardware.
// To start the counter, write a non-zero value. Reads will return
// 1 while the count is running and 0 when it has finished.
// Minimum count value is 4. Count values <4 will be treated as
// count value =4.
// Note that synchronisation to the register clock domain costs 2
// register clock cycles and the counter cannot compensate for
// that.
#define XOSC_COUNT_OFFSET _u(0x00000010)
#define XOSC_COUNT_BITS _u(0x0000ffff)
#define XOSC_COUNT_RESET _u(0x00000000)
#define XOSC_COUNT_MSB _u(15)
#define XOSC_COUNT_LSB _u(0)
#define XOSC_COUNT_ACCESS "RW"
// =============================================================================
#endif // _HARDWARE_REGS_XOSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ACCESSCTRL_H
#define _HARDWARE_STRUCTS_ACCESSCTRL_H
/**
* \file rp2350/accessctrl.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/accessctrl.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_accessctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/accessctrl.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ACCESSCTRL_LOCK_OFFSET) // ACCESSCTRL_LOCK
// Once a LOCK bit is written to 1, ACCESSCTRL silently ignores writes from that master
// 0x00000008 [3] DEBUG (0)
// 0x00000004 [2] DMA (1)
// 0x00000002 [1] CORE1 (0)
// 0x00000001 [0] CORE0 (0)
io_rw_32 lock;
_REG_(ACCESSCTRL_FORCE_CORE_NS_OFFSET) // ACCESSCTRL_FORCE_CORE_NS
// Force core 1's bus accesses to always be Non-secure, no matter the core's internal state
// 0x00000002 [1] CORE1 (0)
io_rw_32 force_core_ns;
_REG_(ACCESSCTRL_CFGRESET_OFFSET) // ACCESSCTRL_CFGRESET
// Write 1 to reset all ACCESSCTRL configuration, except for the LOCK and FORCE_CORE_NS registers
// 0x00000001 [0] CFGRESET (0)
io_wo_32 cfgreset;
// (Description copied from array index 0 register ACCESSCTRL_GPIO_NSMASK0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_GPIO_NSMASK0_OFFSET) // ACCESSCTRL_GPIO_NSMASK0
// Control whether GPIO0
// 0xffffffff [31:0] GPIO_NSMASK0 (0x00000000)
io_rw_32 gpio_nsmask[2];
_REG_(ACCESSCTRL_ROM_OFFSET) // ACCESSCTRL_ROM
// Control access to ROM. Defaults to fully open access.
// 0x00000080 [7] DBG (1) If 1, ROM can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, ROM can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, ROM can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, ROM can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, ROM can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, ROM can be accessed from a...
// 0x00000002 [1] NSP (1) If 1, ROM can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (1) If 1, and NSP is also set, ROM can be accessed from a...
io_rw_32 rom;
_REG_(ACCESSCTRL_XIP_MAIN_OFFSET) // ACCESSCTRL_XIP_MAIN
// Control access to XIP_MAIN. Defaults to fully open access.
// 0x00000080 [7] DBG (1) If 1, XIP_MAIN can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, XIP_MAIN can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, XIP_MAIN can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, XIP_MAIN can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, XIP_MAIN can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, XIP_MAIN can be accessed from...
// 0x00000002 [1] NSP (1) If 1, XIP_MAIN can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (1) If 1, and NSP is also set, XIP_MAIN can be accessed from...
io_rw_32 xip_main;
// (Description copied from array index 0 register ACCESSCTRL_SRAM0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_SRAM0_OFFSET) // ACCESSCTRL_SRAM0
// Control access to SRAM0. Defaults to fully open access.
// 0x00000080 [7] DBG (1) If 1, SRAM0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, SRAM0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, SRAM0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, SRAM0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, SRAM0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, SRAM0 can be accessed from a...
// 0x00000002 [1] NSP (1) If 1, SRAM0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (1) If 1, and NSP is also set, SRAM0 can be accessed from a...
io_rw_32 sram[10];
_REG_(ACCESSCTRL_DMA_OFFSET) // ACCESSCTRL_DMA
// Control access to DMA. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, DMA can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, DMA can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, DMA can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, DMA can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, DMA can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, DMA can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, DMA can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, DMA can be accessed from a...
io_rw_32 dma;
_REG_(ACCESSCTRL_USBCTRL_OFFSET) // ACCESSCTRL_USBCTRL
// Control access to USBCTRL. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, USBCTRL can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, USBCTRL can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, USBCTRL can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, USBCTRL can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, USBCTRL can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, USBCTRL can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, USBCTRL can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, USBCTRL can be accessed from...
io_rw_32 usbctrl;
// (Description copied from array index 0 register ACCESSCTRL_PIO0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_PIO0_OFFSET) // ACCESSCTRL_PIO0
// Control access to PIO0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, PIO0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, PIO0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PIO0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PIO0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PIO0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, PIO0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, PIO0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PIO0 can be accessed from a...
io_rw_32 pio[3];
_REG_(ACCESSCTRL_CORESIGHT_TRACE_OFFSET) // ACCESSCTRL_CORESIGHT_TRACE
// Control access to CORESIGHT_TRACE. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, CORESIGHT_TRACE can be accessed by the debugger,...
// 0x00000040 [6] DMA (0) If 1, CORESIGHT_TRACE can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_TRACE can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_TRACE can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, CORESIGHT_TRACE can be accessed from a Secure,...
// 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_TRACE can be...
// 0x00000002 [1] NSP (0) If 1, CORESIGHT_TRACE can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_TRACE can be...
io_rw_32 coresight_trace;
_REG_(ACCESSCTRL_CORESIGHT_PERIPH_OFFSET) // ACCESSCTRL_CORESIGHT_PERIPH
// Control access to CORESIGHT_PERIPH. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, CORESIGHT_PERIPH can be accessed by the debugger,...
// 0x00000040 [6] DMA (0) If 1, CORESIGHT_PERIPH can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, CORESIGHT_PERIPH can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, CORESIGHT_PERIPH can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, CORESIGHT_PERIPH can be accessed from a Secure,...
// 0x00000004 [2] SU (0) If 1, and SP is also set, CORESIGHT_PERIPH can be...
// 0x00000002 [1] NSP (0) If 1, CORESIGHT_PERIPH can be accessed from a...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, CORESIGHT_PERIPH can be...
io_rw_32 coresight_periph;
_REG_(ACCESSCTRL_SYSINFO_OFFSET) // ACCESSCTRL_SYSINFO
// Control access to SYSINFO. Defaults to fully open access.
// 0x00000080 [7] DBG (1) If 1, SYSINFO can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, SYSINFO can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, SYSINFO can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, SYSINFO can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, SYSINFO can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, SYSINFO can be accessed from a...
// 0x00000002 [1] NSP (1) If 1, SYSINFO can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (1) If 1, and NSP is also set, SYSINFO can be accessed from...
io_rw_32 sysinfo;
_REG_(ACCESSCTRL_RESETS_OFFSET) // ACCESSCTRL_RESETS
// Control access to RESETS. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, RESETS can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, RESETS can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, RESETS can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, RESETS can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, RESETS can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, RESETS can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, RESETS can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, RESETS can be accessed from a...
io_rw_32 resets;
// (Description copied from array index 0 register ACCESSCTRL_IO_BANK0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_IO_BANK0_OFFSET) // ACCESSCTRL_IO_BANK0
// Control access to IO_BANK0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, IO_BANK0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, IO_BANK0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, IO_BANK0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, IO_BANK0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, IO_BANK0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, IO_BANK0 can be accessed from...
// 0x00000002 [1] NSP (0) If 1, IO_BANK0 can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, IO_BANK0 can be accessed from...
io_rw_32 io_bank[2];
_REG_(ACCESSCTRL_PADS_BANK0_OFFSET) // ACCESSCTRL_PADS_BANK0
// Control access to PADS_BANK0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, PADS_BANK0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, PADS_BANK0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PADS_BANK0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PADS_BANK0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PADS_BANK0 can be accessed from a Secure,...
// 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_BANK0 can be accessed...
// 0x00000002 [1] NSP (0) If 1, PADS_BANK0 can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_BANK0 can be accessed...
io_rw_32 pads_bank0;
_REG_(ACCESSCTRL_PADS_QSPI_OFFSET) // ACCESSCTRL_PADS_QSPI
// Control access to PADS_QSPI. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, PADS_QSPI can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, PADS_QSPI can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PADS_QSPI can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PADS_QSPI can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PADS_QSPI can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, PADS_QSPI can be accessed from...
// 0x00000002 [1] NSP (0) If 1, PADS_QSPI can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PADS_QSPI can be accessed...
io_rw_32 pads_qspi;
_REG_(ACCESSCTRL_BUSCTRL_OFFSET) // ACCESSCTRL_BUSCTRL
// Control access to BUSCTRL. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, BUSCTRL can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, BUSCTRL can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, BUSCTRL can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, BUSCTRL can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, BUSCTRL can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, BUSCTRL can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, BUSCTRL can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, BUSCTRL can be accessed from...
io_rw_32 busctrl;
_REG_(ACCESSCTRL_ADC0_OFFSET) // ACCESSCTRL_ADC0
// Control access to ADC0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, ADC0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, ADC0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, ADC0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, ADC0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, ADC0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, ADC0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, ADC0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, ADC0 can be accessed from a...
io_rw_32 adc0;
_REG_(ACCESSCTRL_HSTX_OFFSET) // ACCESSCTRL_HSTX
// Control access to HSTX. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, HSTX can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, HSTX can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, HSTX can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, HSTX can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, HSTX can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, HSTX can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, HSTX can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, HSTX can be accessed from a...
io_rw_32 hstx;
// (Description copied from array index 0 register ACCESSCTRL_I2C0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_I2C0_OFFSET) // ACCESSCTRL_I2C0
// Control access to I2C0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, I2C0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, I2C0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, I2C0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, I2C0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, I2C0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, I2C0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, I2C0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, I2C0 can be accessed from a...
io_rw_32 i2c[2];
_REG_(ACCESSCTRL_PWM_OFFSET) // ACCESSCTRL_PWM
// Control access to PWM. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, PWM can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, PWM can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PWM can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PWM can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PWM can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, PWM can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, PWM can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PWM can be accessed from a...
io_rw_32 pwm;
// (Description copied from array index 0 register ACCESSCTRL_SPI0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_SPI0_OFFSET) // ACCESSCTRL_SPI0
// Control access to SPI0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, SPI0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, SPI0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, SPI0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, SPI0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, SPI0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, SPI0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, SPI0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, SPI0 can be accessed from a...
io_rw_32 spi[2];
// (Description copied from array index 0 register ACCESSCTRL_TIMER0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_TIMER0_OFFSET) // ACCESSCTRL_TIMER0
// Control access to TIMER0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, TIMER0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, TIMER0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, TIMER0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, TIMER0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, TIMER0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, TIMER0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, TIMER0 can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, TIMER0 can be accessed from a...
io_rw_32 timer[2];
// (Description copied from array index 0 register ACCESSCTRL_UART0 applies similarly to other array indexes)
_REG_(ACCESSCTRL_UART0_OFFSET) // ACCESSCTRL_UART0
// Control access to UART0. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, UART0 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, UART0 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, UART0 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, UART0 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, UART0 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, UART0 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, UART0 can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, UART0 can be accessed from a...
io_rw_32 uart[2];
_REG_(ACCESSCTRL_OTP_OFFSET) // ACCESSCTRL_OTP
// Control access to OTP. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, OTP can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, OTP can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, OTP can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, OTP can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, OTP can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, OTP can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, OTP can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, OTP can be accessed from a...
io_rw_32 otp;
_REG_(ACCESSCTRL_TBMAN_OFFSET) // ACCESSCTRL_TBMAN
// Control access to TBMAN. Defaults to Secure access from any master.
// 0x00000080 [7] DBG (1) If 1, TBMAN can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, TBMAN can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, TBMAN can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, TBMAN can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, TBMAN can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (1) If 1, and SP is also set, TBMAN can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, TBMAN can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, TBMAN can be accessed from a...
io_rw_32 tbman;
_REG_(ACCESSCTRL_POWMAN_OFFSET) // ACCESSCTRL_POWMAN
// Control access to POWMAN. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, POWMAN can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, POWMAN can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, POWMAN can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, POWMAN can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, POWMAN can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, POWMAN can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, POWMAN can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, POWMAN can be accessed from a...
io_rw_32 powman;
_REG_(ACCESSCTRL_TRNG_OFFSET) // ACCESSCTRL_TRNG
// Control access to TRNG. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, TRNG can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, TRNG can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, TRNG can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, TRNG can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, TRNG can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, TRNG can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, TRNG can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, TRNG can be accessed from a...
io_rw_32 trng;
_REG_(ACCESSCTRL_SHA256_OFFSET) // ACCESSCTRL_SHA256
// Control access to SHA256. Defaults to Secure, Privileged access only.
// 0x00000080 [7] DBG (1) If 1, SHA256 can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, SHA256 can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, SHA256 can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, SHA256 can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, SHA256 can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, SHA256 can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, SHA256 can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, SHA256 can be accessed from a...
io_rw_32 sha256;
_REG_(ACCESSCTRL_SYSCFG_OFFSET) // ACCESSCTRL_SYSCFG
// Control access to SYSCFG. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, SYSCFG can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, SYSCFG can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, SYSCFG can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, SYSCFG can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, SYSCFG can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, SYSCFG can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, SYSCFG can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, SYSCFG can be accessed from a...
io_rw_32 syscfg;
_REG_(ACCESSCTRL_CLOCKS_OFFSET) // ACCESSCTRL_CLOCKS
// Control access to CLOCKS. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, CLOCKS can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, CLOCKS can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, CLOCKS can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, CLOCKS can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, CLOCKS can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, CLOCKS can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, CLOCKS can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, CLOCKS can be accessed from a...
io_rw_32 clocks;
_REG_(ACCESSCTRL_XOSC_OFFSET) // ACCESSCTRL_XOSC
// Control access to XOSC. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, XOSC can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, XOSC can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, XOSC can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, XOSC can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, XOSC can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, XOSC can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, XOSC can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, XOSC can be accessed from a...
io_rw_32 xosc;
_REG_(ACCESSCTRL_ROSC_OFFSET) // ACCESSCTRL_ROSC
// Control access to ROSC. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, ROSC can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, ROSC can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, ROSC can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, ROSC can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, ROSC can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, ROSC can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, ROSC can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, ROSC can be accessed from a...
io_rw_32 rosc;
_REG_(ACCESSCTRL_PLL_SYS_OFFSET) // ACCESSCTRL_PLL_SYS
// Control access to PLL_SYS. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, PLL_SYS can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, PLL_SYS can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PLL_SYS can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PLL_SYS can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PLL_SYS can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_SYS can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, PLL_SYS can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_SYS can be accessed from...
io_rw_32 pll_sys;
_REG_(ACCESSCTRL_PLL_USB_OFFSET) // ACCESSCTRL_PLL_USB
// Control access to PLL_USB. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, PLL_USB can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, PLL_USB can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, PLL_USB can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, PLL_USB can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, PLL_USB can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, PLL_USB can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, PLL_USB can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, PLL_USB can be accessed from...
io_rw_32 pll_usb;
_REG_(ACCESSCTRL_TICKS_OFFSET) // ACCESSCTRL_TICKS
// Control access to TICKS. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, TICKS can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, TICKS can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, TICKS can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, TICKS can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, TICKS can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, TICKS can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, TICKS can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, TICKS can be accessed from a...
io_rw_32 ticks;
_REG_(ACCESSCTRL_WATCHDOG_OFFSET) // ACCESSCTRL_WATCHDOG
// Control access to WATCHDOG. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, WATCHDOG can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, WATCHDOG can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, WATCHDOG can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, WATCHDOG can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, WATCHDOG can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, WATCHDOG can be accessed from...
// 0x00000002 [1] NSP (0) If 1, WATCHDOG can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, WATCHDOG can be accessed from...
io_rw_32 watchdog;
_REG_(ACCESSCTRL_RSM_OFFSET) // ACCESSCTRL_RSM
// Control access to RSM. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, RSM can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, RSM can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, RSM can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, RSM can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, RSM can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, RSM can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, RSM can be accessed from a Non-secure, Privileged context
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, RSM can be accessed from a...
io_rw_32 rsm;
_REG_(ACCESSCTRL_XIP_CTRL_OFFSET) // ACCESSCTRL_XIP_CTRL
// Control access to XIP_CTRL. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, XIP_CTRL can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, XIP_CTRL can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, XIP_CTRL can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, XIP_CTRL can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, XIP_CTRL can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_CTRL can be accessed from...
// 0x00000002 [1] NSP (0) If 1, XIP_CTRL can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_CTRL can be accessed from...
io_rw_32 xip_ctrl;
_REG_(ACCESSCTRL_XIP_QMI_OFFSET) // ACCESSCTRL_XIP_QMI
// Control access to XIP_QMI. Defaults to Secure, Privileged processor or debug access only.
// 0x00000080 [7] DBG (1) If 1, XIP_QMI can be accessed by the debugger, at...
// 0x00000040 [6] DMA (0) If 1, XIP_QMI can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, XIP_QMI can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, XIP_QMI can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, XIP_QMI can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_QMI can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, XIP_QMI can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_QMI can be accessed from...
io_rw_32 xip_qmi;
_REG_(ACCESSCTRL_XIP_AUX_OFFSET) // ACCESSCTRL_XIP_AUX
// Control access to XIP_AUX. Defaults to Secure, Privileged access only.
// 0x00000080 [7] DBG (1) If 1, XIP_AUX can be accessed by the debugger, at...
// 0x00000040 [6] DMA (1) If 1, XIP_AUX can be accessed by the DMA, at...
// 0x00000020 [5] CORE1 (1) If 1, XIP_AUX can be accessed by core 1, at...
// 0x00000010 [4] CORE0 (1) If 1, XIP_AUX can be accessed by core 0, at...
// 0x00000008 [3] SP (1) If 1, XIP_AUX can be accessed from a Secure, Privileged context
// 0x00000004 [2] SU (0) If 1, and SP is also set, XIP_AUX can be accessed from a...
// 0x00000002 [1] NSP (0) If 1, XIP_AUX can be accessed from a Non-secure,...
// 0x00000001 [0] NSU (0) If 1, and NSP is also set, XIP_AUX can be accessed from...
io_rw_32 xip_aux;
} accessctrl_hw_t;
#define accessctrl_hw ((accessctrl_hw_t *)ACCESSCTRL_BASE)
static_assert(sizeof (accessctrl_hw_t) == 0x00ec, "");
#endif // _HARDWARE_STRUCTS_ACCESSCTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ADC_H
#define _HARDWARE_STRUCTS_ADC_H
/**
* \file rp2350/adc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/adc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_adc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ADC_CS_OFFSET) // ADC_CS
// ADC Control and Status
// 0x01ff0000 [24:16] RROBIN (0x000) Round-robin sampling
// 0x0000f000 [15:12] AINSEL (0x0) Select analog mux input
// 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
// 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
// 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
// 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
// 0x00000004 [2] START_ONCE (0) Start a single conversion
// 0x00000002 [1] TS_EN (0) Power on temperature sensor
// 0x00000001 [0] EN (0) Power on ADC and enable its clock
io_rw_32 cs;
_REG_(ADC_RESULT_OFFSET) // ADC_RESULT
// Result of most recent ADC conversion
// 0x00000fff [11:0] RESULT (0x000)
io_ro_32 result;
_REG_(ADC_FCS_OFFSET) // ADC_FCS
// FIFO control and status
// 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
// 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
// 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
// 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
// 0x00000200 [9] FULL (0)
// 0x00000100 [8] EMPTY (0)
// 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
// 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
// 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
// 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
io_rw_32 fcs;
_REG_(ADC_FIFO_OFFSET) // ADC_FIFO
// Conversion result FIFO
// 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
// 0x00000fff [11:0] VAL (-)
io_ro_32 fifo;
_REG_(ADC_DIV_OFFSET) // ADC_DIV
// Clock divider
// 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
// 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
io_rw_32 div;
_REG_(ADC_INTR_OFFSET) // ADC_INTR
// Raw Interrupts
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 intr;
_REG_(ADC_INTE_OFFSET) // ADC_INTE
// Interrupt Enable
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 inte;
_REG_(ADC_INTF_OFFSET) // ADC_INTF
// Interrupt Force
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 intf;
_REG_(ADC_INTS_OFFSET) // ADC_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 ints;
} adc_hw_t;
#define adc_hw ((adc_hw_t *)ADC_BASE)
static_assert(sizeof (adc_hw_t) == 0x0024, "");
#endif // _HARDWARE_STRUCTS_ADC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_BOOTRAM_H
#define _HARDWARE_STRUCTS_BOOTRAM_H
/**
* \file rp2350/bootram.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/bootram.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_bootram
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/bootram.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
// (Description copied from array index 0 register BOOTRAM_WRITE_ONCE0 applies similarly to other array indexes)
_REG_(BOOTRAM_WRITE_ONCE0_OFFSET) // BOOTRAM_WRITE_ONCE0
// This registers always ORs writes into its current contents
// 0xffffffff [31:0] WRITE_ONCE0 (0x00000000)
io_rw_32 write_once[2];
_REG_(BOOTRAM_BOOTLOCK_STAT_OFFSET) // BOOTRAM_BOOTLOCK_STAT
// Bootlock status register
// 0x000000ff [7:0] BOOTLOCK_STAT (0xff)
io_rw_32 bootlock_stat;
// (Description copied from array index 0 register BOOTRAM_BOOTLOCK0 applies similarly to other array indexes)
_REG_(BOOTRAM_BOOTLOCK0_OFFSET) // BOOTRAM_BOOTLOCK0
// Read to claim and check
// 0xffffffff [31:0] BOOTLOCK0 (0x00000000)
io_rw_32 bootlock[8];
} bootram_hw_t;
#define bootram_hw ((bootram_hw_t *)(BOOTRAM_BASE + BOOTRAM_WRITE_ONCE0_OFFSET))
static_assert(sizeof (bootram_hw_t) == 0x002c, "");
#endif // _HARDWARE_STRUCTS_BOOTRAM_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/busctrl.h"
#define bus_ctrl_hw busctrl_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_BUSCTRL_H
#define _HARDWARE_STRUCTS_BUSCTRL_H
/**
* \file rp2350/busctrl.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/busctrl.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_busctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Bus fabric performance counters on RP2350 (used as typedef \ref bus_ctrl_perf_counter_t)
* \ingroup hardware_busctrl
*/
typedef enum bus_ctrl_perf_counter_rp2350 {
arbiter_rom_perf_event_access = 19,
arbiter_rom_perf_event_access_contested = 18,
arbiter_xip_main_perf_event_access = 17,
arbiter_xip_main_perf_event_access_contested = 16,
arbiter_sram0_perf_event_access = 15,
arbiter_sram0_perf_event_access_contested = 14,
arbiter_sram1_perf_event_access = 13,
arbiter_sram1_perf_event_access_contested = 12,
arbiter_sram2_perf_event_access = 11,
arbiter_sram2_perf_event_access_contested = 10,
arbiter_sram3_perf_event_access = 9,
arbiter_sram3_perf_event_access_contested = 8,
arbiter_sram4_perf_event_access = 7,
arbiter_sram4_perf_event_access_contested = 6,
arbiter_sram5_perf_event_access = 5,
arbiter_sram5_perf_event_access_contested = 4,
arbiter_fastperi_perf_event_access = 3,
arbiter_fastperi_perf_event_access_contested = 2,
arbiter_apb_perf_event_access = 1,
arbiter_apb_perf_event_access_contested = 0
} bus_ctrl_perf_counter_t;
typedef struct {
_REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
// Bus fabric performance counter 0
// 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 +
io_rw_32 value;
_REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
// Bus fabric performance event select for PERFCTR0
// 0x0000007f [6:0] PERFSEL0 (0x1f) Select an event for PERFCTR0
io_rw_32 sel;
} bus_ctrl_perf_hw_t;
typedef struct {
_REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
// Set the priority of each master for bus arbitration
// 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority
// 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority
// 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority
// 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority
io_rw_32 priority;
_REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
// Bus priority acknowledge
// 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new...
io_ro_32 priority_ack;
_REG_(BUSCTRL_PERFCTR_EN_OFFSET) // BUSCTRL_PERFCTR_EN
// Enable the performance counters
// 0x00000001 [0] PERFCTR_EN (0)
io_rw_32 perfctr_en;
bus_ctrl_perf_hw_t counter[4];
} busctrl_hw_t;
#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE)
static_assert(sizeof (busctrl_hw_t) == 0x002c, "");
#endif // _HARDWARE_STRUCTS_BUSCTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_CLOCKS_H
#define _HARDWARE_STRUCTS_CLOCKS_H
/**
* \file rp2350/clocks.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/clocks.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_clocks
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Clock numbers on RP2350 (used as typedef \ref clock_num_t)
* \ingroup hardware_clocks
*/
/// \tag::clkenum[]
typedef enum clock_num_rp2350 {
clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source
clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source
clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source
clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source
clk_ref = 4, ///< Select CLK_REF as clock source
clk_sys = 5, ///< Select CLK_SYS as clock source
clk_peri = 6, ///< Select CLK_PERI as clock source
clk_hstx = 7, ///< Select CLK_HSTX as clock source
clk_usb = 8, ///< Select CLK_USB as clock source
clk_adc = 9, ///< Select CLK_ADC as clock source
CLK_COUNT
} clock_num_t;
/// \end::clkenum[]
/** \brief Clock destination numbers on RP2350 (used as typedef \ref clock_dest_num_t)
* \ingroup hardware_clocks
*/
typedef enum clock_dest_num_rp2350 {
CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination
CLK_DEST_SYS_ACCESSCTRL = 1, ///< Select SYS_ACCESSCTRL as clock destination
CLK_DEST_ADC = 2, ///< Select ADC as clock destination
CLK_DEST_SYS_ADC = 3, ///< Select SYS_ADC as clock destination
CLK_DEST_SYS_BOOTRAM = 4, ///< Select SYS_BOOTRAM as clock destination
CLK_DEST_SYS_BUSCTRL = 5, ///< Select SYS_BUSCTRL as clock destination
CLK_DEST_SYS_BUSFABRIC = 6, ///< Select SYS_BUSFABRIC as clock destination
CLK_DEST_SYS_DMA = 7, ///< Select SYS_DMA as clock destination
CLK_DEST_SYS_GLITCH_DETECTOR = 8, ///< Select SYS_GLITCH_DETECTOR as clock destination
CLK_DEST_HSTX = 9, ///< Select HSTX as clock destination
CLK_DEST_SYS_HSTX = 10, ///< Select SYS_HSTX as clock destination
CLK_DEST_SYS_I2C0 = 11, ///< Select SYS_I2C0 as clock destination
CLK_DEST_SYS_I2C1 = 12, ///< Select SYS_I2C1 as clock destination
CLK_DEST_SYS_IO = 13, ///< Select SYS_IO as clock destination
CLK_DEST_SYS_JTAG = 14, ///< Select SYS_JTAG as clock destination
CLK_DEST_REF_OTP = 15, ///< Select REF_OTP as clock destination
CLK_DEST_SYS_OTP = 16, ///< Select SYS_OTP as clock destination
CLK_DEST_SYS_PADS = 17, ///< Select SYS_PADS as clock destination
CLK_DEST_SYS_PIO0 = 18, ///< Select SYS_PIO0 as clock destination
CLK_DEST_SYS_PIO1 = 19, ///< Select SYS_PIO1 as clock destination
CLK_DEST_SYS_PIO2 = 20, ///< Select SYS_PIO2 as clock destination
CLK_DEST_SYS_PLL_SYS = 21, ///< Select SYS_PLL_SYS as clock destination
CLK_DEST_SYS_PLL_USB = 22, ///< Select SYS_PLL_USB as clock destination
CLK_DEST_REF_POWMAN = 23, ///< Select REF_POWMAN as clock destination
CLK_DEST_SYS_POWMAN = 24, ///< Select SYS_POWMAN as clock destination
CLK_DEST_SYS_PWM = 25, ///< Select SYS_PWM as clock destination
CLK_DEST_SYS_RESETS = 26, ///< Select SYS_RESETS as clock destination
CLK_DEST_SYS_ROM = 27, ///< Select SYS_ROM as clock destination
CLK_DEST_SYS_ROSC = 28, ///< Select SYS_ROSC as clock destination
CLK_DEST_SYS_PSM = 29, ///< Select SYS_PSM as clock destination
CLK_DEST_SYS_SHA256 = 30, ///< Select SYS_SHA256 as clock destination
CLK_DEST_SYS_SIO = 31, ///< Select SYS_SIO as clock destination
CLK_DEST_PERI_SPI0 = 32, ///< Select PERI_SPI0 as clock destination
CLK_DEST_SYS_SPI0 = 33, ///< Select SYS_SPI0 as clock destination
CLK_DEST_PERI_SPI1 = 34, ///< Select PERI_SPI1 as clock destination
CLK_DEST_SYS_SPI1 = 35, ///< Select SYS_SPI1 as clock destination
CLK_DEST_SYS_SRAM0 = 36, ///< Select SYS_SRAM0 as clock destination
CLK_DEST_SYS_SRAM1 = 37, ///< Select SYS_SRAM1 as clock destination
CLK_DEST_SYS_SRAM2 = 38, ///< Select SYS_SRAM2 as clock destination
CLK_DEST_SYS_SRAM3 = 39, ///< Select SYS_SRAM3 as clock destination
CLK_DEST_SYS_SRAM4 = 40, ///< Select SYS_SRAM4 as clock destination
CLK_DEST_SYS_SRAM5 = 41, ///< Select SYS_SRAM5 as clock destination
CLK_DEST_SYS_SRAM6 = 42, ///< Select SYS_SRAM6 as clock destination
CLK_DEST_SYS_SRAM7 = 43, ///< Select SYS_SRAM7 as clock destination
CLK_DEST_SYS_SRAM8 = 44, ///< Select SYS_SRAM8 as clock destination
CLK_DEST_SYS_SRAM9 = 45, ///< Select SYS_SRAM9 as clock destination
CLK_DEST_SYS_SYSCFG = 46, ///< Select SYS_SYSCFG as clock destination
CLK_DEST_SYS_SYSINFO = 47, ///< Select SYS_SYSINFO as clock destination
CLK_DEST_SYS_TBMAN = 48, ///< Select SYS_TBMAN as clock destination
CLK_DEST_REF_TICKS = 49, ///< Select REF_TICKS as clock destination
CLK_DEST_SYS_TICKS = 50, ///< Select SYS_TICKS as clock destination
CLK_DEST_SYS_TIMER0 = 51, ///< Select SYS_TIMER0 as clock destination
CLK_DEST_SYS_TIMER1 = 52, ///< Select SYS_TIMER1 as clock destination
CLK_DEST_SYS_TRNG = 53, ///< Select SYS_TRNG as clock destination
CLK_DEST_PERI_UART0 = 54, ///< Select PERI_UART0 as clock destination
CLK_DEST_SYS_UART0 = 55, ///< Select SYS_UART0 as clock destination
CLK_DEST_PERI_UART1 = 56, ///< Select PERI_UART1 as clock destination
CLK_DEST_SYS_UART1 = 57, ///< Select SYS_UART1 as clock destination
CLK_DEST_SYS_USBCTRL = 58, ///< Select SYS_USBCTRL as clock destination
CLK_DEST_USB = 59, ///< Select USB as clock destination
CLK_DEST_SYS_WATCHDOG = 60, ///< Select SYS_WATCHDOG as clock destination
CLK_DEST_SYS_XIP = 61, ///< Select SYS_XIP as clock destination
CLK_DEST_SYS_XOSC = 62, ///< Select SYS_XOSC as clock destination
NUM_CLOCK_DESTINATIONS
} clock_dest_num_t;
/// \tag::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
// Clock control, can be changed on-the-fly (except for auxsrc)
// 0x10000000 [28] ENABLED (0) clock generator is enabled
// 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
// 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
// 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors, can be...
// 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
// 0x00000400 [10] KILL (0) Asynchronously kills the clock generator, enable must be...
// 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
// 0xffff0000 [31:16] INT (0x0001) Integer part of clock divisor, 0 -> max+1, can be...
// 0x0000ffff [15:0] FRAC (0x0000) Fractional component of the divisor, can be changed on-the-fly
io_rw_32 div;
_REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
// Indicates which src is currently selected (one-hot)
// 0x00000001 [0] CLK_GPOUT0_SELECTED (1) This slice does not have a glitchless mux (only the...
io_ro_32 selected;
} clock_hw_t;
/// \end::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
// 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
// 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
// 0x00000100 [8] ENABLE (0) Enable resus
// 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
// 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
io_ro_32 status;
} clock_resus_hw_t;
typedef struct {
_REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
// Reference clock frequency in kHz
// 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
io_rw_32 ref_khz;
_REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
// Minimum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
io_rw_32 min_khz;
_REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
// Maximum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
io_rw_32 max_khz;
_REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
// Delays the start of frequency counting to allow the mux to settle +
// 0x00000007 [2:0] FC0_DELAY (0x1)
io_rw_32 delay;
_REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
// The test interval is 0
// 0x0000000f [3:0] FC0_INTERVAL (0x8)
io_rw_32 interval;
_REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
// Clock sent to frequency counter, set to 0 when not required +
// 0x000000ff [7:0] FC0_SRC (0x00)
io_rw_32 src;
_REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
// Frequency counter status
// 0x10000000 [28] DIED (0) Test clock stopped during test
// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
// 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
// 0x00010000 [16] FAIL (0) Test failed
// 0x00001000 [12] WAITING (0) Waiting for test clock to start
// 0x00000100 [8] RUNNING (0) Test running
// 0x00000010 [4] DONE (0) Test complete
// 0x00000001 [0] PASS (0) Test passed
io_ro_32 status;
_REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
// Result of frequency measurement, only valid when status_done=1
// 0x3fffffe0 [29:5] KHZ (0x0000000)
// 0x0000001f [4:0] FRAC (0x00)
io_ro_32 result;
} fc_hw_t;
typedef struct {
clock_hw_t clk[10];
_REG_(CLOCKS_DFTCLK_XOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_XOSC_CTRL
// 0x00000003 [1:0] SRC (0x0)
io_rw_32 dftclk_xosc_ctrl;
_REG_(CLOCKS_DFTCLK_ROSC_CTRL_OFFSET) // CLOCKS_DFTCLK_ROSC_CTRL
// 0x00000003 [1:0] SRC (0x0)
io_rw_32 dftclk_rosc_ctrl;
_REG_(CLOCKS_DFTCLK_LPOSC_CTRL_OFFSET) // CLOCKS_DFTCLK_LPOSC_CTRL
// 0x00000003 [1:0] SRC (0x0)
io_rw_32 dftclk_lposc_ctrl;
clock_resus_hw_t resus;
fc_hw_t fc0;
union {
struct {
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SIOB (1)
// 0x40000000 [30] CLK_SYS_SHA256 (1)
// 0x20000000 [29] CLK_SYS_RSM (1)
// 0x10000000 [28] CLK_SYS_ROSC (1)
// 0x08000000 [27] CLK_SYS_ROM (1)
// 0x04000000 [26] CLK_SYS_RESETS (1)
// 0x02000000 [25] CLK_SYS_PWM (1)
// 0x01000000 [24] CLK_SYS_POWMAN (1)
// 0x00800000 [23] CLK_REF_POWMAN (1)
// 0x00400000 [22] CLK_SYS_PLL_USB (1)
// 0x00200000 [21] CLK_SYS_PLL_SYS (1)
// 0x00100000 [20] CLK_SYS_PIO2 (1)
// 0x00080000 [19] CLK_SYS_PIO1 (1)
// 0x00040000 [18] CLK_SYS_PIO0 (1)
// 0x00020000 [17] CLK_SYS_PADS (1)
// 0x00010000 [16] CLK_SYS_OTP (1)
// 0x00008000 [15] CLK_REF_OTP (1)
// 0x00004000 [14] CLK_SYS_JTAG (1)
// 0x00002000 [13] CLK_SYS_IO (1)
// 0x00001000 [12] CLK_SYS_I2C1 (1)
// 0x00000800 [11] CLK_SYS_I2C0 (1)
// 0x00000400 [10] CLK_SYS_HSTX (1)
// 0x00000200 [9] CLK_HSTX (1)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
// 0x00000080 [7] CLK_SYS_DMA (1)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
// 0x00000020 [5] CLK_SYS_BUSCTRL (1)
// 0x00000010 [4] CLK_SYS_BOOTRAM (1)
// 0x00000008 [3] CLK_SYS_ADC (1)
// 0x00000004 [2] CLK_ADC (1)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 wake_en0;
_REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
// enable clock in wake mode
// 0x40000000 [30] CLK_SYS_XOSC (1)
// 0x20000000 [29] CLK_SYS_XIP (1)
// 0x10000000 [28] CLK_SYS_WATCHDOG (1)
// 0x08000000 [27] CLK_USB (1)
// 0x04000000 [26] CLK_SYS_USBCTRL (1)
// 0x02000000 [25] CLK_SYS_UART1 (1)
// 0x01000000 [24] CLK_PERI_UART1 (1)
// 0x00800000 [23] CLK_SYS_UART0 (1)
// 0x00400000 [22] CLK_PERI_UART0 (1)
// 0x00200000 [21] CLK_SYS_TRNG (1)
// 0x00100000 [20] CLK_SYS_TIMER1 (1)
// 0x00080000 [19] CLK_SYS_TIMER0 (1)
// 0x00040000 [18] CLK_SYS_TICKS (1)
// 0x00020000 [17] CLK_REF_TICKS (1)
// 0x00010000 [16] CLK_SYS_TBMAN (1)
// 0x00008000 [15] CLK_SYS_SYSINFO (1)
// 0x00004000 [14] CLK_SYS_SYSCFG (1)
// 0x00002000 [13] CLK_SYS_SRAM9 (1)
// 0x00001000 [12] CLK_SYS_SRAM8 (1)
// 0x00000800 [11] CLK_SYS_SRAM7 (1)
// 0x00000400 [10] CLK_SYS_SRAM6 (1)
// 0x00000200 [9] CLK_SYS_SRAM5 (1)
// 0x00000100 [8] CLK_SYS_SRAM4 (1)
// 0x00000080 [7] CLK_SYS_SRAM3 (1)
// 0x00000040 [6] CLK_SYS_SRAM2 (1)
// 0x00000020 [5] CLK_SYS_SRAM1 (1)
// 0x00000010 [4] CLK_SYS_SRAM0 (1)
// 0x00000008 [3] CLK_SYS_SPI1 (1)
// 0x00000004 [2] CLK_PERI_SPI1 (1)
// 0x00000002 [1] CLK_SYS_SPI0 (1)
// 0x00000001 [0] CLK_PERI_SPI0 (1)
io_rw_32 wake_en1;
};
// (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SIO (1)
// 0x40000000 [30] CLK_SYS_SHA256 (1)
// 0x20000000 [29] CLK_SYS_PSM (1)
// 0x10000000 [28] CLK_SYS_ROSC (1)
// 0x08000000 [27] CLK_SYS_ROM (1)
// 0x04000000 [26] CLK_SYS_RESETS (1)
// 0x02000000 [25] CLK_SYS_PWM (1)
// 0x01000000 [24] CLK_SYS_POWMAN (1)
// 0x00800000 [23] CLK_REF_POWMAN (1)
// 0x00400000 [22] CLK_SYS_PLL_USB (1)
// 0x00200000 [21] CLK_SYS_PLL_SYS (1)
// 0x00100000 [20] CLK_SYS_PIO2 (1)
// 0x00080000 [19] CLK_SYS_PIO1 (1)
// 0x00040000 [18] CLK_SYS_PIO0 (1)
// 0x00020000 [17] CLK_SYS_PADS (1)
// 0x00010000 [16] CLK_SYS_OTP (1)
// 0x00008000 [15] CLK_REF_OTP (1)
// 0x00004000 [14] CLK_SYS_JTAG (1)
// 0x00002000 [13] CLK_SYS_IO (1)
// 0x00001000 [12] CLK_SYS_I2C1 (1)
// 0x00000800 [11] CLK_SYS_I2C0 (1)
// 0x00000400 [10] CLK_SYS_HSTX (1)
// 0x00000200 [9] CLK_HSTX (1)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
// 0x00000080 [7] CLK_SYS_DMA (1)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
// 0x00000020 [5] CLK_SYS_BUSCTRL (1)
// 0x00000010 [4] CLK_SYS_BOOTRAM (1)
// 0x00000008 [3] CLK_SYS_ADC (1)
// 0x00000004 [2] CLK_ADC (1)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 wake_en[2];
};
union {
struct {
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SIOB (1)
// 0x40000000 [30] CLK_SYS_SHA256 (1)
// 0x20000000 [29] CLK_SYS_RSM (1)
// 0x10000000 [28] CLK_SYS_ROSC (1)
// 0x08000000 [27] CLK_SYS_ROM (1)
// 0x04000000 [26] CLK_SYS_RESETS (1)
// 0x02000000 [25] CLK_SYS_PWM (1)
// 0x01000000 [24] CLK_SYS_POWMAN (1)
// 0x00800000 [23] CLK_REF_POWMAN (1)
// 0x00400000 [22] CLK_SYS_PLL_USB (1)
// 0x00200000 [21] CLK_SYS_PLL_SYS (1)
// 0x00100000 [20] CLK_SYS_PIO2 (1)
// 0x00080000 [19] CLK_SYS_PIO1 (1)
// 0x00040000 [18] CLK_SYS_PIO0 (1)
// 0x00020000 [17] CLK_SYS_PADS (1)
// 0x00010000 [16] CLK_SYS_OTP (1)
// 0x00008000 [15] CLK_REF_OTP (1)
// 0x00004000 [14] CLK_SYS_JTAG (1)
// 0x00002000 [13] CLK_SYS_IO (1)
// 0x00001000 [12] CLK_SYS_I2C1 (1)
// 0x00000800 [11] CLK_SYS_I2C0 (1)
// 0x00000400 [10] CLK_SYS_HSTX (1)
// 0x00000200 [9] CLK_HSTX (1)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
// 0x00000080 [7] CLK_SYS_DMA (1)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
// 0x00000020 [5] CLK_SYS_BUSCTRL (1)
// 0x00000010 [4] CLK_SYS_BOOTRAM (1)
// 0x00000008 [3] CLK_SYS_ADC (1)
// 0x00000004 [2] CLK_ADC (1)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 sleep_en0;
_REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
// enable clock in sleep mode
// 0x40000000 [30] CLK_SYS_XOSC (1)
// 0x20000000 [29] CLK_SYS_XIP (1)
// 0x10000000 [28] CLK_SYS_WATCHDOG (1)
// 0x08000000 [27] CLK_USB (1)
// 0x04000000 [26] CLK_SYS_USBCTRL (1)
// 0x02000000 [25] CLK_SYS_UART1 (1)
// 0x01000000 [24] CLK_PERI_UART1 (1)
// 0x00800000 [23] CLK_SYS_UART0 (1)
// 0x00400000 [22] CLK_PERI_UART0 (1)
// 0x00200000 [21] CLK_SYS_TRNG (1)
// 0x00100000 [20] CLK_SYS_TIMER1 (1)
// 0x00080000 [19] CLK_SYS_TIMER0 (1)
// 0x00040000 [18] CLK_SYS_TICKS (1)
// 0x00020000 [17] CLK_REF_TICKS (1)
// 0x00010000 [16] CLK_SYS_TBMAN (1)
// 0x00008000 [15] CLK_SYS_SYSINFO (1)
// 0x00004000 [14] CLK_SYS_SYSCFG (1)
// 0x00002000 [13] CLK_SYS_SRAM9 (1)
// 0x00001000 [12] CLK_SYS_SRAM8 (1)
// 0x00000800 [11] CLK_SYS_SRAM7 (1)
// 0x00000400 [10] CLK_SYS_SRAM6 (1)
// 0x00000200 [9] CLK_SYS_SRAM5 (1)
// 0x00000100 [8] CLK_SYS_SRAM4 (1)
// 0x00000080 [7] CLK_SYS_SRAM3 (1)
// 0x00000040 [6] CLK_SYS_SRAM2 (1)
// 0x00000020 [5] CLK_SYS_SRAM1 (1)
// 0x00000010 [4] CLK_SYS_SRAM0 (1)
// 0x00000008 [3] CLK_SYS_SPI1 (1)
// 0x00000004 [2] CLK_PERI_SPI1 (1)
// 0x00000002 [1] CLK_SYS_SPI0 (1)
// 0x00000001 [0] CLK_PERI_SPI0 (1)
io_rw_32 sleep_en1;
};
// (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SIO (1)
// 0x40000000 [30] CLK_SYS_SHA256 (1)
// 0x20000000 [29] CLK_SYS_PSM (1)
// 0x10000000 [28] CLK_SYS_ROSC (1)
// 0x08000000 [27] CLK_SYS_ROM (1)
// 0x04000000 [26] CLK_SYS_RESETS (1)
// 0x02000000 [25] CLK_SYS_PWM (1)
// 0x01000000 [24] CLK_SYS_POWMAN (1)
// 0x00800000 [23] CLK_REF_POWMAN (1)
// 0x00400000 [22] CLK_SYS_PLL_USB (1)
// 0x00200000 [21] CLK_SYS_PLL_SYS (1)
// 0x00100000 [20] CLK_SYS_PIO2 (1)
// 0x00080000 [19] CLK_SYS_PIO1 (1)
// 0x00040000 [18] CLK_SYS_PIO0 (1)
// 0x00020000 [17] CLK_SYS_PADS (1)
// 0x00010000 [16] CLK_SYS_OTP (1)
// 0x00008000 [15] CLK_REF_OTP (1)
// 0x00004000 [14] CLK_SYS_JTAG (1)
// 0x00002000 [13] CLK_SYS_IO (1)
// 0x00001000 [12] CLK_SYS_I2C1 (1)
// 0x00000800 [11] CLK_SYS_I2C0 (1)
// 0x00000400 [10] CLK_SYS_HSTX (1)
// 0x00000200 [9] CLK_HSTX (1)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (1)
// 0x00000080 [7] CLK_SYS_DMA (1)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (1)
// 0x00000020 [5] CLK_SYS_BUSCTRL (1)
// 0x00000010 [4] CLK_SYS_BOOTRAM (1)
// 0x00000008 [3] CLK_SYS_ADC (1)
// 0x00000004 [2] CLK_ADC (1)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 sleep_en[2];
};
union {
struct {
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SIOB (0)
// 0x40000000 [30] CLK_SYS_SHA256 (0)
// 0x20000000 [29] CLK_SYS_RSM (0)
// 0x10000000 [28] CLK_SYS_ROSC (0)
// 0x08000000 [27] CLK_SYS_ROM (0)
// 0x04000000 [26] CLK_SYS_RESETS (0)
// 0x02000000 [25] CLK_SYS_PWM (0)
// 0x01000000 [24] CLK_SYS_POWMAN (0)
// 0x00800000 [23] CLK_REF_POWMAN (0)
// 0x00400000 [22] CLK_SYS_PLL_USB (0)
// 0x00200000 [21] CLK_SYS_PLL_SYS (0)
// 0x00100000 [20] CLK_SYS_PIO2 (0)
// 0x00080000 [19] CLK_SYS_PIO1 (0)
// 0x00040000 [18] CLK_SYS_PIO0 (0)
// 0x00020000 [17] CLK_SYS_PADS (0)
// 0x00010000 [16] CLK_SYS_OTP (0)
// 0x00008000 [15] CLK_REF_OTP (0)
// 0x00004000 [14] CLK_SYS_JTAG (0)
// 0x00002000 [13] CLK_SYS_IO (0)
// 0x00001000 [12] CLK_SYS_I2C1 (0)
// 0x00000800 [11] CLK_SYS_I2C0 (0)
// 0x00000400 [10] CLK_SYS_HSTX (0)
// 0x00000200 [9] CLK_HSTX (0)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0)
// 0x00000080 [7] CLK_SYS_DMA (0)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (0)
// 0x00000020 [5] CLK_SYS_BUSCTRL (0)
// 0x00000010 [4] CLK_SYS_BOOTRAM (0)
// 0x00000008 [3] CLK_SYS_ADC (0)
// 0x00000004 [2] CLK_ADC (0)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (0)
// 0x00000001 [0] CLK_SYS_CLOCKS (0)
io_ro_32 enabled0;
_REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
// indicates the state of the clock enable
// 0x40000000 [30] CLK_SYS_XOSC (0)
// 0x20000000 [29] CLK_SYS_XIP (0)
// 0x10000000 [28] CLK_SYS_WATCHDOG (0)
// 0x08000000 [27] CLK_USB (0)
// 0x04000000 [26] CLK_SYS_USBCTRL (0)
// 0x02000000 [25] CLK_SYS_UART1 (0)
// 0x01000000 [24] CLK_PERI_UART1 (0)
// 0x00800000 [23] CLK_SYS_UART0 (0)
// 0x00400000 [22] CLK_PERI_UART0 (0)
// 0x00200000 [21] CLK_SYS_TRNG (0)
// 0x00100000 [20] CLK_SYS_TIMER1 (0)
// 0x00080000 [19] CLK_SYS_TIMER0 (0)
// 0x00040000 [18] CLK_SYS_TICKS (0)
// 0x00020000 [17] CLK_REF_TICKS (0)
// 0x00010000 [16] CLK_SYS_TBMAN (0)
// 0x00008000 [15] CLK_SYS_SYSINFO (0)
// 0x00004000 [14] CLK_SYS_SYSCFG (0)
// 0x00002000 [13] CLK_SYS_SRAM9 (0)
// 0x00001000 [12] CLK_SYS_SRAM8 (0)
// 0x00000800 [11] CLK_SYS_SRAM7 (0)
// 0x00000400 [10] CLK_SYS_SRAM6 (0)
// 0x00000200 [9] CLK_SYS_SRAM5 (0)
// 0x00000100 [8] CLK_SYS_SRAM4 (0)
// 0x00000080 [7] CLK_SYS_SRAM3 (0)
// 0x00000040 [6] CLK_SYS_SRAM2 (0)
// 0x00000020 [5] CLK_SYS_SRAM1 (0)
// 0x00000010 [4] CLK_SYS_SRAM0 (0)
// 0x00000008 [3] CLK_SYS_SPI1 (0)
// 0x00000004 [2] CLK_PERI_SPI1 (0)
// 0x00000002 [1] CLK_SYS_SPI0 (0)
// 0x00000001 [0] CLK_PERI_SPI0 (0)
io_ro_32 enabled1;
};
// (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SIO (0)
// 0x40000000 [30] CLK_SYS_SHA256 (0)
// 0x20000000 [29] CLK_SYS_PSM (0)
// 0x10000000 [28] CLK_SYS_ROSC (0)
// 0x08000000 [27] CLK_SYS_ROM (0)
// 0x04000000 [26] CLK_SYS_RESETS (0)
// 0x02000000 [25] CLK_SYS_PWM (0)
// 0x01000000 [24] CLK_SYS_POWMAN (0)
// 0x00800000 [23] CLK_REF_POWMAN (0)
// 0x00400000 [22] CLK_SYS_PLL_USB (0)
// 0x00200000 [21] CLK_SYS_PLL_SYS (0)
// 0x00100000 [20] CLK_SYS_PIO2 (0)
// 0x00080000 [19] CLK_SYS_PIO1 (0)
// 0x00040000 [18] CLK_SYS_PIO0 (0)
// 0x00020000 [17] CLK_SYS_PADS (0)
// 0x00010000 [16] CLK_SYS_OTP (0)
// 0x00008000 [15] CLK_REF_OTP (0)
// 0x00004000 [14] CLK_SYS_JTAG (0)
// 0x00002000 [13] CLK_SYS_IO (0)
// 0x00001000 [12] CLK_SYS_I2C1 (0)
// 0x00000800 [11] CLK_SYS_I2C0 (0)
// 0x00000400 [10] CLK_SYS_HSTX (0)
// 0x00000200 [9] CLK_HSTX (0)
// 0x00000100 [8] CLK_SYS_GLITCH_DETECTOR (0)
// 0x00000080 [7] CLK_SYS_DMA (0)
// 0x00000040 [6] CLK_SYS_BUSFABRIC (0)
// 0x00000020 [5] CLK_SYS_BUSCTRL (0)
// 0x00000010 [4] CLK_SYS_BOOTRAM (0)
// 0x00000008 [3] CLK_SYS_ADC (0)
// 0x00000004 [2] CLK_ADC (0)
// 0x00000002 [1] CLK_SYS_ACCESSCTRL (0)
// 0x00000001 [0] CLK_SYS_CLOCKS (0)
io_ro_32 enabled[2];
};
_REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
// Raw Interrupts
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 intr;
_REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
// Interrupt Enable
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 inte;
_REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
// Interrupt Force
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 intf;
_REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 ints;
} clocks_hw_t;
#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
static_assert(sizeof (clocks_hw_t) == 0x00d4, "");
#endif // _HARDWARE_STRUCTS_CLOCKS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_CORESIGHT_TRACE_H
#define _HARDWARE_STRUCTS_CORESIGHT_TRACE_H
/**
* \file rp2350/coresight_trace.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/coresight_trace.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_coresight_trace
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/coresight_trace.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(CORESIGHT_TRACE_CTRL_STATUS_OFFSET) // CORESIGHT_TRACE_CTRL_STATUS
// Control and status register
// 0x00000002 [1] TRACE_CAPTURE_FIFO_OVERFLOW (0) This status flag is set high when trace data has been...
// 0x00000001 [0] TRACE_CAPTURE_FIFO_FLUSH (1) Set to 1 to continuously hold the trace FIFO in a...
io_rw_32 ctrl_status;
_REG_(CORESIGHT_TRACE_TRACE_CAPTURE_FIFO_OFFSET) // CORESIGHT_TRACE_TRACE_CAPTURE_FIFO
// FIFO for trace data captured from the TPIU
// 0xffffffff [31:0] RDATA (0x00000000) Read from an 8 x 32-bit FIFO containing trace data...
io_ro_32 trace_capture_fifo;
} coresight_trace_hw_t;
#define coresight_trace_hw ((coresight_trace_hw_t *)CORESIGHT_TRACE_BASE)
static_assert(sizeof (coresight_trace_hw_t) == 0x0008, "");
#endif // _HARDWARE_STRUCTS_CORESIGHT_TRACE_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_H
#define _HARDWARE_STRUCTS_DMA_H
/**
* \file rp2350/dma.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
#include "hardware/structs/dma_debug.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
// DMA Channel 0 Read Address pointer
// 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes
io_rw_32 read_addr;
_REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
// DMA Channel 0 Write Address pointer
// 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes
io_rw_32 write_addr;
_REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
// DMA Channel 0 Transfer Count
// 0xf0000000 [31:28] MODE (0x0) When MODE is 0x0, the transfer count decrements with...
// 0x0fffffff [27:0] COUNT (0x0000000) 28-bit transfer count (256 million transfers maximum)
io_rw_32 transfer_count;
_REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
// DMA Channel 0 Control and Status
// 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags
// 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error
// 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error
// 0x04000000 [26] BUSY (0) This flag goes high when the channel starts a new...
// 0x02000000 [25] SNIFF_EN (0) If 1, this channel's data transfers are visible to the...
// 0x01000000 [24] BSWAP (0) Apply byte-swap transformation to DMA data
// 0x00800000 [23] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the...
// 0x007e0000 [22:17] TREQ_SEL (0x00) Select a Transfer Request signal
// 0x0001e000 [16:13] CHAIN_TO (0x0) When this channel completes, it will trigger the channel...
// 0x00001000 [12] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses
// 0x00000f00 [11:8] RING_SIZE (0x0) Size of address wrap region
// 0x00000080 [7] INCR_WRITE_REV (0) If 1, and INCR_WRITE is 1, the write address is...
// 0x00000040 [6] INCR_WRITE (0) If 1, the write address increments with each transfer
// 0x00000020 [5] INCR_READ_REV (0) If 1, and INCR_READ is 1, the read address is...
// 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer
// 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word)
// 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...
// 0x00000001 [0] EN (0) DMA Channel Enable
io_rw_32 ctrl_trig;
_REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL1_CTRL (-)
io_rw_32 al1_ctrl;
_REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL1_READ_ADDR (-)
io_rw_32 al1_read_addr;
_REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-)
io_rw_32 al1_write_addr;
_REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
// Alias for channel 0 TRANS_COUNT register +
// 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-)
io_rw_32 al1_transfer_count_trig;
_REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL2_CTRL (-)
io_rw_32 al2_ctrl;
_REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-)
io_rw_32 al2_transfer_count;
_REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL2_READ_ADDR (-)
io_rw_32 al2_read_addr;
_REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
// Alias for channel 0 WRITE_ADDR register +
// 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-)
io_rw_32 al2_write_addr_trig;
_REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL3_CTRL (-)
io_rw_32 al3_ctrl;
_REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-)
io_rw_32 al3_write_addr;
_REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-)
io_rw_32 al3_transfer_count;
_REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
// Alias for channel 0 READ_ADDR register +
// 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-)
io_rw_32 al3_read_addr_trig;
} dma_channel_hw_t;
typedef struct {
_REG_(DMA_MPU_BAR0_OFFSET) // DMA_MPU_BAR0
// Base address register for MPU region 0
// 0xffffffe0 [31:5] ADDR (0x0000000) This MPU region matches addresses where addr[31:5] (the...
io_rw_32 bar;
_REG_(DMA_MPU_LAR0_OFFSET) // DMA_MPU_LAR0
// Limit address register for MPU region 0
// 0xffffffe0 [31:5] ADDR (0x0000000) Limit address bits 31:5
// 0x00000004 [2] S (0) Determines the Secure/Non-secure (=1/0) status of...
// 0x00000002 [1] P (0) Determines the Privileged/Unprivileged (=1/0) status of...
// 0x00000001 [0] EN (0) Region enable
io_rw_32 lar;
} dma_mpu_region_hw_t;
typedef struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTS0
io_rw_32 intf;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints;
} dma_irq_ctrl_hw_t;
typedef struct {
dma_channel_hw_t ch[16];
union {
struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte0;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
io_rw_32 intf0;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints0;
uint32_t __pad0;
_REG_(DMA_INTE1_OFFSET) // DMA_INTE1
// Interrupt Enables for IRQ 1
// 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1
io_rw_32 inte1;
_REG_(DMA_INTF1_OFFSET) // DMA_INTF1
// Force Interrupts for IRQ 1
// 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1
io_rw_32 intf1;
_REG_(DMA_INTS1_OFFSET) // DMA_INTS1
// Interrupt Status (masked) for IRQ 1
// 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints1;
uint32_t __pad1;
_REG_(DMA_INTE2_OFFSET) // DMA_INTE2
// Interrupt Enables for IRQ 2
// 0x0000ffff [15:0] INTE2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
io_rw_32 inte2;
_REG_(DMA_INTF2_OFFSET) // DMA_INTF2
// Force Interrupts for IRQ 2
// 0x0000ffff [15:0] INTF2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
io_rw_32 intf2;
_REG_(DMA_INTS2_OFFSET) // DMA_INTS2
// Interrupt Status (masked) for IRQ 2
// 0x0000ffff [15:0] INTS2 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 2
io_rw_32 ints2;
uint32_t __pad2;
_REG_(DMA_INTE3_OFFSET) // DMA_INTE3
// Interrupt Enables for IRQ 3
// 0x0000ffff [15:0] INTE3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
io_rw_32 inte3;
_REG_(DMA_INTF3_OFFSET) // DMA_INTF3
// Force Interrupts for IRQ 3
// 0x0000ffff [15:0] INTF3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
io_rw_32 intf3;
_REG_(DMA_INTS3_OFFSET) // DMA_INTS3
// Interrupt Status (masked) for IRQ 3
// 0x0000ffff [15:0] INTS3 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 3
io_rw_32 ints3;
};
dma_irq_ctrl_hw_t irq_ctrl[4];
};
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
// Pacing timer (generate periodic TREQs)
// 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend
// 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor
io_rw_32 timer[4];
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
// Trigger one or more channels simultaneously
// 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel
io_wo_32 multi_channel_trigger;
_REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
// Sniffer Control
// 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)...
// 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read
// 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,...
// 0x000001e0 [8:5] CALC (0x0)
// 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe
// 0x00000001 [0] EN (0) Enable sniffer
io_rw_32 sniff_ctrl;
_REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
// Data accumulator for sniff hardware
// 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA...
io_rw_32 sniff_data;
uint32_t _pad0;
_REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
// Debug RAF, WAF, TDF levels
// 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level
// 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level
// 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level
io_ro_32 fifo_levels;
_REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
// Abort an in-progress transfer sequence on one or more channels
// 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel
io_wo_32 abort;
_REG_(DMA_N_CHANNELS_OFFSET) // DMA_N_CHANNELS
// The number of channels this DMA instance is equipped with
// 0x0000001f [4:0] N_CHANNELS (-)
io_ro_32 n_channels;
uint32_t _pad1[5];
// (Description copied from array index 0 register DMA_SECCFG_CH0 applies similarly to other array indexes)
_REG_(DMA_SECCFG_CH0_OFFSET) // DMA_SECCFG_CH0
// Security level configuration for channel 0.
// 0x00000004 [2] LOCK (0) LOCK is 0 at reset, and is set to 1 automatically upon a...
// 0x00000002 [1] S (1) Secure channel
// 0x00000001 [0] P (1) Privileged channel
io_rw_32 seccfg_ch[16];
// (Description copied from array index 0 register DMA_SECCFG_IRQ0 applies similarly to other array indexes)
_REG_(DMA_SECCFG_IRQ0_OFFSET) // DMA_SECCFG_IRQ0
// Security configuration for IRQ 0
// 0x00000002 [1] S (1) Secure IRQ
// 0x00000001 [0] P (1) Privileged IRQ
io_rw_32 seccfg_irq[4];
_REG_(DMA_SECCFG_MISC_OFFSET) // DMA_SECCFG_MISC
// Miscellaneous security configuration
// 0x00000200 [9] TIMER3_S (1) If 1, the TIMER3 register is only accessible from a...
// 0x00000100 [8] TIMER3_P (1) If 1, the TIMER3 register is only accessible from a...
// 0x00000080 [7] TIMER2_S (1) If 1, the TIMER2 register is only accessible from a...
// 0x00000040 [6] TIMER2_P (1) If 1, the TIMER2 register is only accessible from a...
// 0x00000020 [5] TIMER1_S (1) If 1, the TIMER1 register is only accessible from a...
// 0x00000010 [4] TIMER1_P (1) If 1, the TIMER1 register is only accessible from a...
// 0x00000008 [3] TIMER0_S (1) If 1, the TIMER0 register is only accessible from a...
// 0x00000004 [2] TIMER0_P (1) If 1, the TIMER0 register is only accessible from a...
// 0x00000002 [1] SNIFF_S (1) If 1, the sniffer can see data transfers from Secure...
// 0x00000001 [0] SNIFF_P (1) If 1, the sniffer can see data transfers from Privileged...
io_rw_32 seccfg_misc;
uint32_t _pad2[11];
_REG_(DMA_MPU_CTRL_OFFSET) // DMA_MPU_CTRL
// Control register for DMA MPU
// 0x00000008 [3] NS_HIDE_ADDR (0) By default, when a region's S bit is clear,...
// 0x00000004 [2] S (0) Determine whether an address not covered by an active...
// 0x00000002 [1] P (0) Determine whether an address not covered by an active...
io_rw_32 mpu_ctrl;
dma_mpu_region_hw_t mpu_region[8];
} dma_hw_t;
#define dma_hw ((dma_hw_t *)DMA_BASE)
static_assert(sizeof (dma_hw_t) == 0x0544, "");
#endif // _HARDWARE_STRUCTS_DMA_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H
#define _HARDWARE_STRUCTS_DMA_DEBUG_H
/**
* \file rp2350/dma_debug.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ
// Read: get channel DREQ counter (i
// 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00)
io_rw_32 dbg_ctdreq;
_REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR
// Read to get channel TRANS_COUNT reload value, i
// 0xffffffff [31:0] CH0_DBG_TCR (0x00000000)
io_ro_32 dbg_tcr;
uint32_t _pad0[14];
} dma_debug_channel_hw_t;
typedef struct {
dma_debug_channel_hw_t ch[16];
} dma_debug_hw_t;
#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_GLITCH_DETECTOR_H
#define _HARDWARE_STRUCTS_GLITCH_DETECTOR_H
/**
* \file rp2350/glitch_detector.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/glitch_detector.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_glitch_detector
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/glitch_detector.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(GLITCH_DETECTOR_ARM_OFFSET) // GLITCH_DETECTOR_ARM
// Forcibly arm the glitch detectors, if they are not already armed by OTP
// 0x0000ffff [15:0] ARM (0x5bad)
io_rw_32 arm;
_REG_(GLITCH_DETECTOR_DISARM_OFFSET) // GLITCH_DETECTOR_DISARM
// 0x0000ffff [15:0] DISARM (0x0000) Forcibly disarm the glitch detectors, if they are armed by OTP
io_rw_32 disarm;
_REG_(GLITCH_DETECTOR_SENSITIVITY_OFFSET) // GLITCH_DETECTOR_SENSITIVITY
// Adjust the sensitivity of glitch detectors to values other than their OTP-provided defaults
// 0xff000000 [31:24] DEFAULT (0x00)
// 0x0000c000 [15:14] DET3_INV (0x0) Must be the inverse of DET3, else the default value is used
// 0x00003000 [13:12] DET2_INV (0x0) Must be the inverse of DET2, else the default value is used
// 0x00000c00 [11:10] DET1_INV (0x0) Must be the inverse of DET1, else the default value is used
// 0x00000300 [9:8] DET0_INV (0x0) Must be the inverse of DET0, else the default value is used
// 0x000000c0 [7:6] DET3 (0x0) Set sensitivity for detector 3
// 0x00000030 [5:4] DET2 (0x0) Set sensitivity for detector 2
// 0x0000000c [3:2] DET1 (0x0) Set sensitivity for detector 1
// 0x00000003 [1:0] DET0 (0x0) Set sensitivity for detector 0
io_rw_32 sensitivity;
_REG_(GLITCH_DETECTOR_LOCK_OFFSET) // GLITCH_DETECTOR_LOCK
// 0x000000ff [7:0] LOCK (0x00) Write any nonzero value to disable writes to ARM,...
io_rw_32 lock;
_REG_(GLITCH_DETECTOR_TRIG_STATUS_OFFSET) // GLITCH_DETECTOR_TRIG_STATUS
// Set when a detector output triggers
// 0x00000008 [3] DET3 (0)
// 0x00000004 [2] DET2 (0)
// 0x00000002 [1] DET1 (0)
// 0x00000001 [0] DET0 (0)
io_rw_32 trig_status;
_REG_(GLITCH_DETECTOR_TRIG_FORCE_OFFSET) // GLITCH_DETECTOR_TRIG_FORCE
// Simulate the firing of one or more detectors
// 0x0000000f [3:0] TRIG_FORCE (0x0)
io_wo_32 trig_force;
} glitch_detector_hw_t;
#define glitch_detector_hw ((glitch_detector_hw_t *)GLITCH_DETECTOR_BASE)
static_assert(sizeof (glitch_detector_hw_t) == 0x0018, "");
#endif // _HARDWARE_STRUCTS_GLITCH_DETECTOR_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_HSTX_CTRL_H
#define _HARDWARE_STRUCTS_HSTX_CTRL_H
/**
* \file rp2350/hstx_ctrl.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/hstx_ctrl.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_ctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/hstx_ctrl.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(HSTX_CTRL_CSR_OFFSET) // HSTX_CTRL_CSR
// 0xf0000000 [31:28] CLKDIV (0x1) Clock period of the generated clock, measured in HSTX...
// 0x0f000000 [27:24] CLKPHASE (0x0) Set the initial phase of the generated clock
// 0x001f0000 [20:16] N_SHIFTS (0x05) Number of times to shift the shift register before...
// 0x00001f00 [12:8] SHIFT (0x06) How many bits to right-rotate the shift register by each cycle
// 0x00000060 [6:5] COUPLED_SEL (0x0) Select which PIO to use for coupled mode operation
// 0x00000010 [4] COUPLED_MODE (0) Enable the PIO-to-HSTX 1:1 connection
// 0x00000002 [1] EXPAND_EN (0) Enable the command expander
// 0x00000001 [0] EN (0) When EN is 1, the HSTX will shift out data as it appears...
io_rw_32 csr;
// (Description copied from array index 0 register HSTX_CTRL_BIT0 applies similarly to other array indexes)
_REG_(HSTX_CTRL_BIT0_OFFSET) // HSTX_CTRL_BIT0
// Data control register for output bit 0
// 0x00020000 [17] CLK (0) Connect this output to the generated clock, rather than...
// 0x00010000 [16] INV (0) Invert this data output (logical NOT)
// 0x00001f00 [12:8] SEL_N (0x00) Shift register data bit select for the second half of...
// 0x0000001f [4:0] SEL_P (0x00) Shift register data bit select for the first half of the...
io_rw_32 bit[8];
_REG_(HSTX_CTRL_EXPAND_SHIFT_OFFSET) // HSTX_CTRL_EXPAND_SHIFT
// Configure the optional shifter inside the command expander
// 0x1f000000 [28:24] ENC_N_SHIFTS (0x01) Number of times to consume from the shift register...
// 0x001f0000 [20:16] ENC_SHIFT (0x00) How many bits to right-rotate the shift register by each...
// 0x00001f00 [12:8] RAW_N_SHIFTS (0x01) Number of times to consume from the shift register...
// 0x0000001f [4:0] RAW_SHIFT (0x00) How many bits to right-rotate the shift register by each...
io_rw_32 expand_shift;
_REG_(HSTX_CTRL_EXPAND_TMDS_OFFSET) // HSTX_CTRL_EXPAND_TMDS
// Configure the optional TMDS encoder inside the command expander
// 0x00e00000 [23:21] L2_NBITS (0x0) Number of valid data bits for the lane 2 TMDS encoder,...
// 0x001f0000 [20:16] L2_ROT (0x00) Right-rotate applied to the current shifter data before...
// 0x0000e000 [15:13] L1_NBITS (0x0) Number of valid data bits for the lane 1 TMDS encoder,...
// 0x00001f00 [12:8] L1_ROT (0x00) Right-rotate applied to the current shifter data before...
// 0x000000e0 [7:5] L0_NBITS (0x0) Number of valid data bits for the lane 0 TMDS encoder,...
// 0x0000001f [4:0] L0_ROT (0x00) Right-rotate applied to the current shifter data before...
io_rw_32 expand_tmds;
} hstx_ctrl_hw_t;
#define hstx_ctrl_hw ((hstx_ctrl_hw_t *)HSTX_CTRL_BASE)
static_assert(sizeof (hstx_ctrl_hw_t) == 0x002c, "");
#endif // _HARDWARE_STRUCTS_HSTX_CTRL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_HSTX_FIFO_H
#define _HARDWARE_STRUCTS_HSTX_FIFO_H
/**
* \file rp2350/hstx_fifo.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/hstx_fifo.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_hstx_fifo
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/hstx_fifo.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(HSTX_FIFO_STAT_OFFSET) // HSTX_FIFO_STAT
// FIFO status
// 0x00000400 [10] WOF (0) FIFO was written when full
// 0x00000200 [9] EMPTY (-)
// 0x00000100 [8] FULL (-)
// 0x000000ff [7:0] LEVEL (0x00)
io_rw_32 stat;
_REG_(HSTX_FIFO_FIFO_OFFSET) // HSTX_FIFO_FIFO
// Write access to FIFO
// 0xffffffff [31:0] FIFO (0x00000000)
io_wo_32 fifo;
} hstx_fifo_hw_t;
#define hstx_fifo_hw ((hstx_fifo_hw_t *)HSTX_FIFO_BASE)
static_assert(sizeof (hstx_fifo_hw_t) == 0x0008, "");
#endif // _HARDWARE_STRUCTS_HSTX_FIFO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_I2C_H
#define _HARDWARE_STRUCTS_I2C_H
/**
* \file rp2350/i2c.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/i2c.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_i2c
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
// I2C Control Register
// 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of...
// 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus...
// 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY...
// 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt...
// 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,...
// 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when...
// 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in...
// 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the...
// 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c...
// 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled
io_rw_32 con;
_REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
// I2C Target Address Register
// 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID...
// 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is...
// 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction
io_rw_32 tar;
_REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
// I2C Slave Address Register
// 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is...
io_rw_32 sar;
uint32_t _pad0;
_REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
// I2C Rx/Tx Data Buffer and Command Register
// 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address...
// 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the...
// 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the...
// 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed
// 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or...
io_rw_32 data_cmd;
_REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
// Standard Speed I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_hcnt;
_REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
// Standard Speed I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_lcnt;
_REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_hcnt;
_REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_lcnt;
uint32_t _pad1[2];
_REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
// I2C Interrupt Status Register
// 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
// 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
// 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
// 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
// 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
// 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
// 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
// 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
// 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
// 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
// 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
io_ro_32 intr_stat;
_REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
// I2C Interrupt Mask Register
// 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in...
// 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
// 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register
// 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
// 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
// 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
// 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
// 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
// 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
// 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
// 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
// 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
// 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
io_rw_32 intr_mask;
_REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
// I2C Raw Interrupt Status Register
// 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on...
// 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it...
// 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has...
// 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the...
// 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set...
// 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,...
// 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,...
// 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a...
// 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs...
// 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to...
// 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the...
// 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to...
// 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer...
io_ro_32 raw_intr_stat;
_REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
// I2C Receive FIFO Threshold Register
// 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level
io_rw_32 rx_tl;
_REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
// I2C Transmit FIFO Threshold Register
// 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level
io_rw_32 tx_tl;
_REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
// Clear Combined and Individual Interrupt Register
// 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all...
io_ro_32 clr_intr;
_REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
// Clear RX_UNDER Interrupt Register
// 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit...
io_ro_32 clr_rx_under;
_REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
// Clear RX_OVER Interrupt Register
// 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit...
io_ro_32 clr_rx_over;
_REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
// Clear TX_OVER Interrupt Register
// 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit...
io_ro_32 clr_tx_over;
_REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
// Clear RD_REQ Interrupt Register
// 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)...
io_ro_32 clr_rd_req;
_REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
// Clear TX_ABRT Interrupt Register
// 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit...
io_ro_32 clr_tx_abrt;
_REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
// Clear RX_DONE Interrupt Register
// 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit...
io_ro_32 clr_rx_done;
_REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
// Clear ACTIVITY Interrupt Register
// 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if...
io_ro_32 clr_activity;
_REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
// Clear STOP_DET Interrupt Register
// 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit...
io_ro_32 clr_stop_det;
_REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
// Clear START_DET Interrupt Register
// 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit...
io_ro_32 clr_start_det;
_REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
// Clear GEN_CALL Interrupt Register
// 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit...
io_ro_32 clr_gen_call;
_REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
// I2C ENABLE Register
// 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data...
// 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort
// 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled
io_rw_32 enable;
_REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
// I2C STATUS Register
// 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status
// 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status
// 0x00000010 [4] RFF (0) Receive FIFO Completely Full
// 0x00000008 [3] RFNE (0) Receive FIFO Not Empty
// 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty
// 0x00000002 [1] TFNF (1) Transmit FIFO Not Full
// 0x00000001 [0] ACTIVITY (0) I2C Activity Status
io_ro_32 status;
_REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
// I2C Transmit FIFO Level Register
// 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level
io_ro_32 txflr;
_REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
// I2C Receive FIFO Level Register
// 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level
io_ro_32 rxflr;
_REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
// I2C SDA Hold Time Length Register
// 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk...
// 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk...
io_rw_32 sda_hold;
_REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
// I2C Transmit Abort Source Register
// 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands...
// 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit
// 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode...
// 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while...
// 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read...
// 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost...
// 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a...
// 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT...
// 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START...
// 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed...
// 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode...
// 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has...
// 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit
// 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit...
io_ro_32 tx_abrt_source;
_REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
// Generate Slave Data NACK Register
// 0x00000001 [0] NACK (0) Generate NACK
io_rw_32 slv_data_nack_only;
_REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
// DMA Control Register
// 0x00000002 [1] TDMAE (0) Transmit DMA Enable
// 0x00000001 [0] RDMAE (0) Receive DMA Enable
io_rw_32 dma_cr;
_REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level
io_rw_32 dma_tdlr;
_REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMARDL (0x0) Receive Data Level
io_rw_32 dma_rdlr;
_REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
// I2C SDA Setup Register
// 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup
io_rw_32 sda_setup;
_REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
// I2C ACK General Call Register
// 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call
io_rw_32 ack_general_call;
_REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
// I2C Enable Status Register
// 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost
// 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive)
// 0x00000001 [0] IC_EN (0) ic_en Status
io_ro_32 enable_status;
_REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
// I2C SS, FS or FM+ spike suppression limit
// 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction...
io_rw_32 fs_spklen;
uint32_t _pad2;
_REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
// Clear RESTART_DET Interrupt Register
// 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt...
io_ro_32 clr_restart_det;
uint32_t _pad3[18];
_REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
// Component Parameter Register 1
// 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16
// 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16
// 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible
// 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled
// 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs
// 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode
// 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE
// 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits
io_ro_32 comp_param_1;
_REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
// I2C Component Version Register
// 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a)
io_ro_32 comp_version;
_REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
// I2C Component Type Register
// 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40
io_ro_32 comp_type;
} i2c_hw_t;
#define i2c0_hw ((i2c_hw_t *)I2C0_BASE)
#define i2c1_hw ((i2c_hw_t *)I2C1_BASE)
static_assert(sizeof (i2c_hw_t) == 0x0100, "");
#endif // _HARDWARE_STRUCTS_I2C_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_INTERP_H
#define _HARDWARE_STRUCTS_INTERP_H
/**
* \file rp2350/interp.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
// Read/write access to accumulator 0
// 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000)
io_rw_32 accum[2];
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
// Read/write access to BASE0 register
// 0xffffffff [31:0] INTERP0_BASE0 (0x00000000)
io_rw_32 base[3];
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
// 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000)
io_ro_32 pop[3];
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
// Read LANE0 result, without altering any internal state (PEEK)
// 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000)
io_ro_32 peek[3];
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
// Control register for lane 0
// 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set
// 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set
// 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set
// 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core
// 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the...
// 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result
// 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's...
// 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this...
// 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator...
// 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask...
// 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive)
// 0x0000001f [4:0] SHIFT (0x00) Right-rotate applied to accumulator before masking
io_rw_32 ctrl[2];
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
// Values written here are atomically added to ACCUM0
// 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000)
io_rw_32 add_raw[2];
_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
// 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000)
io_wo_32 base01;
} interp_hw_t;
#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
#define interp_hw_array_ns ((interp_hw_t *)(SIO_NONSEC_BASE + SIO_INTERP0_ACCUM0_OFFSET))
static_assert(sizeof (interp_hw_t) == 0x0040, "");
#define interp0_hw (&interp_hw_array[0])
#define interp1_hw (&interp_hw_array[1])
#endif // _HARDWARE_STRUCTS_INTERP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_BANK0_H
#define _HARDWARE_STRUCTS_IO_BANK0_H
/**
* \file rp2350/io_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief GPIO pin function selectors on RP2350 (used as typedef \ref gpio_function_t)
* \ingroup hardware_gpio
*/
typedef enum gpio_function_rp2350 {
GPIO_FUNC_HSTX = 0, ///< Select HSTX as GPIO pin function
GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function
GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function
GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function
GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function
GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function
GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function
GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function
GPIO_FUNC_PIO2 = 8, ///< Select PIO2 as GPIO pin function
GPIO_FUNC_GPCK = 9, ///< Select GPCK as GPIO pin function
GPIO_FUNC_XIP_CS1 = 9, ///< Select XIP CS1 as GPIO pin function
GPIO_FUNC_CORESIGHT_TRACE = 9, ///< Select CORESIGHT TRACE as GPIO pin function
GPIO_FUNC_USB = 10, ///< Select USB as GPIO pin function
GPIO_FUNC_UART_AUX = 11, ///< Select UART_AUX as GPIO pin function
GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function
} gpio_function_t;
typedef struct {
_REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
io_ro_32 status;
_REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x0000c000 [15:14] OEOVER (0x0)
// 0x00003000 [13:12] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_bank0_status_ctrl_hw_t;
typedef struct {
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
// Interrupt Enable for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 inte[6];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
// Interrupt Force for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intf[6];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
// Interrupt status after masking & forcing for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_ro_32 ints[6];
} io_bank0_irq_ctrl_hw_t;
/// \tag::io_bank0_hw[]
typedef struct {
io_bank0_status_ctrl_hw_t io[48];
uint32_t _pad0[32];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_SECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_PROC0_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_SECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_proc0_secure[2];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC0_NONSECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_proc0_nonsecure[2];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_SECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_PROC1_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_SECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_proc1_secure[2];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_PROC1_NONSECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_proc1_nonsecure[2];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_SECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_dormant_wake_secure[2];
// (Description copied from array index 0 register IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0 applies similarly to other array indexes)
_REG_(IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0_OFFSET) // IO_BANK0_IRQSUMMARY_DORMANT_WAKE_NONSECURE0
// 0x80000000 [31] GPIO31 (0)
// 0x40000000 [30] GPIO30 (0)
// 0x20000000 [29] GPIO29 (0)
// 0x10000000 [28] GPIO28 (0)
// 0x08000000 [27] GPIO27 (0)
// 0x04000000 [26] GPIO26 (0)
// 0x02000000 [25] GPIO25 (0)
// 0x01000000 [24] GPIO24 (0)
// 0x00800000 [23] GPIO23 (0)
// 0x00400000 [22] GPIO22 (0)
// 0x00200000 [21] GPIO21 (0)
// 0x00100000 [20] GPIO20 (0)
// 0x00080000 [19] GPIO19 (0)
// 0x00040000 [18] GPIO18 (0)
// 0x00020000 [17] GPIO17 (0)
// 0x00010000 [16] GPIO16 (0)
// 0x00008000 [15] GPIO15 (0)
// 0x00004000 [14] GPIO14 (0)
// 0x00002000 [13] GPIO13 (0)
// 0x00001000 [12] GPIO12 (0)
// 0x00000800 [11] GPIO11 (0)
// 0x00000400 [10] GPIO10 (0)
// 0x00000200 [9] GPIO9 (0)
// 0x00000100 [8] GPIO8 (0)
// 0x00000080 [7] GPIO7 (0)
// 0x00000040 [6] GPIO6 (0)
// 0x00000020 [5] GPIO5 (0)
// 0x00000010 [4] GPIO4 (0)
// 0x00000008 [3] GPIO3 (0)
// 0x00000004 [2] GPIO2 (0)
// 0x00000002 [1] GPIO1 (0)
// 0x00000001 [0] GPIO0 (0)
io_ro_32 irqsummary_dormant_wake_nonsecure[2];
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
// Raw Interrupts
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intr[6];
union {
struct {
io_bank0_irq_ctrl_hw_t proc0_irq_ctrl;
io_bank0_irq_ctrl_hw_t proc1_irq_ctrl;
io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_bank0_irq_ctrl_hw_t irq_ctrl[3];
};
} io_bank0_hw_t;
/// \end::io_bank0_hw[]
#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE)
static_assert(sizeof (io_bank0_hw_t) == 0x0320, "");
#endif // _HARDWARE_STRUCTS_IO_BANK0_H

316
lib/pico-sdk/rp2350/hardware/structs/io_qspi.h Normal file
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@ -0,0 +1,316 @@
// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
#define _HARDWARE_STRUCTS_IO_QSPI_H
/**
* \file rp2350/io_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_io_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief QSPI pin function selectors on RP2350 (used as typedef \ref gpio_function1_t)
*/
typedef enum gpio_function1_rp2350 {
GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
GPIO_FUNC1_UART = 2, ///< Select UART as QSPI pin function
GPIO_FUNC1_I2C = 3, ///< Select I2C as QSPI pin function
GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
GPIO_FUNC1_UART_AUX = 11, ///< Select UART_AUX as QSPI pin function
GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
} gpio_function1_t;
typedef struct {
_REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
io_ro_32 status;
_REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x0000c000 [15:14] OEOVER (0x0)
// 0x00003000 [13:12] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_qspi_status_ctrl_hw_t;
typedef struct {
_REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
// Interrupt Enable for proc0
// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
io_rw_32 inte;
_REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
// Interrupt Force for proc0
// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
io_rw_32 intf;
_REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
// Interrupt status after masking & forcing for proc0
// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
io_ro_32 ints;
} io_qspi_irq_ctrl_hw_t;
typedef struct {
_REG_(IO_QSPI_USBPHY_DP_STATUS_OFFSET) // IO_QSPI_USBPHY_DP_STATUS
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
io_ro_32 usbphy_dp_status;
_REG_(IO_QSPI_USBPHY_DP_CTRL_OFFSET) // IO_QSPI_USBPHY_DP_CTRL
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x0000c000 [15:14] OEOVER (0x0)
// 0x00003000 [13:12] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 usbphy_dp_ctrl;
_REG_(IO_QSPI_USBPHY_DM_STATUS_OFFSET) // IO_QSPI_USBPHY_DM_STATUS
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before filtering and override are applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
io_ro_32 usbphy_dm_status;
_REG_(IO_QSPI_USBPHY_DM_CTRL_OFFSET) // IO_QSPI_USBPHY_DM_CTRL
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x0000c000 [15:14] OEOVER (0x0)
// 0x00003000 [13:12] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 usbphy_dm_ctrl;
io_qspi_status_ctrl_hw_t io[6];
uint32_t _pad0[112];
_REG_(IO_QSPI_IRQSUMMARY_PROC0_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_SECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_proc0_secure;
_REG_(IO_QSPI_IRQSUMMARY_PROC0_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC0_NONSECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_proc0_nonsecure;
_REG_(IO_QSPI_IRQSUMMARY_PROC1_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_SECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_proc1_secure;
_REG_(IO_QSPI_IRQSUMMARY_PROC1_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_PROC1_NONSECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_proc1_nonsecure;
_REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_SECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_dormant_wake_secure;
_REG_(IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE_OFFSET) // IO_QSPI_IRQSUMMARY_DORMANT_WAKE_NONSECURE
// 0x00000080 [7] GPIO_QSPI_SD3 (0)
// 0x00000040 [6] GPIO_QSPI_SD2 (0)
// 0x00000020 [5] GPIO_QSPI_SD1 (0)
// 0x00000010 [4] GPIO_QSPI_SD0 (0)
// 0x00000008 [3] GPIO_QSPI_SS (0)
// 0x00000004 [2] GPIO_QSPI_SCLK (0)
// 0x00000002 [1] USBPHY_DM (0)
// 0x00000001 [0] USBPHY_DP (0)
io_ro_32 irqsummary_dormant_wake_nonsecure;
_REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
// Raw Interrupts
// 0x80000000 [31] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x40000000 [30] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x20000000 [29] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x08000000 [27] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x04000000 [26] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x02000000 [25] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00800000 [23] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SCLK_LEVEL_LOW (0)
// 0x00000080 [7] USBPHY_DM_EDGE_HIGH (0)
// 0x00000040 [6] USBPHY_DM_EDGE_LOW (0)
// 0x00000020 [5] USBPHY_DM_LEVEL_HIGH (0)
// 0x00000010 [4] USBPHY_DM_LEVEL_LOW (0)
// 0x00000008 [3] USBPHY_DP_EDGE_HIGH (0)
// 0x00000004 [2] USBPHY_DP_EDGE_LOW (0)
// 0x00000002 [1] USBPHY_DP_LEVEL_HIGH (0)
// 0x00000001 [0] USBPHY_DP_LEVEL_LOW (0)
io_rw_32 intr;
union {
struct {
io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_qspi_irq_ctrl_hw_t irq_ctrl[3];
};
} io_qspi_hw_t;
#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
static_assert(sizeof (io_qspi_hw_t) == 0x0240, "");
#endif // _HARDWARE_STRUCTS_IO_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_bank0.h"
#define iobank0_hw io_bank0_hw

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_qspi.h"
#define ioqspi_hw io_qspi_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_M33_EPPB_H
#define _HARDWARE_STRUCTS_M33_EPPB_H
/**
* \file rp2350/m33_eppb.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33_eppb.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33_eppb
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33_eppb.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
// (Description copied from array index 0 register M33_EPPB_NMI_MASK0 applies similarly to other array indexes)
_REG_(M33_EPPB_NMI_MASK0_OFFSET) // M33_EPPB_NMI_MASK0
// NMI mask for IRQs 0 through 31
// 0xffffffff [31:0] NMI_MASK0 (0x00000000)
io_rw_32 nmi_mask[2];
_REG_(M33_EPPB_SLEEPCTRL_OFFSET) // M33_EPPB_SLEEPCTRL
// Nonstandard sleep control register
// 0x00000004 [2] WICENACK (0) Status signal from the processor's interrupt controller
// 0x00000002 [1] WICENREQ (1) Request that the next processor deep sleep is a WIC sleep
// 0x00000001 [0] LIGHT_SLEEP (0) By default, any processor sleep will deassert the...
io_rw_32 sleepctrl;
} m33_eppb_hw_t;
#define eppb_hw ((m33_eppb_hw_t *)EPPB_BASE)
static_assert(sizeof (m33_eppb_hw_t) == 0x000c, "");
#endif // _HARDWARE_STRUCTS_M33_EPPB_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_MPU_H
#define _HARDWARE_STRUCTS_MPU_H
/**
* \file rp2350/mpu.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
_REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE
// The MPU Type Register indicates how many regions the MPU `FTSSS supports
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data...
io_ro_32 type;
_REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL
// Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for...
// 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less...
// 0x00000001 [0] ENABLE (0) Enables the MPU
io_rw_32 ctrl;
_REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR
// Selects the region currently accessed by MPU_RBAR and MPU_RLAR
// 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR
io_rw_32 rnr;
_REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR
// Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS
// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
io_rw_32 rbar;
_REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR
// Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS
// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
// 0x00000001 [0] EN (0) Region enable
io_rw_32 rlar;
_REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1
// Provides indirect read and write access to the base address of the MPU region selected by...
// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
io_rw_32 rbar_a1;
_REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1
// Provides indirect read and write access to the limit address of the currently selected MPU...
// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
// 0x00000001 [0] EN (0) Region enable
io_rw_32 rlar_a1;
_REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2
// Provides indirect read and write access to the base address of the MPU region selected by...
// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
io_rw_32 rbar_a2;
_REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2
// Provides indirect read and write access to the limit address of the currently selected MPU...
// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
// 0x00000001 [0] EN (0) Region enable
io_rw_32 rlar_a2;
_REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3
// Provides indirect read and write access to the base address of the MPU region selected by...
// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
io_rw_32 rbar_a3;
_REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3
// Provides indirect read and write access to the limit address of the currently selected MPU...
// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
// 0x00000001 [0] EN (0) Region enable
io_rw_32 rlar_a3;
uint32_t _pad0;
// (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)
_REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0
// Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values
// 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3
// 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2
// 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1
// 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0
io_rw_32 mair[2];
} mpu_hw_t;
#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET))
static_assert(sizeof (mpu_hw_t) == 0x0038, "");
#endif // _HARDWARE_STRUCTS_MPU_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_NVIC_H
#define _HARDWARE_STRUCTS_NVIC_H
/**
* \file rp2350/nvic.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
// (Description copied from array index 0 register M33_NVIC_ISER0 applies similarly to other array indexes)
_REG_(M33_NVIC_ISER0_OFFSET) // M33_NVIC_ISER0
// Enables or reads the enabled state of each group of 32 interrupts
// 0xffffffff [31:0] SETENA (0x00000000) For SETENA[m] in NVIC_ISER*n, indicates whether...
io_rw_32 iser[2];
uint32_t _pad0[30];
// (Description copied from array index 0 register M33_NVIC_ICER0 applies similarly to other array indexes)
_REG_(M33_NVIC_ICER0_OFFSET) // M33_NVIC_ICER0
// Clears or reads the enabled state of each group of 32 interrupts
// 0xffffffff [31:0] CLRENA (0x00000000) For CLRENA[m] in NVIC_ICER*n, indicates whether...
io_rw_32 icer[2];
uint32_t _pad1[30];
// (Description copied from array index 0 register M33_NVIC_ISPR0 applies similarly to other array indexes)
_REG_(M33_NVIC_ISPR0_OFFSET) // M33_NVIC_ISPR0
// Enables or reads the pending state of each group of 32 interrupts
// 0xffffffff [31:0] SETPEND (0x00000000) For SETPEND[m] in NVIC_ISPR*n, indicates whether...
io_rw_32 ispr[2];
uint32_t _pad2[30];
// (Description copied from array index 0 register M33_NVIC_ICPR0 applies similarly to other array indexes)
_REG_(M33_NVIC_ICPR0_OFFSET) // M33_NVIC_ICPR0
// Clears or reads the pending state of each group of 32 interrupts
// 0xffffffff [31:0] CLRPEND (0x00000000) For CLRPEND[m] in NVIC_ICPR*n, indicates whether...
io_rw_32 icpr[2];
uint32_t _pad3[30];
// (Description copied from array index 0 register M33_NVIC_IABR0 applies similarly to other array indexes)
_REG_(M33_NVIC_IABR0_OFFSET) // M33_NVIC_IABR0
// For each group of 32 interrupts, shows the active state of each interrupt
// 0xffffffff [31:0] ACTIVE (0x00000000) For ACTIVE[m] in NVIC_IABR*n, indicates the active state...
io_rw_32 iabr[2];
uint32_t _pad4[30];
// (Description copied from array index 0 register M33_NVIC_ITNS0 applies similarly to other array indexes)
_REG_(M33_NVIC_ITNS0_OFFSET) // M33_NVIC_ITNS0
// For each group of 32 interrupts, determines whether each interrupt targets Non-secure or Secure state
// 0xffffffff [31:0] ITNS (0x00000000) For ITNS[m] in NVIC_ITNS*n, `IAAMO the target Security...
io_rw_32 itns[2];
uint32_t _pad5[30];
// (Description copied from array index 0 register M33_NVIC_IPR0 applies similarly to other array indexes)
_REG_(M33_NVIC_IPR0_OFFSET) // M33_NVIC_IPR0
// Sets or reads interrupt priorities
// 0xf0000000 [31:28] PRI_N3 (0x0) For register NVIC_IPRn, the priority of interrupt number...
// 0x00f00000 [23:20] PRI_N2 (0x0) For register NVIC_IPRn, the priority of interrupt number...
// 0x0000f000 [15:12] PRI_N1 (0x0) For register NVIC_IPRn, the priority of interrupt number...
// 0x000000f0 [7:4] PRI_N0 (0x0) For register NVIC_IPRn, the priority of interrupt number...
io_rw_32 ipr[16];
} nvic_hw_t;
#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M33_NVIC_ISER0_OFFSET))
#define nvic_ns_hw ((nvic_hw_t *)(PPB_NONSEC_BASE + M33_NVIC_ISER0_OFFSET))
static_assert(sizeof (nvic_hw_t) == 0x0340, "");
#endif // _HARDWARE_STRUCTS_NVIC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_OTP_H
#define _HARDWARE_STRUCTS_OTP_H
/**
* \file rp2350/otp.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/otp.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_otp
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/otp.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
// (Description copied from array index 0 register OTP_SW_LOCK0 applies similarly to other array indexes)
_REG_(OTP_SW_LOCK0_OFFSET) // OTP_SW_LOCK0
// Software lock register for page 0.
// 0x0000000c [3:2] NSEC (-) Non-secure lock status
// 0x00000003 [1:0] SEC (-) Secure lock status
io_rw_32 sw_lock[64];
_REG_(OTP_SBPI_INSTR_OFFSET) // OTP_SBPI_INSTR
// Dispatch instructions to the SBPI interface, used for programming the OTP fuses
// 0x40000000 [30] EXEC (0) Execute instruction
// 0x20000000 [29] IS_WR (0) Payload type is write
// 0x10000000 [28] HAS_PAYLOAD (0) Instruction has payload (data to be written or to be read)
// 0x0f000000 [27:24] PAYLOAD_SIZE_M1 (0x0) Instruction payload size in bytes minus 1
// 0x00ff0000 [23:16] TARGET (0x00) Instruction target, it can be PMC (0x3a) or DAP (0x02)
// 0x0000ff00 [15:8] CMD (0x00)
// 0x000000ff [7:0] SHORT_WDATA (0x00) wdata to be used only when payload_size_m1=0
io_rw_32 sbpi_instr;
// (Description copied from array index 0 register OTP_SBPI_WDATA_0 applies similarly to other array indexes)
_REG_(OTP_SBPI_WDATA_0_OFFSET) // OTP_SBPI_WDATA_0
// SBPI write payload bytes 3
// 0xffffffff [31:0] SBPI_WDATA_0 (0x00000000)
io_rw_32 sbpi_wdata[4];
// (Description copied from array index 0 register OTP_SBPI_RDATA_0 applies similarly to other array indexes)
_REG_(OTP_SBPI_RDATA_0_OFFSET) // OTP_SBPI_RDATA_0
// Read payload bytes 3
// 0xffffffff [31:0] SBPI_RDATA_0 (0x00000000)
io_ro_32 sbpi_rdata[4];
_REG_(OTP_SBPI_STATUS_OFFSET) // OTP_SBPI_STATUS
// 0x00ff0000 [23:16] MISO (-) SBPI MISO (master in - slave out): response from SBPI
// 0x00001000 [12] FLAG (-) SBPI flag
// 0x00000100 [8] INSTR_MISS (0) Last instruction missed (dropped), as the previous has...
// 0x00000010 [4] INSTR_DONE (0) Last instruction done
// 0x00000001 [0] RDATA_VLD (0) Read command has returned data
io_rw_32 sbpi_status;
_REG_(OTP_USR_OFFSET) // OTP_USR
// Controls for APB data read interface (USER interface)
// 0x00000010 [4] PD (0) Power-down; 1 disables current reference
// 0x00000001 [0] DCTRL (1) 1 enables USER interface; 0 disables USER interface...
io_rw_32 usr;
_REG_(OTP_DBG_OFFSET) // OTP_DBG
// Debug for OTP power-on state machine
// 0x00001000 [12] CUSTOMER_RMA_FLAG (-) The chip is in RMA mode
// 0x000000f0 [7:4] PSM_STATE (-) Monitor the PSM FSM's state
// 0x00000008 [3] ROSC_UP (-) Ring oscillator is up and running
// 0x00000004 [2] ROSC_UP_SEEN (0) Ring oscillator was seen up and running
// 0x00000002 [1] BOOT_DONE (-) PSM boot done status flag
// 0x00000001 [0] PSM_DONE (-) PSM done status flag
io_rw_32 dbg;
uint32_t _pad0;
_REG_(OTP_BIST_OFFSET) // OTP_BIST
// During BIST, count address locations that have at least one leaky bit
// 0x40000000 [30] CNT_FAIL (-) Flag if the count of address locations with at least one...
// 0x20000000 [29] CNT_CLR (0) Clear counter before use
// 0x10000000 [28] CNT_ENA (0) Enable the counter before the BIST function is initiated
// 0x0fff0000 [27:16] CNT_MAX (0xfff) The cnt_fail flag will be set if the number of leaky...
// 0x00001fff [12:0] CNT (-) Number of locations that have at least one leaky bit
io_rw_32 bist;
// (Description copied from array index 0 register OTP_CRT_KEY_W0 applies similarly to other array indexes)
_REG_(OTP_CRT_KEY_W0_OFFSET) // OTP_CRT_KEY_W0
// Word 0 (bits 31
// 0xffffffff [31:0] CRT_KEY_W0 (0x00000000)
io_wo_32 crt_key_w[4];
_REG_(OTP_CRITICAL_OFFSET) // OTP_CRITICAL
// Quickly check values of critical flags read during boot up
// 0x00020000 [17] RISCV_DISABLE (0)
// 0x00010000 [16] ARM_DISABLE (0)
// 0x00000060 [6:5] GLITCH_DETECTOR_SENS (0x0)
// 0x00000010 [4] GLITCH_DETECTOR_ENABLE (0)
// 0x00000008 [3] DEFAULT_ARCHSEL (0)
// 0x00000004 [2] DEBUG_DISABLE (0)
// 0x00000002 [1] SECURE_DEBUG_DISABLE (0)
// 0x00000001 [0] SECURE_BOOT_ENABLE (0)
io_ro_32 critical;
_REG_(OTP_KEY_VALID_OFFSET) // OTP_KEY_VALID
// Which keys were valid (enrolled) at boot time
// 0x000000ff [7:0] KEY_VALID (0x00)
io_ro_32 key_valid;
_REG_(OTP_DEBUGEN_OFFSET) // OTP_DEBUGEN
// Enable a debug feature that has been disabled. Debug features are disabled if one of the relevant critical boot flags is set in OTP (DEBUG_DISABLE or SECURE_DEBUG_DISABLE), OR if a debug key is marked valid in OTP, and the matching key value has not been supplied over SWD.
// 0x00000100 [8] MISC (0) Enable other debug components
// 0x00000008 [3] PROC1_SECURE (0) Permit core 1's Mem-AP to generate Secure accesses,...
// 0x00000004 [2] PROC1 (0) Enable core 1's Mem-AP if it is currently disabled
// 0x00000002 [1] PROC0_SECURE (0) Permit core 0's Mem-AP to generate Secure accesses,...
// 0x00000001 [0] PROC0 (0) Enable core 0's Mem-AP if it is currently disabled
io_rw_32 debugen;
_REG_(OTP_DEBUGEN_LOCK_OFFSET) // OTP_DEBUGEN_LOCK
// Write 1s to lock corresponding bits in DEBUGEN
// 0x00000100 [8] MISC (0) Write 1 to lock the MISC bit of DEBUGEN
// 0x00000008 [3] PROC1_SECURE (0) Write 1 to lock the PROC1_SECURE bit of DEBUGEN
// 0x00000004 [2] PROC1 (0) Write 1 to lock the PROC1 bit of DEBUGEN
// 0x00000002 [1] PROC0_SECURE (0) Write 1 to lock the PROC0_SECURE bit of DEBUGEN
// 0x00000001 [0] PROC0 (0) Write 1 to lock the PROC0 bit of DEBUGEN
io_rw_32 debugen_lock;
_REG_(OTP_ARCHSEL_OFFSET) // OTP_ARCHSEL
// Architecture select (Arm/RISC-V), applied on next processor reset. The default and allowable values of this register are constrained by the critical boot flags.
// 0x00000002 [1] CORE1 (0) Select architecture for core 1
// 0x00000001 [0] CORE0 (0) Select architecture for core 0
io_rw_32 archsel;
_REG_(OTP_ARCHSEL_STATUS_OFFSET) // OTP_ARCHSEL_STATUS
// Get the current architecture select state of each core
// 0x00000002 [1] CORE1 (0) Current architecture for core 0
// 0x00000001 [0] CORE0 (0) Current architecture for core 0
io_ro_32 archsel_status;
_REG_(OTP_BOOTDIS_OFFSET) // OTP_BOOTDIS
// Tell the bootrom to ignore scratch register boot vectors (both power manager and watchdog) on the next power up.
// 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents
// 0x00000001 [0] NOW (0) When the core is powered down, the current value of...
io_rw_32 bootdis;
_REG_(OTP_INTR_OFFSET) // OTP_INTR
// Raw Interrupts
// 0x00000010 [4] APB_RD_NSEC_FAIL (0)
// 0x00000008 [3] APB_RD_SEC_FAIL (0)
// 0x00000004 [2] APB_DCTRL_FAIL (0)
// 0x00000002 [1] SBPI_WR_FAIL (0)
// 0x00000001 [0] SBPI_FLAG_N (0)
io_rw_32 intr;
_REG_(OTP_INTE_OFFSET) // OTP_INTE
// Interrupt Enable
// 0x00000010 [4] APB_RD_NSEC_FAIL (0)
// 0x00000008 [3] APB_RD_SEC_FAIL (0)
// 0x00000004 [2] APB_DCTRL_FAIL (0)
// 0x00000002 [1] SBPI_WR_FAIL (0)
// 0x00000001 [0] SBPI_FLAG_N (0)
io_rw_32 inte;
_REG_(OTP_INTF_OFFSET) // OTP_INTF
// Interrupt Force
// 0x00000010 [4] APB_RD_NSEC_FAIL (0)
// 0x00000008 [3] APB_RD_SEC_FAIL (0)
// 0x00000004 [2] APB_DCTRL_FAIL (0)
// 0x00000002 [1] SBPI_WR_FAIL (0)
// 0x00000001 [0] SBPI_FLAG_N (0)
io_rw_32 intf;
_REG_(OTP_INTS_OFFSET) // OTP_INTS
// Interrupt status after masking & forcing
// 0x00000010 [4] APB_RD_NSEC_FAIL (0)
// 0x00000008 [3] APB_RD_SEC_FAIL (0)
// 0x00000004 [2] APB_DCTRL_FAIL (0)
// 0x00000002 [1] SBPI_WR_FAIL (0)
// 0x00000001 [0] SBPI_FLAG_N (0)
io_ro_32 ints;
} otp_hw_t;
#define otp_hw ((otp_hw_t *)OTP_BASE)
static_assert(sizeof (otp_hw_t) == 0x0174, "");
#endif // _HARDWARE_STRUCTS_OTP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H
#define _HARDWARE_STRUCTS_PADS_BANK0_H
/**
* \file rp2350/pads_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
// 0x00000100 [8] ISO (1) Pad isolation control
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (0) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[48];
} pads_bank0_hw_t;
#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE)
static_assert(sizeof (pads_bank0_hw_t) == 0x00c4, "");
#endif // _HARDWARE_STRUCTS_PADS_BANK0_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
#define _HARDWARE_STRUCTS_PADS_QSPI_H
/**
* \file rp2350/pads_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pads_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
// 0x00000100 [8] ISO (1) Pad isolation control
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (1) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[6];
} pads_qspi_hw_t;
#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE)
static_assert(sizeof (pads_qspi_hw_t) == 0x001c, "");
#endif // _HARDWARE_STRUCTS_PADS_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/pads_bank0.h"
#define padsbank0_hw pads_bank0_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PIO_H
#define _HARDWARE_STRUCTS_PIO_H
/**
* \file rp2350/pio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
// Clock divisor register for state machine 0 +
// 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256)
// 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor
io_rw_32 clkdiv;
_REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
// Execution/behavioural settings for state machine 0
// 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...
// 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is...
// 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,...
// 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN
// 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable
// 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +
// 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins
// 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom
// 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address
// 0x00000060 [6:5] STATUS_SEL (0x0) Comparison used for the MOV x, STATUS instruction
// 0x0000001f [4:0] STATUS_N (0x00) Comparison level or IRQ index for the MOV x, STATUS instruction
io_rw_32 execctrl;
_REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
// Control behaviour of the input/output shift registers for state machine 0
// 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and...
// 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and...
// 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or...
// 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or...
// 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right
// 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left)
// 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i
// 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i
// 0x00008000 [15] FJOIN_RX_PUT (0) If 1, disable this state machine's RX FIFO, make its...
// 0x00004000 [14] FJOIN_RX_GET (0) If 1, disable this state machine's RX FIFO, make its...
// 0x0000001f [4:0] IN_COUNT (0x00) Set the number of pins which are not masked to 0 when...
io_rw_32 shiftctrl;
_REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
// Current instruction address of state machine 0
// 0x0000001f [4:0] SM0_ADDR (0x00)
io_ro_32 addr;
_REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
// Read to see the instruction currently addressed by state machine 0's program counter +
// 0x0000ffff [15:0] SM0_INSTR (-)
io_rw_32 instr;
_REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
// State machine pin control
// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...
// 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET
// 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...
// 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of...
// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...
// 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET...
// 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT...
io_rw_32 pinctrl;
} pio_sm_hw_t;
typedef struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00008000 [15] SM7 (0)
// 0x00004000 [14] SM6 (0)
// 0x00002000 [13] SM5 (0)
// 0x00001000 [12] SM4 (0)
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00008000 [15] SM7 (0)
// 0x00004000 [14] SM6 (0)
// 0x00002000 [13] SM5 (0)
// 0x00001000 [12] SM4 (0)
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00008000 [15] SM7 (0)
// 0x00004000 [14] SM6 (0)
// 0x00002000 [13] SM5 (0)
// 0x00001000 [12] SM4 (0)
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints;
} pio_irq_ctrl_hw_t;
typedef struct {
_REG_(PIO_CTRL_OFFSET) // PIO_CTRL
// PIO control register
// 0x04000000 [26] NEXTPREV_CLKDIV_RESTART (0) Write 1 to restart the clock dividers of state machines...
// 0x02000000 [25] NEXTPREV_SM_DISABLE (0) Write 1 to disable state machines in neighbouring PIO...
// 0x01000000 [24] NEXTPREV_SM_ENABLE (0) Write 1 to enable state machines in neighbouring PIO...
// 0x00f00000 [23:20] NEXT_PIO_MASK (0x0) A mask of state machines in the neighbouring...
// 0x000f0000 [19:16] PREV_PIO_MASK (0x0) A mask of state machines in the neighbouring...
// 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial...
// 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may...
// 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by...
io_rw_32 ctrl;
_REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
// FIFO status register
// 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty
// 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full
// 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty
// 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full
io_ro_32 fstat;
_REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
// FIFO debug register
// 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a...
// 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i
// 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i
// 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a...
io_rw_32 fdebug;
_REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
// FIFO levels
// 0xf0000000 [31:28] RX3 (0x0)
// 0x0f000000 [27:24] TX3 (0x0)
// 0x00f00000 [23:20] RX2 (0x0)
// 0x000f0000 [19:16] TX2 (0x0)
// 0x0000f000 [15:12] RX1 (0x0)
// 0x00000f00 [11:8] TX1 (0x0)
// 0x000000f0 [7:4] RX0 (0x0)
// 0x0000000f [3:0] TX0 (0x0)
io_ro_32 flevel;
// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
_REG_(PIO_TXF0_OFFSET) // PIO_TXF0
// Direct write access to the TX FIFO for this state machine
// 0xffffffff [31:0] TXF0 (0x00000000)
io_wo_32 txf[4];
// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
_REG_(PIO_RXF0_OFFSET) // PIO_RXF0
// Direct read access to the RX FIFO for this state machine
// 0xffffffff [31:0] RXF0 (-)
io_ro_32 rxf[4];
_REG_(PIO_IRQ_OFFSET) // PIO_IRQ
// State machine IRQ flags register
// 0x000000ff [7:0] IRQ (0x00)
io_rw_32 irq;
_REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
// 0x000000ff [7:0] IRQ_FORCE (0x00)
io_wo_32 irq_force;
_REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
// 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000)
io_rw_32 input_sync_bypass;
_REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
// Read to sample the pad output values PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOUT (0x00000000)
io_ro_32 dbg_padout;
_REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOE (0x00000000)
io_ro_32 dbg_padoe;
_REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
// The PIO hardware has some free parameters that may vary between chip products
// 0xf0000000 [31:28] VERSION (0x1) Version of the core PIO hardware
// 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of...
// 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with
// 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words
io_ro_32 dbg_cfginfo;
// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
_REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
// Write-only access to instruction memory location 0
// 0x0000ffff [15:0] INSTR_MEM0 (0x0000)
io_wo_32 instr_mem[32];
pio_sm_hw_t sm[4];
// (Description copied from array index 0 register PIO_RXF0_PUTGET0 applies similarly to other array indexes)
_REG_(PIO_RXF0_PUTGET0_OFFSET) // PIO_RXF0_PUTGET0
// Direct read/write access to the RX FIFO on all SMs, if SHIFTCTRL_FJOIN_RX_PUT xor SHIFTCTRL_FJOIN_RX_GET is set
// 0xffffffff [31:0] RXF0_PUTGET0 (0x00000000)
io_rw_32 rxf_putget[4][4];
_REG_(PIO_GPIOBASE_OFFSET) // PIO_GPIOBASE
// Relocate GPIO 0 (from PIO's point of view) in the system GPIO numbering, to access more than 32...
// 0x00000010 [4] GPIOBASE (0)
io_rw_32 gpiobase;
_REG_(PIO_INTR_OFFSET) // PIO_INTR
// Raw Interrupts
// 0x00008000 [15] SM7 (0)
// 0x00004000 [14] SM6 (0)
// 0x00002000 [13] SM5 (0)
// 0x00001000 [12] SM4 (0)
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 intr;
union {
struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte0;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf0;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints0;
_REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
// Interrupt Enable for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte1;
_REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
// Interrupt Force for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf1;
_REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
// Interrupt status after masking & forcing for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints1;
};
pio_irq_ctrl_hw_t irq_ctrl[2];
};
} pio_hw_t;
#define pio0_hw ((pio_hw_t *)PIO0_BASE)
#define pio1_hw ((pio_hw_t *)PIO1_BASE)
#define pio2_hw ((pio_hw_t *)PIO2_BASE)
static_assert(sizeof (pio_hw_t) == 0x0188, "");
#endif // _HARDWARE_STRUCTS_PIO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PLL_H
#define _HARDWARE_STRUCTS_PLL_H
/**
* \file rp2350/pll.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pll.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pll
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/// \tag::pll_hw[]
typedef struct {
_REG_(PLL_CS_OFFSET) // PLL_CS
// Control and Status
// 0x80000000 [31] LOCK (0) PLL is locked
// 0x40000000 [30] LOCK_N (0) PLL is not locked +
// 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the...
// 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock
io_rw_32 cs;
_REG_(PLL_PWR_OFFSET) // PLL_PWR
// Controls the PLL power modes
// 0x00000020 [5] VCOPD (1) PLL VCO powerdown +
// 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown +
// 0x00000004 [2] DSMPD (1) PLL DSM powerdown +
// 0x00000001 [0] PD (1) PLL powerdown +
io_rw_32 pwr;
_REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
// Feedback divisor
// 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints
io_rw_32 fbdiv_int;
_REG_(PLL_PRIM_OFFSET) // PLL_PRIM
// Controls the PLL post dividers for the primary output
// 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7
// 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7
io_rw_32 prim;
_REG_(PLL_INTR_OFFSET) // PLL_INTR
// Raw Interrupts
// 0x00000001 [0] LOCK_N_STICKY (0)
io_rw_32 intr;
_REG_(PLL_INTE_OFFSET) // PLL_INTE
// Interrupt Enable
// 0x00000001 [0] LOCK_N_STICKY (0)
io_rw_32 inte;
_REG_(PLL_INTF_OFFSET) // PLL_INTF
// Interrupt Force
// 0x00000001 [0] LOCK_N_STICKY (0)
io_rw_32 intf;
_REG_(PLL_INTS_OFFSET) // PLL_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] LOCK_N_STICKY (0)
io_ro_32 ints;
} pll_hw_t;
/// \end::pll_hw[]
#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE)
#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE)
static_assert(sizeof (pll_hw_t) == 0x0020, "");
#endif // _HARDWARE_STRUCTS_PLL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_POWMAN_H
#define _HARDWARE_STRUCTS_POWMAN_H
/**
* \file rp2350/powman.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/powman.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_powman
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/powman.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(POWMAN_BADPASSWD_OFFSET) // POWMAN_BADPASSWD
// Indicates a bad password has been used
// 0x00000001 [0] BADPASSWD (0)
io_rw_32 badpasswd;
_REG_(POWMAN_VREG_CTRL_OFFSET) // POWMAN_VREG_CTRL
// Voltage Regulator Control
// 0x00008000 [15] RST_N (1) returns the regulator to its startup settings +
// 0x00002000 [13] UNLOCK (0) unlocks the VREG control interface after power up +
// 0x00001000 [12] ISOLATE (0) isolates the VREG control interface +
// 0x00000100 [8] DISABLE_VOLTAGE_LIMIT (0) 0=not disabled, 1=enabled
// 0x00000070 [6:4] HT_TH (0x5) high temperature protection threshold +
io_rw_32 vreg_ctrl;
_REG_(POWMAN_VREG_STS_OFFSET) // POWMAN_VREG_STS
// Voltage Regulator Status
// 0x00000010 [4] VOUT_OK (0) output regulation status +
// 0x00000001 [0] STARTUP (0) startup status +
io_ro_32 vreg_sts;
_REG_(POWMAN_VREG_OFFSET) // POWMAN_VREG
// Voltage Regulator Settings
// 0x00008000 [15] UPDATE_IN_PROGRESS (0) regulator state is being updated +
// 0x000001f0 [8:4] VSEL (0x0b) output voltage select +
// 0x00000002 [1] HIZ (0) high impedance mode select +
io_rw_32 vreg;
_REG_(POWMAN_VREG_LP_ENTRY_OFFSET) // POWMAN_VREG_LP_ENTRY
// Voltage Regulator Low Power Entry Settings
// 0x000001f0 [8:4] VSEL (0x0b) output voltage select +
// 0x00000004 [2] MODE (1) selects either normal (switching) mode or low power...
// 0x00000002 [1] HIZ (0) high impedance mode select +
io_rw_32 vreg_lp_entry;
_REG_(POWMAN_VREG_LP_EXIT_OFFSET) // POWMAN_VREG_LP_EXIT
// Voltage Regulator Low Power Exit Settings
// 0x000001f0 [8:4] VSEL (0x0b) output voltage select +
// 0x00000004 [2] MODE (0) selects either normal (switching) mode or low power...
// 0x00000002 [1] HIZ (0) high impedance mode select +
io_rw_32 vreg_lp_exit;
_REG_(POWMAN_BOD_CTRL_OFFSET) // POWMAN_BOD_CTRL
// Brown-out Detection Control
// 0x00001000 [12] ISOLATE (0) isolates the brown-out detection control interface +
io_rw_32 bod_ctrl;
_REG_(POWMAN_BOD_OFFSET) // POWMAN_BOD
// Brown-out Detection Settings
// 0x000001f0 [8:4] VSEL (0x0b) threshold select +
// 0x00000001 [0] EN (1) enable brown-out detection +
io_rw_32 bod;
_REG_(POWMAN_BOD_LP_ENTRY_OFFSET) // POWMAN_BOD_LP_ENTRY
// Brown-out Detection Low Power Entry Settings
// 0x000001f0 [8:4] VSEL (0x0b) threshold select +
// 0x00000001 [0] EN (0) enable brown-out detection +
io_rw_32 bod_lp_entry;
_REG_(POWMAN_BOD_LP_EXIT_OFFSET) // POWMAN_BOD_LP_EXIT
// Brown-out Detection Low Power Exit Settings
// 0x000001f0 [8:4] VSEL (0x0b) threshold select +
// 0x00000001 [0] EN (1) enable brown-out detection +
io_rw_32 bod_lp_exit;
_REG_(POWMAN_LPOSC_OFFSET) // POWMAN_LPOSC
// Low power oscillator control register
// 0x000003f0 [9:4] TRIM (0x20) Frequency trim - the trim step is typically 1% of the...
// 0x00000003 [1:0] MODE (0x3) This feature has been removed
io_rw_32 lposc;
_REG_(POWMAN_CHIP_RESET_OFFSET) // POWMAN_CHIP_RESET
// Chip reset control and status
// 0x10000000 [28] HAD_WATCHDOG_RESET_RSM (0) Last reset was a watchdog timeout which was configured...
// 0x08000000 [27] HAD_HZD_SYS_RESET_REQ (0) Last reset was a system reset from the hazard debugger +
// 0x04000000 [26] HAD_GLITCH_DETECT (0) Last reset was due to a power supply glitch +
// 0x02000000 [25] HAD_SWCORE_PD (0) Last reset was a switched core powerdown +
// 0x01000000 [24] HAD_WATCHDOG_RESET_SWCORE (0) Last reset was a watchdog timeout which was configured...
// 0x00800000 [23] HAD_WATCHDOG_RESET_POWMAN (0) Last reset was a watchdog timeout which was configured...
// 0x00400000 [22] HAD_WATCHDOG_RESET_POWMAN_ASYNC (0) Last reset was a watchdog timeout which was configured...
// 0x00200000 [21] HAD_RESCUE (0) Last reset was a rescue reset from the debugger +
// 0x00080000 [19] HAD_DP_RESET_REQ (0) Last reset was an reset request from the arm debugger +
// 0x00040000 [18] HAD_RUN_LOW (0) Last reset was from the RUN pin +
// 0x00020000 [17] HAD_BOR (0) Last reset was from the brown-out detection block +
// 0x00010000 [16] HAD_POR (0) Last reset was from the power-on reset +
// 0x00000010 [4] RESCUE_FLAG (0) This is set by a rescue reset from the RP-AP
// 0x00000001 [0] DOUBLE_TAP (0) This flag is set by double-tapping RUN
io_rw_32 chip_reset;
_REG_(POWMAN_WDSEL_OFFSET) // POWMAN_WDSEL
// Allows a watchdog reset to reset the internal state of powman in addition to the power-on state...
// 0x00001000 [12] RESET_RSM (0) If set to 1, a watchdog reset will run the full power-on...
// 0x00000100 [8] RESET_SWCORE (0) If set to 1, a watchdog reset will reset the switched...
// 0x00000010 [4] RESET_POWMAN (0) If set to 1, a watchdog reset will restore powman...
// 0x00000001 [0] RESET_POWMAN_ASYNC (0) If set to 1, a watchdog reset will restore powman...
io_rw_32 wdsel;
_REG_(POWMAN_SEQ_CFG_OFFSET) // POWMAN_SEQ_CFG
// For configuration of the power sequencer +
// 0x00100000 [20] USING_FAST_POWCK (1) 0 indicates the POWMAN clock is running from the low...
// 0x00020000 [17] USING_BOD_LP (0) Indicates the brown-out detector (BOD) mode +
// 0x00010000 [16] USING_VREG_LP (0) Indicates the voltage regulator (VREG) mode +
// 0x00001000 [12] USE_FAST_POWCK (1) selects the reference clock (clk_ref) as the source of...
// 0x00000100 [8] RUN_LPOSC_IN_LP (1) Set to 0 to stop the low power osc when the...
// 0x00000080 [7] USE_BOD_HP (1) Set to 0 to prevent automatic switching to bod high...
// 0x00000040 [6] USE_BOD_LP (1) Set to 0 to prevent automatic switching to bod low power...
// 0x00000020 [5] USE_VREG_HP (1) Set to 0 to prevent automatic switching to vreg high...
// 0x00000010 [4] USE_VREG_LP (1) Set to 0 to prevent automatic switching to vreg low...
// 0x00000002 [1] HW_PWRUP_SRAM0 (0) Specifies the power state of SRAM0 when powering up...
// 0x00000001 [0] HW_PWRUP_SRAM1 (0) Specifies the power state of SRAM1 when powering up...
io_rw_32 seq_cfg;
_REG_(POWMAN_STATE_OFFSET) // POWMAN_STATE
// This register controls the power state of the 4 power domains
// 0x00002000 [13] CHANGING (0)
// 0x00001000 [12] WAITING (0)
// 0x00000800 [11] BAD_HW_REQ (0) Bad hardware initiated state request
// 0x00000400 [10] BAD_SW_REQ (0) Bad software initiated state request
// 0x00000200 [9] PWRUP_WHILE_WAITING (0) Request ignored because of a pending pwrup request
// 0x00000100 [8] REQ_IGNORED (0)
// 0x000000f0 [7:4] REQ (0x0)
// 0x0000000f [3:0] CURRENT (0xf)
io_rw_32 state;
_REG_(POWMAN_POW_FASTDIV_OFFSET) // POWMAN_POW_FASTDIV
// 0x000007ff [10:0] POW_FASTDIV (0x040) divides the POWMAN clock to provide a tick for the delay...
io_rw_32 pow_fastdiv;
_REG_(POWMAN_POW_DELAY_OFFSET) // POWMAN_POW_DELAY
// power state machine delays
// 0x0000ff00 [15:8] SRAM_STEP (0x20) timing between the sram0 and sram1 power state machine steps +
// 0x000000f0 [7:4] XIP_STEP (0x1) timing between the xip power state machine steps +
// 0x0000000f [3:0] SWCORE_STEP (0x1) timing between the swcore power state machine steps +
io_rw_32 pow_delay;
// (Description copied from array index 0 register POWMAN_EXT_CTRL0 applies similarly to other array indexes)
_REG_(POWMAN_EXT_CTRL0_OFFSET) // POWMAN_EXT_CTRL0
// Configures a gpio as a power mode aware control output
// 0x00004000 [14] LP_EXIT_STATE (0) output level when exiting the low power state
// 0x00002000 [13] LP_ENTRY_STATE (0) output level when entering the low power state
// 0x00001000 [12] INIT_STATE (0)
// 0x00000100 [8] INIT (0)
// 0x0000003f [5:0] GPIO_SELECT (0x3f) selects from gpio 0->30 +
io_rw_32 ext_ctrl[2];
_REG_(POWMAN_EXT_TIME_REF_OFFSET) // POWMAN_EXT_TIME_REF
// Select a GPIO to use as a time reference, the source can be used to drive the low power clock at...
// 0x00000010 [4] DRIVE_LPCK (0) Use the selected GPIO to drive the 32kHz low power...
// 0x00000003 [1:0] SOURCE_SEL (0x0) 0 -> gpio12 +
io_rw_32 ext_time_ref;
_REG_(POWMAN_LPOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_INT
// Informs the AON Timer of the integer component of the clock frequency when running off the LPOSC
// 0x0000003f [5:0] LPOSC_FREQ_KHZ_INT (0x20) Integer component of the LPOSC or GPIO clock source...
io_rw_32 lposc_freq_khz_int;
_REG_(POWMAN_LPOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_LPOSC_FREQ_KHZ_FRAC
// Informs the AON Timer of the fractional component of the clock frequency when running off the LPOSC
// 0x0000ffff [15:0] LPOSC_FREQ_KHZ_FRAC (0xc49c) Fractional component of the LPOSC or GPIO clock source...
io_rw_32 lposc_freq_khz_frac;
_REG_(POWMAN_XOSC_FREQ_KHZ_INT_OFFSET) // POWMAN_XOSC_FREQ_KHZ_INT
// Informs the AON Timer of the integer component of the clock frequency when running off the XOSC
// 0x0000ffff [15:0] XOSC_FREQ_KHZ_INT (0x2ee0) Integer component of the XOSC frequency in kHz
io_rw_32 xosc_freq_khz_int;
_REG_(POWMAN_XOSC_FREQ_KHZ_FRAC_OFFSET) // POWMAN_XOSC_FREQ_KHZ_FRAC
// Informs the AON Timer of the fractional component of the clock frequency when running off the XOSC
// 0x0000ffff [15:0] XOSC_FREQ_KHZ_FRAC (0x0000) Fractional component of the XOSC frequency in kHz
io_rw_32 xosc_freq_khz_frac;
_REG_(POWMAN_SET_TIME_63TO48_OFFSET) // POWMAN_SET_TIME_63TO48
// 0x0000ffff [15:0] SET_TIME_63TO48 (0x0000) For setting the time, do not use for reading the time,...
io_rw_32 set_time_63to48;
_REG_(POWMAN_SET_TIME_47TO32_OFFSET) // POWMAN_SET_TIME_47TO32
// 0x0000ffff [15:0] SET_TIME_47TO32 (0x0000) For setting the time, do not use for reading the time,...
io_rw_32 set_time_47to32;
_REG_(POWMAN_SET_TIME_31TO16_OFFSET) // POWMAN_SET_TIME_31TO16
// 0x0000ffff [15:0] SET_TIME_31TO16 (0x0000) For setting the time, do not use for reading the time,...
io_rw_32 set_time_31to16;
_REG_(POWMAN_SET_TIME_15TO0_OFFSET) // POWMAN_SET_TIME_15TO0
// 0x0000ffff [15:0] SET_TIME_15TO0 (0x0000) For setting the time, do not use for reading the time,...
io_rw_32 set_time_15to0;
_REG_(POWMAN_READ_TIME_UPPER_OFFSET) // POWMAN_READ_TIME_UPPER
// 0xffffffff [31:0] READ_TIME_UPPER (0x00000000) For reading bits 63:32 of the timer
io_ro_32 read_time_upper;
_REG_(POWMAN_READ_TIME_LOWER_OFFSET) // POWMAN_READ_TIME_LOWER
// 0xffffffff [31:0] READ_TIME_LOWER (0x00000000) For reading bits 31:0 of the timer
io_ro_32 read_time_lower;
_REG_(POWMAN_ALARM_TIME_63TO48_OFFSET) // POWMAN_ALARM_TIME_63TO48
// 0x0000ffff [15:0] ALARM_TIME_63TO48 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0
io_rw_32 alarm_time_63to48;
_REG_(POWMAN_ALARM_TIME_47TO32_OFFSET) // POWMAN_ALARM_TIME_47TO32
// 0x0000ffff [15:0] ALARM_TIME_47TO32 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0
io_rw_32 alarm_time_47to32;
_REG_(POWMAN_ALARM_TIME_31TO16_OFFSET) // POWMAN_ALARM_TIME_31TO16
// 0x0000ffff [15:0] ALARM_TIME_31TO16 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0
io_rw_32 alarm_time_31to16;
_REG_(POWMAN_ALARM_TIME_15TO0_OFFSET) // POWMAN_ALARM_TIME_15TO0
// 0x0000ffff [15:0] ALARM_TIME_15TO0 (0x0000) This field must only be written when POWMAN_ALARM_ENAB=0
io_rw_32 alarm_time_15to0;
_REG_(POWMAN_TIMER_OFFSET) // POWMAN_TIMER
// 0x00080000 [19] USING_GPIO_1HZ (0) Timer is synchronised to a 1hz gpio source
// 0x00040000 [18] USING_GPIO_1KHZ (0) Timer is running from a 1khz gpio source
// 0x00020000 [17] USING_LPOSC (0) Timer is running from lposc
// 0x00010000 [16] USING_XOSC (0) Timer is running from xosc
// 0x00002000 [13] USE_GPIO_1HZ (0) Selects the gpio source as the reference for the sec counter
// 0x00000400 [10] USE_GPIO_1KHZ (0) switch to gpio as the source of the 1kHz timer tick
// 0x00000200 [9] USE_XOSC (0) switch to xosc as the source of the 1kHz timer tick
// 0x00000100 [8] USE_LPOSC (0) Switch to lposc as the source of the 1kHz timer tick
// 0x00000040 [6] ALARM (0) Alarm has fired
// 0x00000020 [5] PWRUP_ON_ALARM (0) Alarm wakes the chip from low power mode
// 0x00000010 [4] ALARM_ENAB (0) Enables the alarm
// 0x00000004 [2] CLEAR (0) Clears the timer, does not disable the timer and does...
// 0x00000002 [1] RUN (0) Timer enable
// 0x00000001 [0] NONSEC_WRITE (0) Control whether Non-secure software can write to the...
io_rw_32 timer;
// (Description copied from array index 0 register POWMAN_PWRUP0 applies similarly to other array indexes)
_REG_(POWMAN_PWRUP0_OFFSET) // POWMAN_PWRUP0
// 4 GPIO powerup events can be configured to wake the chip up from a low power state
// 0x00000400 [10] RAW_STATUS (0) Value of selected gpio pin (only if enable == 1)
// 0x00000200 [9] STATUS (0) Status of gpio wakeup
// 0x00000100 [8] MODE (0) Edge or level detect
// 0x00000080 [7] DIRECTION (0)
// 0x00000040 [6] ENABLE (0) Set to 1 to enable the wakeup source
// 0x0000003f [5:0] SOURCE (0x3f)
io_rw_32 pwrup[4];
_REG_(POWMAN_CURRENT_PWRUP_REQ_OFFSET) // POWMAN_CURRENT_PWRUP_REQ
// Indicates current powerup request state +
// 0x0000007f [6:0] CURRENT_PWRUP_REQ (0x00)
io_ro_32 current_pwrup_req;
_REG_(POWMAN_LAST_SWCORE_PWRUP_OFFSET) // POWMAN_LAST_SWCORE_PWRUP
// Indicates which pwrup source triggered the last switched-core power up +
// 0x0000007f [6:0] LAST_SWCORE_PWRUP (0x00)
io_ro_32 last_swcore_pwrup;
_REG_(POWMAN_DBG_PWRCFG_OFFSET) // POWMAN_DBG_PWRCFG
// 0x00000001 [0] IGNORE (0) Ignore pwrup req from debugger
io_rw_32 dbg_pwrcfg;
_REG_(POWMAN_BOOTDIS_OFFSET) // POWMAN_BOOTDIS
// Tell the bootrom to ignore the BOOT0
// 0x00000002 [1] NEXT (0) This flag always ORs writes into its current contents
// 0x00000001 [0] NOW (0) When powman resets the RSM, the current value of...
io_rw_32 bootdis;
_REG_(POWMAN_DBGCONFIG_OFFSET) // POWMAN_DBGCONFIG
// 0x0000000f [3:0] DP_INSTID (0x0) Configure DP instance ID for SWD multidrop selection
io_rw_32 dbgconfig;
// (Description copied from array index 0 register POWMAN_SCRATCH0 applies similarly to other array indexes)
_REG_(POWMAN_SCRATCH0_OFFSET) // POWMAN_SCRATCH0
// Scratch register
// 0xffffffff [31:0] SCRATCH0 (0x00000000)
io_rw_32 scratch[8];
// (Description copied from array index 0 register POWMAN_BOOT0 applies similarly to other array indexes)
_REG_(POWMAN_BOOT0_OFFSET) // POWMAN_BOOT0
// Scratch register
// 0xffffffff [31:0] BOOT0 (0x00000000)
io_rw_32 boot[4];
_REG_(POWMAN_INTR_OFFSET) // POWMAN_INTR
// Raw Interrupts
// 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state
// 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state
// 0x00000002 [1] TIMER (0)
// 0x00000001 [0] VREG_OUTPUT_LOW (0)
io_rw_32 intr;
_REG_(POWMAN_INTE_OFFSET) // POWMAN_INTE
// Interrupt Enable
// 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state
// 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state
// 0x00000002 [1] TIMER (0)
// 0x00000001 [0] VREG_OUTPUT_LOW (0)
io_rw_32 inte;
_REG_(POWMAN_INTF_OFFSET) // POWMAN_INTF
// Interrupt Force
// 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state
// 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state
// 0x00000002 [1] TIMER (0)
// 0x00000001 [0] VREG_OUTPUT_LOW (0)
io_rw_32 intf;
_REG_(POWMAN_INTS_OFFSET) // POWMAN_INTS
// Interrupt status after masking & forcing
// 0x00000008 [3] PWRUP_WHILE_WAITING (0) Source is state
// 0x00000004 [2] STATE_REQ_IGNORED (0) Source is state
// 0x00000002 [1] TIMER (0)
// 0x00000001 [0] VREG_OUTPUT_LOW (0)
io_ro_32 ints;
} powman_hw_t;
#define powman_hw ((powman_hw_t *)POWMAN_BASE)
static_assert(sizeof (powman_hw_t) == 0x00f0, "");
#endif // _HARDWARE_STRUCTS_POWMAN_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PSM_H
#define _HARDWARE_STRUCTS_PSM_H
/**
* \file rp2350/psm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/psm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_psm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
// Force block out of reset (i
// 0x01000000 [24] PROC1 (0)
// 0x00800000 [23] PROC0 (0)
// 0x00400000 [22] ACCESSCTRL (0)
// 0x00200000 [21] SIO (0)
// 0x00100000 [20] XIP (0)
// 0x00080000 [19] SRAM9 (0)
// 0x00040000 [18] SRAM8 (0)
// 0x00020000 [17] SRAM7 (0)
// 0x00010000 [16] SRAM6 (0)
// 0x00008000 [15] SRAM5 (0)
// 0x00004000 [14] SRAM4 (0)
// 0x00002000 [13] SRAM3 (0)
// 0x00001000 [12] SRAM2 (0)
// 0x00000800 [11] SRAM1 (0)
// 0x00000400 [10] SRAM0 (0)
// 0x00000200 [9] BOOTRAM (0)
// 0x00000100 [8] ROM (0)
// 0x00000080 [7] BUSFABRIC (0)
// 0x00000040 [6] PSM_READY (0)
// 0x00000020 [5] CLOCKS (0)
// 0x00000010 [4] RESETS (0)
// 0x00000008 [3] XOSC (0)
// 0x00000004 [2] ROSC (0)
// 0x00000002 [1] OTP (0)
// 0x00000001 [0] PROC_COLD (0)
io_rw_32 frce_on;
_REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
// Force into reset (i
// 0x01000000 [24] PROC1 (0)
// 0x00800000 [23] PROC0 (0)
// 0x00400000 [22] ACCESSCTRL (0)
// 0x00200000 [21] SIO (0)
// 0x00100000 [20] XIP (0)
// 0x00080000 [19] SRAM9 (0)
// 0x00040000 [18] SRAM8 (0)
// 0x00020000 [17] SRAM7 (0)
// 0x00010000 [16] SRAM6 (0)
// 0x00008000 [15] SRAM5 (0)
// 0x00004000 [14] SRAM4 (0)
// 0x00002000 [13] SRAM3 (0)
// 0x00001000 [12] SRAM2 (0)
// 0x00000800 [11] SRAM1 (0)
// 0x00000400 [10] SRAM0 (0)
// 0x00000200 [9] BOOTRAM (0)
// 0x00000100 [8] ROM (0)
// 0x00000080 [7] BUSFABRIC (0)
// 0x00000040 [6] PSM_READY (0)
// 0x00000020 [5] CLOCKS (0)
// 0x00000010 [4] RESETS (0)
// 0x00000008 [3] XOSC (0)
// 0x00000004 [2] ROSC (0)
// 0x00000002 [1] OTP (0)
// 0x00000001 [0] PROC_COLD (0)
io_rw_32 frce_off;
_REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
// Set to 1 if the watchdog should reset this
// 0x01000000 [24] PROC1 (0)
// 0x00800000 [23] PROC0 (0)
// 0x00400000 [22] ACCESSCTRL (0)
// 0x00200000 [21] SIO (0)
// 0x00100000 [20] XIP (0)
// 0x00080000 [19] SRAM9 (0)
// 0x00040000 [18] SRAM8 (0)
// 0x00020000 [17] SRAM7 (0)
// 0x00010000 [16] SRAM6 (0)
// 0x00008000 [15] SRAM5 (0)
// 0x00004000 [14] SRAM4 (0)
// 0x00002000 [13] SRAM3 (0)
// 0x00001000 [12] SRAM2 (0)
// 0x00000800 [11] SRAM1 (0)
// 0x00000400 [10] SRAM0 (0)
// 0x00000200 [9] BOOTRAM (0)
// 0x00000100 [8] ROM (0)
// 0x00000080 [7] BUSFABRIC (0)
// 0x00000040 [6] PSM_READY (0)
// 0x00000020 [5] CLOCKS (0)
// 0x00000010 [4] RESETS (0)
// 0x00000008 [3] XOSC (0)
// 0x00000004 [2] ROSC (0)
// 0x00000002 [1] OTP (0)
// 0x00000001 [0] PROC_COLD (0)
io_rw_32 wdsel;
_REG_(PSM_DONE_OFFSET) // PSM_DONE
// Is the subsystem ready?
// 0x01000000 [24] PROC1 (0)
// 0x00800000 [23] PROC0 (0)
// 0x00400000 [22] ACCESSCTRL (0)
// 0x00200000 [21] SIO (0)
// 0x00100000 [20] XIP (0)
// 0x00080000 [19] SRAM9 (0)
// 0x00040000 [18] SRAM8 (0)
// 0x00020000 [17] SRAM7 (0)
// 0x00010000 [16] SRAM6 (0)
// 0x00008000 [15] SRAM5 (0)
// 0x00004000 [14] SRAM4 (0)
// 0x00002000 [13] SRAM3 (0)
// 0x00001000 [12] SRAM2 (0)
// 0x00000800 [11] SRAM1 (0)
// 0x00000400 [10] SRAM0 (0)
// 0x00000200 [9] BOOTRAM (0)
// 0x00000100 [8] ROM (0)
// 0x00000080 [7] BUSFABRIC (0)
// 0x00000040 [6] PSM_READY (0)
// 0x00000020 [5] CLOCKS (0)
// 0x00000010 [4] RESETS (0)
// 0x00000008 [3] XOSC (0)
// 0x00000004 [2] ROSC (0)
// 0x00000002 [1] OTP (0)
// 0x00000001 [0] PROC_COLD (0)
io_ro_32 done;
} psm_hw_t;
#define psm_hw ((psm_hw_t *)PSM_BASE)
static_assert(sizeof (psm_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_PSM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PWM_H
#define _HARDWARE_STRUCTS_PWM_H
/**
* \file rp2350/pwm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pwm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_pwm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
// Control and status register
// 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
// 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
// 0x00000030 [5:4] DIVMODE (0x0)
// 0x00000008 [3] B_INV (0) Invert output B
// 0x00000004 [2] A_INV (0) Invert output A
// 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
// 0x00000001 [0] EN (0) Enable the PWM channel
io_rw_32 csr;
_REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
// INT and FRAC form a fixed-point fractional number
// 0x00000ff0 [11:4] INT (0x01)
// 0x0000000f [3:0] FRAC (0x0)
io_rw_32 div;
_REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
// Direct access to the PWM counter
// 0x0000ffff [15:0] CH0_CTR (0x0000)
io_rw_32 ctr;
_REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
// Counter compare values
// 0xffff0000 [31:16] B (0x0000)
// 0x0000ffff [15:0] A (0x0000)
io_rw_32 cc;
_REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
// Counter wrap value
// 0x0000ffff [15:0] CH0_TOP (0xffff)
io_rw_32 top;
} pwm_slice_hw_t;
typedef struct {
_REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_ro_32 ints;
} pwm_irq_ctrl_hw_t;
typedef struct {
pwm_slice_hw_t slice[12];
_REG_(PWM_EN_OFFSET) // PWM_EN
// This register aliases the CSR_EN bits for all channels
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 en;
_REG_(PWM_INTR_OFFSET) // PWM_INTR
// Raw Interrupts
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intr;
union {
struct {
_REG_(PWM_IRQ0_INTE_OFFSET) // PWM_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_IRQ0_INTF_OFFSET) // PWM_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_IRQ0_INTS_OFFSET) // PWM_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 ints;
_REG_(PWM_IRQ1_INTE_OFFSET) // PWM_IRQ1_INTE
// Interrupt Enable for irq1
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte1;
_REG_(PWM_IRQ1_INTF_OFFSET) // PWM_IRQ1_INTF
// Interrupt Force for irq1
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf1;
_REG_(PWM_IRQ1_INTS_OFFSET) // PWM_IRQ1_INTS
// Interrupt status after masking & forcing for irq1
// 0x00000800 [11] CH11 (0)
// 0x00000400 [10] CH10 (0)
// 0x00000200 [9] CH9 (0)
// 0x00000100 [8] CH8 (0)
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 ints1;
};
pwm_irq_ctrl_hw_t irq_ctrl[2];
};
} pwm_hw_t;
#define pwm_hw ((pwm_hw_t *)PWM_BASE)
static_assert(sizeof (pwm_hw_t) == 0x0110, "");
#endif // _HARDWARE_STRUCTS_PWM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_QMI_H
#define _HARDWARE_STRUCTS_QMI_H
/**
* \file rp2350/qmi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/qmi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_qmi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/qmi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(QMI_M0_TIMING_OFFSET) // QMI_M0_TIMING
// Timing configuration register for memory address window 0
// 0xc0000000 [31:30] COOLDOWN (0x1) Chip select cooldown period
// 0x30000000 [29:28] PAGEBREAK (0x0) When page break is enabled, chip select will...
// 0x02000000 [25] SELECT_SETUP (0) Add up to one additional system clock cycle of setup...
// 0x01800000 [24:23] SELECT_HOLD (0x0) Add up to three additional system clock cycles of active...
// 0x007e0000 [22:17] MAX_SELECT (0x00) Enforce a maximum assertion duration for this window's...
// 0x0001f000 [16:12] MIN_DESELECT (0x00) After this window's chip select is deasserted, it...
// 0x00000700 [10:8] RXDELAY (0x0) Delay the read data sample timing, in units of one half...
// 0x000000ff [7:0] CLKDIV (0x04) Clock divisor
io_rw_32 timing;
_REG_(QMI_M0_RFMT_OFFSET) // QMI_M0_RFMT
// Read transfer format configuration for memory address window 0.
// 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for read commands:...
// 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data...
// 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits
// 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits
// 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer
// 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any
// 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any
// 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address
// 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any
io_rw_32 rfmt;
_REG_(QMI_M0_RCMD_OFFSET) // QMI_M0_RCMD
// Command constants used for reads from memory address window 0.
// 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if...
// 0x000000ff [7:0] PREFIX (0x03) The command prefix bits to prepend on each new transfer,...
io_rw_32 rcmd;
_REG_(QMI_M0_WFMT_OFFSET) // QMI_M0_WFMT
// Write transfer format configuration for memory address window 0.
// 0x10000000 [28] DTR (0) Enable double transfer rate (DTR) for write commands:...
// 0x00070000 [18:16] DUMMY_LEN (0x0) Length of dummy phase between command suffix and data...
// 0x0000c000 [15:14] SUFFIX_LEN (0x0) Length of post-address command suffix, in units of 4 bits
// 0x00001000 [12] PREFIX_LEN (1) Length of command prefix, in units of 8 bits
// 0x00000300 [9:8] DATA_WIDTH (0x0) The width used for the data transfer
// 0x000000c0 [7:6] DUMMY_WIDTH (0x0) The width used for the dummy phase, if any
// 0x00000030 [5:4] SUFFIX_WIDTH (0x0) The width used for the post-address command suffix, if any
// 0x0000000c [3:2] ADDR_WIDTH (0x0) The transfer width used for the address
// 0x00000003 [1:0] PREFIX_WIDTH (0x0) The transfer width used for the command prefix, if any
io_rw_32 wfmt;
_REG_(QMI_M0_WCMD_OFFSET) // QMI_M0_WCMD
// Command constants used for writes to memory address window 0.
// 0x0000ff00 [15:8] SUFFIX (0xa0) The command suffix bits following the address, if...
// 0x000000ff [7:0] PREFIX (0x02) The command prefix bits to prepend on each new transfer,...
io_rw_32 wcmd;
} qmi_mem_hw_t;
typedef struct {
_REG_(QMI_DIRECT_CSR_OFFSET) // QMI_DIRECT_CSR
// Control and status for direct serial mode
// 0xc0000000 [31:30] RXDELAY (0x0) Delay the read data sample timing, in units of one half...
// 0x3fc00000 [29:22] CLKDIV (0x06) Clock divisor for direct serial mode
// 0x001c0000 [20:18] RXLEVEL (0x0) Current level of DIRECT_RX FIFO
// 0x00020000 [17] RXFULL (0) When 1, the DIRECT_RX FIFO is currently full
// 0x00010000 [16] RXEMPTY (0) When 1, the DIRECT_RX FIFO is currently empty
// 0x00007000 [14:12] TXLEVEL (0x0) Current level of DIRECT_TX FIFO
// 0x00000800 [11] TXEMPTY (0) When 1, the DIRECT_TX FIFO is currently empty
// 0x00000400 [10] TXFULL (0) When 1, the DIRECT_TX FIFO is currently full
// 0x00000080 [7] AUTO_CS1N (0) When 1, automatically assert the CS1n chip select line...
// 0x00000040 [6] AUTO_CS0N (0) When 1, automatically assert the CS0n chip select line...
// 0x00000008 [3] ASSERT_CS1N (0) When 1, assert (i
// 0x00000004 [2] ASSERT_CS0N (0) When 1, assert (i
// 0x00000002 [1] BUSY (0) Direct mode busy flag
// 0x00000001 [0] EN (0) Enable direct mode
io_rw_32 direct_csr;
_REG_(QMI_DIRECT_TX_OFFSET) // QMI_DIRECT_TX
// Transmit FIFO for direct mode
// 0x00100000 [20] NOPUSH (0) Inhibit the RX FIFO push that would correspond to this...
// 0x00080000 [19] OE (0) Output enable (active-high)
// 0x00040000 [18] DWIDTH (0) Data width
// 0x00030000 [17:16] IWIDTH (0x0) Configure whether this FIFO record is transferred with...
// 0x0000ffff [15:0] DATA (0x0000) Data pushed here will be clocked out falling edges of...
io_wo_32 direct_tx;
_REG_(QMI_DIRECT_RX_OFFSET) // QMI_DIRECT_RX
// Receive FIFO for direct mode
// 0x0000ffff [15:0] DIRECT_RX (0x0000) With each byte clocked out on the serial interface, one...
io_ro_32 direct_rx;
qmi_mem_hw_t m[2];
// (Description copied from array index 0 register QMI_ATRANS0 applies similarly to other array indexes)
_REG_(QMI_ATRANS0_OFFSET) // QMI_ATRANS0
// Configure address translation for XIP virtual addresses 0x000000 through 0x3fffff (a 4 MiB window starting at +0 MiB).
// 0x07ff0000 [26:16] SIZE (0x400) Translation aperture size for this virtual address...
// 0x00000fff [11:0] BASE (0x000) Physical address base for this virtual address range, in...
io_rw_32 atrans[8];
} qmi_hw_t;
#define qmi_hw ((qmi_hw_t *)XIP_QMI_BASE)
static_assert(sizeof (qmi_hw_t) == 0x0054, "");
#endif // _HARDWARE_STRUCTS_QMI_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RESETS_H
#define _HARDWARE_STRUCTS_RESETS_H
/**
* \file rp2350/resets.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/resets.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_resets
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Resettable component numbers on RP2350 (used as typedef \ref reset_num_t)
* \ingroup hardware_resets
*/
typedef enum reset_num_rp2350 {
RESET_ADC = 0, ///< Select ADC to be reset
RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset
RESET_DMA = 2, ///< Select DMA to be reset
RESET_HSTX = 3, ///< Select HSTX to be reset
RESET_I2C0 = 4, ///< Select I2C0 to be reset
RESET_I2C1 = 5, ///< Select I2C1 to be reset
RESET_IO_BANK0 = 6, ///< Select IO_BANK0 to be reset
RESET_IO_QSPI = 7, ///< Select IO_QSPI to be reset
RESET_JTAG = 8, ///< Select JTAG to be reset
RESET_PADS_BANK0 = 9, ///< Select PADS_BANK0 to be reset
RESET_PADS_QSPI = 10, ///< Select PADS_QSPI to be reset
RESET_PIO0 = 11, ///< Select PIO0 to be reset
RESET_PIO1 = 12, ///< Select PIO1 to be reset
RESET_PIO2 = 13, ///< Select PIO2 to be reset
RESET_PLL_SYS = 14, ///< Select PLL_SYS to be reset
RESET_PLL_USB = 15, ///< Select PLL_USB to be reset
RESET_PWM = 16, ///< Select PWM to be reset
RESET_SHA256 = 17, ///< Select SHA256 to be reset
RESET_SPI0 = 18, ///< Select SPI0 to be reset
RESET_SPI1 = 19, ///< Select SPI1 to be reset
RESET_SYSCFG = 20, ///< Select SYSCFG to be reset
RESET_SYSINFO = 21, ///< Select SYSINFO to be reset
RESET_TBMAN = 22, ///< Select TBMAN to be reset
RESET_TIMER0 = 23, ///< Select TIMER0 to be reset
RESET_TIMER1 = 24, ///< Select TIMER1 to be reset
RESET_TRNG = 25, ///< Select TRNG to be reset
RESET_UART0 = 26, ///< Select UART0 to be reset
RESET_UART1 = 27, ///< Select UART1 to be reset
RESET_USBCTRL = 28, ///< Select USBCTRL to be reset
RESET_COUNT
} reset_num_t;
/// \tag::resets_hw[]
typedef struct {
_REG_(RESETS_RESET_OFFSET) // RESETS_RESET
// 0x10000000 [28] USBCTRL (1)
// 0x08000000 [27] UART1 (1)
// 0x04000000 [26] UART0 (1)
// 0x02000000 [25] TRNG (1)
// 0x01000000 [24] TIMER1 (1)
// 0x00800000 [23] TIMER0 (1)
// 0x00400000 [22] TBMAN (1)
// 0x00200000 [21] SYSINFO (1)
// 0x00100000 [20] SYSCFG (1)
// 0x00080000 [19] SPI1 (1)
// 0x00040000 [18] SPI0 (1)
// 0x00020000 [17] SHA256 (1)
// 0x00010000 [16] PWM (1)
// 0x00008000 [15] PLL_USB (1)
// 0x00004000 [14] PLL_SYS (1)
// 0x00002000 [13] PIO2 (1)
// 0x00001000 [12] PIO1 (1)
// 0x00000800 [11] PIO0 (1)
// 0x00000400 [10] PADS_QSPI (1)
// 0x00000200 [9] PADS_BANK0 (1)
// 0x00000100 [8] JTAG (1)
// 0x00000080 [7] IO_QSPI (1)
// 0x00000040 [6] IO_BANK0 (1)
// 0x00000020 [5] I2C1 (1)
// 0x00000010 [4] I2C0 (1)
// 0x00000008 [3] HSTX (1)
// 0x00000004 [2] DMA (1)
// 0x00000002 [1] BUSCTRL (1)
// 0x00000001 [0] ADC (1)
io_rw_32 reset;
_REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
// 0x10000000 [28] USBCTRL (0)
// 0x08000000 [27] UART1 (0)
// 0x04000000 [26] UART0 (0)
// 0x02000000 [25] TRNG (0)
// 0x01000000 [24] TIMER1 (0)
// 0x00800000 [23] TIMER0 (0)
// 0x00400000 [22] TBMAN (0)
// 0x00200000 [21] SYSINFO (0)
// 0x00100000 [20] SYSCFG (0)
// 0x00080000 [19] SPI1 (0)
// 0x00040000 [18] SPI0 (0)
// 0x00020000 [17] SHA256 (0)
// 0x00010000 [16] PWM (0)
// 0x00008000 [15] PLL_USB (0)
// 0x00004000 [14] PLL_SYS (0)
// 0x00002000 [13] PIO2 (0)
// 0x00001000 [12] PIO1 (0)
// 0x00000800 [11] PIO0 (0)
// 0x00000400 [10] PADS_QSPI (0)
// 0x00000200 [9] PADS_BANK0 (0)
// 0x00000100 [8] JTAG (0)
// 0x00000080 [7] IO_QSPI (0)
// 0x00000040 [6] IO_BANK0 (0)
// 0x00000020 [5] I2C1 (0)
// 0x00000010 [4] I2C0 (0)
// 0x00000008 [3] HSTX (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_rw_32 wdsel;
_REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
// 0x10000000 [28] USBCTRL (0)
// 0x08000000 [27] UART1 (0)
// 0x04000000 [26] UART0 (0)
// 0x02000000 [25] TRNG (0)
// 0x01000000 [24] TIMER1 (0)
// 0x00800000 [23] TIMER0 (0)
// 0x00400000 [22] TBMAN (0)
// 0x00200000 [21] SYSINFO (0)
// 0x00100000 [20] SYSCFG (0)
// 0x00080000 [19] SPI1 (0)
// 0x00040000 [18] SPI0 (0)
// 0x00020000 [17] SHA256 (0)
// 0x00010000 [16] PWM (0)
// 0x00008000 [15] PLL_USB (0)
// 0x00004000 [14] PLL_SYS (0)
// 0x00002000 [13] PIO2 (0)
// 0x00001000 [12] PIO1 (0)
// 0x00000800 [11] PIO0 (0)
// 0x00000400 [10] PADS_QSPI (0)
// 0x00000200 [9] PADS_BANK0 (0)
// 0x00000100 [8] JTAG (0)
// 0x00000080 [7] IO_QSPI (0)
// 0x00000040 [6] IO_BANK0 (0)
// 0x00000020 [5] I2C1 (0)
// 0x00000010 [4] I2C0 (0)
// 0x00000008 [3] HSTX (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_ro_32 reset_done;
} resets_hw_t;
/// \end::resets_hw[]
#define resets_hw ((resets_hw_t *)RESETS_BASE)
static_assert(sizeof (resets_hw_t) == 0x000c, "");
#endif // _HARDWARE_STRUCTS_RESETS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ROSC_H
#define _HARDWARE_STRUCTS_ROSC_H
/**
* \file rp2350/rosc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/rosc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_rosc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
// Ring Oscillator control
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
// 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
io_rw_32 ctrl;
_REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
// Ring Oscillator frequency control A
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
// 0x00000080 [7] DS1_RANDOM (0) Randomises the stage 1 drive strength
// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
// 0x00000008 [3] DS0_RANDOM (0) Randomises the stage 0 drive strength
// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
io_rw_32 freqa;
_REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
// Ring Oscillator frequency control B
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
// 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
// 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
// 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
io_rw_32 freqb;
_REG_(ROSC_RANDOM_OFFSET) // ROSC_RANDOM
// Loads a value to the LFSR randomiser
// 0xffffffff [31:0] SEED (0x3f04b16d)
io_rw_32 random;
_REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
// Ring Oscillator pause control
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
io_rw_32 dormant;
_REG_(ROSC_DIV_OFFSET) // ROSC_DIV
// Controls the output divider
// 0x0000ffff [15:0] DIV (-) set to 0xaa00 + div where +
io_rw_32 div;
_REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
// Controls the phase shifted output
// 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
// 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
// 0x00000004 [2] FLIP (0) invert the phase-shifted output +
// 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
io_rw_32 phase;
_REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
// Ring Oscillator Status
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
// 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
io_rw_32 status;
_REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
// Returns a 1 bit random value
// 0x00000001 [0] RANDOMBIT (1)
io_ro_32 randombit;
_REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
// A down counter running at the ROSC frequency which counts to zero and stops.
// 0x0000ffff [15:0] COUNT (0x0000)
io_rw_32 count;
} rosc_hw_t;
#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
static_assert(sizeof (rosc_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_ROSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SAU_H
#define _HARDWARE_STRUCTS_SAU_H
/**
* \file rp2350/sau.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
_REG_(M33_SAU_CTRL_OFFSET) // M33_SAU_CTRL
// Allows enabling of the Security Attribution Unit
// 0x00000002 [1] ALLNS (0) When SAU_CTRL
// 0x00000001 [0] ENABLE (0) Enables the SAU
io_rw_32 ctrl;
_REG_(M33_SAU_TYPE_OFFSET) // M33_SAU_TYPE
// Indicates the number of regions implemented by the Security Attribution Unit
// 0x000000ff [7:0] SREGION (0x08) The number of implemented SAU regions
io_ro_32 type;
_REG_(M33_SAU_RNR_OFFSET) // M33_SAU_RNR
// Selects the region currently accessed by SAU_RBAR and SAU_RLAR
// 0x000000ff [7:0] REGION (0x00) Indicates the SAU region accessed by SAU_RBAR and SAU_RLAR
io_rw_32 rnr;
_REG_(M33_SAU_RBAR_OFFSET) // M33_SAU_RBAR
// Provides indirect read and write access to the base address of the currently selected SAU region
// 0xffffffe0 [31:5] BADDR (0x0000000) Holds bits [31:5] of the base address for the selected SAU region
io_rw_32 rbar;
_REG_(M33_SAU_RLAR_OFFSET) // M33_SAU_RLAR
// Provides indirect read and write access to the limit address of the currently selected SAU region
// 0xffffffe0 [31:5] LADDR (0x0000000) Holds bits [31:5] of the limit address for the selected...
// 0x00000002 [1] NSC (0) Controls whether Non-secure state is permitted to...
// 0x00000001 [0] ENABLE (0) SAU region enable
io_rw_32 rlar;
} armv8m_sau_hw_t;
#define sau_hw ((armv8m_sau_hw_t *)(PPB_BASE + M33_SAU_CTRL_OFFSET))
#define sau_ns_hw ((armv8m_sau_hw_t *)(PPB_NONSEC_BASE + M33_SAU_CTRL_OFFSET))
static_assert(sizeof (armv8m_sau_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_SAU_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SCB_H
#define _HARDWARE_STRUCTS_SCB_H
/**
* \file rp2350/scb.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
_REG_(M33_CPUID_OFFSET) // M33_CPUID
// Provides identification information for the PE, including an implementer code for the device and...
// 0xff000000 [31:24] IMPLEMENTER (0x41) This field must hold an implementer code that has been...
// 0x00f00000 [23:20] VARIANT (0x1) IMPLEMENTATION DEFINED variant number
// 0x000f0000 [19:16] ARCHITECTURE (0xf) Defines the Architecture implemented by the PE
// 0x0000fff0 [15:4] PARTNO (0xd21) IMPLEMENTATION DEFINED primary part number for the device
// 0x0000000f [3:0] REVISION (0x0) IMPLEMENTATION DEFINED revision number for the device
io_ro_32 cpuid;
_REG_(M33_ICSR_OFFSET) // M33_ICSR
// Controls and provides status information for NMI, PendSV, SysTick and interrupts
// 0x80000000 [31] PENDNMISET (0) Indicates whether the NMI exception is pending
// 0x40000000 [30] PENDNMICLR (0) Allows the NMI exception pend state to be cleared
// 0x10000000 [28] PENDSVSET (0) Indicates whether the PendSV `FTSSS exception is pending
// 0x08000000 [27] PENDSVCLR (0) Allows the PendSV exception pend state to be cleared `FTSSS
// 0x04000000 [26] PENDSTSET (0) Indicates whether the SysTick `FTSSS exception is pending
// 0x02000000 [25] PENDSTCLR (0) Allows the SysTick exception pend state to be cleared `FTSSS
// 0x01000000 [24] STTNS (0) Controls whether in a single SysTick implementation, the...
// 0x00800000 [23] ISRPREEMPT (0) Indicates whether a pending exception will be serviced...
// 0x00400000 [22] ISRPENDING (0) Indicates whether an external interrupt, generated by...
// 0x001ff000 [20:12] VECTPENDING (0x000) The exception number of the highest priority pending and...
// 0x00000800 [11] RETTOBASE (0) In Handler mode, indicates whether there is more than...
// 0x000001ff [8:0] VECTACTIVE (0x000) The exception number of the current executing exception
io_rw_32 icsr;
_REG_(M33_VTOR_OFFSET) // M33_VTOR
// Vector Table Offset Register
// 0xffffff80 [31:7] TBLOFF (0x0000000) Vector table base offset field
io_rw_32 vtor;
_REG_(M33_AIRCR_OFFSET) // M33_AIRCR
// Application Interrupt and Reset Control Register
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
// 0x00004000 [14] PRIS (0) Prioritize Secure exceptions
// 0x00002000 [13] BFHFNMINS (0) BusFault, HardFault, and NMI Non-secure enable
// 0x00000700 [10:8] PRIGROUP (0x0) Interrupt priority grouping field
// 0x00000008 [3] SYSRESETREQS (0) System reset request, Secure state only
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
io_rw_32 aircr;
_REG_(M33_SCR_OFFSET) // M33_SCR
// System Control Register
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
// 0x00000008 [3] SLEEPDEEPS (0) 0 SLEEPDEEP is available to both security states +
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
io_rw_32 scr;
_REG_(M33_CCR_OFFSET) // M33_CCR
// Sets or returns configuration and control data
// 0x00040000 [18] BP (0) Enables program flow prediction `FTSSS
// 0x00020000 [17] IC (0) This is a global enable bit for instruction caches in...
// 0x00010000 [16] DC (0) Enables data caching of all data accesses to Normal memory `FTSSS
// 0x00000400 [10] STKOFHFNMIGN (0) Controls the effect of a stack limit violation while...
// 0x00000200 [9] RES1 (1) Reserved, RES1
// 0x00000100 [8] BFHFNMIGN (0) Determines the effect of precise BusFaults on handlers...
// 0x00000010 [4] DIV_0_TRP (0) Controls the generation of a DIVBYZERO UsageFault when...
// 0x00000008 [3] UNALIGN_TRP (0) Controls the trapping of unaligned word or halfword accesses
// 0x00000002 [1] USERSETMPEND (0) Determines whether unprivileged accesses are permitted...
// 0x00000001 [0] RES1_1 (1) Reserved, RES1
io_rw_32 ccr;
// (Description copied from array index 0 register M33_SHPR1 applies similarly to other array indexes)
_REG_(M33_SHPR1_OFFSET) // M33_SHPR1
// Sets or returns priority for system handlers 4 - 7
// 0xe0000000 [31:29] PRI_7_3 (0x0) Priority of system handler 7, SecureFault
// 0x00e00000 [23:21] PRI_6_3 (0x0) Priority of system handler 6, SecureFault
// 0x0000e000 [15:13] PRI_5_3 (0x0) Priority of system handler 5, SecureFault
// 0x000000e0 [7:5] PRI_4_3 (0x0) Priority of system handler 4, SecureFault
io_rw_32 shpr[3];
_REG_(M33_SHCSR_OFFSET) // M33_SHCSR
// Provides access to the active and pending status of system exceptions
// 0x00200000 [21] HARDFAULTPENDED (0) `IAAMO the pending state of the HardFault exception `CTTSSS
// 0x00100000 [20] SECUREFAULTPENDED (0) `IAAMO the pending state of the SecureFault exception
// 0x00080000 [19] SECUREFAULTENA (0) `DW the SecureFault exception is enabled
// 0x00040000 [18] USGFAULTENA (0) `DW the UsageFault exception is enabled `FTSSS
// 0x00020000 [17] BUSFAULTENA (0) `DW the BusFault exception is enabled
// 0x00010000 [16] MEMFAULTENA (0) `DW the MemManage exception is enabled `FTSSS
// 0x00008000 [15] SVCALLPENDED (0) `IAAMO the pending state of the SVCall exception `FTSSS
// 0x00004000 [14] BUSFAULTPENDED (0) `IAAMO the pending state of the BusFault exception
// 0x00002000 [13] MEMFAULTPENDED (0) `IAAMO the pending state of the MemManage exception `FTSSS
// 0x00001000 [12] USGFAULTPENDED (0) The UsageFault exception is banked between Security...
// 0x00000800 [11] SYSTICKACT (0) `IAAMO the active state of the SysTick exception `FTSSS
// 0x00000400 [10] PENDSVACT (0) `IAAMO the active state of the PendSV exception `FTSSS
// 0x00000100 [8] MONITORACT (0) `IAAMO the active state of the DebugMonitor exception
// 0x00000080 [7] SVCALLACT (0) `IAAMO the active state of the SVCall exception `FTSSS
// 0x00000020 [5] NMIACT (0) `IAAMO the active state of the NMI exception
// 0x00000010 [4] SECUREFAULTACT (0) `IAAMO the active state of the SecureFault exception
// 0x00000008 [3] USGFAULTACT (0) `IAAMO the active state of the UsageFault exception `FTSSS
// 0x00000004 [2] HARDFAULTACT (0) Indicates and allows limited modification of the active...
// 0x00000002 [1] BUSFAULTACT (0) `IAAMO the active state of the BusFault exception
// 0x00000001 [0] MEMFAULTACT (0) `IAAMO the active state of the MemManage exception `FTSSS
io_rw_32 shcsr;
_REG_(M33_CFSR_OFFSET) // M33_CFSR
// Contains the three Configurable Fault Status Registers
// 0x02000000 [25] UFSR_DIVBYZERO (0) Sticky flag indicating whether an integer division by...
// 0x01000000 [24] UFSR_UNALIGNED (0) Sticky flag indicating whether an unaligned access error...
// 0x00100000 [20] UFSR_STKOF (0) Sticky flag indicating whether a stack overflow error...
// 0x00080000 [19] UFSR_NOCP (0) Sticky flag indicating whether a coprocessor disabled or...
// 0x00040000 [18] UFSR_INVPC (0) Sticky flag indicating whether an integrity check error...
// 0x00020000 [17] UFSR_INVSTATE (0) Sticky flag indicating whether an EPSR
// 0x00010000 [16] UFSR_UNDEFINSTR (0) Sticky flag indicating whether an undefined instruction...
// 0x00008000 [15] BFSR_BFARVALID (0) Indicates validity of the contents of the BFAR register
// 0x00002000 [13] BFSR_LSPERR (0) Records whether a BusFault occurred during FP lazy state...
// 0x00001000 [12] BFSR_STKERR (0) Records whether a derived BusFault occurred during...
// 0x00000800 [11] BFSR_UNSTKERR (0) Records whether a derived BusFault occurred during...
// 0x00000400 [10] BFSR_IMPRECISERR (0) Records whether an imprecise data access error has occurred
// 0x00000200 [9] BFSR_PRECISERR (0) Records whether a precise data access error has occurred
// 0x00000100 [8] BFSR_IBUSERR (0) Records whether a BusFault on an instruction prefetch...
// 0x000000ff [7:0] MMFSR (0x00) Provides information on MemManage exceptions
io_rw_32 cfsr;
_REG_(M33_HFSR_OFFSET) // M33_HFSR
// Shows the cause of any HardFaults
// 0x80000000 [31] DEBUGEVT (0) Indicates when a Debug event has occurred
// 0x40000000 [30] FORCED (0) Indicates that a fault with configurable priority has...
// 0x00000002 [1] VECTTBL (0) Indicates when a fault has occurred because of a vector...
io_rw_32 hfsr;
_REG_(M33_DFSR_OFFSET) // M33_DFSR
// Shows which debug event occurred
// 0x00000010 [4] EXTERNAL (0) Sticky flag indicating whether an External debug request...
// 0x00000008 [3] VCATCH (0) Sticky flag indicating whether a Vector catch debug...
// 0x00000004 [2] DWTTRAP (0) Sticky flag indicating whether a Watchpoint debug event...
// 0x00000002 [1] BKPT (0) Sticky flag indicating whether a Breakpoint debug event...
// 0x00000001 [0] HALTED (0) Sticky flag indicating that a Halt request debug event...
io_rw_32 dfsr;
_REG_(M33_MMFAR_OFFSET) // M33_MMFAR
// Shows the address of the memory location that caused an MPU fault
// 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location...
io_rw_32 mmfar;
_REG_(M33_BFAR_OFFSET) // M33_BFAR
// Shows the address associated with a precise data access BusFault
// 0xffffffff [31:0] ADDRESS (0x00000000) This register is updated with the address of a location...
io_rw_32 bfar;
uint32_t _pad0;
// (Description copied from array index 0 register M33_ID_PFR0 applies similarly to other array indexes)
_REG_(M33_ID_PFR0_OFFSET) // M33_ID_PFR0
// Gives top-level information about the instruction set supported by the PE
// 0x000000f0 [7:4] STATE1 (0x3) T32 instruction set support
// 0x0000000f [3:0] STATE0 (0x0) A32 instruction set support
io_ro_32 id_pfr[2];
_REG_(M33_ID_DFR0_OFFSET) // M33_ID_DFR0
// Provides top level information about the debug system
// 0x00f00000 [23:20] MPROFDBG (0x2) Indicates the supported M-profile debug architecture
io_ro_32 id_dfr0;
_REG_(M33_ID_AFR0_OFFSET) // M33_ID_AFR0
// Provides information about the IMPLEMENTATION DEFINED features of the PE
// 0x0000f000 [15:12] IMPDEF3 (0x0) IMPLEMENTATION DEFINED meaning
// 0x00000f00 [11:8] IMPDEF2 (0x0) IMPLEMENTATION DEFINED meaning
// 0x000000f0 [7:4] IMPDEF1 (0x0) IMPLEMENTATION DEFINED meaning
// 0x0000000f [3:0] IMPDEF0 (0x0) IMPLEMENTATION DEFINED meaning
io_ro_32 id_afr0;
// (Description copied from array index 0 register M33_ID_MMFR0 applies similarly to other array indexes)
_REG_(M33_ID_MMFR0_OFFSET) // M33_ID_MMFR0
// Provides information about the implemented memory model and memory management support
// 0x00f00000 [23:20] AUXREG (0x1) Indicates support for Auxiliary Control Registers
// 0x000f0000 [19:16] TCM (0x0) Indicates support for tightly coupled memories (TCMs)
// 0x0000f000 [15:12] SHARELVL (0x1) Indicates the number of shareability levels implemented
// 0x00000f00 [11:8] OUTERSHR (0xf) Indicates the outermost shareability domain implemented
// 0x000000f0 [7:4] PMSA (0x4) Indicates support for the protected memory system...
io_ro_32 id_mmfr[4];
// (Description copied from array index 0 register M33_ID_ISAR0 applies similarly to other array indexes)
_REG_(M33_ID_ISAR0_OFFSET) // M33_ID_ISAR0
// Provides information about the instruction set implemented by the PE
// 0x0f000000 [27:24] DIVIDE (0x8) Indicates the supported Divide instructions
// 0x00f00000 [23:20] DEBUG (0x0) Indicates the implemented Debug instructions
// 0x000f0000 [19:16] COPROC (0x9) Indicates the supported Coprocessor instructions
// 0x0000f000 [15:12] CMPBRANCH (0x2) Indicates the supported combined Compare and Branch instructions
// 0x00000f00 [11:8] BITFIELD (0x3) Indicates the supported bit field instructions
// 0x000000f0 [7:4] BITCOUNT (0x0) Indicates the supported bit count instructions
io_ro_32 id_isar[6];
uint32_t _pad1;
_REG_(M33_CTR_OFFSET) // M33_CTR
// Provides information about the architecture of the caches
// 0x80000000 [31] RES1 (1) Reserved, RES1
// 0x0f000000 [27:24] CWG (0x0) Log2 of the number of words of the maximum size of...
// 0x00f00000 [23:20] ERG (0x0) Log2 of the number of words of the maximum size of the...
// 0x000f0000 [19:16] DMINLINE (0x0) Log2 of the number of words in the smallest cache line...
// 0x0000c000 [15:14] RES1_1 (0x3) Reserved, RES1
// 0x0000000f [3:0] IMINLINE (0x0) Log2 of the number of words in the smallest cache line...
io_ro_32 ctr;
uint32_t _pad2[2];
_REG_(M33_CPACR_OFFSET) // M33_CPACR
// Specifies the access privileges for coprocessors and the FP Extension
// 0x00c00000 [23:22] CP11 (0x0) The value in this field is ignored
// 0x00300000 [21:20] CP10 (0x0) Defines the access rights for the floating-point functionality
// 0x0000c000 [15:14] CP7 (0x0) Controls access privileges for coprocessor 7
// 0x00003000 [13:12] CP6 (0x0) Controls access privileges for coprocessor 6
// 0x00000c00 [11:10] CP5 (0x0) Controls access privileges for coprocessor 5
// 0x00000300 [9:8] CP4 (0x0) Controls access privileges for coprocessor 4
// 0x000000c0 [7:6] CP3 (0x0) Controls access privileges for coprocessor 3
// 0x00000030 [5:4] CP2 (0x0) Controls access privileges for coprocessor 2
// 0x0000000c [3:2] CP1 (0x0) Controls access privileges for coprocessor 1
// 0x00000003 [1:0] CP0 (0x0) Controls access privileges for coprocessor 0
io_rw_32 cpacr;
_REG_(M33_NSACR_OFFSET) // M33_NSACR
// Defines the Non-secure access permissions for both the FP Extension and coprocessors CP0 to CP7
// 0x00000800 [11] CP11 (0) Enables Non-secure access to the Floating-point Extension
// 0x00000400 [10] CP10 (0) Enables Non-secure access to the Floating-point Extension
// 0x00000080 [7] CP7 (0) Enables Non-secure access to coprocessor CP7
// 0x00000040 [6] CP6 (0) Enables Non-secure access to coprocessor CP6
// 0x00000020 [5] CP5 (0) Enables Non-secure access to coprocessor CP5
// 0x00000010 [4] CP4 (0) Enables Non-secure access to coprocessor CP4
// 0x00000008 [3] CP3 (0) Enables Non-secure access to coprocessor CP3
// 0x00000004 [2] CP2 (0) Enables Non-secure access to coprocessor CP2
// 0x00000002 [1] CP1 (0) Enables Non-secure access to coprocessor CP1
// 0x00000001 [0] CP0 (0) Enables Non-secure access to coprocessor CP0
io_rw_32 nsacr;
} armv8m_scb_hw_t;
#define scb_hw ((armv8m_scb_hw_t *)(PPB_BASE + M33_CPUID_OFFSET))
#define scb_ns_hw ((armv8m_scb_hw_t *)(PPB_NONSEC_BASE + M33_CPUID_OFFSET))
static_assert(sizeof (armv8m_scb_hw_t) == 0x0090, "");
#endif // _HARDWARE_STRUCTS_SCB_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SHA256_H
#define _HARDWARE_STRUCTS_SHA256_H
/**
* \file rp2350/sha256.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sha256.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sha256
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sha256.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SHA256_CSR_OFFSET) // SHA256_CSR
// Control and status register
// 0x00001000 [12] BSWAP (1) Enable byte swapping of 32-bit values at the point they...
// 0x00000300 [9:8] DMA_SIZE (0x2) Configure DREQ logic for the correct DMA data size
// 0x00000010 [4] ERR_WDATA_NOT_RDY (0) Set when a write occurs whilst the SHA-256 core is not...
// 0x00000004 [2] SUM_VLD (1) If 1, the SHA-256 checksum presented in registers SUM0...
// 0x00000002 [1] WDATA_RDY (1) If 1, the SHA-256 core is ready to accept more data...
// 0x00000001 [0] START (0) Write 1 to prepare the SHA-256 core for a new checksum
io_rw_32 csr;
_REG_(SHA256_WDATA_OFFSET) // SHA256_WDATA
// Write data register
// 0xffffffff [31:0] WDATA (0x00000000) After pulsing START and writing 16 words of data to this...
io_wo_32 wdata;
// (Description copied from array index 0 register SHA256_SUM0 applies similarly to other array indexes)
_REG_(SHA256_SUM0_OFFSET) // SHA256_SUM0
// 256-bit checksum result
// 0xffffffff [31:0] SUM0 (0x00000000)
io_ro_32 sum[8];
} sha256_hw_t;
#define sha256_hw ((sha256_hw_t *)SHA256_BASE)
static_assert(sizeof (sha256_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_SHA256_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SIO_H
#define _HARDWARE_STRUCTS_SIO_H
/**
* \file rp2350/sio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
#include "hardware/structs/interp.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SIO_CPUID_OFFSET) // SIO_CPUID
// Processor core identifier
// 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
io_ro_32 cpuid;
_REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
// Input value for GPIO0
// 0xffffffff [31:0] GPIO_IN (0x00000000)
io_ro_32 gpio_in;
_REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
// Input value on GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0) Input value on QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
// 0x08000000 [27] QSPI_CSN (0) Input value on QSPI CSn pin
// 0x04000000 [26] QSPI_SCK (0) Input value on QSPI SCK pin
// 0x02000000 [25] USB_DM (0) Input value on USB D- pin
// 0x01000000 [24] USB_DP (0) Input value on USB D+ pin
// 0x0000ffff [15:0] GPIO (0x0000) Input value on GPIO32
io_ro_32 gpio_hi_in;
uint32_t _pad0;
_REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
// GPIO0
// 0xffffffff [31:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
io_rw_32 gpio_out;
_REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
// Output value for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0) Output value for QSPI SD0 (MOSI), SD1 (MISO), SD2 and SD3 pins
// 0x08000000 [27] QSPI_CSN (0) Output value for QSPI CSn pin
// 0x04000000 [26] QSPI_SCK (0) Output value for QSPI SCK pin
// 0x02000000 [25] USB_DM (0) Output value for USB D- pin
// 0x01000000 [24] USB_DP (0) Output value for USB D+ pin
// 0x0000ffff [15:0] GPIO (0x0000) Output value for GPIO32
io_rw_32 gpio_hi_out;
_REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
// GPIO0
// 0xffffffff [31:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
io_wo_32 gpio_set;
_REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
// Output value set for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_set;
_REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
// GPIO0
// 0xffffffff [31:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
io_wo_32 gpio_clr;
_REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
// Output value clear for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_clr;
_REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
// GPIO0
// 0xffffffff [31:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
io_wo_32 gpio_togl;
_REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
// Output value XOR for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_togl;
_REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
// GPIO0
// 0xffffffff [31:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
io_rw_32 gpio_oe;
_REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
// Output enable value for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0) Output enable value for QSPI SD0 (MOSI), SD1 (MISO), SD2...
// 0x08000000 [27] QSPI_CSN (0) Output enable value for QSPI CSn pin
// 0x04000000 [26] QSPI_SCK (0) Output enable value for QSPI SCK pin
// 0x02000000 [25] USB_DM (0) Output enable value for USB D- pin
// 0x01000000 [24] USB_DP (0) Output enable value for USB D+ pin
// 0x0000ffff [15:0] GPIO (0x0000) Output enable value for GPIO32
io_rw_32 gpio_hi_oe;
_REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
// GPIO0
// 0xffffffff [31:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
io_wo_32 gpio_oe_set;
_REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
// Output enable set for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_oe_set;
_REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
// GPIO0
// 0xffffffff [31:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
io_wo_32 gpio_oe_clr;
_REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
// Output enable clear for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_oe_clr;
_REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
// GPIO0
// 0xffffffff [31:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
io_wo_32 gpio_oe_togl;
_REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
// Output enable XOR for GPIO32
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_wo_32 gpio_hi_oe_togl;
_REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
// Status register for inter-core FIFOs (mailboxes).
// 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
// 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
// 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
// 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
io_rw_32 fifo_st;
_REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
// Write access to this core's TX FIFO
// 0xffffffff [31:0] FIFO_WR (0x00000000)
io_wo_32 fifo_wr;
_REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
// Read access to this core's RX FIFO
// 0xffffffff [31:0] FIFO_RD (-)
io_ro_32 fifo_rd;
_REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
// Spinlock state
// 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
io_ro_32 spinlock_st;
uint32_t _pad1[8];
interp_hw_t interp[2];
// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
_REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
// Spinlock register 0
// 0xffffffff [31:0] SPINLOCK0 (0x00000000)
io_rw_32 spinlock[32];
_REG_(SIO_DOORBELL_OUT_SET_OFFSET) // SIO_DOORBELL_OUT_SET
// Trigger a doorbell interrupt on the opposite core
// 0x000000ff [7:0] DOORBELL_OUT_SET (0x00)
io_rw_32 doorbell_out_set;
_REG_(SIO_DOORBELL_OUT_CLR_OFFSET) // SIO_DOORBELL_OUT_CLR
// Clear doorbells which have been posted to the opposite core
// 0x000000ff [7:0] DOORBELL_OUT_CLR (0x00)
io_rw_32 doorbell_out_clr;
_REG_(SIO_DOORBELL_IN_SET_OFFSET) // SIO_DOORBELL_IN_SET
// Write 1s to trigger doorbell interrupts on this core
// 0x000000ff [7:0] DOORBELL_IN_SET (0x00)
io_rw_32 doorbell_in_set;
_REG_(SIO_DOORBELL_IN_CLR_OFFSET) // SIO_DOORBELL_IN_CLR
// Check and acknowledge doorbells posted to this core
// 0x000000ff [7:0] DOORBELL_IN_CLR (0x00)
io_rw_32 doorbell_in_clr;
_REG_(SIO_PERI_NONSEC_OFFSET) // SIO_PERI_NONSEC
// Detach certain core-local peripherals from Secure SIO, and attach them to Non-secure SIO, so...
// 0x00000020 [5] TMDS (0) IF 1, detach TMDS encoder (of this core) from the Secure...
// 0x00000002 [1] INTERP1 (0) If 1, detach interpolator 1 (of this core) from the...
// 0x00000001 [0] INTERP0 (0) If 1, detach interpolator 0 (of this core) from the...
io_rw_32 peri_nonsec;
uint32_t _pad2[3];
_REG_(SIO_RISCV_SOFTIRQ_OFFSET) // SIO_RISCV_SOFTIRQ
// Control the assertion of the standard software interrupt (MIP
// 0x00000200 [9] CORE1_CLR (0) Write 1 to atomically clear the core 1 software interrupt flag
// 0x00000100 [8] CORE0_CLR (0) Write 1 to atomically clear the core 0 software interrupt flag
// 0x00000002 [1] CORE1_SET (0) Write 1 to atomically set the core 1 software interrupt flag
// 0x00000001 [0] CORE0_SET (0) Write 1 to atomically set the core 0 software interrupt flag
io_rw_32 riscv_softirq;
_REG_(SIO_MTIME_CTRL_OFFSET) // SIO_MTIME_CTRL
// Control register for the RISC-V 64-bit Machine-mode timer
// 0x00000008 [3] DBGPAUSE_CORE1 (1) If 1, the timer pauses when core 1 is in the debug halt state
// 0x00000004 [2] DBGPAUSE_CORE0 (1) If 1, the timer pauses when core 0 is in the debug halt state
// 0x00000002 [1] FULLSPEED (0) If 1, increment the timer every cycle (i
// 0x00000001 [0] EN (1) Timer enable bit
io_rw_32 mtime_ctrl;
uint32_t _pad3[2];
_REG_(SIO_MTIME_OFFSET) // SIO_MTIME
// Read/write access to the high half of RISC-V Machine-mode timer
// 0xffffffff [31:0] MTIME (0x00000000)
io_rw_32 mtime;
_REG_(SIO_MTIMEH_OFFSET) // SIO_MTIMEH
// Read/write access to the high half of RISC-V Machine-mode timer
// 0xffffffff [31:0] MTIMEH (0x00000000)
io_rw_32 mtimeh;
_REG_(SIO_MTIMECMP_OFFSET) // SIO_MTIMECMP
// Low half of RISC-V Machine-mode timer comparator
// 0xffffffff [31:0] MTIMECMP (0xffffffff)
io_rw_32 mtimecmp;
_REG_(SIO_MTIMECMPH_OFFSET) // SIO_MTIMECMPH
// High half of RISC-V Machine-mode timer comparator
// 0xffffffff [31:0] MTIMECMPH (0xffffffff)
io_rw_32 mtimecmph;
_REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL
// Control register for TMDS encoder
// 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders
// 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle...
// 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read...
// 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE
// 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...
// 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...
// 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...
// 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
// 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
// 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
io_rw_32 tmds_ctrl;
_REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA
// Write-only access to the TMDS colour data register
// 0xffffffff [31:0] TMDS_WDATA (0x00000000)
io_wo_32 tmds_wdata;
_REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE
// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols)
// 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000)
io_ro_32 tmds_peek_single;
_REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE
// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value
// 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000)
io_ro_32 tmds_pop_single;
_REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0
// Get lane 0 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000)
io_ro_32 tmds_peek_double_l0;
_REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0
// Get lane 0 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000)
io_ro_32 tmds_pop_double_l0;
_REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1
// Get lane 1 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000)
io_ro_32 tmds_peek_double_l1;
_REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1
// Get lane 1 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000)
io_ro_32 tmds_pop_double_l1;
_REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2
// Get lane 2 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000)
io_ro_32 tmds_peek_double_l2;
_REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2
// Get lane 2 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000)
io_ro_32 tmds_pop_double_l2;
} sio_hw_t;
#define sio_hw ((sio_hw_t *)SIO_BASE)
#define sio_ns_hw ((sio_hw_t *)SIO_NONSEC_BASE)
static_assert(sizeof (sio_hw_t) == 0x01e8, "");
#endif // _HARDWARE_STRUCTS_SIO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SPI_H
#define _HARDWARE_STRUCTS_SPI_H
/**
* \file rp2350/spi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/spi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_spi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
// Control register 0, SSPCR0 on page 3-4
// 0x0000ff00 [15:8] SCR (0x00) Serial clock rate
// 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only
// 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format
// 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation
io_rw_32 cr0;
_REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
// Control register 1, SSPCR1 on page 3-5
// 0x00000008 [3] SOD (0) Slave-mode output disable
// 0x00000004 [2] MS (0) Master or slave mode select
// 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled
// 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled
io_rw_32 cr1;
_REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
// Data register, SSPDR on page 3-6
// 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO
io_rw_32 dr;
_REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
// Status register, SSPSR on page 3-7
// 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle
// 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full
// 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty
// 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full
// 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
io_ro_32 sr;
_REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
// Clock prescale register, SSPCPSR on page 3-8
// 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor
io_rw_32 cpsr;
_REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
// Interrupt mask set or clear register, SSPIMSC on page 3-9
// 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty...
// 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or...
// 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty...
// 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written...
io_rw_32 imsc;
_REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
// Raw interrupt status register, SSPRIS on page 3-10
// 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the...
// 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the...
// 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the...
// 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the...
io_ro_32 ris;
_REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
// Masked interrupt status register, SSPMIS on page 3-11
// 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after...
// 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after...
// 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after...
// 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,...
io_ro_32 mis;
_REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
// Interrupt clear register, SSPICR on page 3-11
// 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt
// 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt
io_rw_32 icr;
_REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
// DMA control register, SSPDMACR on page 3-12
// 0x00000002 [1] TXDMAE (0) Transmit DMA Enable
// 0x00000001 [0] RXDMAE (0) Receive DMA Enable
io_rw_32 dmacr;
} spi_hw_t;
#define spi0_hw ((spi_hw_t *)SPI0_BASE)
#define spi1_hw ((spi_hw_t *)SPI1_BASE)
static_assert(sizeof (spi_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_SPI_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSCFG_H
#define _HARDWARE_STRUCTS_SYSCFG_H
/**
* \file rp2350/syscfg.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/syscfg.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_syscfg
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
// Configuration for processors
// 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted
// 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted
io_ro_32 proc_config;
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
// For each bit, if 1, bypass the input synchronizer between that GPIO +
// 0xffffffff [31:0] GPIO (0x00000000)
io_rw_32 proc_in_sync_bypass;
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
// For each bit, if 1, bypass the input synchronizer between that GPIO +
// 0xf0000000 [31:28] QSPI_SD (0x0)
// 0x08000000 [27] QSPI_CSN (0)
// 0x04000000 [26] QSPI_SCK (0)
// 0x02000000 [25] USB_DM (0)
// 0x01000000 [24] USB_DP (0)
// 0x0000ffff [15:0] GPIO (0x0000)
io_rw_32 proc_in_sync_bypass_hi;
_REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
// Directly control the chip SWD debug port
// 0x00000008 [3] ATTACH (0) Attach chip debug port to syscfg controls, and...
// 0x00000004 [2] SWCLK (1) Directly drive SWCLK, if ATTACH is set
// 0x00000002 [1] SWDI (1) Directly drive SWDIO input, if ATTACH is set
// 0x00000001 [0] SWDO (-) Observe the value of SWDIO output
io_rw_32 dbgforce;
_REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
// Control PD pins to memories
// 0x00001000 [12] BOOTRAM (0)
// 0x00000800 [11] ROM (0)
// 0x00000400 [10] USB (0)
// 0x00000200 [9] SRAM9 (0)
// 0x00000100 [8] SRAM8 (0)
// 0x00000080 [7] SRAM7 (0)
// 0x00000040 [6] SRAM6 (0)
// 0x00000020 [5] SRAM5 (0)
// 0x00000010 [4] SRAM4 (0)
// 0x00000008 [3] SRAM3 (0)
// 0x00000004 [2] SRAM2 (0)
// 0x00000002 [1] SRAM1 (0)
// 0x00000001 [0] SRAM0 (0)
io_rw_32 mempowerdown;
_REG_(SYSCFG_AUXCTRL_OFFSET) // SYSCFG_AUXCTRL
// Auxiliary system control register
// 0x000000ff [7:0] AUXCTRL (0x00) * Bits 7:2: Reserved
io_rw_32 auxctrl;
} syscfg_hw_t;
#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE)
static_assert(sizeof (syscfg_hw_t) == 0x0018, "");
#endif // _HARDWARE_STRUCTS_SYSCFG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSINFO_H
#define _HARDWARE_STRUCTS_SYSINFO_H
/**
* \file rp2350/sysinfo.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sysinfo.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sysinfo
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID
// JEDEC JEP-106 compliant chip identifier
// 0xf0000000 [31:28] REVISION (-)
// 0x0ffff000 [27:12] PART (-)
// 0x00000ffe [11:1] MANUFACTURER (-)
// 0x00000001 [0] STOP_BIT (1)
io_ro_32 chip_id;
_REG_(SYSINFO_PACKAGE_SEL_OFFSET) // SYSINFO_PACKAGE_SEL
// 0x00000001 [0] PACKAGE_SEL (0)
io_ro_32 package_sel;
_REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM
// Platform register
// 0x00000010 [4] GATESIM (-)
// 0x00000008 [3] BATCHSIM (-)
// 0x00000004 [2] HDLSIM (-)
// 0x00000002 [1] ASIC (-)
// 0x00000001 [0] FPGA (-)
io_ro_32 platform;
uint32_t _pad0[2];
_REG_(SYSINFO_GITREF_RP2350_OFFSET) // SYSINFO_GITREF_RP2350
// Git hash of the chip source
// 0xffffffff [31:0] GITREF_RP2350 (-)
io_ro_32 gitref_rp2350;
} sysinfo_hw_t;
#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE)
static_assert(sizeof (sysinfo_hw_t) == 0x0018, "");
#endif // _HARDWARE_STRUCTS_SYSINFO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSTICK_H
#define _HARDWARE_STRUCTS_SYSTICK_H
/**
* \file rp2350/systick.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m33.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
#endif
typedef struct {
_REG_(M33_SYST_CSR_OFFSET) // M33_SYST_CSR
// SysTick Control and Status Register
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
io_rw_32 csr;
_REG_(M33_SYST_RVR_OFFSET) // M33_SYST_RVR
// SysTick Reload Value Register
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
io_rw_32 rvr;
_REG_(M33_SYST_CVR_OFFSET) // M33_SYST_CVR
// SysTick Current Value Register
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
io_rw_32 cvr;
_REG_(M33_SYST_CALIB_OFFSET) // M33_SYST_CALIB
// SysTick Calibration Value Register
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
io_ro_32 calib;
} systick_hw_t;
#define systick_hw ((systick_hw_t *)(PPB_BASE + M33_SYST_CSR_OFFSET))
#define systick_ns_hw ((systick_hw_t *)(PPB_NONSEC_BASE + M33_SYST_CSR_OFFSET))
static_assert(sizeof (systick_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_SYSTICK_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TBMAN_H
#define _HARDWARE_STRUCTS_TBMAN_H
/**
* \file rp2350/tbman.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/tbman.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_tbman
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM
// Indicates the type of platform in use
// 0x00000004 [2] HDLSIM (0) Indicates the platform is a simulation
// 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA
// 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC
io_ro_32 platform;
} tbman_hw_t;
#define tbman_hw ((tbman_hw_t *)TBMAN_BASE)
static_assert(sizeof (tbman_hw_t) == 0x0004, "");
#endif // _HARDWARE_STRUCTS_TBMAN_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TICKS_H
#define _HARDWARE_STRUCTS_TICKS_H
/**
* \file rp2350/ticks.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/ticks.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_ticks
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/ticks.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/*! \brief Tick generator numbers on RP2350 (used as typedef \ref tick_gen_num_t)
* \ingroup hardware_ticks
*/
typedef enum tick_gen_num_rp2350 {
TICK_PROC0 = 0,
TICK_PROC1 = 1,
TICK_TIMER0 = 2,
TICK_TIMER1 = 3,
TICK_WATCHDOG = 4,
TICK_RISCV = 5,
TICK_COUNT
} tick_gen_num_t;
typedef struct {
_REG_(TICKS_PROC0_CTRL_OFFSET) // TICKS_PROC0_CTRL
// Controls the tick generator
// 0x00000002 [1] RUNNING (-) Is the tick generator running?
// 0x00000001 [0] ENABLE (0) start / stop tick generation
io_rw_32 ctrl;
_REG_(TICKS_PROC0_CYCLES_OFFSET) // TICKS_PROC0_CYCLES
// 0x000001ff [8:0] PROC0_CYCLES (0x000) Total number of clk_tick cycles before the next tick
io_rw_32 cycles;
_REG_(TICKS_PROC0_COUNT_OFFSET) // TICKS_PROC0_COUNT
// 0x000001ff [8:0] PROC0_COUNT (-) Count down timer: the remaining number clk_tick cycles...
io_ro_32 count;
} ticks_slice_hw_t;
typedef struct {
ticks_slice_hw_t ticks[6];
} ticks_hw_t;
#define ticks_hw ((ticks_hw_t *)TICKS_BASE)
static_assert(sizeof (ticks_hw_t) == 0x0048, "");
#endif // _HARDWARE_STRUCTS_TICKS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TIMER_H
#define _HARDWARE_STRUCTS_TIMER_H
/**
* \file rp2350/timer.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/timer.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_timer
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
// Write to bits 63:32 of time always write timelw before timehw
// 0xffffffff [31:0] TIMEHW (0x00000000)
io_wo_32 timehw;
_REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
// Write to bits 31:0 of time writes do not get copied to time until timehw is written
// 0xffffffff [31:0] TIMELW (0x00000000)
io_wo_32 timelw;
_REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
// Read from bits 63:32 of time always read timelr before timehr
// 0xffffffff [31:0] TIMEHR (0x00000000)
io_ro_32 timehr;
_REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
// Read from bits 31:0 of time
// 0xffffffff [31:0] TIMELR (0x00000000)
io_ro_32 timelr;
// (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
_REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
// Arm alarm 0, and configure the time it will fire
// 0xffffffff [31:0] ALARM0 (0x00000000)
io_rw_32 alarm[4];
_REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
// Indicates the armed/disarmed status of each alarm
// 0x0000000f [3:0] ARMED (0x0)
io_rw_32 armed;
_REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
// Raw read from bits 63:32 of time (no side effects)
// 0xffffffff [31:0] TIMERAWH (0x00000000)
io_ro_32 timerawh;
_REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
// Raw read from bits 31:0 of time (no side effects)
// 0xffffffff [31:0] TIMERAWL (0x00000000)
io_ro_32 timerawl;
_REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
// Set bits high to enable pause when the corresponding debug ports are active
// 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode
// 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode
io_rw_32 dbgpause;
_REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
// Set high to pause the timer
// 0x00000001 [0] PAUSE (0)
io_rw_32 pause;
_REG_(TIMER_LOCKED_OFFSET) // TIMER_LOCKED
// Set locked bit to disable write access to timer Once set, cannot be cleared (without a reset)
// 0x00000001 [0] LOCKED (0)
io_rw_32 locked;
_REG_(TIMER_SOURCE_OFFSET) // TIMER_SOURCE
// Selects the source for the timer
// 0x00000001 [0] CLK_SYS (0)
io_rw_32 source;
_REG_(TIMER_INTR_OFFSET) // TIMER_INTR
// Raw Interrupts
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 intr;
_REG_(TIMER_INTE_OFFSET) // TIMER_INTE
// Interrupt Enable
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 inte;
_REG_(TIMER_INTF_OFFSET) // TIMER_INTF
// Interrupt Force
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 intf;
_REG_(TIMER_INTS_OFFSET) // TIMER_INTS
// Interrupt status after masking & forcing
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_ro_32 ints;
} timer_hw_t;
#define timer0_hw ((timer_hw_t *)TIMER0_BASE)
#define timer1_hw ((timer_hw_t *)TIMER1_BASE)
static_assert(sizeof (timer_hw_t) == 0x004c, "");
#endif // _HARDWARE_STRUCTS_TIMER_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TMDS_ENCODE_H
#define _HARDWARE_STRUCTS_TMDS_ENCODE_H
/**
* \file rp2350/tmds_encode.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SIO_TMDS_CTRL_OFFSET) // SIO_TMDS_CTRL
// Control register for TMDS encoder
// 0x10000000 [28] CLEAR_BALANCE (0) Clear the running DC balance state of the TMDS encoders
// 0x08000000 [27] PIX2_NOSHIFT (0) When encoding two pixels's worth of symbols in one cycle...
// 0x07000000 [26:24] PIX_SHIFT (0x0) Shift applied to the colour data register with each read...
// 0x00800000 [23] INTERLEAVE (0) Enable lane interleaving for reads of PEEK_SINGLE/POP_SINGLE
// 0x001c0000 [20:18] L2_NBITS (0x0) Number of valid colour MSBs for lane 2 (1-8 bits,...
// 0x00038000 [17:15] L1_NBITS (0x0) Number of valid colour MSBs for lane 1 (1-8 bits,...
// 0x00007000 [14:12] L0_NBITS (0x0) Number of valid colour MSBs for lane 0 (1-8 bits,...
// 0x00000f00 [11:8] L2_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
// 0x000000f0 [7:4] L1_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
// 0x0000000f [3:0] L0_ROT (0x0) Right-rotate the 16 LSBs of the colour accumulator by...
io_rw_32 tmds_ctrl;
_REG_(SIO_TMDS_WDATA_OFFSET) // SIO_TMDS_WDATA
// Write-only access to the TMDS colour data register
// 0xffffffff [31:0] TMDS_WDATA (0x00000000)
io_wo_32 tmds_wdata;
_REG_(SIO_TMDS_PEEK_SINGLE_OFFSET) // SIO_TMDS_PEEK_SINGLE
// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value (3x10-bit symbols)
// 0xffffffff [31:0] TMDS_PEEK_SINGLE (0x00000000)
io_ro_32 tmds_peek_single;
_REG_(SIO_TMDS_POP_SINGLE_OFFSET) // SIO_TMDS_POP_SINGLE
// Get the encoding of one pixel's worth of colour data, packed into a 32-bit value
// 0xffffffff [31:0] TMDS_POP_SINGLE (0x00000000)
io_ro_32 tmds_pop_single;
_REG_(SIO_TMDS_PEEK_DOUBLE_L0_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L0
// Get lane 0 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L0 (0x00000000)
io_ro_32 tmds_peek_double_l0;
_REG_(SIO_TMDS_POP_DOUBLE_L0_OFFSET) // SIO_TMDS_POP_DOUBLE_L0
// Get lane 0 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L0 (0x00000000)
io_ro_32 tmds_pop_double_l0;
_REG_(SIO_TMDS_PEEK_DOUBLE_L1_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L1
// Get lane 1 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L1 (0x00000000)
io_ro_32 tmds_peek_double_l1;
_REG_(SIO_TMDS_POP_DOUBLE_L1_OFFSET) // SIO_TMDS_POP_DOUBLE_L1
// Get lane 1 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L1 (0x00000000)
io_ro_32 tmds_pop_double_l1;
_REG_(SIO_TMDS_PEEK_DOUBLE_L2_OFFSET) // SIO_TMDS_PEEK_DOUBLE_L2
// Get lane 2 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_PEEK_DOUBLE_L2 (0x00000000)
io_ro_32 tmds_peek_double_l2;
_REG_(SIO_TMDS_POP_DOUBLE_L2_OFFSET) // SIO_TMDS_POP_DOUBLE_L2
// Get lane 2 of the encoding of two pixels' worth of colour data
// 0xffffffff [31:0] TMDS_POP_DOUBLE_L2 (0x00000000)
io_ro_32 tmds_pop_double_l2;
} tmds_encode_hw_t;
#define tmds_encode_hw ((tmds_encode_hw_t *)(SIO_BASE + SIO_TMDS_CTRL_OFFSET))
#define tmds_encode_ns_hw ((tmds_encode_hw_t *)(SIO_NONSEC_BASE + SIO_TMDS_CTRL_OFFSET))
static_assert(sizeof (tmds_encode_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_TMDS_ENCODE_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TRNG_H
#define _HARDWARE_STRUCTS_TRNG_H
/**
* \file rp2350/trng.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/trng.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_trng
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/trng.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(TRNG_RNG_IMR_OFFSET) // TRNG_RNG_IMR
// Interrupt masking
// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
// 0x00000008 [3] VN_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
// 0x00000004 [2] CRNGT_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
// 0x00000002 [1] AUTOCORR_ERR_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
// 0x00000001 [0] EHR_VALID_INT_MASK (1) 1'b1-mask interrupt, no interrupt will be generated
io_rw_32 rng_imr;
_REG_(TRNG_RNG_ISR_OFFSET) // TRNG_RNG_ISR
// RNG status register
// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
// 0x00000008 [3] VN_ERR (0) 1'b1 indicates Von Neuman error
// 0x00000004 [2] CRNGT_ERR (0) 1'b1 indicates CRNGT in the RNG test failed
// 0x00000002 [1] AUTOCORR_ERR (0) 1'b1 indicates Autocorrelation test failed four times in a row
// 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that 192 bits have been collected in the...
io_ro_32 rng_isr;
_REG_(TRNG_RNG_ICR_OFFSET) // TRNG_RNG_ICR
// Interrupt/status bit clear Register
// 0xfffffff0 [31:4] RESERVED (0x0000000) RESERVED
// 0x00000008 [3] VN_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR
// 0x00000004 [2] CRNGT_ERR (0) Write 1'b1 - clear corresponding bit in RNG_ISR
// 0x00000002 [1] AUTOCORR_ERR (0) Cannot be cleared by SW! Only RNG reset clears this bit
// 0x00000001 [0] EHR_VALID (0) Write 1'b1 - clear corresponding bit in RNG_ISR
io_rw_32 rng_icr;
_REG_(TRNG_TRNG_CONFIG_OFFSET) // TRNG_TRNG_CONFIG
// Selecting the inverter-chain length
// 0xfffffffc [31:2] RESERVED (0x00000000) RESERVED
// 0x00000003 [1:0] RND_SRC_SEL (0x0) Selects the number of inverters (out of four possible...
io_rw_32 trng_config;
_REG_(TRNG_TRNG_VALID_OFFSET) // TRNG_TRNG_VALID
// 192 bit collection indication
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] EHR_VALID (0) 1'b1 indicates that collection of bits in the RNG is...
io_ro_32 trng_valid;
// (Description copied from array index 0 register TRNG_EHR_DATA0 applies similarly to other array indexes)
_REG_(TRNG_EHR_DATA0_OFFSET) // TRNG_EHR_DATA0
// RNG collected bits
// 0xffffffff [31:0] EHR_DATA0 (0x00000000) Bits [31:0] of Entropy Holding Register (EHR) - RNG...
io_ro_32 ehr_data[6];
_REG_(TRNG_RND_SOURCE_ENABLE_OFFSET) // TRNG_RND_SOURCE_ENABLE
// Enable signal for the random source
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] RND_SRC_EN (0) * 1'b1 - entropy source is enabled
io_rw_32 rnd_source_enable;
_REG_(TRNG_SAMPLE_CNT1_OFFSET) // TRNG_SAMPLE_CNT1
// Counts clocks between sampling of random bit
// 0xffffffff [31:0] SAMPLE_CNTR1 (0x0000ffff) Sets the number of rng_clk cycles between two...
io_rw_32 sample_cnt1;
_REG_(TRNG_AUTOCORR_STATISTIC_OFFSET) // TRNG_AUTOCORR_STATISTIC
// Statistic about Autocorrelation test activations
// 0xffc00000 [31:22] RESERVED (0x000) RESERVED
// 0x003fc000 [21:14] AUTOCORR_FAILS (0x00) Count each time an autocorrelation test fails
// 0x00003fff [13:0] AUTOCORR_TRYS (0x0000) Count each time an autocorrelation test starts
io_rw_32 autocorr_statistic;
_REG_(TRNG_TRNG_DEBUG_CONTROL_OFFSET) // TRNG_TRNG_DEBUG_CONTROL
// Debug register
// 0x00000008 [3] AUTO_CORRELATE_BYPASS (0) When set, the autocorrelation test in the TRNG module is bypassed
// 0x00000004 [2] TRNG_CRNGT_BYPASS (0) When set, the CRNGT test in the RNG is bypassed
// 0x00000002 [1] VNC_BYPASS (0) When set, the Von-Neuman balancer is bypassed (including...
// 0x00000001 [0] RESERVED (0) N/A
io_rw_32 trng_debug_control;
uint32_t _pad0;
_REG_(TRNG_TRNG_SW_RESET_OFFSET) // TRNG_TRNG_SW_RESET
// Generate internal SW reset within the RNG block
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] TRNG_SW_RESET (0) Writing 1'b1 to this register causes an internal RNG reset
io_rw_32 trng_sw_reset;
uint32_t _pad1[28];
_REG_(TRNG_RNG_DEBUG_EN_INPUT_OFFSET) // TRNG_RNG_DEBUG_EN_INPUT
// Enable the RNG debug mode
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] RNG_DEBUG_EN (0) * 1'b1 - debug mode is enabled
io_rw_32 rng_debug_en_input;
_REG_(TRNG_TRNG_BUSY_OFFSET) // TRNG_TRNG_BUSY
// RNG Busy indication
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] TRNG_BUSY (0) Reflects rng_busy status
io_ro_32 trng_busy;
_REG_(TRNG_RST_BITS_COUNTER_OFFSET) // TRNG_RST_BITS_COUNTER
// Reset the counter of collected bits in the RNG
// 0xfffffffe [31:1] RESERVED (0x00000000) RESERVED
// 0x00000001 [0] RST_BITS_COUNTER (0) Writing any value to this address will reset the bits...
io_rw_32 rst_bits_counter;
_REG_(TRNG_RNG_VERSION_OFFSET) // TRNG_RNG_VERSION
// Displays the version settings of the TRNG
// 0xffffff00 [31:8] RESERVED (0x000000) RESERVED
// 0x00000080 [7] RNG_USE_5_SBOXES (0) * 1'b1 - 5 SBOX AES
// 0x00000040 [6] RESEEDING_EXISTS (0) * 1'b1 - Exists
// 0x00000020 [5] KAT_EXISTS (0) * 1'b1 - Exists
// 0x00000010 [4] PRNG_EXISTS (0) * 1'b1 - Exists
// 0x00000008 [3] TRNG_TESTS_BYPASS_EN (0) * 1'b1 - Exists
// 0x00000004 [2] AUTOCORR_EXISTS (0) * 1'b1 - Exists
// 0x00000002 [1] CRNGT_EXISTS (0) * 1'b1 - Exists
// 0x00000001 [0] EHR_WIDTH_192 (0) * 1'b1 - 192-bit EHR
io_ro_32 rng_version;
uint32_t _pad2[7];
// (Description copied from array index 0 register TRNG_RNG_BIST_CNTR_0 applies similarly to other array indexes)
_REG_(TRNG_RNG_BIST_CNTR_0_OFFSET) // TRNG_RNG_BIST_CNTR_0
// Collected BIST results
// 0xffc00000 [31:22] RESERVED (0x000) RESERVED
// 0x003fffff [21:0] ROSC_CNTR_VAL (0x000000) Reflects the results of RNG BIST counter
io_ro_32 rng_bist_cntr[3];
} trng_hw_t;
#define trng_hw ((trng_hw_t *)(TRNG_BASE + TRNG_RNG_IMR_OFFSET))
static_assert(sizeof (trng_hw_t) == 0x00ec, "");
#endif // _HARDWARE_STRUCTS_TRNG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_UART_H
#define _HARDWARE_STRUCTS_UART_H
/**
* \file rp2350/uart.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/uart.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_uart
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(UART_UARTDR_OFFSET) // UART_UARTDR
// Data Register, UARTDR
// 0x00000800 [11] OE (-) Overrun error
// 0x00000400 [10] BE (-) Break error
// 0x00000200 [9] PE (-) Parity error
// 0x00000100 [8] FE (-) Framing error
// 0x000000ff [7:0] DATA (-) Receive (read) data character
io_rw_32 dr;
_REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
// 0x00000008 [3] OE (0) Overrun error
// 0x00000004 [2] BE (0) Break error
// 0x00000002 [1] PE (0) Parity error
// 0x00000001 [0] FE (0) Framing error
io_rw_32 rsr;
uint32_t _pad0[4];
_REG_(UART_UARTFR_OFFSET) // UART_UARTFR
// Flag Register, UARTFR
// 0x00000100 [8] RI (-) Ring indicator
// 0x00000080 [7] TXFE (1) Transmit FIFO empty
// 0x00000040 [6] RXFF (0) Receive FIFO full
// 0x00000020 [5] TXFF (0) Transmit FIFO full
// 0x00000010 [4] RXFE (1) Receive FIFO empty
// 0x00000008 [3] BUSY (0) UART busy
// 0x00000004 [2] DCD (-) Data carrier detect
// 0x00000002 [1] DSR (-) Data set ready
// 0x00000001 [0] CTS (-) Clear to send
io_ro_32 fr;
uint32_t _pad1;
_REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
// IrDA Low-Power Counter Register, UARTILPR
// 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value
io_rw_32 ilpr;
_REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
// Integer Baud Rate Register, UARTIBRD
// 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor
io_rw_32 ibrd;
_REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
// Fractional Baud Rate Register, UARTFBRD
// 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor
io_rw_32 fbrd;
_REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
// Line Control Register, UARTLCR_H
// 0x00000080 [7] SPS (0) Stick parity select
// 0x00000060 [6:5] WLEN (0x0) Word length
// 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)...
// 0x00000008 [3] STP2 (0) Two stop bits select
// 0x00000004 [2] EPS (0) Even parity select
// 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit...
// 0x00000001 [0] BRK (0) Send break
io_rw_32 lcr_h;
_REG_(UART_UARTCR_OFFSET) // UART_UARTCR
// Control Register, UARTCR
// 0x00008000 [15] CTSEN (0) CTS hardware flow control enable
// 0x00004000 [14] RTSEN (0) RTS hardware flow control enable
// 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)...
// 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)...
// 0x00000800 [11] RTS (0) Request to send
// 0x00000400 [10] DTR (0) Data transmit ready
// 0x00000200 [9] RXE (1) Receive enable
// 0x00000100 [8] TXE (1) Transmit enable
// 0x00000080 [7] LBE (0) Loopback enable
// 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode
// 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled
// 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled
io_rw_32 cr;
_REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
// Interrupt FIFO Level Select Register, UARTIFLS
// 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select
// 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select
io_rw_32 ifls;
_REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
// Interrupt Mask Set/Clear Register, UARTIMSC
// 0x00000400 [10] OEIM (0) Overrun error interrupt mask
// 0x00000200 [9] BEIM (0) Break error interrupt mask
// 0x00000100 [8] PEIM (0) Parity error interrupt mask
// 0x00000080 [7] FEIM (0) Framing error interrupt mask
// 0x00000040 [6] RTIM (0) Receive timeout interrupt mask
// 0x00000020 [5] TXIM (0) Transmit interrupt mask
// 0x00000010 [4] RXIM (0) Receive interrupt mask
// 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask
// 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask
// 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask
// 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask
io_rw_32 imsc;
_REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
// Raw Interrupt Status Register, UARTRIS
// 0x00000400 [10] OERIS (0) Overrun error interrupt status
// 0x00000200 [9] BERIS (0) Break error interrupt status
// 0x00000100 [8] PERIS (0) Parity error interrupt status
// 0x00000080 [7] FERIS (0) Framing error interrupt status
// 0x00000040 [6] RTRIS (0) Receive timeout interrupt status
// 0x00000020 [5] TXRIS (0) Transmit interrupt status
// 0x00000010 [4] RXRIS (0) Receive interrupt status
// 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status
// 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status
// 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status
// 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status
io_ro_32 ris;
_REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
// Masked Interrupt Status Register, UARTMIS
// 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status
// 0x00000200 [9] BEMIS (0) Break error masked interrupt status
// 0x00000100 [8] PEMIS (0) Parity error masked interrupt status
// 0x00000080 [7] FEMIS (0) Framing error masked interrupt status
// 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status
// 0x00000020 [5] TXMIS (0) Transmit masked interrupt status
// 0x00000010 [4] RXMIS (0) Receive masked interrupt status
// 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status
// 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status
// 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status
// 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status
io_ro_32 mis;
_REG_(UART_UARTICR_OFFSET) // UART_UARTICR
// Interrupt Clear Register, UARTICR
// 0x00000400 [10] OEIC (-) Overrun error interrupt clear
// 0x00000200 [9] BEIC (-) Break error interrupt clear
// 0x00000100 [8] PEIC (-) Parity error interrupt clear
// 0x00000080 [7] FEIC (-) Framing error interrupt clear
// 0x00000040 [6] RTIC (-) Receive timeout interrupt clear
// 0x00000020 [5] TXIC (-) Transmit interrupt clear
// 0x00000010 [4] RXIC (-) Receive interrupt clear
// 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear
// 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear
// 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear
// 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear
io_rw_32 icr;
_REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
// DMA Control Register, UARTDMACR
// 0x00000004 [2] DMAONERR (0) DMA on error
// 0x00000002 [1] TXDMAE (0) Transmit DMA enable
// 0x00000001 [0] RXDMAE (0) Receive DMA enable
io_rw_32 dmacr;
} uart_hw_t;
#define uart0_hw ((uart_hw_t *)UART0_BASE)
#define uart1_hw ((uart_hw_t *)UART1_BASE)
static_assert(sizeof (uart_hw_t) == 0x004c, "");
#endif // _HARDWARE_STRUCTS_UART_H

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