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lib: Add rp2350 files to pico-sdk
Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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Kevin O'Connor
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107 changed files with 128556 additions and 0 deletions
126
lib/pico-sdk/rp2350/hardware/structs/mpu.h
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lib/pico-sdk/rp2350/hardware/structs/mpu.h
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
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/**
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* Copyright (c) 2024 Raspberry Pi Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _HARDWARE_STRUCTS_MPU_H
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#define _HARDWARE_STRUCTS_MPU_H
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/**
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* \file rp2350/mpu.h
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*/
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#include "hardware/address_mapped.h"
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#include "hardware/regs/m33.h"
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// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_m33
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//
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// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
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// _REG_(x) will link to the corresponding register in hardware/regs/m33.h.
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//
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// Bit-field descriptions are of the form:
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// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
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#if defined(__riscv) && PICO_FORBID_ARM_HEADERS_ON_RISCV
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#error "Arm header included in a RISC-V build with PICO_FORBID_ARM_HEADERS_ON_RISCV=1"
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#endif
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typedef struct {
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_REG_(M33_MPU_TYPE_OFFSET) // M33_MPU_TYPE
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// The MPU Type Register indicates how many regions the MPU `FTSSS supports
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// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
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// 0x00000001 [0] SEPARATE (0) Indicates support for separate instructions and data...
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io_ro_32 type;
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_REG_(M33_MPU_CTRL_OFFSET) // M33_MPU_CTRL
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// Enables the MPU and, when the MPU is enabled, controls whether the default memory map is enabled...
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// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled for...
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// 0x00000002 [1] HFNMIENA (0) Controls whether handlers executing with priority less...
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// 0x00000001 [0] ENABLE (0) Enables the MPU
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io_rw_32 ctrl;
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_REG_(M33_MPU_RNR_OFFSET) // M33_MPU_RNR
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// Selects the region currently accessed by MPU_RBAR and MPU_RLAR
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// 0x00000007 [2:0] REGION (0x0) Indicates the memory region accessed by MPU_RBAR and MPU_RLAR
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io_rw_32 rnr;
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_REG_(M33_MPU_RBAR_OFFSET) // M33_MPU_RBAR
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// Provides indirect read and write access to the base address of the currently selected MPU region `FTSSS
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// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
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// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
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// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
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// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
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io_rw_32 rbar;
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_REG_(M33_MPU_RLAR_OFFSET) // M33_MPU_RLAR
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// Provides indirect read and write access to the limit address of the currently selected MPU region `FTSSS
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// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
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// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
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// 0x00000001 [0] EN (0) Region enable
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io_rw_32 rlar;
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_REG_(M33_MPU_RBAR_A1_OFFSET) // M33_MPU_RBAR_A1
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// Provides indirect read and write access to the base address of the MPU region selected by...
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// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
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// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
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// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
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// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
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io_rw_32 rbar_a1;
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_REG_(M33_MPU_RLAR_A1_OFFSET) // M33_MPU_RLAR_A1
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// Provides indirect read and write access to the limit address of the currently selected MPU...
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// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
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// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
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// 0x00000001 [0] EN (0) Region enable
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io_rw_32 rlar_a1;
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_REG_(M33_MPU_RBAR_A2_OFFSET) // M33_MPU_RBAR_A2
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// Provides indirect read and write access to the base address of the MPU region selected by...
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// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
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// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
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// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
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// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
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io_rw_32 rbar_a2;
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_REG_(M33_MPU_RLAR_A2_OFFSET) // M33_MPU_RLAR_A2
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// Provides indirect read and write access to the limit address of the currently selected MPU...
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// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
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// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
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// 0x00000001 [0] EN (0) Region enable
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io_rw_32 rlar_a2;
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_REG_(M33_MPU_RBAR_A3_OFFSET) // M33_MPU_RBAR_A3
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// Provides indirect read and write access to the base address of the MPU region selected by...
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// 0xffffffe0 [31:5] BASE (0x0000000) Contains bits [31:5] of the lower inclusive limit of the...
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// 0x00000018 [4:3] SH (0x0) Defines the Shareability domain of this region for Normal memory
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// 0x00000006 [2:1] AP (0x0) Defines the access permissions for this region
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// 0x00000001 [0] XN (0) Defines whether code can be executed from this region
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io_rw_32 rbar_a3;
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_REG_(M33_MPU_RLAR_A3_OFFSET) // M33_MPU_RLAR_A3
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// Provides indirect read and write access to the limit address of the currently selected MPU...
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// 0xffffffe0 [31:5] LIMIT (0x0000000) Contains bits [31:5] of the upper inclusive limit of the...
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// 0x0000000e [3:1] ATTRINDX (0x0) Associates a set of attributes in the MPU_MAIR0 and...
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// 0x00000001 [0] EN (0) Region enable
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io_rw_32 rlar_a3;
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uint32_t _pad0;
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// (Description copied from array index 0 register M33_MPU_MAIR0 applies similarly to other array indexes)
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_REG_(M33_MPU_MAIR0_OFFSET) // M33_MPU_MAIR0
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// Along with MPU_MAIR1, provides the memory attribute encodings corresponding to the AttrIndex values
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// 0xff000000 [31:24] ATTR3 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 3
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// 0x00ff0000 [23:16] ATTR2 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 2
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// 0x0000ff00 [15:8] ATTR1 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 1
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// 0x000000ff [7:0] ATTR0 (0x00) Memory attribute encoding for MPU regions with an AttrIndex of 0
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io_rw_32 mair[2];
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} mpu_hw_t;
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#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M33_MPU_TYPE_OFFSET))
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#define mpu_ns_hw ((mpu_hw_t *)(PPB_NONSEC_BASE + M33_MPU_TYPE_OFFSET))
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static_assert(sizeof (mpu_hw_t) == 0x0038, "");
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#endif // _HARDWARE_STRUCTS_MPU_H
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