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lib: Rename lib/cmsis-sam4e/ to lib/sam4e/

Browse source 
This is in preparation for merging the sam3 and sam4 code.

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2018-12-26 15:46:25 -05:00
parent 70bbdf9334
commit e278552d44
95 changed files with 19 additions and 21 deletions
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56
lib/sam4e/include/instance/acc.h Normal file
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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_ACC_INSTANCE_
#define _SAM4E_ACC_INSTANCE_
/* ========== Register definition for ACC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_ACC_CR (0x400BC000U) /**< \brief (ACC) Control Register */
#define REG_ACC_MR (0x400BC004U) /**< \brief (ACC) Mode Register */
#define REG_ACC_IER (0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */
#define REG_ACC_IDR (0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */
#define REG_ACC_IMR (0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */
#define REG_ACC_ISR (0x400BC030U) /**< \brief (ACC) Interrupt Status Register */
#define REG_ACC_ACR (0x400BC094U) /**< \brief (ACC) Analog Control Register */
#define REG_ACC_WPMR (0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */
#define REG_ACC_WPSR (0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */
#else
#define REG_ACC_CR (*(WoReg*)0x400BC000U) /**< \brief (ACC) Control Register */
#define REG_ACC_MR (*(RwReg*)0x400BC004U) /**< \brief (ACC) Mode Register */
#define REG_ACC_IER (*(WoReg*)0x400BC024U) /**< \brief (ACC) Interrupt Enable Register */
#define REG_ACC_IDR (*(WoReg*)0x400BC028U) /**< \brief (ACC) Interrupt Disable Register */
#define REG_ACC_IMR (*(RoReg*)0x400BC02CU) /**< \brief (ACC) Interrupt Mask Register */
#define REG_ACC_ISR (*(RoReg*)0x400BC030U) /**< \brief (ACC) Interrupt Status Register */
#define REG_ACC_ACR (*(RwReg*)0x400BC094U) /**< \brief (ACC) Analog Control Register */
#define REG_ACC_WPMR (*(RwReg*)0x400BC0E4U) /**< \brief (ACC) Write Protect Mode Register */
#define REG_ACC_WPSR (*(RoReg*)0x400BC0E8U) /**< \brief (ACC) Write Protect Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_ACC_INSTANCE_ */

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lib/sam4e/include/instance/aes.h Normal file
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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_AES_INSTANCE_
#define _SAM4E_AES_INSTANCE_
/* ========== Register definition for AES peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AES_CR (0x40004000U) /**< \brief (AES) Control Register */
#define REG_AES_MR (0x40004004U) /**< \brief (AES) Mode Register */
#define REG_AES_IER (0x40004010U) /**< \brief (AES) Interrupt Enable Register */
#define REG_AES_IDR (0x40004014U) /**< \brief (AES) Interrupt Disable Register */
#define REG_AES_IMR (0x40004018U) /**< \brief (AES) Interrupt Mask Register */
#define REG_AES_ISR (0x4000401CU) /**< \brief (AES) Interrupt Status Register */
#define REG_AES_KEYWR (0x40004020U) /**< \brief (AES) Key Word Register */
#define REG_AES_IDATAR (0x40004040U) /**< \brief (AES) Input Data Register */
#define REG_AES_ODATAR (0x40004050U) /**< \brief (AES) Output Data Register */
#define REG_AES_IVR (0x40004060U) /**< \brief (AES) Initialization Vector Register */
#else
#define REG_AES_CR (*(WoReg*)0x40004000U) /**< \brief (AES) Control Register */
#define REG_AES_MR (*(RwReg*)0x40004004U) /**< \brief (AES) Mode Register */
#define REG_AES_IER (*(WoReg*)0x40004010U) /**< \brief (AES) Interrupt Enable Register */
#define REG_AES_IDR (*(WoReg*)0x40004014U) /**< \brief (AES) Interrupt Disable Register */
#define REG_AES_IMR (*(RoReg*)0x40004018U) /**< \brief (AES) Interrupt Mask Register */
#define REG_AES_ISR (*(RoReg*)0x4000401CU) /**< \brief (AES) Interrupt Status Register */
#define REG_AES_KEYWR (*(WoReg*)0x40004020U) /**< \brief (AES) Key Word Register */
#define REG_AES_IDATAR (*(WoReg*)0x40004040U) /**< \brief (AES) Input Data Register */
#define REG_AES_ODATAR (*(RoReg*)0x40004050U) /**< \brief (AES) Output Data Register */
#define REG_AES_IVR (*(WoReg*)0x40004060U) /**< \brief (AES) Initialization Vector Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_AES_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_AFEC0_INSTANCE_
#define _SAM4E_AFEC0_INSTANCE_
/* ========== Register definition for AFEC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AFEC0_CR (0x400B0000U) /**< \brief (AFEC0) Control Register */
#define REG_AFEC0_MR (0x400B0004U) /**< \brief (AFEC0) Mode Register */
#define REG_AFEC0_EMR (0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */
#define REG_AFEC0_SEQ1R (0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */
#define REG_AFEC0_SEQ2R (0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */
#define REG_AFEC0_CHER (0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */
#define REG_AFEC0_CHDR (0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */
#define REG_AFEC0_CHSR (0x400B001CU) /**< \brief (AFEC0) Channel Status Register */
#define REG_AFEC0_LCDR (0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */
#define REG_AFEC0_IER (0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */
#define REG_AFEC0_IDR (0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */
#define REG_AFEC0_IMR (0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */
#define REG_AFEC0_ISR (0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */
#define REG_AFEC0_OVER (0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */
#define REG_AFEC0_CWR (0x400B0050U) /**< \brief (AFEC0) Compare Window Register */
#define REG_AFEC0_CGR (0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */
#define REG_AFEC0_CDOR (0x400B005CU) /**< \brief (AFEC0) Channel DC Offset Register */
#define REG_AFEC0_DIFFR (0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */
#define REG_AFEC0_CSELR (0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */
#define REG_AFEC0_CDR (0x400B0068U) /**< \brief (AFEC0) Channel Data Register */
#define REG_AFEC0_COCR (0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */
#define REG_AFEC0_TEMPMR (0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */
#define REG_AFEC0_TEMPCWR (0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */
#define REG_AFEC0_ACR (0x400B0094U) /**< \brief (AFEC0) Analog Control Register */
#define REG_AFEC0_WPMR (0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */
#define REG_AFEC0_WPSR (0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */
#define REG_AFEC0_RPR (0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */
#define REG_AFEC0_RCR (0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */
#define REG_AFEC0_RNPR (0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */
#define REG_AFEC0_RNCR (0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */
#define REG_AFEC0_PTCR (0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */
#define REG_AFEC0_PTSR (0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */
#else
#define REG_AFEC0_CR (*(WoReg*)0x400B0000U) /**< \brief (AFEC0) Control Register */
#define REG_AFEC0_MR (*(RwReg*)0x400B0004U) /**< \brief (AFEC0) Mode Register */
#define REG_AFEC0_EMR (*(RwReg*)0x400B0008U) /**< \brief (AFEC0) Extended Mode Register */
#define REG_AFEC0_SEQ1R (*(RwReg*)0x400B000CU) /**< \brief (AFEC0) Channel Sequence 1 Register */
#define REG_AFEC0_SEQ2R (*(RwReg*)0x400B0010U) /**< \brief (AFEC0) Channel Sequence 2 Register */
#define REG_AFEC0_CHER (*(WoReg*)0x400B0014U) /**< \brief (AFEC0) Channel Enable Register */
#define REG_AFEC0_CHDR (*(WoReg*)0x400B0018U) /**< \brief (AFEC0) Channel Disable Register */
#define REG_AFEC0_CHSR (*(RoReg*)0x400B001CU) /**< \brief (AFEC0) Channel Status Register */
#define REG_AFEC0_LCDR (*(RoReg*)0x400B0020U) /**< \brief (AFEC0) Last Converted Data Register */
#define REG_AFEC0_IER (*(WoReg*)0x400B0024U) /**< \brief (AFEC0) Interrupt Enable Register */
#define REG_AFEC0_IDR (*(WoReg*)0x400B0028U) /**< \brief (AFEC0) Interrupt Disable Register */
#define REG_AFEC0_IMR (*(RoReg*)0x400B002CU) /**< \brief (AFEC0) Interrupt Mask Register */
#define REG_AFEC0_ISR (*(RoReg*)0x400B0030U) /**< \brief (AFEC0) Interrupt Status Register */
#define REG_AFEC0_OVER (*(RoReg*)0x400B004CU) /**< \brief (AFEC0) Overrun Status Register */
#define REG_AFEC0_CWR (*(RwReg*)0x400B0050U) /**< \brief (AFEC0) Compare Window Register */
#define REG_AFEC0_CGR (*(RwReg*)0x400B0054U) /**< \brief (AFEC0) Channel Gain Register */
#define REG_AFEC0_CDOR (*(RwReg*)0x400B005CU) /**< \brief (AFEC0) Channel DC Offset Register */
#define REG_AFEC0_DIFFR (*(RwReg*)0x400B0060U) /**< \brief (AFEC0) Channel Differential Register */
#define REG_AFEC0_CSELR (*(RoReg*)0x400B0064U) /**< \brief (AFEC0) Channel Register Selection */
#define REG_AFEC0_CDR (*(RoReg*)0x400B0068U) /**< \brief (AFEC0) Channel Data Register */
#define REG_AFEC0_COCR (*(RoReg*)0x400B006CU) /**< \brief (AFEC0) Channel Offset Compensation Register */
#define REG_AFEC0_TEMPMR (*(RwReg*)0x400B0070U) /**< \brief (AFEC0) Temperature Sensor Mode Register */
#define REG_AFEC0_TEMPCWR (*(RwReg*)0x400B0074U) /**< \brief (AFEC0) Temperature Compare Window Register */
#define REG_AFEC0_ACR (*(RwReg*)0x400B0094U) /**< \brief (AFEC0) Analog Control Register */
#define REG_AFEC0_WPMR (*(RwReg*)0x400B00E4U) /**< \brief (AFEC0) Write Protect Mode Register */
#define REG_AFEC0_WPSR (*(RoReg*)0x400B00E8U) /**< \brief (AFEC0) Write Protect Status Register */
#define REG_AFEC0_RPR (*(RwReg*)0x400B0100U) /**< \brief (AFEC0) Receive Pointer Register */
#define REG_AFEC0_RCR (*(RwReg*)0x400B0104U) /**< \brief (AFEC0) Receive Counter Register */
#define REG_AFEC0_RNPR (*(RwReg*)0x400B0110U) /**< \brief (AFEC0) Receive Next Pointer Register */
#define REG_AFEC0_RNCR (*(RwReg*)0x400B0114U) /**< \brief (AFEC0) Receive Next Counter Register */
#define REG_AFEC0_PTCR (*(WoReg*)0x400B0120U) /**< \brief (AFEC0) Transfer Control Register */
#define REG_AFEC0_PTSR (*(RoReg*)0x400B0124U) /**< \brief (AFEC0) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_AFEC0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_AFEC1_INSTANCE_
#define _SAM4E_AFEC1_INSTANCE_
/* ========== Register definition for AFEC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_AFEC1_CR (0x400B4000U) /**< \brief (AFEC1) Control Register */
#define REG_AFEC1_MR (0x400B4004U) /**< \brief (AFEC1) Mode Register */
#define REG_AFEC1_EMR (0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */
#define REG_AFEC1_SEQ1R (0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */
#define REG_AFEC1_SEQ2R (0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */
#define REG_AFEC1_CHER (0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */
#define REG_AFEC1_CHDR (0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */
#define REG_AFEC1_CHSR (0x400B401CU) /**< \brief (AFEC1) Channel Status Register */
#define REG_AFEC1_LCDR (0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */
#define REG_AFEC1_IER (0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */
#define REG_AFEC1_IDR (0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */
#define REG_AFEC1_IMR (0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */
#define REG_AFEC1_ISR (0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */
#define REG_AFEC1_OVER (0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */
#define REG_AFEC1_CWR (0x400B4050U) /**< \brief (AFEC1) Compare Window Register */
#define REG_AFEC1_CGR (0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */
#define REG_AFEC1_CDOR (0x400B405CU) /**< \brief (AFEC1) Channel DC Offset Register */
#define REG_AFEC1_DIFFR (0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */
#define REG_AFEC1_CSELR (0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */
#define REG_AFEC1_CDR (0x400B4068U) /**< \brief (AFEC1) Channel Data Register */
#define REG_AFEC1_COCR (0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */
#define REG_AFEC1_TEMPMR (0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */
#define REG_AFEC1_TEMPCWR (0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */
#define REG_AFEC1_ACR (0x400B4094U) /**< \brief (AFEC1) Analog Control Register */
#define REG_AFEC1_WPMR (0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */
#define REG_AFEC1_WPSR (0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */
#define REG_AFEC1_RPR (0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */
#define REG_AFEC1_RCR (0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */
#define REG_AFEC1_RNPR (0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */
#define REG_AFEC1_RNCR (0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */
#define REG_AFEC1_PTCR (0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */
#define REG_AFEC1_PTSR (0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */
#else
#define REG_AFEC1_CR (*(WoReg*)0x400B4000U) /**< \brief (AFEC1) Control Register */
#define REG_AFEC1_MR (*(RwReg*)0x400B4004U) /**< \brief (AFEC1) Mode Register */
#define REG_AFEC1_EMR (*(RwReg*)0x400B4008U) /**< \brief (AFEC1) Extended Mode Register */
#define REG_AFEC1_SEQ1R (*(RwReg*)0x400B400CU) /**< \brief (AFEC1) Channel Sequence 1 Register */
#define REG_AFEC1_SEQ2R (*(RwReg*)0x400B4010U) /**< \brief (AFEC1) Channel Sequence 2 Register */
#define REG_AFEC1_CHER (*(WoReg*)0x400B4014U) /**< \brief (AFEC1) Channel Enable Register */
#define REG_AFEC1_CHDR (*(WoReg*)0x400B4018U) /**< \brief (AFEC1) Channel Disable Register */
#define REG_AFEC1_CHSR (*(RoReg*)0x400B401CU) /**< \brief (AFEC1) Channel Status Register */
#define REG_AFEC1_LCDR (*(RoReg*)0x400B4020U) /**< \brief (AFEC1) Last Converted Data Register */
#define REG_AFEC1_IER (*(WoReg*)0x400B4024U) /**< \brief (AFEC1) Interrupt Enable Register */
#define REG_AFEC1_IDR (*(WoReg*)0x400B4028U) /**< \brief (AFEC1) Interrupt Disable Register */
#define REG_AFEC1_IMR (*(RoReg*)0x400B402CU) /**< \brief (AFEC1) Interrupt Mask Register */
#define REG_AFEC1_ISR (*(RoReg*)0x400B4030U) /**< \brief (AFEC1) Interrupt Status Register */
#define REG_AFEC1_OVER (*(RoReg*)0x400B404CU) /**< \brief (AFEC1) Overrun Status Register */
#define REG_AFEC1_CWR (*(RwReg*)0x400B4050U) /**< \brief (AFEC1) Compare Window Register */
#define REG_AFEC1_CGR (*(RwReg*)0x400B4054U) /**< \brief (AFEC1) Channel Gain Register */
#define REG_AFEC1_CDOR (*(RwReg*)0x400B405CU) /**< \brief (AFEC1) Channel DC Offset Register */
#define REG_AFEC1_DIFFR (*(RwReg*)0x400B4060U) /**< \brief (AFEC1) Channel Differential Register */
#define REG_AFEC1_CSELR (*(RoReg*)0x400B4064U) /**< \brief (AFEC1) Channel Register Selection */
#define REG_AFEC1_CDR (*(RoReg*)0x400B4068U) /**< \brief (AFEC1) Channel Data Register */
#define REG_AFEC1_COCR (*(RoReg*)0x400B406CU) /**< \brief (AFEC1) Channel Offset Compensation Register */
#define REG_AFEC1_TEMPMR (*(RwReg*)0x400B4070U) /**< \brief (AFEC1) Temperature Sensor Mode Register */
#define REG_AFEC1_TEMPCWR (*(RwReg*)0x400B4074U) /**< \brief (AFEC1) Temperature Compare Window Register */
#define REG_AFEC1_ACR (*(RwReg*)0x400B4094U) /**< \brief (AFEC1) Analog Control Register */
#define REG_AFEC1_WPMR (*(RwReg*)0x400B40E4U) /**< \brief (AFEC1) Write Protect Mode Register */
#define REG_AFEC1_WPSR (*(RoReg*)0x400B40E8U) /**< \brief (AFEC1) Write Protect Status Register */
#define REG_AFEC1_RPR (*(RwReg*)0x400B4100U) /**< \brief (AFEC1) Receive Pointer Register */
#define REG_AFEC1_RCR (*(RwReg*)0x400B4104U) /**< \brief (AFEC1) Receive Counter Register */
#define REG_AFEC1_RNPR (*(RwReg*)0x400B4110U) /**< \brief (AFEC1) Receive Next Pointer Register */
#define REG_AFEC1_RNCR (*(RwReg*)0x400B4114U) /**< \brief (AFEC1) Receive Next Counter Register */
#define REG_AFEC1_PTCR (*(WoReg*)0x400B4120U) /**< \brief (AFEC1) Transfer Control Register */
#define REG_AFEC1_PTSR (*(RoReg*)0x400B4124U) /**< \brief (AFEC1) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_AFEC1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_CAN0_INSTANCE_
#define _SAM4E_CAN0_INSTANCE_
/* ========== Register definition for CAN0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN0_MR (0x40010000U) /**< \brief (CAN0) Mode Register */
#define REG_CAN0_IER (0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */
#define REG_CAN0_IDR (0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */
#define REG_CAN0_IMR (0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */
#define REG_CAN0_SR (0x40010010U) /**< \brief (CAN0) Status Register */
#define REG_CAN0_BR (0x40010014U) /**< \brief (CAN0) Baudrate Register */
#define REG_CAN0_TIM (0x40010018U) /**< \brief (CAN0) Timer Register */
#define REG_CAN0_TIMESTP (0x4001001CU) /**< \brief (CAN0) Timestamp Register */
#define REG_CAN0_ECR (0x40010020U) /**< \brief (CAN0) Error Counter Register */
#define REG_CAN0_TCR (0x40010024U) /**< \brief (CAN0) Transfer Command Register */
#define REG_CAN0_ACR (0x40010028U) /**< \brief (CAN0) Abort Command Register */
#define REG_CAN0_WPMR (0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */
#define REG_CAN0_WPSR (0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */
#define REG_CAN0_MMR0 (0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
#define REG_CAN0_MAM0 (0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN0_MID0 (0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
#define REG_CAN0_MFID0 (0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
#define REG_CAN0_MSR0 (0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
#define REG_CAN0_MDL0 (0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
#define REG_CAN0_MDH0 (0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
#define REG_CAN0_MCR0 (0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
#define REG_CAN0_MMR1 (0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
#define REG_CAN0_MAM1 (0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN0_MID1 (0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
#define REG_CAN0_MFID1 (0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
#define REG_CAN0_MSR1 (0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
#define REG_CAN0_MDL1 (0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
#define REG_CAN0_MDH1 (0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
#define REG_CAN0_MCR1 (0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
#define REG_CAN0_MMR2 (0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
#define REG_CAN0_MAM2 (0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN0_MID2 (0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
#define REG_CAN0_MFID2 (0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
#define REG_CAN0_MSR2 (0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
#define REG_CAN0_MDL2 (0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
#define REG_CAN0_MDH2 (0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
#define REG_CAN0_MCR2 (0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
#define REG_CAN0_MMR3 (0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
#define REG_CAN0_MAM3 (0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN0_MID3 (0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
#define REG_CAN0_MFID3 (0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
#define REG_CAN0_MSR3 (0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
#define REG_CAN0_MDL3 (0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
#define REG_CAN0_MDH3 (0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
#define REG_CAN0_MCR3 (0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
#define REG_CAN0_MMR4 (0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
#define REG_CAN0_MAM4 (0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN0_MID4 (0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
#define REG_CAN0_MFID4 (0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
#define REG_CAN0_MSR4 (0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
#define REG_CAN0_MDL4 (0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
#define REG_CAN0_MDH4 (0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
#define REG_CAN0_MCR4 (0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
#define REG_CAN0_MMR5 (0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
#define REG_CAN0_MAM5 (0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN0_MID5 (0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
#define REG_CAN0_MFID5 (0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
#define REG_CAN0_MSR5 (0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
#define REG_CAN0_MDL5 (0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
#define REG_CAN0_MDH5 (0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
#define REG_CAN0_MCR5 (0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
#define REG_CAN0_MMR6 (0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
#define REG_CAN0_MAM6 (0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN0_MID6 (0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
#define REG_CAN0_MFID6 (0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
#define REG_CAN0_MSR6 (0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
#define REG_CAN0_MDL6 (0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
#define REG_CAN0_MDH6 (0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
#define REG_CAN0_MCR6 (0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
#define REG_CAN0_MMR7 (0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
#define REG_CAN0_MAM7 (0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN0_MID7 (0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
#define REG_CAN0_MFID7 (0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
#define REG_CAN0_MSR7 (0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
#define REG_CAN0_MDL7 (0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
#define REG_CAN0_MDH7 (0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
#define REG_CAN0_MCR7 (0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
#else
#define REG_CAN0_MR (*(RwReg*)0x40010000U) /**< \brief (CAN0) Mode Register */
#define REG_CAN0_IER (*(WoReg*)0x40010004U) /**< \brief (CAN0) Interrupt Enable Register */
#define REG_CAN0_IDR (*(WoReg*)0x40010008U) /**< \brief (CAN0) Interrupt Disable Register */
#define REG_CAN0_IMR (*(RoReg*)0x4001000CU) /**< \brief (CAN0) Interrupt Mask Register */
#define REG_CAN0_SR (*(RoReg*)0x40010010U) /**< \brief (CAN0) Status Register */
#define REG_CAN0_BR (*(RwReg*)0x40010014U) /**< \brief (CAN0) Baudrate Register */
#define REG_CAN0_TIM (*(RoReg*)0x40010018U) /**< \brief (CAN0) Timer Register */
#define REG_CAN0_TIMESTP (*(RoReg*)0x4001001CU) /**< \brief (CAN0) Timestamp Register */
#define REG_CAN0_ECR (*(RoReg*)0x40010020U) /**< \brief (CAN0) Error Counter Register */
#define REG_CAN0_TCR (*(WoReg*)0x40010024U) /**< \brief (CAN0) Transfer Command Register */
#define REG_CAN0_ACR (*(WoReg*)0x40010028U) /**< \brief (CAN0) Abort Command Register */
#define REG_CAN0_WPMR (*(RwReg*)0x400100E4U) /**< \brief (CAN0) Write Protect Mode Register */
#define REG_CAN0_WPSR (*(RoReg*)0x400100E8U) /**< \brief (CAN0) Write Protect Status Register */
#define REG_CAN0_MMR0 (*(RwReg*)0x40010200U) /**< \brief (CAN0) Mailbox Mode Register (MB = 0) */
#define REG_CAN0_MAM0 (*(RwReg*)0x40010204U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN0_MID0 (*(RwReg*)0x40010208U) /**< \brief (CAN0) Mailbox ID Register (MB = 0) */
#define REG_CAN0_MFID0 (*(RoReg*)0x4001020CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 0) */
#define REG_CAN0_MSR0 (*(RoReg*)0x40010210U) /**< \brief (CAN0) Mailbox Status Register (MB = 0) */
#define REG_CAN0_MDL0 (*(RwReg*)0x40010214U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 0) */
#define REG_CAN0_MDH0 (*(RwReg*)0x40010218U) /**< \brief (CAN0) Mailbox Data High Register (MB = 0) */
#define REG_CAN0_MCR0 (*(WoReg*)0x4001021CU) /**< \brief (CAN0) Mailbox Control Register (MB = 0) */
#define REG_CAN0_MMR1 (*(RwReg*)0x40010220U) /**< \brief (CAN0) Mailbox Mode Register (MB = 1) */
#define REG_CAN0_MAM1 (*(RwReg*)0x40010224U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN0_MID1 (*(RwReg*)0x40010228U) /**< \brief (CAN0) Mailbox ID Register (MB = 1) */
#define REG_CAN0_MFID1 (*(RoReg*)0x4001022CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 1) */
#define REG_CAN0_MSR1 (*(RoReg*)0x40010230U) /**< \brief (CAN0) Mailbox Status Register (MB = 1) */
#define REG_CAN0_MDL1 (*(RwReg*)0x40010234U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 1) */
#define REG_CAN0_MDH1 (*(RwReg*)0x40010238U) /**< \brief (CAN0) Mailbox Data High Register (MB = 1) */
#define REG_CAN0_MCR1 (*(WoReg*)0x4001023CU) /**< \brief (CAN0) Mailbox Control Register (MB = 1) */
#define REG_CAN0_MMR2 (*(RwReg*)0x40010240U) /**< \brief (CAN0) Mailbox Mode Register (MB = 2) */
#define REG_CAN0_MAM2 (*(RwReg*)0x40010244U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN0_MID2 (*(RwReg*)0x40010248U) /**< \brief (CAN0) Mailbox ID Register (MB = 2) */
#define REG_CAN0_MFID2 (*(RoReg*)0x4001024CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 2) */
#define REG_CAN0_MSR2 (*(RoReg*)0x40010250U) /**< \brief (CAN0) Mailbox Status Register (MB = 2) */
#define REG_CAN0_MDL2 (*(RwReg*)0x40010254U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 2) */
#define REG_CAN0_MDH2 (*(RwReg*)0x40010258U) /**< \brief (CAN0) Mailbox Data High Register (MB = 2) */
#define REG_CAN0_MCR2 (*(WoReg*)0x4001025CU) /**< \brief (CAN0) Mailbox Control Register (MB = 2) */
#define REG_CAN0_MMR3 (*(RwReg*)0x40010260U) /**< \brief (CAN0) Mailbox Mode Register (MB = 3) */
#define REG_CAN0_MAM3 (*(RwReg*)0x40010264U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN0_MID3 (*(RwReg*)0x40010268U) /**< \brief (CAN0) Mailbox ID Register (MB = 3) */
#define REG_CAN0_MFID3 (*(RoReg*)0x4001026CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 3) */
#define REG_CAN0_MSR3 (*(RoReg*)0x40010270U) /**< \brief (CAN0) Mailbox Status Register (MB = 3) */
#define REG_CAN0_MDL3 (*(RwReg*)0x40010274U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 3) */
#define REG_CAN0_MDH3 (*(RwReg*)0x40010278U) /**< \brief (CAN0) Mailbox Data High Register (MB = 3) */
#define REG_CAN0_MCR3 (*(WoReg*)0x4001027CU) /**< \brief (CAN0) Mailbox Control Register (MB = 3) */
#define REG_CAN0_MMR4 (*(RwReg*)0x40010280U) /**< \brief (CAN0) Mailbox Mode Register (MB = 4) */
#define REG_CAN0_MAM4 (*(RwReg*)0x40010284U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN0_MID4 (*(RwReg*)0x40010288U) /**< \brief (CAN0) Mailbox ID Register (MB = 4) */
#define REG_CAN0_MFID4 (*(RoReg*)0x4001028CU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 4) */
#define REG_CAN0_MSR4 (*(RoReg*)0x40010290U) /**< \brief (CAN0) Mailbox Status Register (MB = 4) */
#define REG_CAN0_MDL4 (*(RwReg*)0x40010294U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 4) */
#define REG_CAN0_MDH4 (*(RwReg*)0x40010298U) /**< \brief (CAN0) Mailbox Data High Register (MB = 4) */
#define REG_CAN0_MCR4 (*(WoReg*)0x4001029CU) /**< \brief (CAN0) Mailbox Control Register (MB = 4) */
#define REG_CAN0_MMR5 (*(RwReg*)0x400102A0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 5) */
#define REG_CAN0_MAM5 (*(RwReg*)0x400102A4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN0_MID5 (*(RwReg*)0x400102A8U) /**< \brief (CAN0) Mailbox ID Register (MB = 5) */
#define REG_CAN0_MFID5 (*(RoReg*)0x400102ACU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 5) */
#define REG_CAN0_MSR5 (*(RoReg*)0x400102B0U) /**< \brief (CAN0) Mailbox Status Register (MB = 5) */
#define REG_CAN0_MDL5 (*(RwReg*)0x400102B4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 5) */
#define REG_CAN0_MDH5 (*(RwReg*)0x400102B8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 5) */
#define REG_CAN0_MCR5 (*(WoReg*)0x400102BCU) /**< \brief (CAN0) Mailbox Control Register (MB = 5) */
#define REG_CAN0_MMR6 (*(RwReg*)0x400102C0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 6) */
#define REG_CAN0_MAM6 (*(RwReg*)0x400102C4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN0_MID6 (*(RwReg*)0x400102C8U) /**< \brief (CAN0) Mailbox ID Register (MB = 6) */
#define REG_CAN0_MFID6 (*(RoReg*)0x400102CCU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 6) */
#define REG_CAN0_MSR6 (*(RoReg*)0x400102D0U) /**< \brief (CAN0) Mailbox Status Register (MB = 6) */
#define REG_CAN0_MDL6 (*(RwReg*)0x400102D4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 6) */
#define REG_CAN0_MDH6 (*(RwReg*)0x400102D8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 6) */
#define REG_CAN0_MCR6 (*(WoReg*)0x400102DCU) /**< \brief (CAN0) Mailbox Control Register (MB = 6) */
#define REG_CAN0_MMR7 (*(RwReg*)0x400102E0U) /**< \brief (CAN0) Mailbox Mode Register (MB = 7) */
#define REG_CAN0_MAM7 (*(RwReg*)0x400102E4U) /**< \brief (CAN0) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN0_MID7 (*(RwReg*)0x400102E8U) /**< \brief (CAN0) Mailbox ID Register (MB = 7) */
#define REG_CAN0_MFID7 (*(RoReg*)0x400102ECU) /**< \brief (CAN0) Mailbox Family ID Register (MB = 7) */
#define REG_CAN0_MSR7 (*(RoReg*)0x400102F0U) /**< \brief (CAN0) Mailbox Status Register (MB = 7) */
#define REG_CAN0_MDL7 (*(RwReg*)0x400102F4U) /**< \brief (CAN0) Mailbox Data Low Register (MB = 7) */
#define REG_CAN0_MDH7 (*(RwReg*)0x400102F8U) /**< \brief (CAN0) Mailbox Data High Register (MB = 7) */
#define REG_CAN0_MCR7 (*(WoReg*)0x400102FCU) /**< \brief (CAN0) Mailbox Control Register (MB = 7) */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_CAN0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_CAN1_INSTANCE_
#define _SAM4E_CAN1_INSTANCE_
/* ========== Register definition for CAN1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CAN1_MR (0x40014000U) /**< \brief (CAN1) Mode Register */
#define REG_CAN1_IER (0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */
#define REG_CAN1_IDR (0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */
#define REG_CAN1_IMR (0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */
#define REG_CAN1_SR (0x40014010U) /**< \brief (CAN1) Status Register */
#define REG_CAN1_BR (0x40014014U) /**< \brief (CAN1) Baudrate Register */
#define REG_CAN1_TIM (0x40014018U) /**< \brief (CAN1) Timer Register */
#define REG_CAN1_TIMESTP (0x4001401CU) /**< \brief (CAN1) Timestamp Register */
#define REG_CAN1_ECR (0x40014020U) /**< \brief (CAN1) Error Counter Register */
#define REG_CAN1_TCR (0x40014024U) /**< \brief (CAN1) Transfer Command Register */
#define REG_CAN1_ACR (0x40014028U) /**< \brief (CAN1) Abort Command Register */
#define REG_CAN1_WPMR (0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */
#define REG_CAN1_WPSR (0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */
#define REG_CAN1_MMR0 (0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
#define REG_CAN1_MAM0 (0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN1_MID0 (0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
#define REG_CAN1_MFID0 (0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
#define REG_CAN1_MSR0 (0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
#define REG_CAN1_MDL0 (0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
#define REG_CAN1_MDH0 (0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
#define REG_CAN1_MCR0 (0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
#define REG_CAN1_MMR1 (0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
#define REG_CAN1_MAM1 (0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN1_MID1 (0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
#define REG_CAN1_MFID1 (0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
#define REG_CAN1_MSR1 (0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
#define REG_CAN1_MDL1 (0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
#define REG_CAN1_MDH1 (0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
#define REG_CAN1_MCR1 (0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
#define REG_CAN1_MMR2 (0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
#define REG_CAN1_MAM2 (0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN1_MID2 (0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
#define REG_CAN1_MFID2 (0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
#define REG_CAN1_MSR2 (0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
#define REG_CAN1_MDL2 (0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
#define REG_CAN1_MDH2 (0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
#define REG_CAN1_MCR2 (0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
#define REG_CAN1_MMR3 (0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
#define REG_CAN1_MAM3 (0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN1_MID3 (0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
#define REG_CAN1_MFID3 (0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
#define REG_CAN1_MSR3 (0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
#define REG_CAN1_MDL3 (0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
#define REG_CAN1_MDH3 (0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
#define REG_CAN1_MCR3 (0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
#define REG_CAN1_MMR4 (0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
#define REG_CAN1_MAM4 (0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN1_MID4 (0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
#define REG_CAN1_MFID4 (0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
#define REG_CAN1_MSR4 (0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
#define REG_CAN1_MDL4 (0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
#define REG_CAN1_MDH4 (0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
#define REG_CAN1_MCR4 (0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
#define REG_CAN1_MMR5 (0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
#define REG_CAN1_MAM5 (0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN1_MID5 (0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
#define REG_CAN1_MFID5 (0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
#define REG_CAN1_MSR5 (0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
#define REG_CAN1_MDL5 (0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
#define REG_CAN1_MDH5 (0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
#define REG_CAN1_MCR5 (0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
#define REG_CAN1_MMR6 (0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
#define REG_CAN1_MAM6 (0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN1_MID6 (0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
#define REG_CAN1_MFID6 (0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
#define REG_CAN1_MSR6 (0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
#define REG_CAN1_MDL6 (0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
#define REG_CAN1_MDH6 (0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
#define REG_CAN1_MCR6 (0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
#define REG_CAN1_MMR7 (0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
#define REG_CAN1_MAM7 (0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN1_MID7 (0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
#define REG_CAN1_MFID7 (0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
#define REG_CAN1_MSR7 (0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
#define REG_CAN1_MDL7 (0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
#define REG_CAN1_MDH7 (0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
#define REG_CAN1_MCR7 (0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
#else
#define REG_CAN1_MR (*(RwReg*)0x40014000U) /**< \brief (CAN1) Mode Register */
#define REG_CAN1_IER (*(WoReg*)0x40014004U) /**< \brief (CAN1) Interrupt Enable Register */
#define REG_CAN1_IDR (*(WoReg*)0x40014008U) /**< \brief (CAN1) Interrupt Disable Register */
#define REG_CAN1_IMR (*(RoReg*)0x4001400CU) /**< \brief (CAN1) Interrupt Mask Register */
#define REG_CAN1_SR (*(RoReg*)0x40014010U) /**< \brief (CAN1) Status Register */
#define REG_CAN1_BR (*(RwReg*)0x40014014U) /**< \brief (CAN1) Baudrate Register */
#define REG_CAN1_TIM (*(RoReg*)0x40014018U) /**< \brief (CAN1) Timer Register */
#define REG_CAN1_TIMESTP (*(RoReg*)0x4001401CU) /**< \brief (CAN1) Timestamp Register */
#define REG_CAN1_ECR (*(RoReg*)0x40014020U) /**< \brief (CAN1) Error Counter Register */
#define REG_CAN1_TCR (*(WoReg*)0x40014024U) /**< \brief (CAN1) Transfer Command Register */
#define REG_CAN1_ACR (*(WoReg*)0x40014028U) /**< \brief (CAN1) Abort Command Register */
#define REG_CAN1_WPMR (*(RwReg*)0x400140E4U) /**< \brief (CAN1) Write Protect Mode Register */
#define REG_CAN1_WPSR (*(RoReg*)0x400140E8U) /**< \brief (CAN1) Write Protect Status Register */
#define REG_CAN1_MMR0 (*(RwReg*)0x40014200U) /**< \brief (CAN1) Mailbox Mode Register (MB = 0) */
#define REG_CAN1_MAM0 (*(RwReg*)0x40014204U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 0) */
#define REG_CAN1_MID0 (*(RwReg*)0x40014208U) /**< \brief (CAN1) Mailbox ID Register (MB = 0) */
#define REG_CAN1_MFID0 (*(RoReg*)0x4001420CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 0) */
#define REG_CAN1_MSR0 (*(RoReg*)0x40014210U) /**< \brief (CAN1) Mailbox Status Register (MB = 0) */
#define REG_CAN1_MDL0 (*(RwReg*)0x40014214U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 0) */
#define REG_CAN1_MDH0 (*(RwReg*)0x40014218U) /**< \brief (CAN1) Mailbox Data High Register (MB = 0) */
#define REG_CAN1_MCR0 (*(WoReg*)0x4001421CU) /**< \brief (CAN1) Mailbox Control Register (MB = 0) */
#define REG_CAN1_MMR1 (*(RwReg*)0x40014220U) /**< \brief (CAN1) Mailbox Mode Register (MB = 1) */
#define REG_CAN1_MAM1 (*(RwReg*)0x40014224U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 1) */
#define REG_CAN1_MID1 (*(RwReg*)0x40014228U) /**< \brief (CAN1) Mailbox ID Register (MB = 1) */
#define REG_CAN1_MFID1 (*(RoReg*)0x4001422CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 1) */
#define REG_CAN1_MSR1 (*(RoReg*)0x40014230U) /**< \brief (CAN1) Mailbox Status Register (MB = 1) */
#define REG_CAN1_MDL1 (*(RwReg*)0x40014234U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 1) */
#define REG_CAN1_MDH1 (*(RwReg*)0x40014238U) /**< \brief (CAN1) Mailbox Data High Register (MB = 1) */
#define REG_CAN1_MCR1 (*(WoReg*)0x4001423CU) /**< \brief (CAN1) Mailbox Control Register (MB = 1) */
#define REG_CAN1_MMR2 (*(RwReg*)0x40014240U) /**< \brief (CAN1) Mailbox Mode Register (MB = 2) */
#define REG_CAN1_MAM2 (*(RwReg*)0x40014244U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 2) */
#define REG_CAN1_MID2 (*(RwReg*)0x40014248U) /**< \brief (CAN1) Mailbox ID Register (MB = 2) */
#define REG_CAN1_MFID2 (*(RoReg*)0x4001424CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 2) */
#define REG_CAN1_MSR2 (*(RoReg*)0x40014250U) /**< \brief (CAN1) Mailbox Status Register (MB = 2) */
#define REG_CAN1_MDL2 (*(RwReg*)0x40014254U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 2) */
#define REG_CAN1_MDH2 (*(RwReg*)0x40014258U) /**< \brief (CAN1) Mailbox Data High Register (MB = 2) */
#define REG_CAN1_MCR2 (*(WoReg*)0x4001425CU) /**< \brief (CAN1) Mailbox Control Register (MB = 2) */
#define REG_CAN1_MMR3 (*(RwReg*)0x40014260U) /**< \brief (CAN1) Mailbox Mode Register (MB = 3) */
#define REG_CAN1_MAM3 (*(RwReg*)0x40014264U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 3) */
#define REG_CAN1_MID3 (*(RwReg*)0x40014268U) /**< \brief (CAN1) Mailbox ID Register (MB = 3) */
#define REG_CAN1_MFID3 (*(RoReg*)0x4001426CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 3) */
#define REG_CAN1_MSR3 (*(RoReg*)0x40014270U) /**< \brief (CAN1) Mailbox Status Register (MB = 3) */
#define REG_CAN1_MDL3 (*(RwReg*)0x40014274U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 3) */
#define REG_CAN1_MDH3 (*(RwReg*)0x40014278U) /**< \brief (CAN1) Mailbox Data High Register (MB = 3) */
#define REG_CAN1_MCR3 (*(WoReg*)0x4001427CU) /**< \brief (CAN1) Mailbox Control Register (MB = 3) */
#define REG_CAN1_MMR4 (*(RwReg*)0x40014280U) /**< \brief (CAN1) Mailbox Mode Register (MB = 4) */
#define REG_CAN1_MAM4 (*(RwReg*)0x40014284U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 4) */
#define REG_CAN1_MID4 (*(RwReg*)0x40014288U) /**< \brief (CAN1) Mailbox ID Register (MB = 4) */
#define REG_CAN1_MFID4 (*(RoReg*)0x4001428CU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 4) */
#define REG_CAN1_MSR4 (*(RoReg*)0x40014290U) /**< \brief (CAN1) Mailbox Status Register (MB = 4) */
#define REG_CAN1_MDL4 (*(RwReg*)0x40014294U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 4) */
#define REG_CAN1_MDH4 (*(RwReg*)0x40014298U) /**< \brief (CAN1) Mailbox Data High Register (MB = 4) */
#define REG_CAN1_MCR4 (*(WoReg*)0x4001429CU) /**< \brief (CAN1) Mailbox Control Register (MB = 4) */
#define REG_CAN1_MMR5 (*(RwReg*)0x400142A0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 5) */
#define REG_CAN1_MAM5 (*(RwReg*)0x400142A4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 5) */
#define REG_CAN1_MID5 (*(RwReg*)0x400142A8U) /**< \brief (CAN1) Mailbox ID Register (MB = 5) */
#define REG_CAN1_MFID5 (*(RoReg*)0x400142ACU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 5) */
#define REG_CAN1_MSR5 (*(RoReg*)0x400142B0U) /**< \brief (CAN1) Mailbox Status Register (MB = 5) */
#define REG_CAN1_MDL5 (*(RwReg*)0x400142B4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 5) */
#define REG_CAN1_MDH5 (*(RwReg*)0x400142B8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 5) */
#define REG_CAN1_MCR5 (*(WoReg*)0x400142BCU) /**< \brief (CAN1) Mailbox Control Register (MB = 5) */
#define REG_CAN1_MMR6 (*(RwReg*)0x400142C0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 6) */
#define REG_CAN1_MAM6 (*(RwReg*)0x400142C4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 6) */
#define REG_CAN1_MID6 (*(RwReg*)0x400142C8U) /**< \brief (CAN1) Mailbox ID Register (MB = 6) */
#define REG_CAN1_MFID6 (*(RoReg*)0x400142CCU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 6) */
#define REG_CAN1_MSR6 (*(RoReg*)0x400142D0U) /**< \brief (CAN1) Mailbox Status Register (MB = 6) */
#define REG_CAN1_MDL6 (*(RwReg*)0x400142D4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 6) */
#define REG_CAN1_MDH6 (*(RwReg*)0x400142D8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 6) */
#define REG_CAN1_MCR6 (*(WoReg*)0x400142DCU) /**< \brief (CAN1) Mailbox Control Register (MB = 6) */
#define REG_CAN1_MMR7 (*(RwReg*)0x400142E0U) /**< \brief (CAN1) Mailbox Mode Register (MB = 7) */
#define REG_CAN1_MAM7 (*(RwReg*)0x400142E4U) /**< \brief (CAN1) Mailbox Acceptance Mask Register (MB = 7) */
#define REG_CAN1_MID7 (*(RwReg*)0x400142E8U) /**< \brief (CAN1) Mailbox ID Register (MB = 7) */
#define REG_CAN1_MFID7 (*(RoReg*)0x400142ECU) /**< \brief (CAN1) Mailbox Family ID Register (MB = 7) */
#define REG_CAN1_MSR7 (*(RoReg*)0x400142F0U) /**< \brief (CAN1) Mailbox Status Register (MB = 7) */
#define REG_CAN1_MDL7 (*(RwReg*)0x400142F4U) /**< \brief (CAN1) Mailbox Data Low Register (MB = 7) */
#define REG_CAN1_MDH7 (*(RwReg*)0x400142F8U) /**< \brief (CAN1) Mailbox Data High Register (MB = 7) */
#define REG_CAN1_MCR7 (*(WoReg*)0x400142FCU) /**< \brief (CAN1) Mailbox Control Register (MB = 7) */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_CAN1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_CHIPID_INSTANCE_
#define _SAM4E_CHIPID_INSTANCE_
/* ========== Register definition for CHIPID peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CHIPID_CIDR (0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
#define REG_CHIPID_EXID (0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
#else
#define REG_CHIPID_CIDR (*(RoReg*)0x400E0740U) /**< \brief (CHIPID) Chip ID Register */
#define REG_CHIPID_EXID (*(RoReg*)0x400E0744U) /**< \brief (CHIPID) Chip ID Extension Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_CHIPID_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_CMCC_INSTANCE_
#define _SAM4E_CMCC_INSTANCE_
/* ========== Register definition for CMCC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CMCC_TYPE (0x400C4000U) /**< \brief (CMCC) Cache Type Register */
#define REG_CMCC_CFG (0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */
#define REG_CMCC_CTRL (0x400C4008U) /**< \brief (CMCC) Cache Control Register */
#define REG_CMCC_SR (0x400C400CU) /**< \brief (CMCC) Cache Status Register */
#define REG_CMCC_MAINT0 (0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */
#define REG_CMCC_MAINT1 (0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */
#define REG_CMCC_MCFG (0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */
#define REG_CMCC_MEN (0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */
#define REG_CMCC_MCTRL (0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */
#define REG_CMCC_MSR (0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */
#else
#define REG_CMCC_TYPE (*(RoReg*)0x400C4000U) /**< \brief (CMCC) Cache Type Register */
#define REG_CMCC_CFG (*(RwReg*)0x400C4004U) /**< \brief (CMCC) Cache Configuration Register */
#define REG_CMCC_CTRL (*(WoReg*)0x400C4008U) /**< \brief (CMCC) Cache Control Register */
#define REG_CMCC_SR (*(RoReg*)0x400C400CU) /**< \brief (CMCC) Cache Status Register */
#define REG_CMCC_MAINT0 (*(WoReg*)0x400C4020U) /**< \brief (CMCC) Cache Maintenance Register 0 */
#define REG_CMCC_MAINT1 (*(WoReg*)0x400C4024U) /**< \brief (CMCC) Cache Maintenance Register 1 */
#define REG_CMCC_MCFG (*(RwReg*)0x400C4028U) /**< \brief (CMCC) Cache Monitor Configuration Register */
#define REG_CMCC_MEN (*(RwReg*)0x400C402CU) /**< \brief (CMCC) Cache Monitor Enable Register */
#define REG_CMCC_MCTRL (*(WoReg*)0x400C4030U) /**< \brief (CMCC) Cache Monitor Control Register */
#define REG_CMCC_MSR (*(RoReg*)0x400C4034U) /**< \brief (CMCC) Cache Monitor Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_CMCC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_CRCCU_INSTANCE_
#define _SAM4E_CRCCU_INSTANCE_
/* ========== Register definition for CRCCU peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_CRCCU_DSCR (0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
#define REG_CRCCU_DMA_EN (0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
#define REG_CRCCU_DMA_DIS (0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
#define REG_CRCCU_DMA_SR (0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
#define REG_CRCCU_DMA_IER (0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
#define REG_CRCCU_DMA_IDR (0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
#define REG_CRCCU_DMA_IMR (0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
#define REG_CRCCU_DMA_ISR (0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
#define REG_CRCCU_CR (0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
#define REG_CRCCU_MR (0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
#define REG_CRCCU_SR (0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
#define REG_CRCCU_IER (0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
#define REG_CRCCU_IDR (0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
#define REG_CRCCU_IMR (0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
#define REG_CRCCU_ISR (0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
#else
#define REG_CRCCU_DSCR (*(RwReg*)0x40044000U) /**< \brief (CRCCU) CRCCU Descriptor Base Register */
#define REG_CRCCU_DMA_EN (*(WoReg*)0x40044008U) /**< \brief (CRCCU) CRCCU DMA Enable Register */
#define REG_CRCCU_DMA_DIS (*(WoReg*)0x4004400CU) /**< \brief (CRCCU) CRCCU DMA Disable Register */
#define REG_CRCCU_DMA_SR (*(RoReg*)0x40044010U) /**< \brief (CRCCU) CRCCU DMA Status Register */
#define REG_CRCCU_DMA_IER (*(WoReg*)0x40044014U) /**< \brief (CRCCU) CRCCU DMA Interrupt Enable Register */
#define REG_CRCCU_DMA_IDR (*(WoReg*)0x40044018U) /**< \brief (CRCCU) CRCCU DMA Interrupt Disable Register */
#define REG_CRCCU_DMA_IMR (*(RoReg*)0x4004401CU) /**< \brief (CRCCU) CRCCU DMA Interrupt Mask Register */
#define REG_CRCCU_DMA_ISR (*(RoReg*)0x40044020U) /**< \brief (CRCCU) CRCCU DMA Interrupt Status Register */
#define REG_CRCCU_CR (*(WoReg*)0x40044034U) /**< \brief (CRCCU) CRCCU Control Register */
#define REG_CRCCU_MR (*(RwReg*)0x40044038U) /**< \brief (CRCCU) CRCCU Mode Register */
#define REG_CRCCU_SR (*(RoReg*)0x4004403CU) /**< \brief (CRCCU) CRCCU Status Register */
#define REG_CRCCU_IER (*(WoReg*)0x40044040U) /**< \brief (CRCCU) CRCCU Interrupt Enable Register */
#define REG_CRCCU_IDR (*(WoReg*)0x40044044U) /**< \brief (CRCCU) CRCCU Interrupt Disable Register */
#define REG_CRCCU_IMR (*(RoReg*)0x40044048U) /**< \brief (CRCCU) CRCCU Interrupt Mask Register */
#define REG_CRCCU_ISR (*(RoReg*)0x4004404CU) /**< \brief (CRCCU) CRCCU Interrupt Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_CRCCU_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_DACC_INSTANCE_
#define _SAM4E_DACC_INSTANCE_
/* ========== Register definition for DACC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DACC_CR (0x400B8000U) /**< \brief (DACC) Control Register */
#define REG_DACC_MR (0x400B8004U) /**< \brief (DACC) Mode Register */
#define REG_DACC_CHER (0x400B8010U) /**< \brief (DACC) Channel Enable Register */
#define REG_DACC_CHDR (0x400B8014U) /**< \brief (DACC) Channel Disable Register */
#define REG_DACC_CHSR (0x400B8018U) /**< \brief (DACC) Channel Status Register */
#define REG_DACC_CDR (0x400B8020U) /**< \brief (DACC) Conversion Data Register */
#define REG_DACC_IER (0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */
#define REG_DACC_IDR (0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */
#define REG_DACC_IMR (0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */
#define REG_DACC_ISR (0x400B8030U) /**< \brief (DACC) Interrupt Status Register */
#define REG_DACC_ACR (0x400B8094U) /**< \brief (DACC) Analog Current Register */
#define REG_DACC_WPMR (0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */
#define REG_DACC_WPSR (0x400B80E8U) /**< \brief (DACC) Write Protect Status register */
#define REG_DACC_TPR (0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */
#define REG_DACC_TCR (0x400B810CU) /**< \brief (DACC) Transmit Counter Register */
#define REG_DACC_TNPR (0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */
#define REG_DACC_TNCR (0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */
#define REG_DACC_PTCR (0x400B8120U) /**< \brief (DACC) Transfer Control Register */
#define REG_DACC_PTSR (0x400B8124U) /**< \brief (DACC) Transfer Status Register */
#else
#define REG_DACC_CR (*(WoReg*)0x400B8000U) /**< \brief (DACC) Control Register */
#define REG_DACC_MR (*(RwReg*)0x400B8004U) /**< \brief (DACC) Mode Register */
#define REG_DACC_CHER (*(WoReg*)0x400B8010U) /**< \brief (DACC) Channel Enable Register */
#define REG_DACC_CHDR (*(WoReg*)0x400B8014U) /**< \brief (DACC) Channel Disable Register */
#define REG_DACC_CHSR (*(RoReg*)0x400B8018U) /**< \brief (DACC) Channel Status Register */
#define REG_DACC_CDR (*(WoReg*)0x400B8020U) /**< \brief (DACC) Conversion Data Register */
#define REG_DACC_IER (*(WoReg*)0x400B8024U) /**< \brief (DACC) Interrupt Enable Register */
#define REG_DACC_IDR (*(WoReg*)0x400B8028U) /**< \brief (DACC) Interrupt Disable Register */
#define REG_DACC_IMR (*(RoReg*)0x400B802CU) /**< \brief (DACC) Interrupt Mask Register */
#define REG_DACC_ISR (*(RoReg*)0x400B8030U) /**< \brief (DACC) Interrupt Status Register */
#define REG_DACC_ACR (*(RwReg*)0x400B8094U) /**< \brief (DACC) Analog Current Register */
#define REG_DACC_WPMR (*(RwReg*)0x400B80E4U) /**< \brief (DACC) Write Protect Mode register */
#define REG_DACC_WPSR (*(RoReg*)0x400B80E8U) /**< \brief (DACC) Write Protect Status register */
#define REG_DACC_TPR (*(RwReg*)0x400B8108U) /**< \brief (DACC) Transmit Pointer Register */
#define REG_DACC_TCR (*(RwReg*)0x400B810CU) /**< \brief (DACC) Transmit Counter Register */
#define REG_DACC_TNPR (*(RwReg*)0x400B8118U) /**< \brief (DACC) Transmit Next Pointer Register */
#define REG_DACC_TNCR (*(RwReg*)0x400B811CU) /**< \brief (DACC) Transmit Next Counter Register */
#define REG_DACC_PTCR (*(WoReg*)0x400B8120U) /**< \brief (DACC) Transfer Control Register */
#define REG_DACC_PTSR (*(RoReg*)0x400B8124U) /**< \brief (DACC) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_DACC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_DMAC_INSTANCE_
#define _SAM4E_DMAC_INSTANCE_
/* ========== Register definition for DMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_DMAC_GCFG (0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
#define REG_DMAC_EN (0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */
#define REG_DMAC_SREQ (0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
#define REG_DMAC_CREQ (0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC_LAST (0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
#define REG_DMAC_EBCIER (0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC_EBCIDR (0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC_EBCIMR (0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC_EBCISR (0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC_CHER (0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
#define REG_DMAC_CHDR (0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
#define REG_DMAC_CHSR (0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
#define REG_DMAC_SADDR0 (0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC_DADDR0 (0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC_DSCR0 (0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC_CTRLA0 (0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC_CTRLB0 (0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC_CFG0 (0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC_SADDR1 (0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC_DADDR1 (0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC_DSCR1 (0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC_CTRLA1 (0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC_CTRLB1 (0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC_CFG1 (0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC_SADDR2 (0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC_DADDR2 (0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC_DSCR2 (0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC_CTRLA2 (0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC_CTRLB2 (0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC_CFG2 (0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC_SADDR3 (0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC_DADDR3 (0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC_DSCR3 (0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC_CTRLA3 (0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC_CTRLB3 (0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC_CFG3 (0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC_WPMR (0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
#define REG_DMAC_WPSR (0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
#else
#define REG_DMAC_GCFG (*(RwReg*)0x400C0000U) /**< \brief (DMAC) DMAC Global Configuration Register */
#define REG_DMAC_EN (*(RwReg*)0x400C0004U) /**< \brief (DMAC) DMAC Enable Register */
#define REG_DMAC_SREQ (*(RwReg*)0x400C0008U) /**< \brief (DMAC) DMAC Software Single Request Register */
#define REG_DMAC_CREQ (*(RwReg*)0x400C000CU) /**< \brief (DMAC) DMAC Software Chunk Transfer Request Register */
#define REG_DMAC_LAST (*(RwReg*)0x400C0010U) /**< \brief (DMAC) DMAC Software Last Transfer Flag Register */
#define REG_DMAC_EBCIER (*(WoReg*)0x400C0018U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. */
#define REG_DMAC_EBCIDR (*(WoReg*)0x400C001CU) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. */
#define REG_DMAC_EBCIMR (*(RoReg*)0x400C0020U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. */
#define REG_DMAC_EBCISR (*(RoReg*)0x400C0024U) /**< \brief (DMAC) DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. */
#define REG_DMAC_CHER (*(WoReg*)0x400C0028U) /**< \brief (DMAC) DMAC Channel Handler Enable Register */
#define REG_DMAC_CHDR (*(WoReg*)0x400C002CU) /**< \brief (DMAC) DMAC Channel Handler Disable Register */
#define REG_DMAC_CHSR (*(RoReg*)0x400C0030U) /**< \brief (DMAC) DMAC Channel Handler Status Register */
#define REG_DMAC_SADDR0 (*(RwReg*)0x400C003CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 0) */
#define REG_DMAC_DADDR0 (*(RwReg*)0x400C0040U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 0) */
#define REG_DMAC_DSCR0 (*(RwReg*)0x400C0044U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 0) */
#define REG_DMAC_CTRLA0 (*(RwReg*)0x400C0048U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 0) */
#define REG_DMAC_CTRLB0 (*(RwReg*)0x400C004CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 0) */
#define REG_DMAC_CFG0 (*(RwReg*)0x400C0050U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 0) */
#define REG_DMAC_SADDR1 (*(RwReg*)0x400C0064U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 1) */
#define REG_DMAC_DADDR1 (*(RwReg*)0x400C0068U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 1) */
#define REG_DMAC_DSCR1 (*(RwReg*)0x400C006CU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 1) */
#define REG_DMAC_CTRLA1 (*(RwReg*)0x400C0070U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 1) */
#define REG_DMAC_CTRLB1 (*(RwReg*)0x400C0074U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 1) */
#define REG_DMAC_CFG1 (*(RwReg*)0x400C0078U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 1) */
#define REG_DMAC_SADDR2 (*(RwReg*)0x400C008CU) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 2) */
#define REG_DMAC_DADDR2 (*(RwReg*)0x400C0090U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 2) */
#define REG_DMAC_DSCR2 (*(RwReg*)0x400C0094U) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 2) */
#define REG_DMAC_CTRLA2 (*(RwReg*)0x400C0098U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 2) */
#define REG_DMAC_CTRLB2 (*(RwReg*)0x400C009CU) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 2) */
#define REG_DMAC_CFG2 (*(RwReg*)0x400C00A0U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 2) */
#define REG_DMAC_SADDR3 (*(RwReg*)0x400C00B4U) /**< \brief (DMAC) DMAC Channel Source Address Register (ch_num = 3) */
#define REG_DMAC_DADDR3 (*(RwReg*)0x400C00B8U) /**< \brief (DMAC) DMAC Channel Destination Address Register (ch_num = 3) */
#define REG_DMAC_DSCR3 (*(RwReg*)0x400C00BCU) /**< \brief (DMAC) DMAC Channel Descriptor Address Register (ch_num = 3) */
#define REG_DMAC_CTRLA3 (*(RwReg*)0x400C00C0U) /**< \brief (DMAC) DMAC Channel Control A Register (ch_num = 3) */
#define REG_DMAC_CTRLB3 (*(RwReg*)0x400C00C4U) /**< \brief (DMAC) DMAC Channel Control B Register (ch_num = 3) */
#define REG_DMAC_CFG3 (*(RwReg*)0x400C00C8U) /**< \brief (DMAC) DMAC Channel Configuration Register (ch_num = 3) */
#define REG_DMAC_WPMR (*(RwReg*)0x400C01E4U) /**< \brief (DMAC) DMAC Write Protect Mode Register */
#define REG_DMAC_WPSR (*(RoReg*)0x400C01E8U) /**< \brief (DMAC) DMAC Write Protect Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_DMAC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_EFC_INSTANCE_
#define _SAM4E_EFC_INSTANCE_
/* ========== Register definition for EFC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_EFC_FMR (0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
#define REG_EFC_FCR (0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
#define REG_EFC_FSR (0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
#define REG_EFC_FRR (0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
#else
#define REG_EFC_FMR (*(RwReg*)0x400E0A00U) /**< \brief (EFC) EEFC Flash Mode Register */
#define REG_EFC_FCR (*(WoReg*)0x400E0A04U) /**< \brief (EFC) EEFC Flash Command Register */
#define REG_EFC_FSR (*(RoReg*)0x400E0A08U) /**< \brief (EFC) EEFC Flash Status Register */
#define REG_EFC_FRR (*(RoReg*)0x400E0A0CU) /**< \brief (EFC) EEFC Flash Result Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_EFC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_GMAC_INSTANCE_
#define _SAM4E_GMAC_INSTANCE_
/* ========== Register definition for GMAC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GMAC_NCR (0x40034000U) /**< \brief (GMAC) Network Control Register */
#define REG_GMAC_NCFGR (0x40034004U) /**< \brief (GMAC) Network Configuration Register */
#define REG_GMAC_NSR (0x40034008U) /**< \brief (GMAC) Network Status Register */
#define REG_GMAC_UR (0x4003400CU) /**< \brief (GMAC) User Register */
#define REG_GMAC_DCFGR (0x40034010U) /**< \brief (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR (0x40034014U) /**< \brief (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB (0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */
#define REG_GMAC_TBQB (0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
#define REG_GMAC_RSR (0x40034020U) /**< \brief (GMAC) Receive Status Register */
#define REG_GMAC_ISR (0x40034024U) /**< \brief (GMAC) Interrupt Status Register */
#define REG_GMAC_IER (0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR (0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR (0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN (0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ (0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ (0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_HRB (0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */
#define REG_GMAC_HRT (0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */
#define REG_GMAC_SAB1 (0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */
#define REG_GMAC_SAT1 (0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */
#define REG_GMAC_SAB2 (0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */
#define REG_GMAC_SAT2 (0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */
#define REG_GMAC_SAB3 (0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */
#define REG_GMAC_SAT3 (0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */
#define REG_GMAC_SAB4 (0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */
#define REG_GMAC_SAT4 (0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */
#define REG_GMAC_TIDM (0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */
#define REG_GMAC_IPGS (0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN (0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP (0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1 (0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
#define REG_GMAC_SAMT1 (0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
#define REG_GMAC_OTLO (0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
#define REG_GMAC_OTHI (0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
#define REG_GMAC_FT (0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT (0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT (0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT (0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64 (0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127 (0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255 (0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511 (0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023 (0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518 (0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518 (0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR (0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */
#define REG_GMAC_SCF (0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF (0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC (0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC (0x40034144U) /**< \brief (GMAC) Late Collisions Register */
#define REG_GMAC_DTF (0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE (0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO (0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */
#define REG_GMAC_ORHI (0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */
#define REG_GMAC_FR (0x40034158U) /**< \brief (GMAC) Frames Received Register */
#define REG_GMAC_BCFR (0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR (0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR (0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64 (0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127 (0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255 (0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511 (0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
#define REG_GMAC_TBFR1023 (0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518 (0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR (0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR (0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR (0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR (0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE (0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE (0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE (0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE (0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE (0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE (0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE (0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE (0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE (0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TSSS (0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */
#define REG_GMAC_TSSN (0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
#define REG_GMAC_TS (0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */
#define REG_GMAC_TN (0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA (0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI (0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTS (0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */
#define REG_GMAC_EFTN (0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
#define REG_GMAC_EFRS (0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */
#define REG_GMAC_EFRN (0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
#define REG_GMAC_PEFTS (0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */
#define REG_GMAC_PEFTN (0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
#define REG_GMAC_PEFRS (0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */
#define REG_GMAC_PEFRN (0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
#else
#define REG_GMAC_NCR (*(RwReg*)0x40034000U) /**< \brief (GMAC) Network Control Register */
#define REG_GMAC_NCFGR (*(RwReg*)0x40034004U) /**< \brief (GMAC) Network Configuration Register */
#define REG_GMAC_NSR (*(RoReg*)0x40034008U) /**< \brief (GMAC) Network Status Register */
#define REG_GMAC_UR (*(RwReg*)0x4003400CU) /**< \brief (GMAC) User Register */
#define REG_GMAC_DCFGR (*(RwReg*)0x40034010U) /**< \brief (GMAC) DMA Configuration Register */
#define REG_GMAC_TSR (*(RwReg*)0x40034014U) /**< \brief (GMAC) Transmit Status Register */
#define REG_GMAC_RBQB (*(RwReg*)0x40034018U) /**< \brief (GMAC) Receive Buffer Queue Base Address */
#define REG_GMAC_TBQB (*(RwReg*)0x4003401CU) /**< \brief (GMAC) Transmit Buffer Queue Base Address */
#define REG_GMAC_RSR (*(RwReg*)0x40034020U) /**< \brief (GMAC) Receive Status Register */
#define REG_GMAC_ISR (*(RoReg*)0x40034024U) /**< \brief (GMAC) Interrupt Status Register */
#define REG_GMAC_IER (*(WoReg*)0x40034028U) /**< \brief (GMAC) Interrupt Enable Register */
#define REG_GMAC_IDR (*(WoReg*)0x4003402CU) /**< \brief (GMAC) Interrupt Disable Register */
#define REG_GMAC_IMR (*(RoReg*)0x40034030U) /**< \brief (GMAC) Interrupt Mask Register */
#define REG_GMAC_MAN (*(RwReg*)0x40034034U) /**< \brief (GMAC) PHY Maintenance Register */
#define REG_GMAC_RPQ (*(RoReg*)0x40034038U) /**< \brief (GMAC) Received Pause Quantum Register */
#define REG_GMAC_TPQ (*(RwReg*)0x4003403CU) /**< \brief (GMAC) Transmit Pause Quantum Register */
#define REG_GMAC_HRB (*(RwReg*)0x40034080U) /**< \brief (GMAC) Hash Register Bottom [31:0] */
#define REG_GMAC_HRT (*(RwReg*)0x40034084U) /**< \brief (GMAC) Hash Register Top [63:32] */
#define REG_GMAC_SAB1 (*(RwReg*)0x40034088U) /**< \brief (GMAC) Specific Address 1 Bottom [31:0] Register */
#define REG_GMAC_SAT1 (*(RwReg*)0x4003408CU) /**< \brief (GMAC) Specific Address 1 Top [47:32] Register */
#define REG_GMAC_SAB2 (*(RwReg*)0x40034090U) /**< \brief (GMAC) Specific Address 2 Bottom [31:0] Register */
#define REG_GMAC_SAT2 (*(RwReg*)0x40034094U) /**< \brief (GMAC) Specific Address 2 Top [47:32] Register */
#define REG_GMAC_SAB3 (*(RwReg*)0x40034098U) /**< \brief (GMAC) Specific Address 3 Bottom [31:0] Register */
#define REG_GMAC_SAT3 (*(RwReg*)0x4003409CU) /**< \brief (GMAC) Specific Address 3 Top [47:32] Register */
#define REG_GMAC_SAB4 (*(RwReg*)0x400340A0U) /**< \brief (GMAC) Specific Address 4 Bottom [31:0] Register */
#define REG_GMAC_SAT4 (*(RwReg*)0x400340A4U) /**< \brief (GMAC) Specific Address 4 Top [47:32] Register */
#define REG_GMAC_TIDM (*(RwReg*)0x400340A8U) /**< \brief (GMAC) Type ID Match 1 Register */
#define REG_GMAC_IPGS (*(RwReg*)0x400340BCU) /**< \brief (GMAC) IPG Stretch Register */
#define REG_GMAC_SVLAN (*(RwReg*)0x400340C0U) /**< \brief (GMAC) Stacked VLAN Register */
#define REG_GMAC_TPFCP (*(RwReg*)0x400340C4U) /**< \brief (GMAC) Transmit PFC Pause Register */
#define REG_GMAC_SAMB1 (*(RwReg*)0x400340C8U) /**< \brief (GMAC) Specific Address 1 Mask Bottom [31:0] Register */
#define REG_GMAC_SAMT1 (*(RwReg*)0x400340CCU) /**< \brief (GMAC) Specific Address 1 Mask Top [47:32] Register */
#define REG_GMAC_OTLO (*(RoReg*)0x40034100U) /**< \brief (GMAC) Octets Transmitted [31:0] Register */
#define REG_GMAC_OTHI (*(RoReg*)0x40034104U) /**< \brief (GMAC) Octets Transmitted [47:32] Register */
#define REG_GMAC_FT (*(RoReg*)0x40034108U) /**< \brief (GMAC) Frames Transmitted Register */
#define REG_GMAC_BCFT (*(RoReg*)0x4003410CU) /**< \brief (GMAC) Broadcast Frames Transmitted Register */
#define REG_GMAC_MFT (*(RoReg*)0x40034110U) /**< \brief (GMAC) Multicast Frames Transmitted Register */
#define REG_GMAC_PFT (*(RoReg*)0x40034114U) /**< \brief (GMAC) Pause Frames Transmitted Register */
#define REG_GMAC_BFT64 (*(RoReg*)0x40034118U) /**< \brief (GMAC) 64 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT127 (*(RoReg*)0x4003411CU) /**< \brief (GMAC) 65 to 127 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT255 (*(RoReg*)0x40034120U) /**< \brief (GMAC) 128 to 255 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT511 (*(RoReg*)0x40034124U) /**< \brief (GMAC) 256 to 511 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1023 (*(RoReg*)0x40034128U) /**< \brief (GMAC) 512 to 1023 Byte Frames Transmitted Register */
#define REG_GMAC_TBFT1518 (*(RoReg*)0x4003412CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
#define REG_GMAC_GTBFT1518 (*(RoReg*)0x40034130U) /**< \brief (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
#define REG_GMAC_TUR (*(RoReg*)0x40034134U) /**< \brief (GMAC) Transmit Under Runs Register */
#define REG_GMAC_SCF (*(RoReg*)0x40034138U) /**< \brief (GMAC) Single Collision Frames Register */
#define REG_GMAC_MCF (*(RoReg*)0x4003413CU) /**< \brief (GMAC) Multiple Collision Frames Register */
#define REG_GMAC_EC (*(RoReg*)0x40034140U) /**< \brief (GMAC) Excessive Collisions Register */
#define REG_GMAC_LC (*(RoReg*)0x40034144U) /**< \brief (GMAC) Late Collisions Register */
#define REG_GMAC_DTF (*(RoReg*)0x40034148U) /**< \brief (GMAC) Deferred Transmission Frames Register */
#define REG_GMAC_CSE (*(RoReg*)0x4003414CU) /**< \brief (GMAC) Carrier Sense Errors Register */
#define REG_GMAC_ORLO (*(RoReg*)0x40034150U) /**< \brief (GMAC) Octets Received [31:0] Received */
#define REG_GMAC_ORHI (*(RoReg*)0x40034154U) /**< \brief (GMAC) Octets Received [47:32] Received */
#define REG_GMAC_FR (*(RoReg*)0x40034158U) /**< \brief (GMAC) Frames Received Register */
#define REG_GMAC_BCFR (*(RoReg*)0x4003415CU) /**< \brief (GMAC) Broadcast Frames Received Register */
#define REG_GMAC_MFR (*(RoReg*)0x40034160U) /**< \brief (GMAC) Multicast Frames Received Register */
#define REG_GMAC_PFR (*(RoReg*)0x40034164U) /**< \brief (GMAC) Pause Frames Received Register */
#define REG_GMAC_BFR64 (*(RoReg*)0x40034168U) /**< \brief (GMAC) 64 Byte Frames Received Register */
#define REG_GMAC_TBFR127 (*(RoReg*)0x4003416CU) /**< \brief (GMAC) 65 to 127 Byte Frames Received Register */
#define REG_GMAC_TBFR255 (*(RoReg*)0x40034170U) /**< \brief (GMAC) 128 to 255 Byte Frames Received Register */
#define REG_GMAC_TBFR511 (*(RoReg*)0x40034174U) /**< \brief (GMAC) 256 to 511Byte Frames Received Register */
#define REG_GMAC_TBFR1023 (*(RoReg*)0x40034178U) /**< \brief (GMAC) 512 to 1023 Byte Frames Received Register */
#define REG_GMAC_TBFR1518 (*(RoReg*)0x4003417CU) /**< \brief (GMAC) 1024 to 1518 Byte Frames Received Register */
#define REG_GMAC_TMXBFR (*(RoReg*)0x40034180U) /**< \brief (GMAC) 1519 to Maximum Byte Frames Received Register */
#define REG_GMAC_UFR (*(RoReg*)0x40034184U) /**< \brief (GMAC) Undersize Frames Received Register */
#define REG_GMAC_OFR (*(RoReg*)0x40034188U) /**< \brief (GMAC) Oversize Frames Received Register */
#define REG_GMAC_JR (*(RoReg*)0x4003418CU) /**< \brief (GMAC) Jabbers Received Register */
#define REG_GMAC_FCSE (*(RoReg*)0x40034190U) /**< \brief (GMAC) Frame Check Sequence Errors Register */
#define REG_GMAC_LFFE (*(RoReg*)0x40034194U) /**< \brief (GMAC) Length Field Frame Errors Register */
#define REG_GMAC_RSE (*(RoReg*)0x40034198U) /**< \brief (GMAC) Receive Symbol Errors Register */
#define REG_GMAC_AE (*(RoReg*)0x4003419CU) /**< \brief (GMAC) Alignment Errors Register */
#define REG_GMAC_RRE (*(RoReg*)0x400341A0U) /**< \brief (GMAC) Receive Resource Errors Register */
#define REG_GMAC_ROE (*(RoReg*)0x400341A4U) /**< \brief (GMAC) Receive Overrun Register */
#define REG_GMAC_IHCE (*(RoReg*)0x400341A8U) /**< \brief (GMAC) IP Header Checksum Errors Register */
#define REG_GMAC_TCE (*(RoReg*)0x400341ACU) /**< \brief (GMAC) TCP Checksum Errors Register */
#define REG_GMAC_UCE (*(RoReg*)0x400341B0U) /**< \brief (GMAC) UDP Checksum Errors Register */
#define REG_GMAC_TSSS (*(RwReg*)0x400341C8U) /**< \brief (GMAC) 1588 Timer Sync Strobe Seconds Register */
#define REG_GMAC_TSSN (*(RwReg*)0x400341CCU) /**< \brief (GMAC) 1588 Timer Sync Strobe Nanoseconds Register */
#define REG_GMAC_TS (*(RwReg*)0x400341D0U) /**< \brief (GMAC) 1588 Timer Seconds Register */
#define REG_GMAC_TN (*(RwReg*)0x400341D4U) /**< \brief (GMAC) 1588 Timer Nanoseconds Register */
#define REG_GMAC_TA (*(WoReg*)0x400341D8U) /**< \brief (GMAC) 1588 Timer Adjust Register */
#define REG_GMAC_TI (*(RwReg*)0x400341DCU) /**< \brief (GMAC) 1588 Timer Increment Register */
#define REG_GMAC_EFTS (*(RoReg*)0x400341E0U) /**< \brief (GMAC) PTP Event Frame Transmitted Seconds */
#define REG_GMAC_EFTN (*(RoReg*)0x400341E4U) /**< \brief (GMAC) PTP Event Frame Transmitted Nanoseconds */
#define REG_GMAC_EFRS (*(RoReg*)0x400341E8U) /**< \brief (GMAC) PTP Event Frame Received Seconds */
#define REG_GMAC_EFRN (*(RoReg*)0x400341ECU) /**< \brief (GMAC) PTP Event Frame Received Nanoseconds */
#define REG_GMAC_PEFTS (*(RoReg*)0x400341F0U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Seconds */
#define REG_GMAC_PEFTN (*(RoReg*)0x400341F4U) /**< \brief (GMAC) PTP Peer Event Frame Transmitted Nanoseconds */
#define REG_GMAC_PEFRS (*(RoReg*)0x400341F8U) /**< \brief (GMAC) PTP Peer Event Frame Received Seconds */
#define REG_GMAC_PEFRN (*(RoReg*)0x400341FCU) /**< \brief (GMAC) PTP Peer Event Frame Received Nanoseconds */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_GMAC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_GPBR_INSTANCE_
#define _SAM4E_GPBR_INSTANCE_
/* ========== Register definition for GPBR peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_GPBR_GPBR (0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
#else
#define REG_GPBR_GPBR (*(RwReg*)0x400E1890U) /**< \brief (GPBR) General Purpose Backup Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_GPBR_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_HSMCI_INSTANCE_
#define _SAM4E_HSMCI_INSTANCE_
/* ========== Register definition for HSMCI peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_HSMCI_CR (0x40080000U) /**< \brief (HSMCI) Control Register */
#define REG_HSMCI_MR (0x40080004U) /**< \brief (HSMCI) Mode Register */
#define REG_HSMCI_DTOR (0x40080008U) /**< \brief (HSMCI) Data Timeout Register */
#define REG_HSMCI_SDCR (0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
#define REG_HSMCI_ARGR (0x40080010U) /**< \brief (HSMCI) Argument Register */
#define REG_HSMCI_CMDR (0x40080014U) /**< \brief (HSMCI) Command Register */
#define REG_HSMCI_BLKR (0x40080018U) /**< \brief (HSMCI) Block Register */
#define REG_HSMCI_CSTOR (0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
#define REG_HSMCI_RSPR (0x40080020U) /**< \brief (HSMCI) Response Register */
#define REG_HSMCI_RDR (0x40080030U) /**< \brief (HSMCI) Receive Data Register */
#define REG_HSMCI_TDR (0x40080034U) /**< \brief (HSMCI) Transmit Data Register */
#define REG_HSMCI_SR (0x40080040U) /**< \brief (HSMCI) Status Register */
#define REG_HSMCI_IER (0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */
#define REG_HSMCI_IDR (0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */
#define REG_HSMCI_IMR (0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */
#define REG_HSMCI_CFG (0x40080054U) /**< \brief (HSMCI) Configuration Register */
#define REG_HSMCI_WPMR (0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */
#define REG_HSMCI_WPSR (0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */
#define REG_HSMCI_RPR (0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */
#define REG_HSMCI_RCR (0x40080104U) /**< \brief (HSMCI) Receive Counter Register */
#define REG_HSMCI_TPR (0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */
#define REG_HSMCI_TCR (0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */
#define REG_HSMCI_RNPR (0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */
#define REG_HSMCI_RNCR (0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */
#define REG_HSMCI_TNPR (0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
#define REG_HSMCI_TNCR (0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
#define REG_HSMCI_PTCR (0x40080120U) /**< \brief (HSMCI) Transfer Control Register */
#define REG_HSMCI_PTSR (0x40080124U) /**< \brief (HSMCI) Transfer Status Register */
#define REG_HSMCI_FIFO (0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
#else
#define REG_HSMCI_CR (*(WoReg*)0x40080000U) /**< \brief (HSMCI) Control Register */
#define REG_HSMCI_MR (*(RwReg*)0x40080004U) /**< \brief (HSMCI) Mode Register */
#define REG_HSMCI_DTOR (*(RwReg*)0x40080008U) /**< \brief (HSMCI) Data Timeout Register */
#define REG_HSMCI_SDCR (*(RwReg*)0x4008000CU) /**< \brief (HSMCI) SD/SDIO Card Register */
#define REG_HSMCI_ARGR (*(RwReg*)0x40080010U) /**< \brief (HSMCI) Argument Register */
#define REG_HSMCI_CMDR (*(WoReg*)0x40080014U) /**< \brief (HSMCI) Command Register */
#define REG_HSMCI_BLKR (*(RwReg*)0x40080018U) /**< \brief (HSMCI) Block Register */
#define REG_HSMCI_CSTOR (*(RwReg*)0x4008001CU) /**< \brief (HSMCI) Completion Signal Timeout Register */
#define REG_HSMCI_RSPR (*(RoReg*)0x40080020U) /**< \brief (HSMCI) Response Register */
#define REG_HSMCI_RDR (*(RoReg*)0x40080030U) /**< \brief (HSMCI) Receive Data Register */
#define REG_HSMCI_TDR (*(WoReg*)0x40080034U) /**< \brief (HSMCI) Transmit Data Register */
#define REG_HSMCI_SR (*(RoReg*)0x40080040U) /**< \brief (HSMCI) Status Register */
#define REG_HSMCI_IER (*(WoReg*)0x40080044U) /**< \brief (HSMCI) Interrupt Enable Register */
#define REG_HSMCI_IDR (*(WoReg*)0x40080048U) /**< \brief (HSMCI) Interrupt Disable Register */
#define REG_HSMCI_IMR (*(RoReg*)0x4008004CU) /**< \brief (HSMCI) Interrupt Mask Register */
#define REG_HSMCI_CFG (*(RwReg*)0x40080054U) /**< \brief (HSMCI) Configuration Register */
#define REG_HSMCI_WPMR (*(RwReg*)0x400800E4U) /**< \brief (HSMCI) Write Protection Mode Register */
#define REG_HSMCI_WPSR (*(RoReg*)0x400800E8U) /**< \brief (HSMCI) Write Protection Status Register */
#define REG_HSMCI_RPR (*(RwReg*)0x40080100U) /**< \brief (HSMCI) Receive Pointer Register */
#define REG_HSMCI_RCR (*(RwReg*)0x40080104U) /**< \brief (HSMCI) Receive Counter Register */
#define REG_HSMCI_TPR (*(RwReg*)0x40080108U) /**< \brief (HSMCI) Transmit Pointer Register */
#define REG_HSMCI_TCR (*(RwReg*)0x4008010CU) /**< \brief (HSMCI) Transmit Counter Register */
#define REG_HSMCI_RNPR (*(RwReg*)0x40080110U) /**< \brief (HSMCI) Receive Next Pointer Register */
#define REG_HSMCI_RNCR (*(RwReg*)0x40080114U) /**< \brief (HSMCI) Receive Next Counter Register */
#define REG_HSMCI_TNPR (*(RwReg*)0x40080118U) /**< \brief (HSMCI) Transmit Next Pointer Register */
#define REG_HSMCI_TNCR (*(RwReg*)0x4008011CU) /**< \brief (HSMCI) Transmit Next Counter Register */
#define REG_HSMCI_PTCR (*(WoReg*)0x40080120U) /**< \brief (HSMCI) Transfer Control Register */
#define REG_HSMCI_PTSR (*(RoReg*)0x40080124U) /**< \brief (HSMCI) Transfer Status Register */
#define REG_HSMCI_FIFO (*(RwReg*)0x40080200U) /**< \brief (HSMCI) FIFO Memory Aperture0 */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_HSMCI_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_MATRIX_INSTANCE_
#define _SAM4E_MATRIX_INSTANCE_
/* ========== Register definition for MATRIX peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_MATRIX_MCFG (0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
#define REG_MATRIX_SCFG (0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
#define REG_MATRIX_PRAS0 (0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0 (0x400E0284U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1 (0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1 (0x400E028CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2 (0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2 (0x400E0294U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3 (0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3 (0x400E029CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4 (0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4 (0x400E02A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5 (0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5 (0x400E02ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6 (0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6 (0x400E02B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7 (0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7 (0x400E02BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8 (0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8 (0x400E02C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_PRAS9 (0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
#define REG_MATRIX_PRBS9 (0x400E02CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
#define REG_MATRIX_PRAS10 (0x400E02D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
#define REG_MATRIX_PRBS10 (0x400E02D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
#define REG_MATRIX_PRAS11 (0x400E02D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
#define REG_MATRIX_PRBS11 (0x400E02DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
#define REG_MATRIX_PRAS12 (0x400E02E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
#define REG_MATRIX_PRBS12 (0x400E02E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
#define REG_MATRIX_PRAS13 (0x400E02E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
#define REG_MATRIX_PRBS13 (0x400E02ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
#define REG_MATRIX_PRAS14 (0x400E02F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
#define REG_MATRIX_PRBS14 (0x400E02F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
#define REG_MATRIX_PRAS15 (0x400E02F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
#define REG_MATRIX_PRBS15 (0x400E02FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
#define REG_MATRIX_MRCR (0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
#define REG_MATRIX_SFR (0x400E0310U) /**< \brief (MATRIX) Special Function Register */
#define REG_MATRIX_WPMR (0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
#define REG_MATRIX_WPSR (0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
#else
#define REG_MATRIX_MCFG (*(RwReg*)0x400E0200U) /**< \brief (MATRIX) Master Configuration Register */
#define REG_MATRIX_SCFG (*(RwReg*)0x400E0240U) /**< \brief (MATRIX) Slave Configuration Register */
#define REG_MATRIX_PRAS0 (*(RwReg*)0x400E0280U) /**< \brief (MATRIX) Priority Register A for Slave 0 */
#define REG_MATRIX_PRBS0 (*(RwReg*)0x400E0284U) /**< \brief (MATRIX) Priority Register B for Slave 0 */
#define REG_MATRIX_PRAS1 (*(RwReg*)0x400E0288U) /**< \brief (MATRIX) Priority Register A for Slave 1 */
#define REG_MATRIX_PRBS1 (*(RwReg*)0x400E028CU) /**< \brief (MATRIX) Priority Register B for Slave 1 */
#define REG_MATRIX_PRAS2 (*(RwReg*)0x400E0290U) /**< \brief (MATRIX) Priority Register A for Slave 2 */
#define REG_MATRIX_PRBS2 (*(RwReg*)0x400E0294U) /**< \brief (MATRIX) Priority Register B for Slave 2 */
#define REG_MATRIX_PRAS3 (*(RwReg*)0x400E0298U) /**< \brief (MATRIX) Priority Register A for Slave 3 */
#define REG_MATRIX_PRBS3 (*(RwReg*)0x400E029CU) /**< \brief (MATRIX) Priority Register B for Slave 3 */
#define REG_MATRIX_PRAS4 (*(RwReg*)0x400E02A0U) /**< \brief (MATRIX) Priority Register A for Slave 4 */
#define REG_MATRIX_PRBS4 (*(RwReg*)0x400E02A4U) /**< \brief (MATRIX) Priority Register B for Slave 4 */
#define REG_MATRIX_PRAS5 (*(RwReg*)0x400E02A8U) /**< \brief (MATRIX) Priority Register A for Slave 5 */
#define REG_MATRIX_PRBS5 (*(RwReg*)0x400E02ACU) /**< \brief (MATRIX) Priority Register B for Slave 5 */
#define REG_MATRIX_PRAS6 (*(RwReg*)0x400E02B0U) /**< \brief (MATRIX) Priority Register A for Slave 6 */
#define REG_MATRIX_PRBS6 (*(RwReg*)0x400E02B4U) /**< \brief (MATRIX) Priority Register B for Slave 6 */
#define REG_MATRIX_PRAS7 (*(RwReg*)0x400E02B8U) /**< \brief (MATRIX) Priority Register A for Slave 7 */
#define REG_MATRIX_PRBS7 (*(RwReg*)0x400E02BCU) /**< \brief (MATRIX) Priority Register B for Slave 7 */
#define REG_MATRIX_PRAS8 (*(RwReg*)0x400E02C0U) /**< \brief (MATRIX) Priority Register A for Slave 8 */
#define REG_MATRIX_PRBS8 (*(RwReg*)0x400E02C4U) /**< \brief (MATRIX) Priority Register B for Slave 8 */
#define REG_MATRIX_PRAS9 (*(RwReg*)0x400E02C8U) /**< \brief (MATRIX) Priority Register A for Slave 9 */
#define REG_MATRIX_PRBS9 (*(RwReg*)0x400E02CCU) /**< \brief (MATRIX) Priority Register B for Slave 9 */
#define REG_MATRIX_PRAS10 (*(RwReg*)0x400E02D0U) /**< \brief (MATRIX) Priority Register A for Slave 10 */
#define REG_MATRIX_PRBS10 (*(RwReg*)0x400E02D4U) /**< \brief (MATRIX) Priority Register B for Slave 10 */
#define REG_MATRIX_PRAS11 (*(RwReg*)0x400E02D8U) /**< \brief (MATRIX) Priority Register A for Slave 11 */
#define REG_MATRIX_PRBS11 (*(RwReg*)0x400E02DCU) /**< \brief (MATRIX) Priority Register B for Slave 11 */
#define REG_MATRIX_PRAS12 (*(RwReg*)0x400E02E0U) /**< \brief (MATRIX) Priority Register A for Slave 12 */
#define REG_MATRIX_PRBS12 (*(RwReg*)0x400E02E4U) /**< \brief (MATRIX) Priority Register B for Slave 12 */
#define REG_MATRIX_PRAS13 (*(RwReg*)0x400E02E8U) /**< \brief (MATRIX) Priority Register A for Slave 13 */
#define REG_MATRIX_PRBS13 (*(RwReg*)0x400E02ECU) /**< \brief (MATRIX) Priority Register B for Slave 13 */
#define REG_MATRIX_PRAS14 (*(RwReg*)0x400E02F0U) /**< \brief (MATRIX) Priority Register A for Slave 14 */
#define REG_MATRIX_PRBS14 (*(RwReg*)0x400E02F4U) /**< \brief (MATRIX) Priority Register B for Slave 14 */
#define REG_MATRIX_PRAS15 (*(RwReg*)0x400E02F8U) /**< \brief (MATRIX) Priority Register A for Slave 15 */
#define REG_MATRIX_PRBS15 (*(RwReg*)0x400E02FCU) /**< \brief (MATRIX) Priority Register B for Slave 15 */
#define REG_MATRIX_MRCR (*(RwReg*)0x400E0300U) /**< \brief (MATRIX) Master Remap Control Register */
#define REG_MATRIX_SFR (*(RwReg*)0x400E0310U) /**< \brief (MATRIX) Special Function Register */
#define REG_MATRIX_WPMR (*(RwReg*)0x400E03E4U) /**< \brief (MATRIX) Write Protect Mode Register */
#define REG_MATRIX_WPSR (*(RoReg*)0x400E03E8U) /**< \brief (MATRIX) Write Protect Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_MATRIX_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PIOA_INSTANCE_
#define _SAM4E_PIOA_INSTANCE_
/* ========== Register definition for PIOA peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOA_PER (0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
#define REG_PIOA_PDR (0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
#define REG_PIOA_PSR (0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
#define REG_PIOA_OER (0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
#define REG_PIOA_ODR (0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
#define REG_PIOA_OSR (0x400E0E18U) /**< \brief (PIOA) Output Status Register */
#define REG_PIOA_IFER (0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR (0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR (0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR (0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
#define REG_PIOA_CODR (0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR (0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR (0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
#define REG_PIOA_IER (0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR (0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR (0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR (0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER (0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR (0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR (0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR (0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER (0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR (0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR (0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
#define REG_PIOA_IFSCDR (0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER (0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR (0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR (0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR (0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER (0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR (0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER (0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
#define REG_PIOA_OWDR (0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
#define REG_PIOA_OWSR (0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER (0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR (0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
#define REG_PIOA_AIMMR (0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR (0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
#define REG_PIOA_LSR (0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
#define REG_PIOA_ELSR (0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR (0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
#define REG_PIOA_REHLSR (0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
#define REG_PIOA_FRLHSR (0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR (0x400E0EE0U) /**< \brief (PIOA) Lock Status */
#define REG_PIOA_WPMR (0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
#define REG_PIOA_WPSR (0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
#define REG_PIOA_SCHMITT (0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DELAYR (0x400E0F10U) /**< \brief (PIOA) IO Delay Register */
#define REG_PIOA_PCMR (0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
#define REG_PIOA_PCIER (0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
#define REG_PIOA_PCIDR (0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
#define REG_PIOA_PCIMR (0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
#define REG_PIOA_PCISR (0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
#define REG_PIOA_PCRHR (0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
#define REG_PIOA_RPR (0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
#define REG_PIOA_RCR (0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
#define REG_PIOA_RNPR (0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
#define REG_PIOA_RNCR (0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
#define REG_PIOA_PTCR (0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
#define REG_PIOA_PTSR (0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
#else
#define REG_PIOA_PER (*(WoReg*)0x400E0E00U) /**< \brief (PIOA) PIO Enable Register */
#define REG_PIOA_PDR (*(WoReg*)0x400E0E04U) /**< \brief (PIOA) PIO Disable Register */
#define REG_PIOA_PSR (*(RoReg*)0x400E0E08U) /**< \brief (PIOA) PIO Status Register */
#define REG_PIOA_OER (*(WoReg*)0x400E0E10U) /**< \brief (PIOA) Output Enable Register */
#define REG_PIOA_ODR (*(WoReg*)0x400E0E14U) /**< \brief (PIOA) Output Disable Register */
#define REG_PIOA_OSR (*(RoReg*)0x400E0E18U) /**< \brief (PIOA) Output Status Register */
#define REG_PIOA_IFER (*(WoReg*)0x400E0E20U) /**< \brief (PIOA) Glitch Input Filter Enable Register */
#define REG_PIOA_IFDR (*(WoReg*)0x400E0E24U) /**< \brief (PIOA) Glitch Input Filter Disable Register */
#define REG_PIOA_IFSR (*(RoReg*)0x400E0E28U) /**< \brief (PIOA) Glitch Input Filter Status Register */
#define REG_PIOA_SODR (*(WoReg*)0x400E0E30U) /**< \brief (PIOA) Set Output Data Register */
#define REG_PIOA_CODR (*(WoReg*)0x400E0E34U) /**< \brief (PIOA) Clear Output Data Register */
#define REG_PIOA_ODSR (*(RwReg*)0x400E0E38U) /**< \brief (PIOA) Output Data Status Register */
#define REG_PIOA_PDSR (*(RoReg*)0x400E0E3CU) /**< \brief (PIOA) Pin Data Status Register */
#define REG_PIOA_IER (*(WoReg*)0x400E0E40U) /**< \brief (PIOA) Interrupt Enable Register */
#define REG_PIOA_IDR (*(WoReg*)0x400E0E44U) /**< \brief (PIOA) Interrupt Disable Register */
#define REG_PIOA_IMR (*(RoReg*)0x400E0E48U) /**< \brief (PIOA) Interrupt Mask Register */
#define REG_PIOA_ISR (*(RoReg*)0x400E0E4CU) /**< \brief (PIOA) Interrupt Status Register */
#define REG_PIOA_MDER (*(WoReg*)0x400E0E50U) /**< \brief (PIOA) Multi-driver Enable Register */
#define REG_PIOA_MDDR (*(WoReg*)0x400E0E54U) /**< \brief (PIOA) Multi-driver Disable Register */
#define REG_PIOA_MDSR (*(RoReg*)0x400E0E58U) /**< \brief (PIOA) Multi-driver Status Register */
#define REG_PIOA_PUDR (*(WoReg*)0x400E0E60U) /**< \brief (PIOA) Pull-up Disable Register */
#define REG_PIOA_PUER (*(WoReg*)0x400E0E64U) /**< \brief (PIOA) Pull-up Enable Register */
#define REG_PIOA_PUSR (*(RoReg*)0x400E0E68U) /**< \brief (PIOA) Pad Pull-up Status Register */
#define REG_PIOA_ABCDSR (*(RwReg*)0x400E0E70U) /**< \brief (PIOA) Peripheral Select Register */
#define REG_PIOA_IFSCDR (*(WoReg*)0x400E0E80U) /**< \brief (PIOA) Input Filter Slow Clock Disable Register */
#define REG_PIOA_IFSCER (*(WoReg*)0x400E0E84U) /**< \brief (PIOA) Input Filter Slow Clock Enable Register */
#define REG_PIOA_IFSCSR (*(RoReg*)0x400E0E88U) /**< \brief (PIOA) Input Filter Slow Clock Status Register */
#define REG_PIOA_SCDR (*(RwReg*)0x400E0E8CU) /**< \brief (PIOA) Slow Clock Divider Debouncing Register */
#define REG_PIOA_PPDDR (*(WoReg*)0x400E0E90U) /**< \brief (PIOA) Pad Pull-down Disable Register */
#define REG_PIOA_PPDER (*(WoReg*)0x400E0E94U) /**< \brief (PIOA) Pad Pull-down Enable Register */
#define REG_PIOA_PPDSR (*(RoReg*)0x400E0E98U) /**< \brief (PIOA) Pad Pull-down Status Register */
#define REG_PIOA_OWER (*(WoReg*)0x400E0EA0U) /**< \brief (PIOA) Output Write Enable */
#define REG_PIOA_OWDR (*(WoReg*)0x400E0EA4U) /**< \brief (PIOA) Output Write Disable */
#define REG_PIOA_OWSR (*(RoReg*)0x400E0EA8U) /**< \brief (PIOA) Output Write Status Register */
#define REG_PIOA_AIMER (*(WoReg*)0x400E0EB0U) /**< \brief (PIOA) Additional Interrupt Modes Enable Register */
#define REG_PIOA_AIMDR (*(WoReg*)0x400E0EB4U) /**< \brief (PIOA) Additional Interrupt Modes Disables Register */
#define REG_PIOA_AIMMR (*(RoReg*)0x400E0EB8U) /**< \brief (PIOA) Additional Interrupt Modes Mask Register */
#define REG_PIOA_ESR (*(WoReg*)0x400E0EC0U) /**< \brief (PIOA) Edge Select Register */
#define REG_PIOA_LSR (*(WoReg*)0x400E0EC4U) /**< \brief (PIOA) Level Select Register */
#define REG_PIOA_ELSR (*(RoReg*)0x400E0EC8U) /**< \brief (PIOA) Edge/Level Status Register */
#define REG_PIOA_FELLSR (*(WoReg*)0x400E0ED0U) /**< \brief (PIOA) Falling Edge/Low Level Select Register */
#define REG_PIOA_REHLSR (*(WoReg*)0x400E0ED4U) /**< \brief (PIOA) Rising Edge/ High Level Select Register */
#define REG_PIOA_FRLHSR (*(RoReg*)0x400E0ED8U) /**< \brief (PIOA) Fall/Rise - Low/High Status Register */
#define REG_PIOA_LOCKSR (*(RoReg*)0x400E0EE0U) /**< \brief (PIOA) Lock Status */
#define REG_PIOA_WPMR (*(RwReg*)0x400E0EE4U) /**< \brief (PIOA) Write Protect Mode Register */
#define REG_PIOA_WPSR (*(RoReg*)0x400E0EE8U) /**< \brief (PIOA) Write Protect Status Register */
#define REG_PIOA_SCHMITT (*(RwReg*)0x400E0F00U) /**< \brief (PIOA) Schmitt Trigger Register */
#define REG_PIOA_DELAYR (*(RwReg*)0x400E0F10U) /**< \brief (PIOA) IO Delay Register */
#define REG_PIOA_PCMR (*(RwReg*)0x400E0F50U) /**< \brief (PIOA) Parallel Capture Mode Register */
#define REG_PIOA_PCIER (*(WoReg*)0x400E0F54U) /**< \brief (PIOA) Parallel Capture Interrupt Enable Register */
#define REG_PIOA_PCIDR (*(WoReg*)0x400E0F58U) /**< \brief (PIOA) Parallel Capture Interrupt Disable Register */
#define REG_PIOA_PCIMR (*(RoReg*)0x400E0F5CU) /**< \brief (PIOA) Parallel Capture Interrupt Mask Register */
#define REG_PIOA_PCISR (*(RoReg*)0x400E0F60U) /**< \brief (PIOA) Parallel Capture Interrupt Status Register */
#define REG_PIOA_PCRHR (*(RoReg*)0x400E0F64U) /**< \brief (PIOA) Parallel Capture Reception Holding Register */
#define REG_PIOA_RPR (*(RwReg*)0x400E0F68U) /**< \brief (PIOA) Receive Pointer Register */
#define REG_PIOA_RCR (*(RwReg*)0x400E0F6CU) /**< \brief (PIOA) Receive Counter Register */
#define REG_PIOA_RNPR (*(RwReg*)0x400E0F78U) /**< \brief (PIOA) Receive Next Pointer Register */
#define REG_PIOA_RNCR (*(RwReg*)0x400E0F7CU) /**< \brief (PIOA) Receive Next Counter Register */
#define REG_PIOA_PTCR (*(WoReg*)0x400E0F88U) /**< \brief (PIOA) Transfer Control Register */
#define REG_PIOA_PTSR (*(RoReg*)0x400E0F8CU) /**< \brief (PIOA) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PIOA_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PIOB_INSTANCE_
#define _SAM4E_PIOB_INSTANCE_
/* ========== Register definition for PIOB peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOB_PER (0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
#define REG_PIOB_PDR (0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
#define REG_PIOB_PSR (0x400E1008U) /**< \brief (PIOB) PIO Status Register */
#define REG_PIOB_OER (0x400E1010U) /**< \brief (PIOB) Output Enable Register */
#define REG_PIOB_ODR (0x400E1014U) /**< \brief (PIOB) Output Disable Register */
#define REG_PIOB_OSR (0x400E1018U) /**< \brief (PIOB) Output Status Register */
#define REG_PIOB_IFER (0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR (0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR (0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR (0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
#define REG_PIOB_CODR (0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR (0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR (0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
#define REG_PIOB_IER (0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR (0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR (0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR (0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER (0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR (0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR (0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR (0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER (0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR (0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR (0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
#define REG_PIOB_IFSCDR (0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER (0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR (0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR (0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR (0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER (0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR (0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER (0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
#define REG_PIOB_OWDR (0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
#define REG_PIOB_OWSR (0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER (0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR (0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
#define REG_PIOB_AIMMR (0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR (0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
#define REG_PIOB_LSR (0x400E10C4U) /**< \brief (PIOB) Level Select Register */
#define REG_PIOB_ELSR (0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR (0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
#define REG_PIOB_REHLSR (0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
#define REG_PIOB_FRLHSR (0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR (0x400E10E0U) /**< \brief (PIOB) Lock Status */
#define REG_PIOB_WPMR (0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
#define REG_PIOB_WPSR (0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
#define REG_PIOB_SCHMITT (0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DELAYR (0x400E1110U) /**< \brief (PIOB) IO Delay Register */
#define REG_PIOB_PCMR (0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
#define REG_PIOB_PCIER (0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
#define REG_PIOB_PCIDR (0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
#define REG_PIOB_PCIMR (0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
#define REG_PIOB_PCISR (0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
#define REG_PIOB_PCRHR (0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
#else
#define REG_PIOB_PER (*(WoReg*)0x400E1000U) /**< \brief (PIOB) PIO Enable Register */
#define REG_PIOB_PDR (*(WoReg*)0x400E1004U) /**< \brief (PIOB) PIO Disable Register */
#define REG_PIOB_PSR (*(RoReg*)0x400E1008U) /**< \brief (PIOB) PIO Status Register */
#define REG_PIOB_OER (*(WoReg*)0x400E1010U) /**< \brief (PIOB) Output Enable Register */
#define REG_PIOB_ODR (*(WoReg*)0x400E1014U) /**< \brief (PIOB) Output Disable Register */
#define REG_PIOB_OSR (*(RoReg*)0x400E1018U) /**< \brief (PIOB) Output Status Register */
#define REG_PIOB_IFER (*(WoReg*)0x400E1020U) /**< \brief (PIOB) Glitch Input Filter Enable Register */
#define REG_PIOB_IFDR (*(WoReg*)0x400E1024U) /**< \brief (PIOB) Glitch Input Filter Disable Register */
#define REG_PIOB_IFSR (*(RoReg*)0x400E1028U) /**< \brief (PIOB) Glitch Input Filter Status Register */
#define REG_PIOB_SODR (*(WoReg*)0x400E1030U) /**< \brief (PIOB) Set Output Data Register */
#define REG_PIOB_CODR (*(WoReg*)0x400E1034U) /**< \brief (PIOB) Clear Output Data Register */
#define REG_PIOB_ODSR (*(RwReg*)0x400E1038U) /**< \brief (PIOB) Output Data Status Register */
#define REG_PIOB_PDSR (*(RoReg*)0x400E103CU) /**< \brief (PIOB) Pin Data Status Register */
#define REG_PIOB_IER (*(WoReg*)0x400E1040U) /**< \brief (PIOB) Interrupt Enable Register */
#define REG_PIOB_IDR (*(WoReg*)0x400E1044U) /**< \brief (PIOB) Interrupt Disable Register */
#define REG_PIOB_IMR (*(RoReg*)0x400E1048U) /**< \brief (PIOB) Interrupt Mask Register */
#define REG_PIOB_ISR (*(RoReg*)0x400E104CU) /**< \brief (PIOB) Interrupt Status Register */
#define REG_PIOB_MDER (*(WoReg*)0x400E1050U) /**< \brief (PIOB) Multi-driver Enable Register */
#define REG_PIOB_MDDR (*(WoReg*)0x400E1054U) /**< \brief (PIOB) Multi-driver Disable Register */
#define REG_PIOB_MDSR (*(RoReg*)0x400E1058U) /**< \brief (PIOB) Multi-driver Status Register */
#define REG_PIOB_PUDR (*(WoReg*)0x400E1060U) /**< \brief (PIOB) Pull-up Disable Register */
#define REG_PIOB_PUER (*(WoReg*)0x400E1064U) /**< \brief (PIOB) Pull-up Enable Register */
#define REG_PIOB_PUSR (*(RoReg*)0x400E1068U) /**< \brief (PIOB) Pad Pull-up Status Register */
#define REG_PIOB_ABCDSR (*(RwReg*)0x400E1070U) /**< \brief (PIOB) Peripheral Select Register */
#define REG_PIOB_IFSCDR (*(WoReg*)0x400E1080U) /**< \brief (PIOB) Input Filter Slow Clock Disable Register */
#define REG_PIOB_IFSCER (*(WoReg*)0x400E1084U) /**< \brief (PIOB) Input Filter Slow Clock Enable Register */
#define REG_PIOB_IFSCSR (*(RoReg*)0x400E1088U) /**< \brief (PIOB) Input Filter Slow Clock Status Register */
#define REG_PIOB_SCDR (*(RwReg*)0x400E108CU) /**< \brief (PIOB) Slow Clock Divider Debouncing Register */
#define REG_PIOB_PPDDR (*(WoReg*)0x400E1090U) /**< \brief (PIOB) Pad Pull-down Disable Register */
#define REG_PIOB_PPDER (*(WoReg*)0x400E1094U) /**< \brief (PIOB) Pad Pull-down Enable Register */
#define REG_PIOB_PPDSR (*(RoReg*)0x400E1098U) /**< \brief (PIOB) Pad Pull-down Status Register */
#define REG_PIOB_OWER (*(WoReg*)0x400E10A0U) /**< \brief (PIOB) Output Write Enable */
#define REG_PIOB_OWDR (*(WoReg*)0x400E10A4U) /**< \brief (PIOB) Output Write Disable */
#define REG_PIOB_OWSR (*(RoReg*)0x400E10A8U) /**< \brief (PIOB) Output Write Status Register */
#define REG_PIOB_AIMER (*(WoReg*)0x400E10B0U) /**< \brief (PIOB) Additional Interrupt Modes Enable Register */
#define REG_PIOB_AIMDR (*(WoReg*)0x400E10B4U) /**< \brief (PIOB) Additional Interrupt Modes Disables Register */
#define REG_PIOB_AIMMR (*(RoReg*)0x400E10B8U) /**< \brief (PIOB) Additional Interrupt Modes Mask Register */
#define REG_PIOB_ESR (*(WoReg*)0x400E10C0U) /**< \brief (PIOB) Edge Select Register */
#define REG_PIOB_LSR (*(WoReg*)0x400E10C4U) /**< \brief (PIOB) Level Select Register */
#define REG_PIOB_ELSR (*(RoReg*)0x400E10C8U) /**< \brief (PIOB) Edge/Level Status Register */
#define REG_PIOB_FELLSR (*(WoReg*)0x400E10D0U) /**< \brief (PIOB) Falling Edge/Low Level Select Register */
#define REG_PIOB_REHLSR (*(WoReg*)0x400E10D4U) /**< \brief (PIOB) Rising Edge/ High Level Select Register */
#define REG_PIOB_FRLHSR (*(RoReg*)0x400E10D8U) /**< \brief (PIOB) Fall/Rise - Low/High Status Register */
#define REG_PIOB_LOCKSR (*(RoReg*)0x400E10E0U) /**< \brief (PIOB) Lock Status */
#define REG_PIOB_WPMR (*(RwReg*)0x400E10E4U) /**< \brief (PIOB) Write Protect Mode Register */
#define REG_PIOB_WPSR (*(RoReg*)0x400E10E8U) /**< \brief (PIOB) Write Protect Status Register */
#define REG_PIOB_SCHMITT (*(RwReg*)0x400E1100U) /**< \brief (PIOB) Schmitt Trigger Register */
#define REG_PIOB_DELAYR (*(RwReg*)0x400E1110U) /**< \brief (PIOB) IO Delay Register */
#define REG_PIOB_PCMR (*(RwReg*)0x400E1150U) /**< \brief (PIOB) Parallel Capture Mode Register */
#define REG_PIOB_PCIER (*(WoReg*)0x400E1154U) /**< \brief (PIOB) Parallel Capture Interrupt Enable Register */
#define REG_PIOB_PCIDR (*(WoReg*)0x400E1158U) /**< \brief (PIOB) Parallel Capture Interrupt Disable Register */
#define REG_PIOB_PCIMR (*(RoReg*)0x400E115CU) /**< \brief (PIOB) Parallel Capture Interrupt Mask Register */
#define REG_PIOB_PCISR (*(RoReg*)0x400E1160U) /**< \brief (PIOB) Parallel Capture Interrupt Status Register */
#define REG_PIOB_PCRHR (*(RoReg*)0x400E1164U) /**< \brief (PIOB) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PIOB_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PIOC_INSTANCE_
#define _SAM4E_PIOC_INSTANCE_
/* ========== Register definition for PIOC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOC_PER (0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
#define REG_PIOC_PDR (0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
#define REG_PIOC_PSR (0x400E1208U) /**< \brief (PIOC) PIO Status Register */
#define REG_PIOC_OER (0x400E1210U) /**< \brief (PIOC) Output Enable Register */
#define REG_PIOC_ODR (0x400E1214U) /**< \brief (PIOC) Output Disable Register */
#define REG_PIOC_OSR (0x400E1218U) /**< \brief (PIOC) Output Status Register */
#define REG_PIOC_IFER (0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR (0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR (0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR (0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
#define REG_PIOC_CODR (0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR (0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR (0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
#define REG_PIOC_IER (0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR (0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR (0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR (0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER (0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR (0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR (0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR (0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER (0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR (0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR (0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
#define REG_PIOC_IFSCDR (0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER (0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR (0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR (0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR (0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER (0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR (0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER (0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
#define REG_PIOC_OWDR (0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
#define REG_PIOC_OWSR (0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER (0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR (0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
#define REG_PIOC_AIMMR (0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR (0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
#define REG_PIOC_LSR (0x400E12C4U) /**< \brief (PIOC) Level Select Register */
#define REG_PIOC_ELSR (0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR (0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
#define REG_PIOC_REHLSR (0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
#define REG_PIOC_FRLHSR (0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR (0x400E12E0U) /**< \brief (PIOC) Lock Status */
#define REG_PIOC_WPMR (0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
#define REG_PIOC_WPSR (0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
#define REG_PIOC_SCHMITT (0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DELAYR (0x400E1310U) /**< \brief (PIOC) IO Delay Register */
#define REG_PIOC_PCMR (0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
#define REG_PIOC_PCIER (0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
#define REG_PIOC_PCIDR (0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
#define REG_PIOC_PCIMR (0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
#define REG_PIOC_PCISR (0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
#define REG_PIOC_PCRHR (0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
#else
#define REG_PIOC_PER (*(WoReg*)0x400E1200U) /**< \brief (PIOC) PIO Enable Register */
#define REG_PIOC_PDR (*(WoReg*)0x400E1204U) /**< \brief (PIOC) PIO Disable Register */
#define REG_PIOC_PSR (*(RoReg*)0x400E1208U) /**< \brief (PIOC) PIO Status Register */
#define REG_PIOC_OER (*(WoReg*)0x400E1210U) /**< \brief (PIOC) Output Enable Register */
#define REG_PIOC_ODR (*(WoReg*)0x400E1214U) /**< \brief (PIOC) Output Disable Register */
#define REG_PIOC_OSR (*(RoReg*)0x400E1218U) /**< \brief (PIOC) Output Status Register */
#define REG_PIOC_IFER (*(WoReg*)0x400E1220U) /**< \brief (PIOC) Glitch Input Filter Enable Register */
#define REG_PIOC_IFDR (*(WoReg*)0x400E1224U) /**< \brief (PIOC) Glitch Input Filter Disable Register */
#define REG_PIOC_IFSR (*(RoReg*)0x400E1228U) /**< \brief (PIOC) Glitch Input Filter Status Register */
#define REG_PIOC_SODR (*(WoReg*)0x400E1230U) /**< \brief (PIOC) Set Output Data Register */
#define REG_PIOC_CODR (*(WoReg*)0x400E1234U) /**< \brief (PIOC) Clear Output Data Register */
#define REG_PIOC_ODSR (*(RwReg*)0x400E1238U) /**< \brief (PIOC) Output Data Status Register */
#define REG_PIOC_PDSR (*(RoReg*)0x400E123CU) /**< \brief (PIOC) Pin Data Status Register */
#define REG_PIOC_IER (*(WoReg*)0x400E1240U) /**< \brief (PIOC) Interrupt Enable Register */
#define REG_PIOC_IDR (*(WoReg*)0x400E1244U) /**< \brief (PIOC) Interrupt Disable Register */
#define REG_PIOC_IMR (*(RoReg*)0x400E1248U) /**< \brief (PIOC) Interrupt Mask Register */
#define REG_PIOC_ISR (*(RoReg*)0x400E124CU) /**< \brief (PIOC) Interrupt Status Register */
#define REG_PIOC_MDER (*(WoReg*)0x400E1250U) /**< \brief (PIOC) Multi-driver Enable Register */
#define REG_PIOC_MDDR (*(WoReg*)0x400E1254U) /**< \brief (PIOC) Multi-driver Disable Register */
#define REG_PIOC_MDSR (*(RoReg*)0x400E1258U) /**< \brief (PIOC) Multi-driver Status Register */
#define REG_PIOC_PUDR (*(WoReg*)0x400E1260U) /**< \brief (PIOC) Pull-up Disable Register */
#define REG_PIOC_PUER (*(WoReg*)0x400E1264U) /**< \brief (PIOC) Pull-up Enable Register */
#define REG_PIOC_PUSR (*(RoReg*)0x400E1268U) /**< \brief (PIOC) Pad Pull-up Status Register */
#define REG_PIOC_ABCDSR (*(RwReg*)0x400E1270U) /**< \brief (PIOC) Peripheral Select Register */
#define REG_PIOC_IFSCDR (*(WoReg*)0x400E1280U) /**< \brief (PIOC) Input Filter Slow Clock Disable Register */
#define REG_PIOC_IFSCER (*(WoReg*)0x400E1284U) /**< \brief (PIOC) Input Filter Slow Clock Enable Register */
#define REG_PIOC_IFSCSR (*(RoReg*)0x400E1288U) /**< \brief (PIOC) Input Filter Slow Clock Status Register */
#define REG_PIOC_SCDR (*(RwReg*)0x400E128CU) /**< \brief (PIOC) Slow Clock Divider Debouncing Register */
#define REG_PIOC_PPDDR (*(WoReg*)0x400E1290U) /**< \brief (PIOC) Pad Pull-down Disable Register */
#define REG_PIOC_PPDER (*(WoReg*)0x400E1294U) /**< \brief (PIOC) Pad Pull-down Enable Register */
#define REG_PIOC_PPDSR (*(RoReg*)0x400E1298U) /**< \brief (PIOC) Pad Pull-down Status Register */
#define REG_PIOC_OWER (*(WoReg*)0x400E12A0U) /**< \brief (PIOC) Output Write Enable */
#define REG_PIOC_OWDR (*(WoReg*)0x400E12A4U) /**< \brief (PIOC) Output Write Disable */
#define REG_PIOC_OWSR (*(RoReg*)0x400E12A8U) /**< \brief (PIOC) Output Write Status Register */
#define REG_PIOC_AIMER (*(WoReg*)0x400E12B0U) /**< \brief (PIOC) Additional Interrupt Modes Enable Register */
#define REG_PIOC_AIMDR (*(WoReg*)0x400E12B4U) /**< \brief (PIOC) Additional Interrupt Modes Disables Register */
#define REG_PIOC_AIMMR (*(RoReg*)0x400E12B8U) /**< \brief (PIOC) Additional Interrupt Modes Mask Register */
#define REG_PIOC_ESR (*(WoReg*)0x400E12C0U) /**< \brief (PIOC) Edge Select Register */
#define REG_PIOC_LSR (*(WoReg*)0x400E12C4U) /**< \brief (PIOC) Level Select Register */
#define REG_PIOC_ELSR (*(RoReg*)0x400E12C8U) /**< \brief (PIOC) Edge/Level Status Register */
#define REG_PIOC_FELLSR (*(WoReg*)0x400E12D0U) /**< \brief (PIOC) Falling Edge/Low Level Select Register */
#define REG_PIOC_REHLSR (*(WoReg*)0x400E12D4U) /**< \brief (PIOC) Rising Edge/ High Level Select Register */
#define REG_PIOC_FRLHSR (*(RoReg*)0x400E12D8U) /**< \brief (PIOC) Fall/Rise - Low/High Status Register */
#define REG_PIOC_LOCKSR (*(RoReg*)0x400E12E0U) /**< \brief (PIOC) Lock Status */
#define REG_PIOC_WPMR (*(RwReg*)0x400E12E4U) /**< \brief (PIOC) Write Protect Mode Register */
#define REG_PIOC_WPSR (*(RoReg*)0x400E12E8U) /**< \brief (PIOC) Write Protect Status Register */
#define REG_PIOC_SCHMITT (*(RwReg*)0x400E1300U) /**< \brief (PIOC) Schmitt Trigger Register */
#define REG_PIOC_DELAYR (*(RwReg*)0x400E1310U) /**< \brief (PIOC) IO Delay Register */
#define REG_PIOC_PCMR (*(RwReg*)0x400E1350U) /**< \brief (PIOC) Parallel Capture Mode Register */
#define REG_PIOC_PCIER (*(WoReg*)0x400E1354U) /**< \brief (PIOC) Parallel Capture Interrupt Enable Register */
#define REG_PIOC_PCIDR (*(WoReg*)0x400E1358U) /**< \brief (PIOC) Parallel Capture Interrupt Disable Register */
#define REG_PIOC_PCIMR (*(RoReg*)0x400E135CU) /**< \brief (PIOC) Parallel Capture Interrupt Mask Register */
#define REG_PIOC_PCISR (*(RoReg*)0x400E1360U) /**< \brief (PIOC) Parallel Capture Interrupt Status Register */
#define REG_PIOC_PCRHR (*(RoReg*)0x400E1364U) /**< \brief (PIOC) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PIOC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PIOD_INSTANCE_
#define _SAM4E_PIOD_INSTANCE_
/* ========== Register definition for PIOD peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOD_PER (0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR (0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR (0x400E1408U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER (0x400E1410U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR (0x400E1414U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR (0x400E1418U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER (0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR (0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR (0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR (0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR (0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR (0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR (0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER (0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR (0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR (0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR (0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER (0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR (0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR (0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR (0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER (0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR (0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR (0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR (0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER (0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR (0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR (0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR (0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER (0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR (0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER (0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR (0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR (0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER (0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR (0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR (0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR (0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR (0x400E14C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR (0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR (0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR (0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR (0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR (0x400E14E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR (0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR (0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT (0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DELAYR (0x400E1510U) /**< \brief (PIOD) IO Delay Register */
#define REG_PIOD_PCMR (0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER (0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR (0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR (0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR (0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR (0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
#else
#define REG_PIOD_PER (*(WoReg*)0x400E1400U) /**< \brief (PIOD) PIO Enable Register */
#define REG_PIOD_PDR (*(WoReg*)0x400E1404U) /**< \brief (PIOD) PIO Disable Register */
#define REG_PIOD_PSR (*(RoReg*)0x400E1408U) /**< \brief (PIOD) PIO Status Register */
#define REG_PIOD_OER (*(WoReg*)0x400E1410U) /**< \brief (PIOD) Output Enable Register */
#define REG_PIOD_ODR (*(WoReg*)0x400E1414U) /**< \brief (PIOD) Output Disable Register */
#define REG_PIOD_OSR (*(RoReg*)0x400E1418U) /**< \brief (PIOD) Output Status Register */
#define REG_PIOD_IFER (*(WoReg*)0x400E1420U) /**< \brief (PIOD) Glitch Input Filter Enable Register */
#define REG_PIOD_IFDR (*(WoReg*)0x400E1424U) /**< \brief (PIOD) Glitch Input Filter Disable Register */
#define REG_PIOD_IFSR (*(RoReg*)0x400E1428U) /**< \brief (PIOD) Glitch Input Filter Status Register */
#define REG_PIOD_SODR (*(WoReg*)0x400E1430U) /**< \brief (PIOD) Set Output Data Register */
#define REG_PIOD_CODR (*(WoReg*)0x400E1434U) /**< \brief (PIOD) Clear Output Data Register */
#define REG_PIOD_ODSR (*(RwReg*)0x400E1438U) /**< \brief (PIOD) Output Data Status Register */
#define REG_PIOD_PDSR (*(RoReg*)0x400E143CU) /**< \brief (PIOD) Pin Data Status Register */
#define REG_PIOD_IER (*(WoReg*)0x400E1440U) /**< \brief (PIOD) Interrupt Enable Register */
#define REG_PIOD_IDR (*(WoReg*)0x400E1444U) /**< \brief (PIOD) Interrupt Disable Register */
#define REG_PIOD_IMR (*(RoReg*)0x400E1448U) /**< \brief (PIOD) Interrupt Mask Register */
#define REG_PIOD_ISR (*(RoReg*)0x400E144CU) /**< \brief (PIOD) Interrupt Status Register */
#define REG_PIOD_MDER (*(WoReg*)0x400E1450U) /**< \brief (PIOD) Multi-driver Enable Register */
#define REG_PIOD_MDDR (*(WoReg*)0x400E1454U) /**< \brief (PIOD) Multi-driver Disable Register */
#define REG_PIOD_MDSR (*(RoReg*)0x400E1458U) /**< \brief (PIOD) Multi-driver Status Register */
#define REG_PIOD_PUDR (*(WoReg*)0x400E1460U) /**< \brief (PIOD) Pull-up Disable Register */
#define REG_PIOD_PUER (*(WoReg*)0x400E1464U) /**< \brief (PIOD) Pull-up Enable Register */
#define REG_PIOD_PUSR (*(RoReg*)0x400E1468U) /**< \brief (PIOD) Pad Pull-up Status Register */
#define REG_PIOD_ABCDSR (*(RwReg*)0x400E1470U) /**< \brief (PIOD) Peripheral Select Register */
#define REG_PIOD_IFSCDR (*(WoReg*)0x400E1480U) /**< \brief (PIOD) Input Filter Slow Clock Disable Register */
#define REG_PIOD_IFSCER (*(WoReg*)0x400E1484U) /**< \brief (PIOD) Input Filter Slow Clock Enable Register */
#define REG_PIOD_IFSCSR (*(RoReg*)0x400E1488U) /**< \brief (PIOD) Input Filter Slow Clock Status Register */
#define REG_PIOD_SCDR (*(RwReg*)0x400E148CU) /**< \brief (PIOD) Slow Clock Divider Debouncing Register */
#define REG_PIOD_PPDDR (*(WoReg*)0x400E1490U) /**< \brief (PIOD) Pad Pull-down Disable Register */
#define REG_PIOD_PPDER (*(WoReg*)0x400E1494U) /**< \brief (PIOD) Pad Pull-down Enable Register */
#define REG_PIOD_PPDSR (*(RoReg*)0x400E1498U) /**< \brief (PIOD) Pad Pull-down Status Register */
#define REG_PIOD_OWER (*(WoReg*)0x400E14A0U) /**< \brief (PIOD) Output Write Enable */
#define REG_PIOD_OWDR (*(WoReg*)0x400E14A4U) /**< \brief (PIOD) Output Write Disable */
#define REG_PIOD_OWSR (*(RoReg*)0x400E14A8U) /**< \brief (PIOD) Output Write Status Register */
#define REG_PIOD_AIMER (*(WoReg*)0x400E14B0U) /**< \brief (PIOD) Additional Interrupt Modes Enable Register */
#define REG_PIOD_AIMDR (*(WoReg*)0x400E14B4U) /**< \brief (PIOD) Additional Interrupt Modes Disables Register */
#define REG_PIOD_AIMMR (*(RoReg*)0x400E14B8U) /**< \brief (PIOD) Additional Interrupt Modes Mask Register */
#define REG_PIOD_ESR (*(WoReg*)0x400E14C0U) /**< \brief (PIOD) Edge Select Register */
#define REG_PIOD_LSR (*(WoReg*)0x400E14C4U) /**< \brief (PIOD) Level Select Register */
#define REG_PIOD_ELSR (*(RoReg*)0x400E14C8U) /**< \brief (PIOD) Edge/Level Status Register */
#define REG_PIOD_FELLSR (*(WoReg*)0x400E14D0U) /**< \brief (PIOD) Falling Edge/Low Level Select Register */
#define REG_PIOD_REHLSR (*(WoReg*)0x400E14D4U) /**< \brief (PIOD) Rising Edge/ High Level Select Register */
#define REG_PIOD_FRLHSR (*(RoReg*)0x400E14D8U) /**< \brief (PIOD) Fall/Rise - Low/High Status Register */
#define REG_PIOD_LOCKSR (*(RoReg*)0x400E14E0U) /**< \brief (PIOD) Lock Status */
#define REG_PIOD_WPMR (*(RwReg*)0x400E14E4U) /**< \brief (PIOD) Write Protect Mode Register */
#define REG_PIOD_WPSR (*(RoReg*)0x400E14E8U) /**< \brief (PIOD) Write Protect Status Register */
#define REG_PIOD_SCHMITT (*(RwReg*)0x400E1500U) /**< \brief (PIOD) Schmitt Trigger Register */
#define REG_PIOD_DELAYR (*(RwReg*)0x400E1510U) /**< \brief (PIOD) IO Delay Register */
#define REG_PIOD_PCMR (*(RwReg*)0x400E1550U) /**< \brief (PIOD) Parallel Capture Mode Register */
#define REG_PIOD_PCIER (*(WoReg*)0x400E1554U) /**< \brief (PIOD) Parallel Capture Interrupt Enable Register */
#define REG_PIOD_PCIDR (*(WoReg*)0x400E1558U) /**< \brief (PIOD) Parallel Capture Interrupt Disable Register */
#define REG_PIOD_PCIMR (*(RoReg*)0x400E155CU) /**< \brief (PIOD) Parallel Capture Interrupt Mask Register */
#define REG_PIOD_PCISR (*(RoReg*)0x400E1560U) /**< \brief (PIOD) Parallel Capture Interrupt Status Register */
#define REG_PIOD_PCRHR (*(RoReg*)0x400E1564U) /**< \brief (PIOD) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PIOD_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PIOE_INSTANCE_
#define _SAM4E_PIOE_INSTANCE_
/* ========== Register definition for PIOE peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PIOE_PER (0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
#define REG_PIOE_PDR (0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
#define REG_PIOE_PSR (0x400E1608U) /**< \brief (PIOE) PIO Status Register */
#define REG_PIOE_OER (0x400E1610U) /**< \brief (PIOE) Output Enable Register */
#define REG_PIOE_ODR (0x400E1614U) /**< \brief (PIOE) Output Disable Register */
#define REG_PIOE_OSR (0x400E1618U) /**< \brief (PIOE) Output Status Register */
#define REG_PIOE_IFER (0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR (0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR (0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR (0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
#define REG_PIOE_CODR (0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR (0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR (0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
#define REG_PIOE_IER (0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR (0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR (0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR (0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER (0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR (0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR (0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR (0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER (0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR (0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR (0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
#define REG_PIOE_IFSCDR (0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER (0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR (0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR (0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR (0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER (0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR (0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER (0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
#define REG_PIOE_OWDR (0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
#define REG_PIOE_OWSR (0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER (0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR (0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
#define REG_PIOE_AIMMR (0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR (0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
#define REG_PIOE_LSR (0x400E16C4U) /**< \brief (PIOE) Level Select Register */
#define REG_PIOE_ELSR (0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR (0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
#define REG_PIOE_REHLSR (0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
#define REG_PIOE_FRLHSR (0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR (0x400E16E0U) /**< \brief (PIOE) Lock Status */
#define REG_PIOE_WPMR (0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
#define REG_PIOE_WPSR (0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
#define REG_PIOE_SCHMITT (0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DELAYR (0x400E1710U) /**< \brief (PIOE) IO Delay Register */
#define REG_PIOE_PCMR (0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
#define REG_PIOE_PCIER (0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
#define REG_PIOE_PCIDR (0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
#define REG_PIOE_PCIMR (0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
#define REG_PIOE_PCISR (0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
#define REG_PIOE_PCRHR (0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
#else
#define REG_PIOE_PER (*(WoReg*)0x400E1600U) /**< \brief (PIOE) PIO Enable Register */
#define REG_PIOE_PDR (*(WoReg*)0x400E1604U) /**< \brief (PIOE) PIO Disable Register */
#define REG_PIOE_PSR (*(RoReg*)0x400E1608U) /**< \brief (PIOE) PIO Status Register */
#define REG_PIOE_OER (*(WoReg*)0x400E1610U) /**< \brief (PIOE) Output Enable Register */
#define REG_PIOE_ODR (*(WoReg*)0x400E1614U) /**< \brief (PIOE) Output Disable Register */
#define REG_PIOE_OSR (*(RoReg*)0x400E1618U) /**< \brief (PIOE) Output Status Register */
#define REG_PIOE_IFER (*(WoReg*)0x400E1620U) /**< \brief (PIOE) Glitch Input Filter Enable Register */
#define REG_PIOE_IFDR (*(WoReg*)0x400E1624U) /**< \brief (PIOE) Glitch Input Filter Disable Register */
#define REG_PIOE_IFSR (*(RoReg*)0x400E1628U) /**< \brief (PIOE) Glitch Input Filter Status Register */
#define REG_PIOE_SODR (*(WoReg*)0x400E1630U) /**< \brief (PIOE) Set Output Data Register */
#define REG_PIOE_CODR (*(WoReg*)0x400E1634U) /**< \brief (PIOE) Clear Output Data Register */
#define REG_PIOE_ODSR (*(RwReg*)0x400E1638U) /**< \brief (PIOE) Output Data Status Register */
#define REG_PIOE_PDSR (*(RoReg*)0x400E163CU) /**< \brief (PIOE) Pin Data Status Register */
#define REG_PIOE_IER (*(WoReg*)0x400E1640U) /**< \brief (PIOE) Interrupt Enable Register */
#define REG_PIOE_IDR (*(WoReg*)0x400E1644U) /**< \brief (PIOE) Interrupt Disable Register */
#define REG_PIOE_IMR (*(RoReg*)0x400E1648U) /**< \brief (PIOE) Interrupt Mask Register */
#define REG_PIOE_ISR (*(RoReg*)0x400E164CU) /**< \brief (PIOE) Interrupt Status Register */
#define REG_PIOE_MDER (*(WoReg*)0x400E1650U) /**< \brief (PIOE) Multi-driver Enable Register */
#define REG_PIOE_MDDR (*(WoReg*)0x400E1654U) /**< \brief (PIOE) Multi-driver Disable Register */
#define REG_PIOE_MDSR (*(RoReg*)0x400E1658U) /**< \brief (PIOE) Multi-driver Status Register */
#define REG_PIOE_PUDR (*(WoReg*)0x400E1660U) /**< \brief (PIOE) Pull-up Disable Register */
#define REG_PIOE_PUER (*(WoReg*)0x400E1664U) /**< \brief (PIOE) Pull-up Enable Register */
#define REG_PIOE_PUSR (*(RoReg*)0x400E1668U) /**< \brief (PIOE) Pad Pull-up Status Register */
#define REG_PIOE_ABCDSR (*(RwReg*)0x400E1670U) /**< \brief (PIOE) Peripheral Select Register */
#define REG_PIOE_IFSCDR (*(WoReg*)0x400E1680U) /**< \brief (PIOE) Input Filter Slow Clock Disable Register */
#define REG_PIOE_IFSCER (*(WoReg*)0x400E1684U) /**< \brief (PIOE) Input Filter Slow Clock Enable Register */
#define REG_PIOE_IFSCSR (*(RoReg*)0x400E1688U) /**< \brief (PIOE) Input Filter Slow Clock Status Register */
#define REG_PIOE_SCDR (*(RwReg*)0x400E168CU) /**< \brief (PIOE) Slow Clock Divider Debouncing Register */
#define REG_PIOE_PPDDR (*(WoReg*)0x400E1690U) /**< \brief (PIOE) Pad Pull-down Disable Register */
#define REG_PIOE_PPDER (*(WoReg*)0x400E1694U) /**< \brief (PIOE) Pad Pull-down Enable Register */
#define REG_PIOE_PPDSR (*(RoReg*)0x400E1698U) /**< \brief (PIOE) Pad Pull-down Status Register */
#define REG_PIOE_OWER (*(WoReg*)0x400E16A0U) /**< \brief (PIOE) Output Write Enable */
#define REG_PIOE_OWDR (*(WoReg*)0x400E16A4U) /**< \brief (PIOE) Output Write Disable */
#define REG_PIOE_OWSR (*(RoReg*)0x400E16A8U) /**< \brief (PIOE) Output Write Status Register */
#define REG_PIOE_AIMER (*(WoReg*)0x400E16B0U) /**< \brief (PIOE) Additional Interrupt Modes Enable Register */
#define REG_PIOE_AIMDR (*(WoReg*)0x400E16B4U) /**< \brief (PIOE) Additional Interrupt Modes Disables Register */
#define REG_PIOE_AIMMR (*(RoReg*)0x400E16B8U) /**< \brief (PIOE) Additional Interrupt Modes Mask Register */
#define REG_PIOE_ESR (*(WoReg*)0x400E16C0U) /**< \brief (PIOE) Edge Select Register */
#define REG_PIOE_LSR (*(WoReg*)0x400E16C4U) /**< \brief (PIOE) Level Select Register */
#define REG_PIOE_ELSR (*(RoReg*)0x400E16C8U) /**< \brief (PIOE) Edge/Level Status Register */
#define REG_PIOE_FELLSR (*(WoReg*)0x400E16D0U) /**< \brief (PIOE) Falling Edge/Low Level Select Register */
#define REG_PIOE_REHLSR (*(WoReg*)0x400E16D4U) /**< \brief (PIOE) Rising Edge/ High Level Select Register */
#define REG_PIOE_FRLHSR (*(RoReg*)0x400E16D8U) /**< \brief (PIOE) Fall/Rise - Low/High Status Register */
#define REG_PIOE_LOCKSR (*(RoReg*)0x400E16E0U) /**< \brief (PIOE) Lock Status */
#define REG_PIOE_WPMR (*(RwReg*)0x400E16E4U) /**< \brief (PIOE) Write Protect Mode Register */
#define REG_PIOE_WPSR (*(RoReg*)0x400E16E8U) /**< \brief (PIOE) Write Protect Status Register */
#define REG_PIOE_SCHMITT (*(RwReg*)0x400E1700U) /**< \brief (PIOE) Schmitt Trigger Register */
#define REG_PIOE_DELAYR (*(RwReg*)0x400E1710U) /**< \brief (PIOE) IO Delay Register */
#define REG_PIOE_PCMR (*(RwReg*)0x400E1750U) /**< \brief (PIOE) Parallel Capture Mode Register */
#define REG_PIOE_PCIER (*(WoReg*)0x400E1754U) /**< \brief (PIOE) Parallel Capture Interrupt Enable Register */
#define REG_PIOE_PCIDR (*(WoReg*)0x400E1758U) /**< \brief (PIOE) Parallel Capture Interrupt Disable Register */
#define REG_PIOE_PCIMR (*(RoReg*)0x400E175CU) /**< \brief (PIOE) Parallel Capture Interrupt Mask Register */
#define REG_PIOE_PCISR (*(RoReg*)0x400E1760U) /**< \brief (PIOE) Parallel Capture Interrupt Status Register */
#define REG_PIOE_PCRHR (*(RoReg*)0x400E1764U) /**< \brief (PIOE) Parallel Capture Reception Holding Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PIOE_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PMC_INSTANCE_
#define _SAM4E_PMC_INSTANCE_
/* ========== Register definition for PMC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PMC_SCER (0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
#define REG_PMC_SCDR (0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
#define REG_PMC_SCSR (0x400E0408U) /**< \brief (PMC) System Clock Status Register */
#define REG_PMC_PCER0 (0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0 (0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0 (0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_MOR (0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR (0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR (0x400E0428U) /**< \brief (PMC) PLLA Register */
#define REG_PMC_MCKR (0x400E0430U) /**< \brief (PMC) Master Clock Register */
#define REG_PMC_USB (0x400E0438U) /**< \brief (PMC) USB Clock Register */
#define REG_PMC_PCK (0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
#define REG_PMC_IER (0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
#define REG_PMC_IDR (0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
#define REG_PMC_SR (0x400E0468U) /**< \brief (PMC) Status Register */
#define REG_PMC_IMR (0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
#define REG_PMC_FSMR (0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
#define REG_PMC_FSPR (0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
#define REG_PMC_FOCR (0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
#define REG_PMC_WPMR (0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
#define REG_PMC_WPSR (0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
#define REG_PMC_PCER1 (0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1 (0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1 (0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_OCR (0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
#else
#define REG_PMC_SCER (*(WoReg*)0x400E0400U) /**< \brief (PMC) System Clock Enable Register */
#define REG_PMC_SCDR (*(WoReg*)0x400E0404U) /**< \brief (PMC) System Clock Disable Register */
#define REG_PMC_SCSR (*(RoReg*)0x400E0408U) /**< \brief (PMC) System Clock Status Register */
#define REG_PMC_PCER0 (*(WoReg*)0x400E0410U) /**< \brief (PMC) Peripheral Clock Enable Register 0 */
#define REG_PMC_PCDR0 (*(WoReg*)0x400E0414U) /**< \brief (PMC) Peripheral Clock Disable Register 0 */
#define REG_PMC_PCSR0 (*(RoReg*)0x400E0418U) /**< \brief (PMC) Peripheral Clock Status Register 0 */
#define REG_CKGR_MOR (*(RwReg*)0x400E0420U) /**< \brief (PMC) Main Oscillator Register */
#define REG_CKGR_MCFR (*(RwReg*)0x400E0424U) /**< \brief (PMC) Main Clock Frequency Register */
#define REG_CKGR_PLLAR (*(RwReg*)0x400E0428U) /**< \brief (PMC) PLLA Register */
#define REG_PMC_MCKR (*(RwReg*)0x400E0430U) /**< \brief (PMC) Master Clock Register */
#define REG_PMC_USB (*(RwReg*)0x400E0438U) /**< \brief (PMC) USB Clock Register */
#define REG_PMC_PCK (*(RwReg*)0x400E0440U) /**< \brief (PMC) Programmable Clock 0 Register */
#define REG_PMC_IER (*(WoReg*)0x400E0460U) /**< \brief (PMC) Interrupt Enable Register */
#define REG_PMC_IDR (*(WoReg*)0x400E0464U) /**< \brief (PMC) Interrupt Disable Register */
#define REG_PMC_SR (*(RoReg*)0x400E0468U) /**< \brief (PMC) Status Register */
#define REG_PMC_IMR (*(RoReg*)0x400E046CU) /**< \brief (PMC) Interrupt Mask Register */
#define REG_PMC_FSMR (*(RwReg*)0x400E0470U) /**< \brief (PMC) Fast Startup Mode Register */
#define REG_PMC_FSPR (*(RwReg*)0x400E0474U) /**< \brief (PMC) Fast Startup Polarity Register */
#define REG_PMC_FOCR (*(WoReg*)0x400E0478U) /**< \brief (PMC) Fault Output Clear Register */
#define REG_PMC_WPMR (*(RwReg*)0x400E04E4U) /**< \brief (PMC) Write Protect Mode Register */
#define REG_PMC_WPSR (*(RoReg*)0x400E04E8U) /**< \brief (PMC) Write Protect Status Register */
#define REG_PMC_PCER1 (*(WoReg*)0x400E0500U) /**< \brief (PMC) Peripheral Clock Enable Register 1 */
#define REG_PMC_PCDR1 (*(WoReg*)0x400E0504U) /**< \brief (PMC) Peripheral Clock Disable Register 1 */
#define REG_PMC_PCSR1 (*(RoReg*)0x400E0508U) /**< \brief (PMC) Peripheral Clock Status Register 1 */
#define REG_PMC_OCR (*(RwReg*)0x400E0510U) /**< \brief (PMC) Oscillator Calibration Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PMC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_PWM_INSTANCE_
#define _SAM4E_PWM_INSTANCE_
/* ========== Register definition for PWM peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_PWM_CLK (0x40000000U) /**< \brief (PWM) PWM Clock Register */
#define REG_PWM_ENA (0x40000004U) /**< \brief (PWM) PWM Enable Register */
#define REG_PWM_DIS (0x40000008U) /**< \brief (PWM) PWM Disable Register */
#define REG_PWM_SR (0x4000000CU) /**< \brief (PWM) PWM Status Register */
#define REG_PWM_IER1 (0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
#define REG_PWM_IDR1 (0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
#define REG_PWM_IMR1 (0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
#define REG_PWM_ISR1 (0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
#define REG_PWM_SCM (0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
#define REG_PWM_SCUC (0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
#define REG_PWM_SCUP (0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
#define REG_PWM_SCUPUPD (0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
#define REG_PWM_IER2 (0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
#define REG_PWM_IDR2 (0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
#define REG_PWM_IMR2 (0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
#define REG_PWM_ISR2 (0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
#define REG_PWM_OOV (0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */
#define REG_PWM_OS (0x40000048U) /**< \brief (PWM) PWM Output Selection Register */
#define REG_PWM_OSS (0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */
#define REG_PWM_OSC (0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */
#define REG_PWM_OSSUPD (0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
#define REG_PWM_OSCUPD (0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
#define REG_PWM_FMR (0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */
#define REG_PWM_FSR (0x40000060U) /**< \brief (PWM) PWM Fault Status Register */
#define REG_PWM_FCR (0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */
#define REG_PWM_FPV1 (0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */
#define REG_PWM_FPE (0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
#define REG_PWM_ELMR (0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
#define REG_PWM_SSPR (0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */
#define REG_PWM_SSPUP (0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */
#define REG_PWM_SMMR (0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
#define REG_PWM_FPV2 (0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */
#define REG_PWM_WPCR (0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */
#define REG_PWM_WPSR (0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */
#define REG_PWM_TPR (0x40000108U) /**< \brief (PWM) Transmit Pointer Register */
#define REG_PWM_TCR (0x4000010CU) /**< \brief (PWM) Transmit Counter Register */
#define REG_PWM_TNPR (0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */
#define REG_PWM_TNCR (0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */
#define REG_PWM_PTCR (0x40000120U) /**< \brief (PWM) Transfer Control Register */
#define REG_PWM_PTSR (0x40000124U) /**< \brief (PWM) Transfer Status Register */
#define REG_PWM_CMPV0 (0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
#define REG_PWM_CMPVUPD0 (0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
#define REG_PWM_CMPM0 (0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
#define REG_PWM_CMPMUPD0 (0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
#define REG_PWM_CMPV1 (0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
#define REG_PWM_CMPVUPD1 (0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
#define REG_PWM_CMPM1 (0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
#define REG_PWM_CMPMUPD1 (0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
#define REG_PWM_CMPV2 (0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
#define REG_PWM_CMPVUPD2 (0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
#define REG_PWM_CMPM2 (0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
#define REG_PWM_CMPMUPD2 (0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
#define REG_PWM_CMPV3 (0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
#define REG_PWM_CMPVUPD3 (0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
#define REG_PWM_CMPM3 (0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
#define REG_PWM_CMPMUPD3 (0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
#define REG_PWM_CMPV4 (0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
#define REG_PWM_CMPVUPD4 (0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
#define REG_PWM_CMPM4 (0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
#define REG_PWM_CMPMUPD4 (0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
#define REG_PWM_CMPV5 (0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
#define REG_PWM_CMPVUPD5 (0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
#define REG_PWM_CMPM5 (0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
#define REG_PWM_CMPMUPD5 (0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
#define REG_PWM_CMPV6 (0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
#define REG_PWM_CMPVUPD6 (0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
#define REG_PWM_CMPM6 (0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
#define REG_PWM_CMPMUPD6 (0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
#define REG_PWM_CMPV7 (0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
#define REG_PWM_CMPVUPD7 (0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
#define REG_PWM_CMPM7 (0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
#define REG_PWM_CMPMUPD7 (0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
#define REG_PWM_CMR0 (0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
#define REG_PWM_CDTY0 (0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
#define REG_PWM_CDTYUPD0 (0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
#define REG_PWM_CPRD0 (0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
#define REG_PWM_CPRDUPD0 (0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
#define REG_PWM_CCNT0 (0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
#define REG_PWM_DT0 (0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
#define REG_PWM_DTUPD0 (0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
#define REG_PWM_CMR1 (0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
#define REG_PWM_CDTY1 (0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
#define REG_PWM_CDTYUPD1 (0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
#define REG_PWM_CPRD1 (0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
#define REG_PWM_CPRDUPD1 (0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
#define REG_PWM_CCNT1 (0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
#define REG_PWM_DT1 (0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
#define REG_PWM_DTUPD1 (0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
#define REG_PWM_CMR2 (0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
#define REG_PWM_CDTY2 (0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
#define REG_PWM_CDTYUPD2 (0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
#define REG_PWM_CPRD2 (0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
#define REG_PWM_CPRDUPD2 (0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
#define REG_PWM_CCNT2 (0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
#define REG_PWM_DT2 (0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
#define REG_PWM_DTUPD2 (0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
#define REG_PWM_CMR3 (0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
#define REG_PWM_CDTY3 (0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
#define REG_PWM_CDTYUPD3 (0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
#define REG_PWM_CPRD3 (0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
#define REG_PWM_CPRDUPD3 (0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
#define REG_PWM_CCNT3 (0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
#define REG_PWM_DT3 (0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
#define REG_PWM_DTUPD3 (0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
#define REG_PWM_CMUPD0 (0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM_CAE0 (0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */
#define REG_PWM_CAEUPD0 (0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */
#define REG_PWM_CMUPD1 (0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM_CAE1 (0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */
#define REG_PWM_CAEUPD1 (0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */
#define REG_PWM_CMUPD2 (0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM_CAE2 (0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */
#define REG_PWM_CAEUPD2 (0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */
#define REG_PWM_CMUPD3 (0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */
#define REG_PWM_CAE3 (0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */
#define REG_PWM_CAEUPD3 (0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */
#else
#define REG_PWM_CLK (*(RwReg*)0x40000000U) /**< \brief (PWM) PWM Clock Register */
#define REG_PWM_ENA (*(WoReg*)0x40000004U) /**< \brief (PWM) PWM Enable Register */
#define REG_PWM_DIS (*(WoReg*)0x40000008U) /**< \brief (PWM) PWM Disable Register */
#define REG_PWM_SR (*(RoReg*)0x4000000CU) /**< \brief (PWM) PWM Status Register */
#define REG_PWM_IER1 (*(WoReg*)0x40000010U) /**< \brief (PWM) PWM Interrupt Enable Register 1 */
#define REG_PWM_IDR1 (*(WoReg*)0x40000014U) /**< \brief (PWM) PWM Interrupt Disable Register 1 */
#define REG_PWM_IMR1 (*(RoReg*)0x40000018U) /**< \brief (PWM) PWM Interrupt Mask Register 1 */
#define REG_PWM_ISR1 (*(RoReg*)0x4000001CU) /**< \brief (PWM) PWM Interrupt Status Register 1 */
#define REG_PWM_SCM (*(RwReg*)0x40000020U) /**< \brief (PWM) PWM Sync Channels Mode Register */
#define REG_PWM_SCUC (*(RwReg*)0x40000028U) /**< \brief (PWM) PWM Sync Channels Update Control Register */
#define REG_PWM_SCUP (*(RwReg*)0x4000002CU) /**< \brief (PWM) PWM Sync Channels Update Period Register */
#define REG_PWM_SCUPUPD (*(WoReg*)0x40000030U) /**< \brief (PWM) PWM Sync Channels Update Period Update Register */
#define REG_PWM_IER2 (*(WoReg*)0x40000034U) /**< \brief (PWM) PWM Interrupt Enable Register 2 */
#define REG_PWM_IDR2 (*(WoReg*)0x40000038U) /**< \brief (PWM) PWM Interrupt Disable Register 2 */
#define REG_PWM_IMR2 (*(RoReg*)0x4000003CU) /**< \brief (PWM) PWM Interrupt Mask Register 2 */
#define REG_PWM_ISR2 (*(RoReg*)0x40000040U) /**< \brief (PWM) PWM Interrupt Status Register 2 */
#define REG_PWM_OOV (*(RwReg*)0x40000044U) /**< \brief (PWM) PWM Output Override Value Register */
#define REG_PWM_OS (*(RwReg*)0x40000048U) /**< \brief (PWM) PWM Output Selection Register */
#define REG_PWM_OSS (*(WoReg*)0x4000004CU) /**< \brief (PWM) PWM Output Selection Set Register */
#define REG_PWM_OSC (*(WoReg*)0x40000050U) /**< \brief (PWM) PWM Output Selection Clear Register */
#define REG_PWM_OSSUPD (*(WoReg*)0x40000054U) /**< \brief (PWM) PWM Output Selection Set Update Register */
#define REG_PWM_OSCUPD (*(WoReg*)0x40000058U) /**< \brief (PWM) PWM Output Selection Clear Update Register */
#define REG_PWM_FMR (*(RwReg*)0x4000005CU) /**< \brief (PWM) PWM Fault Mode Register */
#define REG_PWM_FSR (*(RoReg*)0x40000060U) /**< \brief (PWM) PWM Fault Status Register */
#define REG_PWM_FCR (*(WoReg*)0x40000064U) /**< \brief (PWM) PWM Fault Clear Register */
#define REG_PWM_FPV1 (*(RwReg*)0x40000068U) /**< \brief (PWM) PWM Fault Protection Value Register 1 */
#define REG_PWM_FPE (*(RwReg*)0x4000006CU) /**< \brief (PWM) PWM Fault Protection Enable Register */
#define REG_PWM_ELMR (*(RwReg*)0x4000007CU) /**< \brief (PWM) PWM Event Line 0 Mode Register */
#define REG_PWM_SSPR (*(RwReg*)0x400000A0U) /**< \brief (PWM) PWM Spread Spectrum Register */
#define REG_PWM_SSPUP (*(WoReg*)0x400000A4U) /**< \brief (PWM) PWM Spread Spectrum Update Register */
#define REG_PWM_SMMR (*(RwReg*)0x400000B0U) /**< \brief (PWM) PWM Stepper Motor Mode Register */
#define REG_PWM_FPV2 (*(RwReg*)0x400000C0U) /**< \brief (PWM) PWM Fault Protection Value 2 Register */
#define REG_PWM_WPCR (*(WoReg*)0x400000E4U) /**< \brief (PWM) PWM Write Protect Control Register */
#define REG_PWM_WPSR (*(RoReg*)0x400000E8U) /**< \brief (PWM) PWM Write Protect Status Register */
#define REG_PWM_TPR (*(RwReg*)0x40000108U) /**< \brief (PWM) Transmit Pointer Register */
#define REG_PWM_TCR (*(RwReg*)0x4000010CU) /**< \brief (PWM) Transmit Counter Register */
#define REG_PWM_TNPR (*(RwReg*)0x40000118U) /**< \brief (PWM) Transmit Next Pointer Register */
#define REG_PWM_TNCR (*(RwReg*)0x4000011CU) /**< \brief (PWM) Transmit Next Counter Register */
#define REG_PWM_PTCR (*(WoReg*)0x40000120U) /**< \brief (PWM) Transfer Control Register */
#define REG_PWM_PTSR (*(RoReg*)0x40000124U) /**< \brief (PWM) Transfer Status Register */
#define REG_PWM_CMPV0 (*(RwReg*)0x40000130U) /**< \brief (PWM) PWM Comparison 0 Value Register */
#define REG_PWM_CMPVUPD0 (*(WoReg*)0x40000134U) /**< \brief (PWM) PWM Comparison 0 Value Update Register */
#define REG_PWM_CMPM0 (*(RwReg*)0x40000138U) /**< \brief (PWM) PWM Comparison 0 Mode Register */
#define REG_PWM_CMPMUPD0 (*(WoReg*)0x4000013CU) /**< \brief (PWM) PWM Comparison 0 Mode Update Register */
#define REG_PWM_CMPV1 (*(RwReg*)0x40000140U) /**< \brief (PWM) PWM Comparison 1 Value Register */
#define REG_PWM_CMPVUPD1 (*(WoReg*)0x40000144U) /**< \brief (PWM) PWM Comparison 1 Value Update Register */
#define REG_PWM_CMPM1 (*(RwReg*)0x40000148U) /**< \brief (PWM) PWM Comparison 1 Mode Register */
#define REG_PWM_CMPMUPD1 (*(WoReg*)0x4000014CU) /**< \brief (PWM) PWM Comparison 1 Mode Update Register */
#define REG_PWM_CMPV2 (*(RwReg*)0x40000150U) /**< \brief (PWM) PWM Comparison 2 Value Register */
#define REG_PWM_CMPVUPD2 (*(WoReg*)0x40000154U) /**< \brief (PWM) PWM Comparison 2 Value Update Register */
#define REG_PWM_CMPM2 (*(RwReg*)0x40000158U) /**< \brief (PWM) PWM Comparison 2 Mode Register */
#define REG_PWM_CMPMUPD2 (*(WoReg*)0x4000015CU) /**< \brief (PWM) PWM Comparison 2 Mode Update Register */
#define REG_PWM_CMPV3 (*(RwReg*)0x40000160U) /**< \brief (PWM) PWM Comparison 3 Value Register */
#define REG_PWM_CMPVUPD3 (*(WoReg*)0x40000164U) /**< \brief (PWM) PWM Comparison 3 Value Update Register */
#define REG_PWM_CMPM3 (*(RwReg*)0x40000168U) /**< \brief (PWM) PWM Comparison 3 Mode Register */
#define REG_PWM_CMPMUPD3 (*(WoReg*)0x4000016CU) /**< \brief (PWM) PWM Comparison 3 Mode Update Register */
#define REG_PWM_CMPV4 (*(RwReg*)0x40000170U) /**< \brief (PWM) PWM Comparison 4 Value Register */
#define REG_PWM_CMPVUPD4 (*(WoReg*)0x40000174U) /**< \brief (PWM) PWM Comparison 4 Value Update Register */
#define REG_PWM_CMPM4 (*(RwReg*)0x40000178U) /**< \brief (PWM) PWM Comparison 4 Mode Register */
#define REG_PWM_CMPMUPD4 (*(WoReg*)0x4000017CU) /**< \brief (PWM) PWM Comparison 4 Mode Update Register */
#define REG_PWM_CMPV5 (*(RwReg*)0x40000180U) /**< \brief (PWM) PWM Comparison 5 Value Register */
#define REG_PWM_CMPVUPD5 (*(WoReg*)0x40000184U) /**< \brief (PWM) PWM Comparison 5 Value Update Register */
#define REG_PWM_CMPM5 (*(RwReg*)0x40000188U) /**< \brief (PWM) PWM Comparison 5 Mode Register */
#define REG_PWM_CMPMUPD5 (*(WoReg*)0x4000018CU) /**< \brief (PWM) PWM Comparison 5 Mode Update Register */
#define REG_PWM_CMPV6 (*(RwReg*)0x40000190U) /**< \brief (PWM) PWM Comparison 6 Value Register */
#define REG_PWM_CMPVUPD6 (*(WoReg*)0x40000194U) /**< \brief (PWM) PWM Comparison 6 Value Update Register */
#define REG_PWM_CMPM6 (*(RwReg*)0x40000198U) /**< \brief (PWM) PWM Comparison 6 Mode Register */
#define REG_PWM_CMPMUPD6 (*(WoReg*)0x4000019CU) /**< \brief (PWM) PWM Comparison 6 Mode Update Register */
#define REG_PWM_CMPV7 (*(RwReg*)0x400001A0U) /**< \brief (PWM) PWM Comparison 7 Value Register */
#define REG_PWM_CMPVUPD7 (*(WoReg*)0x400001A4U) /**< \brief (PWM) PWM Comparison 7 Value Update Register */
#define REG_PWM_CMPM7 (*(RwReg*)0x400001A8U) /**< \brief (PWM) PWM Comparison 7 Mode Register */
#define REG_PWM_CMPMUPD7 (*(WoReg*)0x400001ACU) /**< \brief (PWM) PWM Comparison 7 Mode Update Register */
#define REG_PWM_CMR0 (*(RwReg*)0x40000200U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 0) */
#define REG_PWM_CDTY0 (*(RwReg*)0x40000204U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 0) */
#define REG_PWM_CDTYUPD0 (*(WoReg*)0x40000208U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 0) */
#define REG_PWM_CPRD0 (*(RwReg*)0x4000020CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 0) */
#define REG_PWM_CPRDUPD0 (*(WoReg*)0x40000210U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 0) */
#define REG_PWM_CCNT0 (*(RoReg*)0x40000214U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 0) */
#define REG_PWM_DT0 (*(RwReg*)0x40000218U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 0) */
#define REG_PWM_DTUPD0 (*(WoReg*)0x4000021CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 0) */
#define REG_PWM_CMR1 (*(RwReg*)0x40000220U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 1) */
#define REG_PWM_CDTY1 (*(RwReg*)0x40000224U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 1) */
#define REG_PWM_CDTYUPD1 (*(WoReg*)0x40000228U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 1) */
#define REG_PWM_CPRD1 (*(RwReg*)0x4000022CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 1) */
#define REG_PWM_CPRDUPD1 (*(WoReg*)0x40000230U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 1) */
#define REG_PWM_CCNT1 (*(RoReg*)0x40000234U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 1) */
#define REG_PWM_DT1 (*(RwReg*)0x40000238U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 1) */
#define REG_PWM_DTUPD1 (*(WoReg*)0x4000023CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 1) */
#define REG_PWM_CMR2 (*(RwReg*)0x40000240U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 2) */
#define REG_PWM_CDTY2 (*(RwReg*)0x40000244U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 2) */
#define REG_PWM_CDTYUPD2 (*(WoReg*)0x40000248U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 2) */
#define REG_PWM_CPRD2 (*(RwReg*)0x4000024CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 2) */
#define REG_PWM_CPRDUPD2 (*(WoReg*)0x40000250U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 2) */
#define REG_PWM_CCNT2 (*(RoReg*)0x40000254U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 2) */
#define REG_PWM_DT2 (*(RwReg*)0x40000258U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 2) */
#define REG_PWM_DTUPD2 (*(WoReg*)0x4000025CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 2) */
#define REG_PWM_CMR3 (*(RwReg*)0x40000260U) /**< \brief (PWM) PWM Channel Mode Register (ch_num = 3) */
#define REG_PWM_CDTY3 (*(RwReg*)0x40000264U) /**< \brief (PWM) PWM Channel Duty Cycle Register (ch_num = 3) */
#define REG_PWM_CDTYUPD3 (*(WoReg*)0x40000268U) /**< \brief (PWM) PWM Channel Duty Cycle Update Register (ch_num = 3) */
#define REG_PWM_CPRD3 (*(RwReg*)0x4000026CU) /**< \brief (PWM) PWM Channel Period Register (ch_num = 3) */
#define REG_PWM_CPRDUPD3 (*(WoReg*)0x40000270U) /**< \brief (PWM) PWM Channel Period Update Register (ch_num = 3) */
#define REG_PWM_CCNT3 (*(RoReg*)0x40000274U) /**< \brief (PWM) PWM Channel Counter Register (ch_num = 3) */
#define REG_PWM_DT3 (*(RwReg*)0x40000278U) /**< \brief (PWM) PWM Channel Dead Time Register (ch_num = 3) */
#define REG_PWM_DTUPD3 (*(WoReg*)0x4000027CU) /**< \brief (PWM) PWM Channel Dead Time Update Register (ch_num = 3) */
#define REG_PWM_CMUPD0 (*(WoReg*)0x40000400U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 0) */
#define REG_PWM_CAE0 (*(RwReg*)0x40000404U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 0) */
#define REG_PWM_CAEUPD0 (*(WoReg*)0x40000408U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 0) */
#define REG_PWM_CMUPD1 (*(WoReg*)0x40000420U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 1) */
#define REG_PWM_CAE1 (*(RwReg*)0x40000424U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 1) */
#define REG_PWM_CAEUPD1 (*(WoReg*)0x40000428U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 1) */
#define REG_PWM_CMUPD2 (*(WoReg*)0x40000440U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 2) */
#define REG_PWM_CAE2 (*(RwReg*)0x40000444U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 2) */
#define REG_PWM_CAEUPD2 (*(WoReg*)0x40000448U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 2) */
#define REG_PWM_CMUPD3 (*(WoReg*)0x40000460U) /**< \brief (PWM) PWM Channel Mode Update Register (ch_num = 3) */
#define REG_PWM_CAE3 (*(RwReg*)0x40000464U) /**< \brief (PWM) PWM Channel Additional Edge Register (ch_num = 3) */
#define REG_PWM_CAEUPD3 (*(WoReg*)0x40000468U) /**< \brief (PWM) PWM Channel Additional Edge Update Register (ch_num = 3) */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_PWM_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_RSTC_INSTANCE_
#define _SAM4E_RSTC_INSTANCE_
/* ========== Register definition for RSTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RSTC_CR (0x400E1800U) /**< \brief (RSTC) Control Register */
#define REG_RSTC_SR (0x400E1804U) /**< \brief (RSTC) Status Register */
#define REG_RSTC_MR (0x400E1808U) /**< \brief (RSTC) Mode Register */
#else
#define REG_RSTC_CR (*(WoReg*)0x400E1800U) /**< \brief (RSTC) Control Register */
#define REG_RSTC_SR (*(RoReg*)0x400E1804U) /**< \brief (RSTC) Status Register */
#define REG_RSTC_MR (*(RwReg*)0x400E1808U) /**< \brief (RSTC) Mode Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_RSTC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_RTC_INSTANCE_
#define _SAM4E_RTC_INSTANCE_
/* ========== Register definition for RTC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTC_CR (0x400E1860U) /**< \brief (RTC) Control Register */
#define REG_RTC_MR (0x400E1864U) /**< \brief (RTC) Mode Register */
#define REG_RTC_TIMR (0x400E1868U) /**< \brief (RTC) Time Register */
#define REG_RTC_CALR (0x400E186CU) /**< \brief (RTC) Calendar Register */
#define REG_RTC_TIMALR (0x400E1870U) /**< \brief (RTC) Time Alarm Register */
#define REG_RTC_CALALR (0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
#define REG_RTC_SR (0x400E1878U) /**< \brief (RTC) Status Register */
#define REG_RTC_SCCR (0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
#define REG_RTC_IER (0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
#define REG_RTC_IDR (0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
#define REG_RTC_IMR (0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
#define REG_RTC_VER (0x400E188CU) /**< \brief (RTC) Valid Entry Register */
#else
#define REG_RTC_CR (*(RwReg*)0x400E1860U) /**< \brief (RTC) Control Register */
#define REG_RTC_MR (*(RwReg*)0x400E1864U) /**< \brief (RTC) Mode Register */
#define REG_RTC_TIMR (*(RwReg*)0x400E1868U) /**< \brief (RTC) Time Register */
#define REG_RTC_CALR (*(RwReg*)0x400E186CU) /**< \brief (RTC) Calendar Register */
#define REG_RTC_TIMALR (*(RwReg*)0x400E1870U) /**< \brief (RTC) Time Alarm Register */
#define REG_RTC_CALALR (*(RwReg*)0x400E1874U) /**< \brief (RTC) Calendar Alarm Register */
#define REG_RTC_SR (*(RoReg*)0x400E1878U) /**< \brief (RTC) Status Register */
#define REG_RTC_SCCR (*(WoReg*)0x400E187CU) /**< \brief (RTC) Status Clear Command Register */
#define REG_RTC_IER (*(WoReg*)0x400E1880U) /**< \brief (RTC) Interrupt Enable Register */
#define REG_RTC_IDR (*(WoReg*)0x400E1884U) /**< \brief (RTC) Interrupt Disable Register */
#define REG_RTC_IMR (*(RoReg*)0x400E1888U) /**< \brief (RTC) Interrupt Mask Register */
#define REG_RTC_VER (*(RoReg*)0x400E188CU) /**< \brief (RTC) Valid Entry Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_RTC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_RTT_INSTANCE_
#define _SAM4E_RTT_INSTANCE_
/* ========== Register definition for RTT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_RTT_MR (0x400E1830U) /**< \brief (RTT) Mode Register */
#define REG_RTT_AR (0x400E1834U) /**< \brief (RTT) Alarm Register */
#define REG_RTT_VR (0x400E1838U) /**< \brief (RTT) Value Register */
#define REG_RTT_SR (0x400E183CU) /**< \brief (RTT) Status Register */
#else
#define REG_RTT_MR (*(RwReg*)0x400E1830U) /**< \brief (RTT) Mode Register */
#define REG_RTT_AR (*(RwReg*)0x400E1834U) /**< \brief (RTT) Alarm Register */
#define REG_RTT_VR (*(RoReg*)0x400E1838U) /**< \brief (RTT) Value Register */
#define REG_RTT_SR (*(RoReg*)0x400E183CU) /**< \brief (RTT) Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_RTT_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_SMC_INSTANCE_
#define _SAM4E_SMC_INSTANCE_
/* ========== Register definition for SMC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SMC_SETUP0 (0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
#define REG_SMC_PULSE0 (0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
#define REG_SMC_CYCLE0 (0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
#define REG_SMC_MODE0 (0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
#define REG_SMC_SETUP1 (0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
#define REG_SMC_PULSE1 (0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
#define REG_SMC_CYCLE1 (0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
#define REG_SMC_MODE1 (0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
#define REG_SMC_SETUP2 (0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
#define REG_SMC_PULSE2 (0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
#define REG_SMC_CYCLE2 (0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
#define REG_SMC_MODE2 (0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
#define REG_SMC_SETUP3 (0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
#define REG_SMC_PULSE3 (0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
#define REG_SMC_CYCLE3 (0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
#define REG_SMC_MODE3 (0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
#define REG_SMC_OCMS (0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */
#define REG_SMC_KEY1 (0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2 (0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPMR (0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
#define REG_SMC_WPSR (0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */
#else
#define REG_SMC_SETUP0 (*(RwReg*)0x40060000U) /**< \brief (SMC) SMC Setup Register (CS_number = 0) */
#define REG_SMC_PULSE0 (*(RwReg*)0x40060004U) /**< \brief (SMC) SMC Pulse Register (CS_number = 0) */
#define REG_SMC_CYCLE0 (*(RwReg*)0x40060008U) /**< \brief (SMC) SMC Cycle Register (CS_number = 0) */
#define REG_SMC_MODE0 (*(RwReg*)0x4006000CU) /**< \brief (SMC) SMC Mode Register (CS_number = 0) */
#define REG_SMC_SETUP1 (*(RwReg*)0x40060010U) /**< \brief (SMC) SMC Setup Register (CS_number = 1) */
#define REG_SMC_PULSE1 (*(RwReg*)0x40060014U) /**< \brief (SMC) SMC Pulse Register (CS_number = 1) */
#define REG_SMC_CYCLE1 (*(RwReg*)0x40060018U) /**< \brief (SMC) SMC Cycle Register (CS_number = 1) */
#define REG_SMC_MODE1 (*(RwReg*)0x4006001CU) /**< \brief (SMC) SMC Mode Register (CS_number = 1) */
#define REG_SMC_SETUP2 (*(RwReg*)0x40060020U) /**< \brief (SMC) SMC Setup Register (CS_number = 2) */
#define REG_SMC_PULSE2 (*(RwReg*)0x40060024U) /**< \brief (SMC) SMC Pulse Register (CS_number = 2) */
#define REG_SMC_CYCLE2 (*(RwReg*)0x40060028U) /**< \brief (SMC) SMC Cycle Register (CS_number = 2) */
#define REG_SMC_MODE2 (*(RwReg*)0x4006002CU) /**< \brief (SMC) SMC Mode Register (CS_number = 2) */
#define REG_SMC_SETUP3 (*(RwReg*)0x40060030U) /**< \brief (SMC) SMC Setup Register (CS_number = 3) */
#define REG_SMC_PULSE3 (*(RwReg*)0x40060034U) /**< \brief (SMC) SMC Pulse Register (CS_number = 3) */
#define REG_SMC_CYCLE3 (*(RwReg*)0x40060038U) /**< \brief (SMC) SMC Cycle Register (CS_number = 3) */
#define REG_SMC_MODE3 (*(RwReg*)0x4006003CU) /**< \brief (SMC) SMC Mode Register (CS_number = 3) */
#define REG_SMC_OCMS (*(RwReg*)0x40060080U) /**< \brief (SMC) SMC OCMS MODE Register */
#define REG_SMC_KEY1 (*(WoReg*)0x40060084U) /**< \brief (SMC) SMC OCMS KEY1 Register */
#define REG_SMC_KEY2 (*(WoReg*)0x40060088U) /**< \brief (SMC) SMC OCMS KEY2 Register */
#define REG_SMC_WPMR (*(RwReg*)0x400600E4U) /**< \brief (SMC) SMC Write Protect Mode Register */
#define REG_SMC_WPSR (*(RoReg*)0x400600E8U) /**< \brief (SMC) SMC Write Protect Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_SMC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_SPI_INSTANCE_
#define _SAM4E_SPI_INSTANCE_
/* ========== Register definition for SPI peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SPI_CR (0x40088000U) /**< \brief (SPI) Control Register */
#define REG_SPI_MR (0x40088004U) /**< \brief (SPI) Mode Register */
#define REG_SPI_RDR (0x40088008U) /**< \brief (SPI) Receive Data Register */
#define REG_SPI_TDR (0x4008800CU) /**< \brief (SPI) Transmit Data Register */
#define REG_SPI_SR (0x40088010U) /**< \brief (SPI) Status Register */
#define REG_SPI_IER (0x40088014U) /**< \brief (SPI) Interrupt Enable Register */
#define REG_SPI_IDR (0x40088018U) /**< \brief (SPI) Interrupt Disable Register */
#define REG_SPI_IMR (0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */
#define REG_SPI_CSR (0x40088030U) /**< \brief (SPI) Chip Select Register */
#define REG_SPI_WPMR (0x400880E4U) /**< \brief (SPI) Write Protection Control Register */
#define REG_SPI_WPSR (0x400880E8U) /**< \brief (SPI) Write Protection Status Register */
#define REG_SPI_RPR (0x40088100U) /**< \brief (SPI) Receive Pointer Register */
#define REG_SPI_RCR (0x40088104U) /**< \brief (SPI) Receive Counter Register */
#define REG_SPI_TPR (0x40088108U) /**< \brief (SPI) Transmit Pointer Register */
#define REG_SPI_TCR (0x4008810CU) /**< \brief (SPI) Transmit Counter Register */
#define REG_SPI_RNPR (0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */
#define REG_SPI_RNCR (0x40088114U) /**< \brief (SPI) Receive Next Counter Register */
#define REG_SPI_TNPR (0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */
#define REG_SPI_TNCR (0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */
#define REG_SPI_PTCR (0x40088120U) /**< \brief (SPI) Transfer Control Register */
#define REG_SPI_PTSR (0x40088124U) /**< \brief (SPI) Transfer Status Register */
#else
#define REG_SPI_CR (*(WoReg*)0x40088000U) /**< \brief (SPI) Control Register */
#define REG_SPI_MR (*(RwReg*)0x40088004U) /**< \brief (SPI) Mode Register */
#define REG_SPI_RDR (*(RoReg*)0x40088008U) /**< \brief (SPI) Receive Data Register */
#define REG_SPI_TDR (*(WoReg*)0x4008800CU) /**< \brief (SPI) Transmit Data Register */
#define REG_SPI_SR (*(RoReg*)0x40088010U) /**< \brief (SPI) Status Register */
#define REG_SPI_IER (*(WoReg*)0x40088014U) /**< \brief (SPI) Interrupt Enable Register */
#define REG_SPI_IDR (*(WoReg*)0x40088018U) /**< \brief (SPI) Interrupt Disable Register */
#define REG_SPI_IMR (*(RoReg*)0x4008801CU) /**< \brief (SPI) Interrupt Mask Register */
#define REG_SPI_CSR (*(RwReg*)0x40088030U) /**< \brief (SPI) Chip Select Register */
#define REG_SPI_WPMR (*(RwReg*)0x400880E4U) /**< \brief (SPI) Write Protection Control Register */
#define REG_SPI_WPSR (*(RoReg*)0x400880E8U) /**< \brief (SPI) Write Protection Status Register */
#define REG_SPI_RPR (*(RwReg*)0x40088100U) /**< \brief (SPI) Receive Pointer Register */
#define REG_SPI_RCR (*(RwReg*)0x40088104U) /**< \brief (SPI) Receive Counter Register */
#define REG_SPI_TPR (*(RwReg*)0x40088108U) /**< \brief (SPI) Transmit Pointer Register */
#define REG_SPI_TCR (*(RwReg*)0x4008810CU) /**< \brief (SPI) Transmit Counter Register */
#define REG_SPI_RNPR (*(RwReg*)0x40088110U) /**< \brief (SPI) Receive Next Pointer Register */
#define REG_SPI_RNCR (*(RwReg*)0x40088114U) /**< \brief (SPI) Receive Next Counter Register */
#define REG_SPI_TNPR (*(RwReg*)0x40088118U) /**< \brief (SPI) Transmit Next Pointer Register */
#define REG_SPI_TNCR (*(RwReg*)0x4008811CU) /**< \brief (SPI) Transmit Next Counter Register */
#define REG_SPI_PTCR (*(WoReg*)0x40088120U) /**< \brief (SPI) Transfer Control Register */
#define REG_SPI_PTSR (*(RoReg*)0x40088124U) /**< \brief (SPI) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_SPI_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_SUPC_INSTANCE_
#define _SAM4E_SUPC_INSTANCE_
/* ========== Register definition for SUPC peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_SUPC_CR (0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
#define REG_SUPC_SMMR (0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
#define REG_SUPC_MR (0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
#define REG_SUPC_WUMR (0x400E181CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
#define REG_SUPC_WUIR (0x400E1820U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
#define REG_SUPC_SR (0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
#else
#define REG_SUPC_CR (*(WoReg*)0x400E1810U) /**< \brief (SUPC) Supply Controller Control Register */
#define REG_SUPC_SMMR (*(RwReg*)0x400E1814U) /**< \brief (SUPC) Supply Controller Supply Monitor Mode Register */
#define REG_SUPC_MR (*(RwReg*)0x400E1818U) /**< \brief (SUPC) Supply Controller Mode Register */
#define REG_SUPC_WUMR (*(RwReg*)0x400E181CU) /**< \brief (SUPC) Supply Controller Wake Up Mode Register */
#define REG_SUPC_WUIR (*(RwReg*)0x400E1820U) /**< \brief (SUPC) Supply Controller Wake Up Inputs Register */
#define REG_SUPC_SR (*(RoReg*)0x400E1824U) /**< \brief (SUPC) Supply Controller Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_SUPC_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_TC0_INSTANCE_
#define _SAM4E_TC0_INSTANCE_
/* ========== Register definition for TC0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC0_CCR0 (0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
#define REG_TC0_CMR0 (0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
#define REG_TC0_SMMR0 (0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
#define REG_TC0_RAB0 (0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */
#define REG_TC0_CV0 (0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */
#define REG_TC0_RA0 (0x40090014U) /**< \brief (TC0) Register A (channel = 0) */
#define REG_TC0_RB0 (0x40090018U) /**< \brief (TC0) Register B (channel = 0) */
#define REG_TC0_RC0 (0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */
#define REG_TC0_SR0 (0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */
#define REG_TC0_IER0 (0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
#define REG_TC0_IDR0 (0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
#define REG_TC0_IMR0 (0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
#define REG_TC0_EMR0 (0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
#define REG_TC0_CCR1 (0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
#define REG_TC0_CMR1 (0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
#define REG_TC0_SMMR1 (0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
#define REG_TC0_RAB1 (0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */
#define REG_TC0_CV1 (0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */
#define REG_TC0_RA1 (0x40090054U) /**< \brief (TC0) Register A (channel = 1) */
#define REG_TC0_RB1 (0x40090058U) /**< \brief (TC0) Register B (channel = 1) */
#define REG_TC0_RC1 (0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */
#define REG_TC0_SR1 (0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */
#define REG_TC0_IER1 (0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
#define REG_TC0_IDR1 (0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
#define REG_TC0_IMR1 (0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
#define REG_TC0_EMR1 (0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
#define REG_TC0_CCR2 (0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
#define REG_TC0_CMR2 (0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
#define REG_TC0_SMMR2 (0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
#define REG_TC0_RAB2 (0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */
#define REG_TC0_CV2 (0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */
#define REG_TC0_RA2 (0x40090094U) /**< \brief (TC0) Register A (channel = 2) */
#define REG_TC0_RB2 (0x40090098U) /**< \brief (TC0) Register B (channel = 2) */
#define REG_TC0_RC2 (0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */
#define REG_TC0_SR2 (0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */
#define REG_TC0_IER2 (0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
#define REG_TC0_IDR2 (0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
#define REG_TC0_IMR2 (0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
#define REG_TC0_EMR2 (0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
#define REG_TC0_BCR (0x400900C0U) /**< \brief (TC0) Block Control Register */
#define REG_TC0_BMR (0x400900C4U) /**< \brief (TC0) Block Mode Register */
#define REG_TC0_QIER (0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
#define REG_TC0_QIDR (0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
#define REG_TC0_QIMR (0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
#define REG_TC0_QISR (0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
#define REG_TC0_FMR (0x400900D8U) /**< \brief (TC0) Fault Mode Register */
#define REG_TC0_WPMR (0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */
#define REG_TC0_RPR0 (0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */
#define REG_TC0_RCR0 (0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */
#define REG_TC0_RNPR0 (0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */
#define REG_TC0_RNCR0 (0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */
#define REG_TC0_PTCR0 (0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */
#define REG_TC0_PTSR0 (0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */
#define REG_TC0_RPR1 (0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */
#define REG_TC0_RCR1 (0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */
#define REG_TC0_RNPR1 (0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */
#define REG_TC0_RNCR1 (0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */
#define REG_TC0_PTCR1 (0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */
#define REG_TC0_PTSR1 (0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */
#define REG_TC0_RPR2 (0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */
#define REG_TC0_RCR2 (0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */
#define REG_TC0_RNPR2 (0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */
#define REG_TC0_RNCR2 (0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */
#define REG_TC0_PTCR2 (0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */
#define REG_TC0_PTSR2 (0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */
#else
#define REG_TC0_CCR0 (*(WoReg*)0x40090000U) /**< \brief (TC0) Channel Control Register (channel = 0) */
#define REG_TC0_CMR0 (*(RwReg*)0x40090004U) /**< \brief (TC0) Channel Mode Register (channel = 0) */
#define REG_TC0_SMMR0 (*(RwReg*)0x40090008U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 0) */
#define REG_TC0_RAB0 (*(RoReg*)0x4009000CU) /**< \brief (TC0) Register AB (channel = 0) */
#define REG_TC0_CV0 (*(RoReg*)0x40090010U) /**< \brief (TC0) Counter Value (channel = 0) */
#define REG_TC0_RA0 (*(RwReg*)0x40090014U) /**< \brief (TC0) Register A (channel = 0) */
#define REG_TC0_RB0 (*(RwReg*)0x40090018U) /**< \brief (TC0) Register B (channel = 0) */
#define REG_TC0_RC0 (*(RwReg*)0x4009001CU) /**< \brief (TC0) Register C (channel = 0) */
#define REG_TC0_SR0 (*(RoReg*)0x40090020U) /**< \brief (TC0) Status Register (channel = 0) */
#define REG_TC0_IER0 (*(WoReg*)0x40090024U) /**< \brief (TC0) Interrupt Enable Register (channel = 0) */
#define REG_TC0_IDR0 (*(WoReg*)0x40090028U) /**< \brief (TC0) Interrupt Disable Register (channel = 0) */
#define REG_TC0_IMR0 (*(RoReg*)0x4009002CU) /**< \brief (TC0) Interrupt Mask Register (channel = 0) */
#define REG_TC0_EMR0 (*(RwReg*)0x40090030U) /**< \brief (TC0) Extended Mode Register (channel = 0) */
#define REG_TC0_CCR1 (*(WoReg*)0x40090040U) /**< \brief (TC0) Channel Control Register (channel = 1) */
#define REG_TC0_CMR1 (*(RwReg*)0x40090044U) /**< \brief (TC0) Channel Mode Register (channel = 1) */
#define REG_TC0_SMMR1 (*(RwReg*)0x40090048U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 1) */
#define REG_TC0_RAB1 (*(RoReg*)0x4009004CU) /**< \brief (TC0) Register AB (channel = 1) */
#define REG_TC0_CV1 (*(RoReg*)0x40090050U) /**< \brief (TC0) Counter Value (channel = 1) */
#define REG_TC0_RA1 (*(RwReg*)0x40090054U) /**< \brief (TC0) Register A (channel = 1) */
#define REG_TC0_RB1 (*(RwReg*)0x40090058U) /**< \brief (TC0) Register B (channel = 1) */
#define REG_TC0_RC1 (*(RwReg*)0x4009005CU) /**< \brief (TC0) Register C (channel = 1) */
#define REG_TC0_SR1 (*(RoReg*)0x40090060U) /**< \brief (TC0) Status Register (channel = 1) */
#define REG_TC0_IER1 (*(WoReg*)0x40090064U) /**< \brief (TC0) Interrupt Enable Register (channel = 1) */
#define REG_TC0_IDR1 (*(WoReg*)0x40090068U) /**< \brief (TC0) Interrupt Disable Register (channel = 1) */
#define REG_TC0_IMR1 (*(RoReg*)0x4009006CU) /**< \brief (TC0) Interrupt Mask Register (channel = 1) */
#define REG_TC0_EMR1 (*(RwReg*)0x40090070U) /**< \brief (TC0) Extended Mode Register (channel = 1) */
#define REG_TC0_CCR2 (*(WoReg*)0x40090080U) /**< \brief (TC0) Channel Control Register (channel = 2) */
#define REG_TC0_CMR2 (*(RwReg*)0x40090084U) /**< \brief (TC0) Channel Mode Register (channel = 2) */
#define REG_TC0_SMMR2 (*(RwReg*)0x40090088U) /**< \brief (TC0) Stepper Motor Mode Register (channel = 2) */
#define REG_TC0_RAB2 (*(RoReg*)0x4009008CU) /**< \brief (TC0) Register AB (channel = 2) */
#define REG_TC0_CV2 (*(RoReg*)0x40090090U) /**< \brief (TC0) Counter Value (channel = 2) */
#define REG_TC0_RA2 (*(RwReg*)0x40090094U) /**< \brief (TC0) Register A (channel = 2) */
#define REG_TC0_RB2 (*(RwReg*)0x40090098U) /**< \brief (TC0) Register B (channel = 2) */
#define REG_TC0_RC2 (*(RwReg*)0x4009009CU) /**< \brief (TC0) Register C (channel = 2) */
#define REG_TC0_SR2 (*(RoReg*)0x400900A0U) /**< \brief (TC0) Status Register (channel = 2) */
#define REG_TC0_IER2 (*(WoReg*)0x400900A4U) /**< \brief (TC0) Interrupt Enable Register (channel = 2) */
#define REG_TC0_IDR2 (*(WoReg*)0x400900A8U) /**< \brief (TC0) Interrupt Disable Register (channel = 2) */
#define REG_TC0_IMR2 (*(RoReg*)0x400900ACU) /**< \brief (TC0) Interrupt Mask Register (channel = 2) */
#define REG_TC0_EMR2 (*(RwReg*)0x400900B0U) /**< \brief (TC0) Extended Mode Register (channel = 2) */
#define REG_TC0_BCR (*(WoReg*)0x400900C0U) /**< \brief (TC0) Block Control Register */
#define REG_TC0_BMR (*(RwReg*)0x400900C4U) /**< \brief (TC0) Block Mode Register */
#define REG_TC0_QIER (*(WoReg*)0x400900C8U) /**< \brief (TC0) QDEC Interrupt Enable Register */
#define REG_TC0_QIDR (*(WoReg*)0x400900CCU) /**< \brief (TC0) QDEC Interrupt Disable Register */
#define REG_TC0_QIMR (*(RoReg*)0x400900D0U) /**< \brief (TC0) QDEC Interrupt Mask Register */
#define REG_TC0_QISR (*(RoReg*)0x400900D4U) /**< \brief (TC0) QDEC Interrupt Status Register */
#define REG_TC0_FMR (*(RwReg*)0x400900D8U) /**< \brief (TC0) Fault Mode Register */
#define REG_TC0_WPMR (*(RwReg*)0x400900E4U) /**< \brief (TC0) Write Protect Mode Register */
#define REG_TC0_RPR0 (*(RwReg*)0x40090100U) /**< \brief (TC0) Receive Pointer Register (pdc = 0) */
#define REG_TC0_RCR0 (*(RwReg*)0x40090104U) /**< \brief (TC0) Receive Counter Register (pdc = 0) */
#define REG_TC0_RNPR0 (*(RwReg*)0x40090110U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 0) */
#define REG_TC0_RNCR0 (*(RwReg*)0x40090114U) /**< \brief (TC0) Receive Next Counter Register (pdc = 0) */
#define REG_TC0_PTCR0 (*(WoReg*)0x40090120U) /**< \brief (TC0) Transfer Control Register (pdc = 0) */
#define REG_TC0_PTSR0 (*(RoReg*)0x40090124U) /**< \brief (TC0) Transfer Status Register (pdc = 0) */
#define REG_TC0_RPR1 (*(RwReg*)0x40090140U) /**< \brief (TC0) Receive Pointer Register (pdc = 1) */
#define REG_TC0_RCR1 (*(RwReg*)0x40090144U) /**< \brief (TC0) Receive Counter Register (pdc = 1) */
#define REG_TC0_RNPR1 (*(RwReg*)0x40090150U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 1) */
#define REG_TC0_RNCR1 (*(RwReg*)0x40090154U) /**< \brief (TC0) Receive Next Counter Register (pdc = 1) */
#define REG_TC0_PTCR1 (*(WoReg*)0x40090160U) /**< \brief (TC0) Transfer Control Register (pdc = 1) */
#define REG_TC0_PTSR1 (*(RoReg*)0x40090164U) /**< \brief (TC0) Transfer Status Register (pdc = 1) */
#define REG_TC0_RPR2 (*(RwReg*)0x40090180U) /**< \brief (TC0) Receive Pointer Register (pdc = 2) */
#define REG_TC0_RCR2 (*(RwReg*)0x40090184U) /**< \brief (TC0) Receive Counter Register (pdc = 2) */
#define REG_TC0_RNPR2 (*(RwReg*)0x40090190U) /**< \brief (TC0) Receive Next Pointer Register (pdc = 2) */
#define REG_TC0_RNCR2 (*(RwReg*)0x40090194U) /**< \brief (TC0) Receive Next Counter Register (pdc = 2) */
#define REG_TC0_PTCR2 (*(WoReg*)0x400901A0U) /**< \brief (TC0) Transfer Control Register (pdc = 2) */
#define REG_TC0_PTSR2 (*(RoReg*)0x400901A4U) /**< \brief (TC0) Transfer Status Register (pdc = 2) */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_TC0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_TC1_INSTANCE_
#define _SAM4E_TC1_INSTANCE_
/* ========== Register definition for TC1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC1_CCR0 (0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
#define REG_TC1_CMR0 (0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
#define REG_TC1_SMMR0 (0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
#define REG_TC1_RAB0 (0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */
#define REG_TC1_CV0 (0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */
#define REG_TC1_RA0 (0x40094014U) /**< \brief (TC1) Register A (channel = 0) */
#define REG_TC1_RB0 (0x40094018U) /**< \brief (TC1) Register B (channel = 0) */
#define REG_TC1_RC0 (0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */
#define REG_TC1_SR0 (0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */
#define REG_TC1_IER0 (0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
#define REG_TC1_IDR0 (0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
#define REG_TC1_IMR0 (0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
#define REG_TC1_EMR0 (0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
#define REG_TC1_CCR1 (0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
#define REG_TC1_CMR1 (0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
#define REG_TC1_SMMR1 (0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
#define REG_TC1_RAB1 (0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */
#define REG_TC1_CV1 (0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */
#define REG_TC1_RA1 (0x40094054U) /**< \brief (TC1) Register A (channel = 1) */
#define REG_TC1_RB1 (0x40094058U) /**< \brief (TC1) Register B (channel = 1) */
#define REG_TC1_RC1 (0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */
#define REG_TC1_SR1 (0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */
#define REG_TC1_IER1 (0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
#define REG_TC1_IDR1 (0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
#define REG_TC1_IMR1 (0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
#define REG_TC1_EMR1 (0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
#define REG_TC1_CCR2 (0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
#define REG_TC1_CMR2 (0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
#define REG_TC1_SMMR2 (0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
#define REG_TC1_RAB2 (0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */
#define REG_TC1_CV2 (0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */
#define REG_TC1_RA2 (0x40094094U) /**< \brief (TC1) Register A (channel = 2) */
#define REG_TC1_RB2 (0x40094098U) /**< \brief (TC1) Register B (channel = 2) */
#define REG_TC1_RC2 (0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */
#define REG_TC1_SR2 (0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */
#define REG_TC1_IER2 (0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
#define REG_TC1_IDR2 (0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
#define REG_TC1_IMR2 (0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
#define REG_TC1_EMR2 (0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
#define REG_TC1_BCR (0x400940C0U) /**< \brief (TC1) Block Control Register */
#define REG_TC1_BMR (0x400940C4U) /**< \brief (TC1) Block Mode Register */
#define REG_TC1_QIER (0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
#define REG_TC1_QIDR (0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
#define REG_TC1_QIMR (0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
#define REG_TC1_QISR (0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
#define REG_TC1_FMR (0x400940D8U) /**< \brief (TC1) Fault Mode Register */
#define REG_TC1_WPMR (0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */
#define REG_TC1_RPR0 (0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */
#define REG_TC1_RCR0 (0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */
#define REG_TC1_RNPR0 (0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */
#define REG_TC1_RNCR0 (0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */
#define REG_TC1_PTCR0 (0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */
#define REG_TC1_PTSR0 (0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */
#define REG_TC1_RPR1 (0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */
#define REG_TC1_RCR1 (0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */
#define REG_TC1_RNPR1 (0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */
#define REG_TC1_RNCR1 (0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */
#define REG_TC1_PTCR1 (0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */
#define REG_TC1_PTSR1 (0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */
#define REG_TC1_RPR2 (0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */
#define REG_TC1_RCR2 (0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */
#define REG_TC1_RNPR2 (0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */
#define REG_TC1_RNCR2 (0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */
#define REG_TC1_PTCR2 (0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */
#define REG_TC1_PTSR2 (0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */
#else
#define REG_TC1_CCR0 (*(WoReg*)0x40094000U) /**< \brief (TC1) Channel Control Register (channel = 0) */
#define REG_TC1_CMR0 (*(RwReg*)0x40094004U) /**< \brief (TC1) Channel Mode Register (channel = 0) */
#define REG_TC1_SMMR0 (*(RwReg*)0x40094008U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 0) */
#define REG_TC1_RAB0 (*(RoReg*)0x4009400CU) /**< \brief (TC1) Register AB (channel = 0) */
#define REG_TC1_CV0 (*(RoReg*)0x40094010U) /**< \brief (TC1) Counter Value (channel = 0) */
#define REG_TC1_RA0 (*(RwReg*)0x40094014U) /**< \brief (TC1) Register A (channel = 0) */
#define REG_TC1_RB0 (*(RwReg*)0x40094018U) /**< \brief (TC1) Register B (channel = 0) */
#define REG_TC1_RC0 (*(RwReg*)0x4009401CU) /**< \brief (TC1) Register C (channel = 0) */
#define REG_TC1_SR0 (*(RoReg*)0x40094020U) /**< \brief (TC1) Status Register (channel = 0) */
#define REG_TC1_IER0 (*(WoReg*)0x40094024U) /**< \brief (TC1) Interrupt Enable Register (channel = 0) */
#define REG_TC1_IDR0 (*(WoReg*)0x40094028U) /**< \brief (TC1) Interrupt Disable Register (channel = 0) */
#define REG_TC1_IMR0 (*(RoReg*)0x4009402CU) /**< \brief (TC1) Interrupt Mask Register (channel = 0) */
#define REG_TC1_EMR0 (*(RwReg*)0x40094030U) /**< \brief (TC1) Extended Mode Register (channel = 0) */
#define REG_TC1_CCR1 (*(WoReg*)0x40094040U) /**< \brief (TC1) Channel Control Register (channel = 1) */
#define REG_TC1_CMR1 (*(RwReg*)0x40094044U) /**< \brief (TC1) Channel Mode Register (channel = 1) */
#define REG_TC1_SMMR1 (*(RwReg*)0x40094048U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 1) */
#define REG_TC1_RAB1 (*(RoReg*)0x4009404CU) /**< \brief (TC1) Register AB (channel = 1) */
#define REG_TC1_CV1 (*(RoReg*)0x40094050U) /**< \brief (TC1) Counter Value (channel = 1) */
#define REG_TC1_RA1 (*(RwReg*)0x40094054U) /**< \brief (TC1) Register A (channel = 1) */
#define REG_TC1_RB1 (*(RwReg*)0x40094058U) /**< \brief (TC1) Register B (channel = 1) */
#define REG_TC1_RC1 (*(RwReg*)0x4009405CU) /**< \brief (TC1) Register C (channel = 1) */
#define REG_TC1_SR1 (*(RoReg*)0x40094060U) /**< \brief (TC1) Status Register (channel = 1) */
#define REG_TC1_IER1 (*(WoReg*)0x40094064U) /**< \brief (TC1) Interrupt Enable Register (channel = 1) */
#define REG_TC1_IDR1 (*(WoReg*)0x40094068U) /**< \brief (TC1) Interrupt Disable Register (channel = 1) */
#define REG_TC1_IMR1 (*(RoReg*)0x4009406CU) /**< \brief (TC1) Interrupt Mask Register (channel = 1) */
#define REG_TC1_EMR1 (*(RwReg*)0x40094070U) /**< \brief (TC1) Extended Mode Register (channel = 1) */
#define REG_TC1_CCR2 (*(WoReg*)0x40094080U) /**< \brief (TC1) Channel Control Register (channel = 2) */
#define REG_TC1_CMR2 (*(RwReg*)0x40094084U) /**< \brief (TC1) Channel Mode Register (channel = 2) */
#define REG_TC1_SMMR2 (*(RwReg*)0x40094088U) /**< \brief (TC1) Stepper Motor Mode Register (channel = 2) */
#define REG_TC1_RAB2 (*(RoReg*)0x4009408CU) /**< \brief (TC1) Register AB (channel = 2) */
#define REG_TC1_CV2 (*(RoReg*)0x40094090U) /**< \brief (TC1) Counter Value (channel = 2) */
#define REG_TC1_RA2 (*(RwReg*)0x40094094U) /**< \brief (TC1) Register A (channel = 2) */
#define REG_TC1_RB2 (*(RwReg*)0x40094098U) /**< \brief (TC1) Register B (channel = 2) */
#define REG_TC1_RC2 (*(RwReg*)0x4009409CU) /**< \brief (TC1) Register C (channel = 2) */
#define REG_TC1_SR2 (*(RoReg*)0x400940A0U) /**< \brief (TC1) Status Register (channel = 2) */
#define REG_TC1_IER2 (*(WoReg*)0x400940A4U) /**< \brief (TC1) Interrupt Enable Register (channel = 2) */
#define REG_TC1_IDR2 (*(WoReg*)0x400940A8U) /**< \brief (TC1) Interrupt Disable Register (channel = 2) */
#define REG_TC1_IMR2 (*(RoReg*)0x400940ACU) /**< \brief (TC1) Interrupt Mask Register (channel = 2) */
#define REG_TC1_EMR2 (*(RwReg*)0x400940B0U) /**< \brief (TC1) Extended Mode Register (channel = 2) */
#define REG_TC1_BCR (*(WoReg*)0x400940C0U) /**< \brief (TC1) Block Control Register */
#define REG_TC1_BMR (*(RwReg*)0x400940C4U) /**< \brief (TC1) Block Mode Register */
#define REG_TC1_QIER (*(WoReg*)0x400940C8U) /**< \brief (TC1) QDEC Interrupt Enable Register */
#define REG_TC1_QIDR (*(WoReg*)0x400940CCU) /**< \brief (TC1) QDEC Interrupt Disable Register */
#define REG_TC1_QIMR (*(RoReg*)0x400940D0U) /**< \brief (TC1) QDEC Interrupt Mask Register */
#define REG_TC1_QISR (*(RoReg*)0x400940D4U) /**< \brief (TC1) QDEC Interrupt Status Register */
#define REG_TC1_FMR (*(RwReg*)0x400940D8U) /**< \brief (TC1) Fault Mode Register */
#define REG_TC1_WPMR (*(RwReg*)0x400940E4U) /**< \brief (TC1) Write Protect Mode Register */
#define REG_TC1_RPR0 (*(RwReg*)0x40094100U) /**< \brief (TC1) Receive Pointer Register (pdc = 0) */
#define REG_TC1_RCR0 (*(RwReg*)0x40094104U) /**< \brief (TC1) Receive Counter Register (pdc = 0) */
#define REG_TC1_RNPR0 (*(RwReg*)0x40094110U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 0) */
#define REG_TC1_RNCR0 (*(RwReg*)0x40094114U) /**< \brief (TC1) Receive Next Counter Register (pdc = 0) */
#define REG_TC1_PTCR0 (*(WoReg*)0x40094120U) /**< \brief (TC1) Transfer Control Register (pdc = 0) */
#define REG_TC1_PTSR0 (*(RoReg*)0x40094124U) /**< \brief (TC1) Transfer Status Register (pdc = 0) */
#define REG_TC1_RPR1 (*(RwReg*)0x40094140U) /**< \brief (TC1) Receive Pointer Register (pdc = 1) */
#define REG_TC1_RCR1 (*(RwReg*)0x40094144U) /**< \brief (TC1) Receive Counter Register (pdc = 1) */
#define REG_TC1_RNPR1 (*(RwReg*)0x40094150U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 1) */
#define REG_TC1_RNCR1 (*(RwReg*)0x40094154U) /**< \brief (TC1) Receive Next Counter Register (pdc = 1) */
#define REG_TC1_PTCR1 (*(WoReg*)0x40094160U) /**< \brief (TC1) Transfer Control Register (pdc = 1) */
#define REG_TC1_PTSR1 (*(RoReg*)0x40094164U) /**< \brief (TC1) Transfer Status Register (pdc = 1) */
#define REG_TC1_RPR2 (*(RwReg*)0x40094180U) /**< \brief (TC1) Receive Pointer Register (pdc = 2) */
#define REG_TC1_RCR2 (*(RwReg*)0x40094184U) /**< \brief (TC1) Receive Counter Register (pdc = 2) */
#define REG_TC1_RNPR2 (*(RwReg*)0x40094190U) /**< \brief (TC1) Receive Next Pointer Register (pdc = 2) */
#define REG_TC1_RNCR2 (*(RwReg*)0x40094194U) /**< \brief (TC1) Receive Next Counter Register (pdc = 2) */
#define REG_TC1_PTCR2 (*(WoReg*)0x400941A0U) /**< \brief (TC1) Transfer Control Register (pdc = 2) */
#define REG_TC1_PTSR2 (*(RoReg*)0x400941A4U) /**< \brief (TC1) Transfer Status Register (pdc = 2) */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_TC1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_TC2_INSTANCE_
#define _SAM4E_TC2_INSTANCE_
/* ========== Register definition for TC2 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TC2_CCR0 (0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
#define REG_TC2_CMR0 (0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
#define REG_TC2_SMMR0 (0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
#define REG_TC2_RAB0 (0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */
#define REG_TC2_CV0 (0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */
#define REG_TC2_RA0 (0x40098014U) /**< \brief (TC2) Register A (channel = 0) */
#define REG_TC2_RB0 (0x40098018U) /**< \brief (TC2) Register B (channel = 0) */
#define REG_TC2_RC0 (0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */
#define REG_TC2_SR0 (0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */
#define REG_TC2_IER0 (0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
#define REG_TC2_IDR0 (0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
#define REG_TC2_IMR0 (0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
#define REG_TC2_EMR0 (0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
#define REG_TC2_CCR1 (0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
#define REG_TC2_CMR1 (0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
#define REG_TC2_SMMR1 (0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
#define REG_TC2_RAB1 (0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */
#define REG_TC2_CV1 (0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */
#define REG_TC2_RA1 (0x40098054U) /**< \brief (TC2) Register A (channel = 1) */
#define REG_TC2_RB1 (0x40098058U) /**< \brief (TC2) Register B (channel = 1) */
#define REG_TC2_RC1 (0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */
#define REG_TC2_SR1 (0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */
#define REG_TC2_IER1 (0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
#define REG_TC2_IDR1 (0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
#define REG_TC2_IMR1 (0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
#define REG_TC2_EMR1 (0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
#define REG_TC2_CCR2 (0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
#define REG_TC2_CMR2 (0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
#define REG_TC2_SMMR2 (0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
#define REG_TC2_RAB2 (0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */
#define REG_TC2_CV2 (0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */
#define REG_TC2_RA2 (0x40098094U) /**< \brief (TC2) Register A (channel = 2) */
#define REG_TC2_RB2 (0x40098098U) /**< \brief (TC2) Register B (channel = 2) */
#define REG_TC2_RC2 (0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */
#define REG_TC2_SR2 (0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */
#define REG_TC2_IER2 (0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
#define REG_TC2_IDR2 (0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
#define REG_TC2_IMR2 (0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
#define REG_TC2_EMR2 (0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
#define REG_TC2_BCR (0x400980C0U) /**< \brief (TC2) Block Control Register */
#define REG_TC2_BMR (0x400980C4U) /**< \brief (TC2) Block Mode Register */
#define REG_TC2_QIER (0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
#define REG_TC2_QIDR (0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
#define REG_TC2_QIMR (0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
#define REG_TC2_QISR (0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
#define REG_TC2_FMR (0x400980D8U) /**< \brief (TC2) Fault Mode Register */
#define REG_TC2_WPMR (0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */
#else
#define REG_TC2_CCR0 (*(WoReg*)0x40098000U) /**< \brief (TC2) Channel Control Register (channel = 0) */
#define REG_TC2_CMR0 (*(RwReg*)0x40098004U) /**< \brief (TC2) Channel Mode Register (channel = 0) */
#define REG_TC2_SMMR0 (*(RwReg*)0x40098008U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 0) */
#define REG_TC2_RAB0 (*(RoReg*)0x4009800CU) /**< \brief (TC2) Register AB (channel = 0) */
#define REG_TC2_CV0 (*(RoReg*)0x40098010U) /**< \brief (TC2) Counter Value (channel = 0) */
#define REG_TC2_RA0 (*(RwReg*)0x40098014U) /**< \brief (TC2) Register A (channel = 0) */
#define REG_TC2_RB0 (*(RwReg*)0x40098018U) /**< \brief (TC2) Register B (channel = 0) */
#define REG_TC2_RC0 (*(RwReg*)0x4009801CU) /**< \brief (TC2) Register C (channel = 0) */
#define REG_TC2_SR0 (*(RoReg*)0x40098020U) /**< \brief (TC2) Status Register (channel = 0) */
#define REG_TC2_IER0 (*(WoReg*)0x40098024U) /**< \brief (TC2) Interrupt Enable Register (channel = 0) */
#define REG_TC2_IDR0 (*(WoReg*)0x40098028U) /**< \brief (TC2) Interrupt Disable Register (channel = 0) */
#define REG_TC2_IMR0 (*(RoReg*)0x4009802CU) /**< \brief (TC2) Interrupt Mask Register (channel = 0) */
#define REG_TC2_EMR0 (*(RwReg*)0x40098030U) /**< \brief (TC2) Extended Mode Register (channel = 0) */
#define REG_TC2_CCR1 (*(WoReg*)0x40098040U) /**< \brief (TC2) Channel Control Register (channel = 1) */
#define REG_TC2_CMR1 (*(RwReg*)0x40098044U) /**< \brief (TC2) Channel Mode Register (channel = 1) */
#define REG_TC2_SMMR1 (*(RwReg*)0x40098048U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 1) */
#define REG_TC2_RAB1 (*(RoReg*)0x4009804CU) /**< \brief (TC2) Register AB (channel = 1) */
#define REG_TC2_CV1 (*(RoReg*)0x40098050U) /**< \brief (TC2) Counter Value (channel = 1) */
#define REG_TC2_RA1 (*(RwReg*)0x40098054U) /**< \brief (TC2) Register A (channel = 1) */
#define REG_TC2_RB1 (*(RwReg*)0x40098058U) /**< \brief (TC2) Register B (channel = 1) */
#define REG_TC2_RC1 (*(RwReg*)0x4009805CU) /**< \brief (TC2) Register C (channel = 1) */
#define REG_TC2_SR1 (*(RoReg*)0x40098060U) /**< \brief (TC2) Status Register (channel = 1) */
#define REG_TC2_IER1 (*(WoReg*)0x40098064U) /**< \brief (TC2) Interrupt Enable Register (channel = 1) */
#define REG_TC2_IDR1 (*(WoReg*)0x40098068U) /**< \brief (TC2) Interrupt Disable Register (channel = 1) */
#define REG_TC2_IMR1 (*(RoReg*)0x4009806CU) /**< \brief (TC2) Interrupt Mask Register (channel = 1) */
#define REG_TC2_EMR1 (*(RwReg*)0x40098070U) /**< \brief (TC2) Extended Mode Register (channel = 1) */
#define REG_TC2_CCR2 (*(WoReg*)0x40098080U) /**< \brief (TC2) Channel Control Register (channel = 2) */
#define REG_TC2_CMR2 (*(RwReg*)0x40098084U) /**< \brief (TC2) Channel Mode Register (channel = 2) */
#define REG_TC2_SMMR2 (*(RwReg*)0x40098088U) /**< \brief (TC2) Stepper Motor Mode Register (channel = 2) */
#define REG_TC2_RAB2 (*(RoReg*)0x4009808CU) /**< \brief (TC2) Register AB (channel = 2) */
#define REG_TC2_CV2 (*(RoReg*)0x40098090U) /**< \brief (TC2) Counter Value (channel = 2) */
#define REG_TC2_RA2 (*(RwReg*)0x40098094U) /**< \brief (TC2) Register A (channel = 2) */
#define REG_TC2_RB2 (*(RwReg*)0x40098098U) /**< \brief (TC2) Register B (channel = 2) */
#define REG_TC2_RC2 (*(RwReg*)0x4009809CU) /**< \brief (TC2) Register C (channel = 2) */
#define REG_TC2_SR2 (*(RoReg*)0x400980A0U) /**< \brief (TC2) Status Register (channel = 2) */
#define REG_TC2_IER2 (*(WoReg*)0x400980A4U) /**< \brief (TC2) Interrupt Enable Register (channel = 2) */
#define REG_TC2_IDR2 (*(WoReg*)0x400980A8U) /**< \brief (TC2) Interrupt Disable Register (channel = 2) */
#define REG_TC2_IMR2 (*(RoReg*)0x400980ACU) /**< \brief (TC2) Interrupt Mask Register (channel = 2) */
#define REG_TC2_EMR2 (*(RwReg*)0x400980B0U) /**< \brief (TC2) Extended Mode Register (channel = 2) */
#define REG_TC2_BCR (*(WoReg*)0x400980C0U) /**< \brief (TC2) Block Control Register */
#define REG_TC2_BMR (*(RwReg*)0x400980C4U) /**< \brief (TC2) Block Mode Register */
#define REG_TC2_QIER (*(WoReg*)0x400980C8U) /**< \brief (TC2) QDEC Interrupt Enable Register */
#define REG_TC2_QIDR (*(WoReg*)0x400980CCU) /**< \brief (TC2) QDEC Interrupt Disable Register */
#define REG_TC2_QIMR (*(RoReg*)0x400980D0U) /**< \brief (TC2) QDEC Interrupt Mask Register */
#define REG_TC2_QISR (*(RoReg*)0x400980D4U) /**< \brief (TC2) QDEC Interrupt Status Register */
#define REG_TC2_FMR (*(RwReg*)0x400980D8U) /**< \brief (TC2) Fault Mode Register */
#define REG_TC2_WPMR (*(RwReg*)0x400980E4U) /**< \brief (TC2) Write Protect Mode Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_TC2_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_TWI0_INSTANCE_
#define _SAM4E_TWI0_INSTANCE_
/* ========== Register definition for TWI0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TWI0_CR (0x400A8000U) /**< \brief (TWI0) Control Register */
#define REG_TWI0_MMR (0x400A8004U) /**< \brief (TWI0) Master Mode Register */
#define REG_TWI0_SMR (0x400A8008U) /**< \brief (TWI0) Slave Mode Register */
#define REG_TWI0_IADR (0x400A800CU) /**< \brief (TWI0) Internal Address Register */
#define REG_TWI0_CWGR (0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */
#define REG_TWI0_SR (0x400A8020U) /**< \brief (TWI0) Status Register */
#define REG_TWI0_IER (0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */
#define REG_TWI0_IDR (0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */
#define REG_TWI0_IMR (0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */
#define REG_TWI0_RHR (0x400A8030U) /**< \brief (TWI0) Receive Holding Register */
#define REG_TWI0_THR (0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */
#define REG_TWI0_WPROT_MODE (0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */
#define REG_TWI0_WPROT_STATUS (0x400A80E8U) /**< \brief (TWI0) Protection Status Register */
#define REG_TWI0_RPR (0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */
#define REG_TWI0_RCR (0x400A8104U) /**< \brief (TWI0) Receive Counter Register */
#define REG_TWI0_TPR (0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */
#define REG_TWI0_TCR (0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */
#define REG_TWI0_RNPR (0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */
#define REG_TWI0_RNCR (0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */
#define REG_TWI0_TNPR (0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */
#define REG_TWI0_TNCR (0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */
#define REG_TWI0_PTCR (0x400A8120U) /**< \brief (TWI0) Transfer Control Register */
#define REG_TWI0_PTSR (0x400A8124U) /**< \brief (TWI0) Transfer Status Register */
#else
#define REG_TWI0_CR (*(WoReg*)0x400A8000U) /**< \brief (TWI0) Control Register */
#define REG_TWI0_MMR (*(RwReg*)0x400A8004U) /**< \brief (TWI0) Master Mode Register */
#define REG_TWI0_SMR (*(RwReg*)0x400A8008U) /**< \brief (TWI0) Slave Mode Register */
#define REG_TWI0_IADR (*(RwReg*)0x400A800CU) /**< \brief (TWI0) Internal Address Register */
#define REG_TWI0_CWGR (*(RwReg*)0x400A8010U) /**< \brief (TWI0) Clock Waveform Generator Register */
#define REG_TWI0_SR (*(RoReg*)0x400A8020U) /**< \brief (TWI0) Status Register */
#define REG_TWI0_IER (*(WoReg*)0x400A8024U) /**< \brief (TWI0) Interrupt Enable Register */
#define REG_TWI0_IDR (*(WoReg*)0x400A8028U) /**< \brief (TWI0) Interrupt Disable Register */
#define REG_TWI0_IMR (*(RoReg*)0x400A802CU) /**< \brief (TWI0) Interrupt Mask Register */
#define REG_TWI0_RHR (*(RoReg*)0x400A8030U) /**< \brief (TWI0) Receive Holding Register */
#define REG_TWI0_THR (*(WoReg*)0x400A8034U) /**< \brief (TWI0) Transmit Holding Register */
#define REG_TWI0_WPROT_MODE (*(RwReg*)0x400A80E4U) /**< \brief (TWI0) Protection Mode Register */
#define REG_TWI0_WPROT_STATUS (*(RoReg*)0x400A80E8U) /**< \brief (TWI0) Protection Status Register */
#define REG_TWI0_RPR (*(RwReg*)0x400A8100U) /**< \brief (TWI0) Receive Pointer Register */
#define REG_TWI0_RCR (*(RwReg*)0x400A8104U) /**< \brief (TWI0) Receive Counter Register */
#define REG_TWI0_TPR (*(RwReg*)0x400A8108U) /**< \brief (TWI0) Transmit Pointer Register */
#define REG_TWI0_TCR (*(RwReg*)0x400A810CU) /**< \brief (TWI0) Transmit Counter Register */
#define REG_TWI0_RNPR (*(RwReg*)0x400A8110U) /**< \brief (TWI0) Receive Next Pointer Register */
#define REG_TWI0_RNCR (*(RwReg*)0x400A8114U) /**< \brief (TWI0) Receive Next Counter Register */
#define REG_TWI0_TNPR (*(RwReg*)0x400A8118U) /**< \brief (TWI0) Transmit Next Pointer Register */
#define REG_TWI0_TNCR (*(RwReg*)0x400A811CU) /**< \brief (TWI0) Transmit Next Counter Register */
#define REG_TWI0_PTCR (*(WoReg*)0x400A8120U) /**< \brief (TWI0) Transfer Control Register */
#define REG_TWI0_PTSR (*(RoReg*)0x400A8124U) /**< \brief (TWI0) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_TWI0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_TWI1_INSTANCE_
#define _SAM4E_TWI1_INSTANCE_
/* ========== Register definition for TWI1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_TWI1_CR (0x400AC000U) /**< \brief (TWI1) Control Register */
#define REG_TWI1_MMR (0x400AC004U) /**< \brief (TWI1) Master Mode Register */
#define REG_TWI1_SMR (0x400AC008U) /**< \brief (TWI1) Slave Mode Register */
#define REG_TWI1_IADR (0x400AC00CU) /**< \brief (TWI1) Internal Address Register */
#define REG_TWI1_CWGR (0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */
#define REG_TWI1_SR (0x400AC020U) /**< \brief (TWI1) Status Register */
#define REG_TWI1_IER (0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */
#define REG_TWI1_IDR (0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */
#define REG_TWI1_IMR (0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */
#define REG_TWI1_RHR (0x400AC030U) /**< \brief (TWI1) Receive Holding Register */
#define REG_TWI1_THR (0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */
#define REG_TWI1_WPROT_MODE (0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */
#define REG_TWI1_WPROT_STATUS (0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */
#define REG_TWI1_RPR (0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */
#define REG_TWI1_RCR (0x400AC104U) /**< \brief (TWI1) Receive Counter Register */
#define REG_TWI1_TPR (0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */
#define REG_TWI1_TCR (0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */
#define REG_TWI1_RNPR (0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */
#define REG_TWI1_RNCR (0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */
#define REG_TWI1_TNPR (0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */
#define REG_TWI1_TNCR (0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */
#define REG_TWI1_PTCR (0x400AC120U) /**< \brief (TWI1) Transfer Control Register */
#define REG_TWI1_PTSR (0x400AC124U) /**< \brief (TWI1) Transfer Status Register */
#else
#define REG_TWI1_CR (*(WoReg*)0x400AC000U) /**< \brief (TWI1) Control Register */
#define REG_TWI1_MMR (*(RwReg*)0x400AC004U) /**< \brief (TWI1) Master Mode Register */
#define REG_TWI1_SMR (*(RwReg*)0x400AC008U) /**< \brief (TWI1) Slave Mode Register */
#define REG_TWI1_IADR (*(RwReg*)0x400AC00CU) /**< \brief (TWI1) Internal Address Register */
#define REG_TWI1_CWGR (*(RwReg*)0x400AC010U) /**< \brief (TWI1) Clock Waveform Generator Register */
#define REG_TWI1_SR (*(RoReg*)0x400AC020U) /**< \brief (TWI1) Status Register */
#define REG_TWI1_IER (*(WoReg*)0x400AC024U) /**< \brief (TWI1) Interrupt Enable Register */
#define REG_TWI1_IDR (*(WoReg*)0x400AC028U) /**< \brief (TWI1) Interrupt Disable Register */
#define REG_TWI1_IMR (*(RoReg*)0x400AC02CU) /**< \brief (TWI1) Interrupt Mask Register */
#define REG_TWI1_RHR (*(RoReg*)0x400AC030U) /**< \brief (TWI1) Receive Holding Register */
#define REG_TWI1_THR (*(WoReg*)0x400AC034U) /**< \brief (TWI1) Transmit Holding Register */
#define REG_TWI1_WPROT_MODE (*(RwReg*)0x400AC0E4U) /**< \brief (TWI1) Protection Mode Register */
#define REG_TWI1_WPROT_STATUS (*(RoReg*)0x400AC0E8U) /**< \brief (TWI1) Protection Status Register */
#define REG_TWI1_RPR (*(RwReg*)0x400AC100U) /**< \brief (TWI1) Receive Pointer Register */
#define REG_TWI1_RCR (*(RwReg*)0x400AC104U) /**< \brief (TWI1) Receive Counter Register */
#define REG_TWI1_TPR (*(RwReg*)0x400AC108U) /**< \brief (TWI1) Transmit Pointer Register */
#define REG_TWI1_TCR (*(RwReg*)0x400AC10CU) /**< \brief (TWI1) Transmit Counter Register */
#define REG_TWI1_RNPR (*(RwReg*)0x400AC110U) /**< \brief (TWI1) Receive Next Pointer Register */
#define REG_TWI1_RNCR (*(RwReg*)0x400AC114U) /**< \brief (TWI1) Receive Next Counter Register */
#define REG_TWI1_TNPR (*(RwReg*)0x400AC118U) /**< \brief (TWI1) Transmit Next Pointer Register */
#define REG_TWI1_TNCR (*(RwReg*)0x400AC11CU) /**< \brief (TWI1) Transmit Next Counter Register */
#define REG_TWI1_PTCR (*(WoReg*)0x400AC120U) /**< \brief (TWI1) Transfer Control Register */
#define REG_TWI1_PTSR (*(RoReg*)0x400AC124U) /**< \brief (TWI1) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_TWI1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_UART0_INSTANCE_
#define _SAM4E_UART0_INSTANCE_
/* ========== Register definition for UART0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART0_CR (0x400E0600U) /**< \brief (UART0) Control Register */
#define REG_UART0_MR (0x400E0604U) /**< \brief (UART0) Mode Register */
#define REG_UART0_IER (0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
#define REG_UART0_IDR (0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
#define REG_UART0_IMR (0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
#define REG_UART0_SR (0x400E0614U) /**< \brief (UART0) Status Register */
#define REG_UART0_RHR (0x400E0618U) /**< \brief (UART0) Receive Holding Register */
#define REG_UART0_THR (0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
#define REG_UART0_BRGR (0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
#define REG_UART0_RPR (0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
#define REG_UART0_RCR (0x400E0704U) /**< \brief (UART0) Receive Counter Register */
#define REG_UART0_TPR (0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
#define REG_UART0_TCR (0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
#define REG_UART0_RNPR (0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
#define REG_UART0_RNCR (0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
#define REG_UART0_TNPR (0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
#define REG_UART0_TNCR (0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
#define REG_UART0_PTCR (0x400E0720U) /**< \brief (UART0) Transfer Control Register */
#define REG_UART0_PTSR (0x400E0724U) /**< \brief (UART0) Transfer Status Register */
#else
#define REG_UART0_CR (*(WoReg*)0x400E0600U) /**< \brief (UART0) Control Register */
#define REG_UART0_MR (*(RwReg*)0x400E0604U) /**< \brief (UART0) Mode Register */
#define REG_UART0_IER (*(WoReg*)0x400E0608U) /**< \brief (UART0) Interrupt Enable Register */
#define REG_UART0_IDR (*(WoReg*)0x400E060CU) /**< \brief (UART0) Interrupt Disable Register */
#define REG_UART0_IMR (*(RoReg*)0x400E0610U) /**< \brief (UART0) Interrupt Mask Register */
#define REG_UART0_SR (*(RoReg*)0x400E0614U) /**< \brief (UART0) Status Register */
#define REG_UART0_RHR (*(RoReg*)0x400E0618U) /**< \brief (UART0) Receive Holding Register */
#define REG_UART0_THR (*(WoReg*)0x400E061CU) /**< \brief (UART0) Transmit Holding Register */
#define REG_UART0_BRGR (*(RwReg*)0x400E0620U) /**< \brief (UART0) Baud Rate Generator Register */
#define REG_UART0_RPR (*(RwReg*)0x400E0700U) /**< \brief (UART0) Receive Pointer Register */
#define REG_UART0_RCR (*(RwReg*)0x400E0704U) /**< \brief (UART0) Receive Counter Register */
#define REG_UART0_TPR (*(RwReg*)0x400E0708U) /**< \brief (UART0) Transmit Pointer Register */
#define REG_UART0_TCR (*(RwReg*)0x400E070CU) /**< \brief (UART0) Transmit Counter Register */
#define REG_UART0_RNPR (*(RwReg*)0x400E0710U) /**< \brief (UART0) Receive Next Pointer Register */
#define REG_UART0_RNCR (*(RwReg*)0x400E0714U) /**< \brief (UART0) Receive Next Counter Register */
#define REG_UART0_TNPR (*(RwReg*)0x400E0718U) /**< \brief (UART0) Transmit Next Pointer Register */
#define REG_UART0_TNCR (*(RwReg*)0x400E071CU) /**< \brief (UART0) Transmit Next Counter Register */
#define REG_UART0_PTCR (*(WoReg*)0x400E0720U) /**< \brief (UART0) Transfer Control Register */
#define REG_UART0_PTSR (*(RoReg*)0x400E0724U) /**< \brief (UART0) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_UART0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_UART1_INSTANCE_
#define _SAM4E_UART1_INSTANCE_
/* ========== Register definition for UART1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UART1_CR (0x40060600U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR (0x40060604U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER (0x40060608U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR (0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR (0x40060610U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR (0x40060614U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR (0x40060618U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR (0x4006061CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR (0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */
#define REG_UART1_RPR (0x40060700U) /**< \brief (UART1) Receive Pointer Register */
#define REG_UART1_RCR (0x40060704U) /**< \brief (UART1) Receive Counter Register */
#define REG_UART1_TPR (0x40060708U) /**< \brief (UART1) Transmit Pointer Register */
#define REG_UART1_TCR (0x4006070CU) /**< \brief (UART1) Transmit Counter Register */
#define REG_UART1_RNPR (0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */
#define REG_UART1_RNCR (0x40060714U) /**< \brief (UART1) Receive Next Counter Register */
#define REG_UART1_TNPR (0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */
#define REG_UART1_TNCR (0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */
#define REG_UART1_PTCR (0x40060720U) /**< \brief (UART1) Transfer Control Register */
#define REG_UART1_PTSR (0x40060724U) /**< \brief (UART1) Transfer Status Register */
#else
#define REG_UART1_CR (*(WoReg*)0x40060600U) /**< \brief (UART1) Control Register */
#define REG_UART1_MR (*(RwReg*)0x40060604U) /**< \brief (UART1) Mode Register */
#define REG_UART1_IER (*(WoReg*)0x40060608U) /**< \brief (UART1) Interrupt Enable Register */
#define REG_UART1_IDR (*(WoReg*)0x4006060CU) /**< \brief (UART1) Interrupt Disable Register */
#define REG_UART1_IMR (*(RoReg*)0x40060610U) /**< \brief (UART1) Interrupt Mask Register */
#define REG_UART1_SR (*(RoReg*)0x40060614U) /**< \brief (UART1) Status Register */
#define REG_UART1_RHR (*(RoReg*)0x40060618U) /**< \brief (UART1) Receive Holding Register */
#define REG_UART1_THR (*(WoReg*)0x4006061CU) /**< \brief (UART1) Transmit Holding Register */
#define REG_UART1_BRGR (*(RwReg*)0x40060620U) /**< \brief (UART1) Baud Rate Generator Register */
#define REG_UART1_RPR (*(RwReg*)0x40060700U) /**< \brief (UART1) Receive Pointer Register */
#define REG_UART1_RCR (*(RwReg*)0x40060704U) /**< \brief (UART1) Receive Counter Register */
#define REG_UART1_TPR (*(RwReg*)0x40060708U) /**< \brief (UART1) Transmit Pointer Register */
#define REG_UART1_TCR (*(RwReg*)0x4006070CU) /**< \brief (UART1) Transmit Counter Register */
#define REG_UART1_RNPR (*(RwReg*)0x40060710U) /**< \brief (UART1) Receive Next Pointer Register */
#define REG_UART1_RNCR (*(RwReg*)0x40060714U) /**< \brief (UART1) Receive Next Counter Register */
#define REG_UART1_TNPR (*(RwReg*)0x40060718U) /**< \brief (UART1) Transmit Next Pointer Register */
#define REG_UART1_TNCR (*(RwReg*)0x4006071CU) /**< \brief (UART1) Transmit Next Counter Register */
#define REG_UART1_PTCR (*(WoReg*)0x40060720U) /**< \brief (UART1) Transfer Control Register */
#define REG_UART1_PTSR (*(RoReg*)0x40060724U) /**< \brief (UART1) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_UART1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_UDP_INSTANCE_
#define _SAM4E_UDP_INSTANCE_
/* ========== Register definition for UDP peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_UDP_FRM_NUM (0x40084000U) /**< \brief (UDP) Frame Number Register */
#define REG_UDP_GLB_STAT (0x40084004U) /**< \brief (UDP) Global State Register */
#define REG_UDP_FADDR (0x40084008U) /**< \brief (UDP) Function Address Register */
#define REG_UDP_IER (0x40084010U) /**< \brief (UDP) Interrupt Enable Register */
#define REG_UDP_IDR (0x40084014U) /**< \brief (UDP) Interrupt Disable Register */
#define REG_UDP_IMR (0x40084018U) /**< \brief (UDP) Interrupt Mask Register */
#define REG_UDP_ISR (0x4008401CU) /**< \brief (UDP) Interrupt Status Register */
#define REG_UDP_ICR (0x40084020U) /**< \brief (UDP) Interrupt Clear Register */
#define REG_UDP_RST_EP (0x40084028U) /**< \brief (UDP) Reset Endpoint Register */
#define REG_UDP_CSR (0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */
#define REG_UDP_FDR (0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */
#define REG_UDP_TXVC (0x40084074U) /**< \brief (UDP) Transceiver Control Register */
#else
#define REG_UDP_FRM_NUM (*(RoReg*)0x40084000U) /**< \brief (UDP) Frame Number Register */
#define REG_UDP_GLB_STAT (*(RwReg*)0x40084004U) /**< \brief (UDP) Global State Register */
#define REG_UDP_FADDR (*(RwReg*)0x40084008U) /**< \brief (UDP) Function Address Register */
#define REG_UDP_IER (*(WoReg*)0x40084010U) /**< \brief (UDP) Interrupt Enable Register */
#define REG_UDP_IDR (*(WoReg*)0x40084014U) /**< \brief (UDP) Interrupt Disable Register */
#define REG_UDP_IMR (*(RoReg*)0x40084018U) /**< \brief (UDP) Interrupt Mask Register */
#define REG_UDP_ISR (*(RoReg*)0x4008401CU) /**< \brief (UDP) Interrupt Status Register */
#define REG_UDP_ICR (*(WoReg*)0x40084020U) /**< \brief (UDP) Interrupt Clear Register */
#define REG_UDP_RST_EP (*(RwReg*)0x40084028U) /**< \brief (UDP) Reset Endpoint Register */
#define REG_UDP_CSR (*(RwReg*)0x40084030U) /**< \brief (UDP) Endpoint Control and Status Register */
#define REG_UDP_FDR (*(RwReg*)0x40084050U) /**< \brief (UDP) Endpoint FIFO Data Register */
#define REG_UDP_TXVC (*(RwReg*)0x40084074U) /**< \brief (UDP) Transceiver Control Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_UDP_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_USART0_INSTANCE_
#define _SAM4E_USART0_INSTANCE_
/* ========== Register definition for USART0 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USART0_CR (0x400A0000U) /**< \brief (USART0) Control Register */
#define REG_USART0_MR (0x400A0004U) /**< \brief (USART0) Mode Register */
#define REG_USART0_IER (0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */
#define REG_USART0_IDR (0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */
#define REG_USART0_IMR (0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */
#define REG_USART0_CSR (0x400A0014U) /**< \brief (USART0) Channel Status Register */
#define REG_USART0_RHR (0x400A0018U) /**< \brief (USART0) Receiver Holding Register */
#define REG_USART0_THR (0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */
#define REG_USART0_BRGR (0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */
#define REG_USART0_RTOR (0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */
#define REG_USART0_TTGR (0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */
#define REG_USART0_FIDI (0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */
#define REG_USART0_NER (0x400A0044U) /**< \brief (USART0) Number of Errors Register */
#define REG_USART0_IF (0x400A004CU) /**< \brief (USART0) IrDA Filter Register */
#define REG_USART0_MAN (0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
#define REG_USART0_WPMR (0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */
#define REG_USART0_WPSR (0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */
#define REG_USART0_RPR (0x400A0100U) /**< \brief (USART0) Receive Pointer Register */
#define REG_USART0_RCR (0x400A0104U) /**< \brief (USART0) Receive Counter Register */
#define REG_USART0_TPR (0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */
#define REG_USART0_TCR (0x400A010CU) /**< \brief (USART0) Transmit Counter Register */
#define REG_USART0_RNPR (0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */
#define REG_USART0_RNCR (0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */
#define REG_USART0_TNPR (0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */
#define REG_USART0_TNCR (0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */
#define REG_USART0_PTCR (0x400A0120U) /**< \brief (USART0) Transfer Control Register */
#define REG_USART0_PTSR (0x400A0124U) /**< \brief (USART0) Transfer Status Register */
#else
#define REG_USART0_CR (*(WoReg*)0x400A0000U) /**< \brief (USART0) Control Register */
#define REG_USART0_MR (*(RwReg*)0x400A0004U) /**< \brief (USART0) Mode Register */
#define REG_USART0_IER (*(WoReg*)0x400A0008U) /**< \brief (USART0) Interrupt Enable Register */
#define REG_USART0_IDR (*(WoReg*)0x400A000CU) /**< \brief (USART0) Interrupt Disable Register */
#define REG_USART0_IMR (*(RoReg*)0x400A0010U) /**< \brief (USART0) Interrupt Mask Register */
#define REG_USART0_CSR (*(RoReg*)0x400A0014U) /**< \brief (USART0) Channel Status Register */
#define REG_USART0_RHR (*(RoReg*)0x400A0018U) /**< \brief (USART0) Receiver Holding Register */
#define REG_USART0_THR (*(WoReg*)0x400A001CU) /**< \brief (USART0) Transmitter Holding Register */
#define REG_USART0_BRGR (*(RwReg*)0x400A0020U) /**< \brief (USART0) Baud Rate Generator Register */
#define REG_USART0_RTOR (*(RwReg*)0x400A0024U) /**< \brief (USART0) Receiver Time-out Register */
#define REG_USART0_TTGR (*(RwReg*)0x400A0028U) /**< \brief (USART0) Transmitter Timeguard Register */
#define REG_USART0_FIDI (*(RwReg*)0x400A0040U) /**< \brief (USART0) FI DI Ratio Register */
#define REG_USART0_NER (*(RoReg*)0x400A0044U) /**< \brief (USART0) Number of Errors Register */
#define REG_USART0_IF (*(RwReg*)0x400A004CU) /**< \brief (USART0) IrDA Filter Register */
#define REG_USART0_MAN (*(RwReg*)0x400A0050U) /**< \brief (USART0) Manchester Encoder Decoder Register */
#define REG_USART0_WPMR (*(RwReg*)0x400A00E4U) /**< \brief (USART0) Write Protect Mode Register */
#define REG_USART0_WPSR (*(RoReg*)0x400A00E8U) /**< \brief (USART0) Write Protect Status Register */
#define REG_USART0_RPR (*(RwReg*)0x400A0100U) /**< \brief (USART0) Receive Pointer Register */
#define REG_USART0_RCR (*(RwReg*)0x400A0104U) /**< \brief (USART0) Receive Counter Register */
#define REG_USART0_TPR (*(RwReg*)0x400A0108U) /**< \brief (USART0) Transmit Pointer Register */
#define REG_USART0_TCR (*(RwReg*)0x400A010CU) /**< \brief (USART0) Transmit Counter Register */
#define REG_USART0_RNPR (*(RwReg*)0x400A0110U) /**< \brief (USART0) Receive Next Pointer Register */
#define REG_USART0_RNCR (*(RwReg*)0x400A0114U) /**< \brief (USART0) Receive Next Counter Register */
#define REG_USART0_TNPR (*(RwReg*)0x400A0118U) /**< \brief (USART0) Transmit Next Pointer Register */
#define REG_USART0_TNCR (*(RwReg*)0x400A011CU) /**< \brief (USART0) Transmit Next Counter Register */
#define REG_USART0_PTCR (*(WoReg*)0x400A0120U) /**< \brief (USART0) Transfer Control Register */
#define REG_USART0_PTSR (*(RoReg*)0x400A0124U) /**< \brief (USART0) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_USART0_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_USART1_INSTANCE_
#define _SAM4E_USART1_INSTANCE_
/* ========== Register definition for USART1 peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_USART1_CR (0x400A4000U) /**< \brief (USART1) Control Register */
#define REG_USART1_MR (0x400A4004U) /**< \brief (USART1) Mode Register */
#define REG_USART1_IER (0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */
#define REG_USART1_IDR (0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */
#define REG_USART1_IMR (0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */
#define REG_USART1_CSR (0x400A4014U) /**< \brief (USART1) Channel Status Register */
#define REG_USART1_RHR (0x400A4018U) /**< \brief (USART1) Receiver Holding Register */
#define REG_USART1_THR (0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */
#define REG_USART1_BRGR (0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */
#define REG_USART1_RTOR (0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */
#define REG_USART1_TTGR (0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */
#define REG_USART1_FIDI (0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */
#define REG_USART1_NER (0x400A4044U) /**< \brief (USART1) Number of Errors Register */
#define REG_USART1_IF (0x400A404CU) /**< \brief (USART1) IrDA Filter Register */
#define REG_USART1_MAN (0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
#define REG_USART1_WPMR (0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */
#define REG_USART1_WPSR (0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */
#define REG_USART1_RPR (0x400A4100U) /**< \brief (USART1) Receive Pointer Register */
#define REG_USART1_RCR (0x400A4104U) /**< \brief (USART1) Receive Counter Register */
#define REG_USART1_TPR (0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */
#define REG_USART1_TCR (0x400A410CU) /**< \brief (USART1) Transmit Counter Register */
#define REG_USART1_RNPR (0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */
#define REG_USART1_RNCR (0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */
#define REG_USART1_TNPR (0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */
#define REG_USART1_TNCR (0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */
#define REG_USART1_PTCR (0x400A4120U) /**< \brief (USART1) Transfer Control Register */
#define REG_USART1_PTSR (0x400A4124U) /**< \brief (USART1) Transfer Status Register */
#else
#define REG_USART1_CR (*(WoReg*)0x400A4000U) /**< \brief (USART1) Control Register */
#define REG_USART1_MR (*(RwReg*)0x400A4004U) /**< \brief (USART1) Mode Register */
#define REG_USART1_IER (*(WoReg*)0x400A4008U) /**< \brief (USART1) Interrupt Enable Register */
#define REG_USART1_IDR (*(WoReg*)0x400A400CU) /**< \brief (USART1) Interrupt Disable Register */
#define REG_USART1_IMR (*(RoReg*)0x400A4010U) /**< \brief (USART1) Interrupt Mask Register */
#define REG_USART1_CSR (*(RoReg*)0x400A4014U) /**< \brief (USART1) Channel Status Register */
#define REG_USART1_RHR (*(RoReg*)0x400A4018U) /**< \brief (USART1) Receiver Holding Register */
#define REG_USART1_THR (*(WoReg*)0x400A401CU) /**< \brief (USART1) Transmitter Holding Register */
#define REG_USART1_BRGR (*(RwReg*)0x400A4020U) /**< \brief (USART1) Baud Rate Generator Register */
#define REG_USART1_RTOR (*(RwReg*)0x400A4024U) /**< \brief (USART1) Receiver Time-out Register */
#define REG_USART1_TTGR (*(RwReg*)0x400A4028U) /**< \brief (USART1) Transmitter Timeguard Register */
#define REG_USART1_FIDI (*(RwReg*)0x400A4040U) /**< \brief (USART1) FI DI Ratio Register */
#define REG_USART1_NER (*(RoReg*)0x400A4044U) /**< \brief (USART1) Number of Errors Register */
#define REG_USART1_IF (*(RwReg*)0x400A404CU) /**< \brief (USART1) IrDA Filter Register */
#define REG_USART1_MAN (*(RwReg*)0x400A4050U) /**< \brief (USART1) Manchester Encoder Decoder Register */
#define REG_USART1_WPMR (*(RwReg*)0x400A40E4U) /**< \brief (USART1) Write Protect Mode Register */
#define REG_USART1_WPSR (*(RoReg*)0x400A40E8U) /**< \brief (USART1) Write Protect Status Register */
#define REG_USART1_RPR (*(RwReg*)0x400A4100U) /**< \brief (USART1) Receive Pointer Register */
#define REG_USART1_RCR (*(RwReg*)0x400A4104U) /**< \brief (USART1) Receive Counter Register */
#define REG_USART1_TPR (*(RwReg*)0x400A4108U) /**< \brief (USART1) Transmit Pointer Register */
#define REG_USART1_TCR (*(RwReg*)0x400A410CU) /**< \brief (USART1) Transmit Counter Register */
#define REG_USART1_RNPR (*(RwReg*)0x400A4110U) /**< \brief (USART1) Receive Next Pointer Register */
#define REG_USART1_RNCR (*(RwReg*)0x400A4114U) /**< \brief (USART1) Receive Next Counter Register */
#define REG_USART1_TNPR (*(RwReg*)0x400A4118U) /**< \brief (USART1) Transmit Next Pointer Register */
#define REG_USART1_TNCR (*(RwReg*)0x400A411CU) /**< \brief (USART1) Transmit Next Counter Register */
#define REG_USART1_PTCR (*(WoReg*)0x400A4120U) /**< \brief (USART1) Transfer Control Register */
#define REG_USART1_PTSR (*(RoReg*)0x400A4124U) /**< \brief (USART1) Transfer Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_USART1_INSTANCE_ */

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/* ---------------------------------------------------------------------------- */
/* Atmel Microcontroller Software Support */
/* SAM Software Package License */
/* ---------------------------------------------------------------------------- */
/* Copyright (c) %copyright_year%, Atmel Corporation */
/* */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or without */
/* modification, are permitted provided that the following condition is met: */
/* */
/* - Redistributions of source code must retain the above copyright notice, */
/* this list of conditions and the disclaimer below. */
/* */
/* Atmel's name may not be used to endorse or promote products derived from */
/* this software without specific prior written permission. */
/* */
/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
/* ---------------------------------------------------------------------------- */
#ifndef _SAM4E_WDT_INSTANCE_
#define _SAM4E_WDT_INSTANCE_
/* ========== Register definition for WDT peripheral ========== */
#if (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
#define REG_WDT_CR (0x400E1850U) /**< \brief (WDT) Control Register */
#define REG_WDT_MR (0x400E1854U) /**< \brief (WDT) Mode Register */
#define REG_WDT_SR (0x400E1858U) /**< \brief (WDT) Status Register */
#else
#define REG_WDT_CR (*(WoReg*)0x400E1850U) /**< \brief (WDT) Control Register */
#define REG_WDT_MR (*(RwReg*)0x400E1854U) /**< \brief (WDT) Mode Register */
#define REG_WDT_SR (*(RoReg*)0x400E1858U) /**< \brief (WDT) Status Register */
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#endif /* _SAM4E_WDT_INSTANCE_ */