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lib: Update lib/rp2040 to v2.0.0 SDK release

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2024-10-24 19:41:55 -04:00
parent 9f328cab95
commit c75eb53c0c
139 changed files with 13359 additions and 8309 deletions
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96
lib/pico-sdk/rp2040/hardware/structs/adc.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ADC_H
#define _HARDWARE_STRUCTS_ADC_H
/**
* \file rp2040/adc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/adc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_adc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/adc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ADC_CS_OFFSET) // ADC_CS
// ADC Control and Status
// 0x001f0000 [20:16] RROBIN (0x00) Round-robin sampling
// 0x00007000 [14:12] AINSEL (0x0) Select analog mux input
// 0x00000400 [10] ERR_STICKY (0) Some past ADC conversion encountered an error
// 0x00000200 [9] ERR (0) The most recent ADC conversion encountered an error;...
// 0x00000100 [8] READY (0) 1 if the ADC is ready to start a new conversion
// 0x00000008 [3] START_MANY (0) Continuously perform conversions whilst this bit is 1
// 0x00000004 [2] START_ONCE (0) Start a single conversion
// 0x00000002 [1] TS_EN (0) Power on temperature sensor
// 0x00000001 [0] EN (0) Power on ADC and enable its clock
io_rw_32 cs;
_REG_(ADC_RESULT_OFFSET) // ADC_RESULT
// Result of most recent ADC conversion
// 0x00000fff [11:0] RESULT (0x000)
io_ro_32 result;
_REG_(ADC_FCS_OFFSET) // ADC_FCS
// FIFO control and status
// 0x0f000000 [27:24] THRESH (0x0) DREQ/IRQ asserted when level >= threshold
// 0x000f0000 [19:16] LEVEL (0x0) The number of conversion results currently waiting in the FIFO
// 0x00000800 [11] OVER (0) 1 if the FIFO has been overflowed
// 0x00000400 [10] UNDER (0) 1 if the FIFO has been underflowed
// 0x00000200 [9] FULL (0)
// 0x00000100 [8] EMPTY (0)
// 0x00000008 [3] DREQ_EN (0) If 1: assert DMA requests when FIFO contains data
// 0x00000004 [2] ERR (0) If 1: conversion error bit appears in the FIFO alongside...
// 0x00000002 [1] SHIFT (0) If 1: FIFO results are right-shifted to be one byte in size
// 0x00000001 [0] EN (0) If 1: write result to the FIFO after each conversion
io_rw_32 fcs;
_REG_(ADC_FIFO_OFFSET) // ADC_FIFO
// Conversion result FIFO
// 0x00008000 [15] ERR (-) 1 if this particular sample experienced a conversion error
// 0x00000fff [11:0] VAL (-)
io_ro_32 fifo;
_REG_(ADC_DIV_OFFSET) // ADC_DIV
// Clock divider
// 0x00ffff00 [23:8] INT (0x0000) Integer part of clock divisor
// 0x000000ff [7:0] FRAC (0x00) Fractional part of clock divisor
io_rw_32 div;
_REG_(ADC_INTR_OFFSET) // ADC_INTR
// Raw Interrupts
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 intr;
_REG_(ADC_INTE_OFFSET) // ADC_INTE
// Interrupt Enable
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 inte;
_REG_(ADC_INTF_OFFSET) // ADC_INTF
// Interrupt Force
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_rw_32 intf;
_REG_(ADC_INTS_OFFSET) // ADC_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] FIFO (0) Triggered when the sample FIFO reaches a certain level
io_ro_32 ints;
} adc_hw_t;
#define adc_hw ((adc_hw_t *)ADC_BASE)
static_assert(sizeof (adc_hw_t) == 0x0024, "");
#endif // _HARDWARE_STRUCTS_ADC_H

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lib/pico-sdk/rp2040/hardware/structs/bus_ctrl.h Normal file
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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/busctrl.h"
#define bus_ctrl_hw busctrl_hw

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lib/pico-sdk/rp2040/hardware/structs/busctrl.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_BUSCTRL_H
#define _HARDWARE_STRUCTS_BUSCTRL_H
/**
* \file rp2040/busctrl.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/busctrl.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_busctrl
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/busctrl.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Bus fabric performance counters on RP2040 (used as typedef \ref bus_ctrl_perf_counter_t)
* \ingroup hardware_busctrl
*/
typedef enum bus_ctrl_perf_counter_rp2040 {
arbiter_rom_perf_event_access = 19,
arbiter_rom_perf_event_access_contested = 18,
arbiter_xip_main_perf_event_access = 17,
arbiter_xip_main_perf_event_access_contested = 16,
arbiter_sram0_perf_event_access = 15,
arbiter_sram0_perf_event_access_contested = 14,
arbiter_sram1_perf_event_access = 13,
arbiter_sram1_perf_event_access_contested = 12,
arbiter_sram2_perf_event_access = 11,
arbiter_sram2_perf_event_access_contested = 10,
arbiter_sram3_perf_event_access = 9,
arbiter_sram3_perf_event_access_contested = 8,
arbiter_sram4_perf_event_access = 7,
arbiter_sram4_perf_event_access_contested = 6,
arbiter_sram5_perf_event_access = 5,
arbiter_sram5_perf_event_access_contested = 4,
arbiter_fastperi_perf_event_access = 3,
arbiter_fastperi_perf_event_access_contested = 2,
arbiter_apb_perf_event_access = 1,
arbiter_apb_perf_event_access_contested = 0
} bus_ctrl_perf_counter_t;
typedef struct {
_REG_(BUSCTRL_PERFCTR0_OFFSET) // BUSCTRL_PERFCTR0
// Bus fabric performance counter 0
// 0x00ffffff [23:0] PERFCTR0 (0x000000) Busfabric saturating performance counter 0 +
io_rw_32 value;
_REG_(BUSCTRL_PERFSEL0_OFFSET) // BUSCTRL_PERFSEL0
// Bus fabric performance event select for PERFCTR0
// 0x0000001f [4:0] PERFSEL0 (0x1f) Select an event for PERFCTR0
io_rw_32 sel;
} bus_ctrl_perf_hw_t;
typedef struct {
_REG_(BUSCTRL_BUS_PRIORITY_OFFSET) // BUSCTRL_BUS_PRIORITY
// Set the priority of each master for bus arbitration
// 0x00001000 [12] DMA_W (0) 0 - low priority, 1 - high priority
// 0x00000100 [8] DMA_R (0) 0 - low priority, 1 - high priority
// 0x00000010 [4] PROC1 (0) 0 - low priority, 1 - high priority
// 0x00000001 [0] PROC0 (0) 0 - low priority, 1 - high priority
io_rw_32 priority;
_REG_(BUSCTRL_BUS_PRIORITY_ACK_OFFSET) // BUSCTRL_BUS_PRIORITY_ACK
// Bus priority acknowledge
// 0x00000001 [0] BUS_PRIORITY_ACK (0) Goes to 1 once all arbiters have registered the new...
io_ro_32 priority_ack;
bus_ctrl_perf_hw_t counter[4];
} busctrl_hw_t;
#define busctrl_hw ((busctrl_hw_t *)BUSCTRL_BASE)
static_assert(sizeof (busctrl_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_BUSCTRL_H

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lib/pico-sdk/rp2040/hardware/structs/clocks.h Normal file
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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_CLOCKS_H
#define _HARDWARE_STRUCTS_CLOCKS_H
/**
* \file rp2040/clocks.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/clocks.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_clocks
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/clocks.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Clock numbers on RP2040 (used as typedef \ref clock_num_t)
* \ingroup hardware_clocks
*/
/// \tag::clkenum[]
typedef enum clock_num_rp2040 {
clk_gpout0 = 0, ///< Select CLK_GPOUT0 as clock source
clk_gpout1 = 1, ///< Select CLK_GPOUT1 as clock source
clk_gpout2 = 2, ///< Select CLK_GPOUT2 as clock source
clk_gpout3 = 3, ///< Select CLK_GPOUT3 as clock source
clk_ref = 4, ///< Select CLK_REF as clock source
clk_sys = 5, ///< Select CLK_SYS as clock source
clk_peri = 6, ///< Select CLK_PERI as clock source
clk_usb = 7, ///< Select CLK_USB as clock source
clk_adc = 8, ///< Select CLK_ADC as clock source
clk_rtc = 9, ///< Select CLK_RTC as clock source
CLK_COUNT
} clock_num_t;
/// \end::clkenum[]
/** \brief Clock destination numbers on RP2040 (used as typedef \ref clock_dest_num_t)
* \ingroup hardware_clocks
*/
typedef enum clock_dest_num_rp2040 {
CLK_DEST_SYS_CLOCKS = 0, ///< Select SYS_CLOCKS as clock destination
CLK_DEST_ADC_ADC = 1, ///< Select ADC_ADC as clock destination
CLK_DEST_SYS_ADC = 2, ///< Select SYS_ADC as clock destination
CLK_DEST_SYS_BUSCTRL = 3, ///< Select SYS_BUSCTRL as clock destination
CLK_DEST_SYS_BUSFABRIC = 4, ///< Select SYS_BUSFABRIC as clock destination
CLK_DEST_SYS_DMA = 5, ///< Select SYS_DMA as clock destination
CLK_DEST_SYS_I2C0 = 6, ///< Select SYS_I2C0 as clock destination
CLK_DEST_SYS_I2C1 = 7, ///< Select SYS_I2C1 as clock destination
CLK_DEST_SYS_IO = 8, ///< Select SYS_IO as clock destination
CLK_DEST_SYS_JTAG = 9, ///< Select SYS_JTAG as clock destination
CLK_DEST_SYS_VREG_AND_CHIP_RESET = 10, ///< Select SYS_VREG_AND_CHIP_RESET as clock destination
CLK_DEST_SYS_PADS = 11, ///< Select SYS_PADS as clock destination
CLK_DEST_SYS_PIO0 = 12, ///< Select SYS_PIO0 as clock destination
CLK_DEST_SYS_PIO1 = 13, ///< Select SYS_PIO1 as clock destination
CLK_DEST_SYS_PLL_SYS = 14, ///< Select SYS_PLL_SYS as clock destination
CLK_DEST_SYS_PLL_USB = 15, ///< Select SYS_PLL_USB as clock destination
CLK_DEST_SYS_PSM = 16, ///< Select SYS_PSM as clock destination
CLK_DEST_SYS_PWM = 17, ///< Select SYS_PWM as clock destination
CLK_DEST_SYS_RESETS = 18, ///< Select SYS_RESETS as clock destination
CLK_DEST_SYS_ROM = 19, ///< Select SYS_ROM as clock destination
CLK_DEST_SYS_ROSC = 20, ///< Select SYS_ROSC as clock destination
CLK_DEST_RTC_RTC = 21, ///< Select RTC_RTC as clock destination
CLK_DEST_SYS_RTC = 22, ///< Select SYS_RTC as clock destination
CLK_DEST_SYS_SIO = 23, ///< Select SYS_SIO as clock destination
CLK_DEST_PERI_SPI0 = 24, ///< Select PERI_SPI0 as clock destination
CLK_DEST_SYS_SPI0 = 25, ///< Select SYS_SPI0 as clock destination
CLK_DEST_PERI_SPI1 = 26, ///< Select PERI_SPI1 as clock destination
CLK_DEST_SYS_SPI1 = 27, ///< Select SYS_SPI1 as clock destination
CLK_DEST_SYS_SRAM0 = 28, ///< Select SYS_SRAM0 as clock destination
CLK_DEST_SYS_SRAM1 = 29, ///< Select SYS_SRAM1 as clock destination
CLK_DEST_SYS_SRAM2 = 30, ///< Select SYS_SRAM2 as clock destination
CLK_DEST_SYS_SRAM3 = 31, ///< Select SYS_SRAM3 as clock destination
CLK_DEST_SYS_SRAM4 = 32, ///< Select SYS_SRAM4 as clock destination
CLK_DEST_SYS_SRAM5 = 33, ///< Select SYS_SRAM5 as clock destination
CLK_DEST_SYS_SYSCFG = 34, ///< Select SYS_SYSCFG as clock destination
CLK_DEST_SYS_SYSINFO = 35, ///< Select SYS_SYSINFO as clock destination
CLK_DEST_SYS_TBMAN = 36, ///< Select SYS_TBMAN as clock destination
CLK_DEST_SYS_TIMER = 37, ///< Select SYS_TIMER as clock destination
CLK_DEST_PERI_UART0 = 38, ///< Select PERI_UART0 as clock destination
CLK_DEST_SYS_UART0 = 39, ///< Select SYS_UART0 as clock destination
CLK_DEST_PERI_UART1 = 40, ///< Select PERI_UART1 as clock destination
CLK_DEST_SYS_UART1 = 41, ///< Select SYS_UART1 as clock destination
CLK_DEST_SYS_USBCTRL = 42, ///< Select SYS_USBCTRL as clock destination
CLK_DEST_USB_USBCTRL = 43, ///< Select USB_USBCTRL as clock destination
CLK_DEST_SYS_WATCHDOG = 44, ///< Select SYS_WATCHDOG as clock destination
CLK_DEST_SYS_XIP = 45, ///< Select SYS_XIP as clock destination
CLK_DEST_SYS_XOSC = 46, ///< Select SYS_XOSC as clock destination
NUM_CLOCK_DESTINATIONS
} clock_dest_num_t;
/// \tag::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_GPOUT0_CTRL_OFFSET) // CLOCKS_CLK_GPOUT0_CTRL
// Clock control, can be changed on-the-fly (except for auxsrc)
// 0x00100000 [20] NUDGE (0) An edge on this signal shifts the phase of the output by...
// 0x00030000 [17:16] PHASE (0x0) This delays the enable signal by up to 3 cycles of the...
// 0x00001000 [12] DC50 (0) Enables duty cycle correction for odd divisors
// 0x00000800 [11] ENABLE (0) Starts and stops the clock generator cleanly
// 0x00000400 [10] KILL (0) Asynchronously kills the clock generator
// 0x000001e0 [8:5] AUXSRC (0x0) Selects the auxiliary clock source, will glitch when switching
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_GPOUT0_DIV_OFFSET) // CLOCKS_CLK_GPOUT0_DIV
// Clock divisor, can be changed on-the-fly
// 0xffffff00 [31:8] INT (0x000001) Integer component of the divisor, 0 -> divide by 2^16
// 0x000000ff [7:0] FRAC (0x00) Fractional component of the divisor
io_rw_32 div;
_REG_(CLOCKS_CLK_GPOUT0_SELECTED_OFFSET) // CLOCKS_CLK_GPOUT0_SELECTED
// Indicates which SRC is currently selected by the glitchless mux (one-hot)
// 0xffffffff [31:0] CLK_GPOUT0_SELECTED (0x00000001) This slice does not have a glitchless mux (only the...
io_ro_32 selected;
} clock_hw_t;
/// \end::clock_hw[]
typedef struct {
_REG_(CLOCKS_CLK_SYS_RESUS_CTRL_OFFSET) // CLOCKS_CLK_SYS_RESUS_CTRL
// 0x00010000 [16] CLEAR (0) For clearing the resus after the fault that triggered it...
// 0x00001000 [12] FRCE (0) Force a resus, for test purposes only
// 0x00000100 [8] ENABLE (0) Enable resus
// 0x000000ff [7:0] TIMEOUT (0xff) This is expressed as a number of clk_ref cycles +
io_rw_32 ctrl;
_REG_(CLOCKS_CLK_SYS_RESUS_STATUS_OFFSET) // CLOCKS_CLK_SYS_RESUS_STATUS
// 0x00000001 [0] RESUSSED (0) Clock has been resuscitated, correct the error then send...
io_ro_32 status;
} clock_resus_hw_t;
typedef struct {
_REG_(CLOCKS_FC0_REF_KHZ_OFFSET) // CLOCKS_FC0_REF_KHZ
// Reference clock frequency in kHz
// 0x000fffff [19:0] FC0_REF_KHZ (0x00000)
io_rw_32 ref_khz;
_REG_(CLOCKS_FC0_MIN_KHZ_OFFSET) // CLOCKS_FC0_MIN_KHZ
// Minimum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MIN_KHZ (0x0000000)
io_rw_32 min_khz;
_REG_(CLOCKS_FC0_MAX_KHZ_OFFSET) // CLOCKS_FC0_MAX_KHZ
// Maximum pass frequency in kHz
// 0x01ffffff [24:0] FC0_MAX_KHZ (0x1ffffff)
io_rw_32 max_khz;
_REG_(CLOCKS_FC0_DELAY_OFFSET) // CLOCKS_FC0_DELAY
// Delays the start of frequency counting to allow the mux to settle +
// 0x00000007 [2:0] FC0_DELAY (0x1)
io_rw_32 delay;
_REG_(CLOCKS_FC0_INTERVAL_OFFSET) // CLOCKS_FC0_INTERVAL
// The test interval is 0
// 0x0000000f [3:0] FC0_INTERVAL (0x8)
io_rw_32 interval;
_REG_(CLOCKS_FC0_SRC_OFFSET) // CLOCKS_FC0_SRC
// Clock sent to frequency counter, set to 0 when not required +
// 0x000000ff [7:0] FC0_SRC (0x00)
io_rw_32 src;
_REG_(CLOCKS_FC0_STATUS_OFFSET) // CLOCKS_FC0_STATUS
// Frequency counter status
// 0x10000000 [28] DIED (0) Test clock stopped during test
// 0x01000000 [24] FAST (0) Test clock faster than expected, only valid when status_done=1
// 0x00100000 [20] SLOW (0) Test clock slower than expected, only valid when status_done=1
// 0x00010000 [16] FAIL (0) Test failed
// 0x00001000 [12] WAITING (0) Waiting for test clock to start
// 0x00000100 [8] RUNNING (0) Test running
// 0x00000010 [4] DONE (0) Test complete
// 0x00000001 [0] PASS (0) Test passed
io_ro_32 status;
_REG_(CLOCKS_FC0_RESULT_OFFSET) // CLOCKS_FC0_RESULT
// Result of frequency measurement, only valid when status_done=1
// 0x3fffffe0 [29:5] KHZ (0x0000000)
// 0x0000001f [4:0] FRAC (0x00)
io_ro_32 result;
} fc_hw_t;
typedef struct {
clock_hw_t clk[10];
clock_resus_hw_t resus;
fc_hw_t fc0;
union {
struct {
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIOB (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_POWER (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC0 (1)
// 0x00000002 [1] CLK_ADC_ADC0 (1)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
io_rw_32 wake_en0;
_REG_(CLOCKS_WAKE_EN1_OFFSET) // CLOCKS_WAKE_EN1
// enable clock in wake mode
// 0x00004000 [14] CLK_SYS_XOSC (1)
// 0x00002000 [13] CLK_SYS_XIP (1)
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
// 0x00000800 [11] CLK_USB_USBCTRL (1)
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
// 0x00000200 [9] CLK_SYS_UART1 (1)
// 0x00000100 [8] CLK_PERI_UART1 (1)
// 0x00000080 [7] CLK_SYS_UART0 (1)
// 0x00000040 [6] CLK_PERI_UART0 (1)
// 0x00000020 [5] CLK_SYS_TIMER (1)
// 0x00000010 [4] CLK_SYS_TBMAN (1)
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
io_rw_32 wake_en1;
};
// (Description copied from array index 0 register CLOCKS_WAKE_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_WAKE_EN0_OFFSET) // CLOCKS_WAKE_EN0
// enable clock in wake mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIO (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_PSM (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC (1)
// 0x00000002 [1] CLK_ADC_ADC (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 wake_en[2];
};
union {
struct {
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIOB (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_POWER (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_LDO_POR (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC0 (1)
// 0x00000002 [1] CLK_ADC_ADC0 (1)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (1)
io_rw_32 sleep_en0;
_REG_(CLOCKS_SLEEP_EN1_OFFSET) // CLOCKS_SLEEP_EN1
// enable clock in sleep mode
// 0x00004000 [14] CLK_SYS_XOSC (1)
// 0x00002000 [13] CLK_SYS_XIP (1)
// 0x00001000 [12] CLK_SYS_WATCHDOG (1)
// 0x00000800 [11] CLK_USB_USBCTRL (1)
// 0x00000400 [10] CLK_SYS_USBCTRL (1)
// 0x00000200 [9] CLK_SYS_UART1 (1)
// 0x00000100 [8] CLK_PERI_UART1 (1)
// 0x00000080 [7] CLK_SYS_UART0 (1)
// 0x00000040 [6] CLK_PERI_UART0 (1)
// 0x00000020 [5] CLK_SYS_TIMER (1)
// 0x00000010 [4] CLK_SYS_TBMAN (1)
// 0x00000008 [3] CLK_SYS_SYSINFO (1)
// 0x00000004 [2] CLK_SYS_SYSCFG (1)
// 0x00000002 [1] CLK_SYS_SRAM5 (1)
// 0x00000001 [0] CLK_SYS_SRAM4 (1)
io_rw_32 sleep_en1;
};
// (Description copied from array index 0 register CLOCKS_SLEEP_EN0 applies similarly to other array indexes)
_REG_(CLOCKS_SLEEP_EN0_OFFSET) // CLOCKS_SLEEP_EN0
// enable clock in sleep mode
// 0x80000000 [31] CLK_SYS_SRAM3 (1)
// 0x40000000 [30] CLK_SYS_SRAM2 (1)
// 0x20000000 [29] CLK_SYS_SRAM1 (1)
// 0x10000000 [28] CLK_SYS_SRAM0 (1)
// 0x08000000 [27] CLK_SYS_SPI1 (1)
// 0x04000000 [26] CLK_PERI_SPI1 (1)
// 0x02000000 [25] CLK_SYS_SPI0 (1)
// 0x01000000 [24] CLK_PERI_SPI0 (1)
// 0x00800000 [23] CLK_SYS_SIO (1)
// 0x00400000 [22] CLK_SYS_RTC (1)
// 0x00200000 [21] CLK_RTC_RTC (1)
// 0x00100000 [20] CLK_SYS_ROSC (1)
// 0x00080000 [19] CLK_SYS_ROM (1)
// 0x00040000 [18] CLK_SYS_RESETS (1)
// 0x00020000 [17] CLK_SYS_PWM (1)
// 0x00010000 [16] CLK_SYS_PSM (1)
// 0x00008000 [15] CLK_SYS_PLL_USB (1)
// 0x00004000 [14] CLK_SYS_PLL_SYS (1)
// 0x00002000 [13] CLK_SYS_PIO1 (1)
// 0x00001000 [12] CLK_SYS_PIO0 (1)
// 0x00000800 [11] CLK_SYS_PADS (1)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (1)
// 0x00000200 [9] CLK_SYS_JTAG (1)
// 0x00000100 [8] CLK_SYS_IO (1)
// 0x00000080 [7] CLK_SYS_I2C1 (1)
// 0x00000040 [6] CLK_SYS_I2C0 (1)
// 0x00000020 [5] CLK_SYS_DMA (1)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (1)
// 0x00000008 [3] CLK_SYS_BUSCTRL (1)
// 0x00000004 [2] CLK_SYS_ADC (1)
// 0x00000002 [1] CLK_ADC_ADC (1)
// 0x00000001 [0] CLK_SYS_CLOCKS (1)
io_rw_32 sleep_en[2];
};
union {
struct {
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
// 0x08000000 [27] CLK_SYS_SPI1 (0)
// 0x04000000 [26] CLK_PERI_SPI1 (0)
// 0x02000000 [25] CLK_SYS_SPI0 (0)
// 0x01000000 [24] CLK_PERI_SPI0 (0)
// 0x00800000 [23] CLK_SYS_SIOB (0)
// 0x00400000 [22] CLK_SYS_RTC (0)
// 0x00200000 [21] CLK_RTC_RTC (0)
// 0x00100000 [20] CLK_SYS_ROSC (0)
// 0x00080000 [19] CLK_SYS_ROM (0)
// 0x00040000 [18] CLK_SYS_RESETS (0)
// 0x00020000 [17] CLK_SYS_PWM (0)
// 0x00010000 [16] CLK_SYS_POWER (0)
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
// 0x00002000 [13] CLK_SYS_PIO1 (0)
// 0x00001000 [12] CLK_SYS_PIO0 (0)
// 0x00000800 [11] CLK_SYS_PADS (0)
// 0x00000400 [10] CLK_SYS_LDO_POR (0)
// 0x00000200 [9] CLK_SYS_JTAG (0)
// 0x00000100 [8] CLK_SYS_IO (0)
// 0x00000080 [7] CLK_SYS_I2C1 (0)
// 0x00000040 [6] CLK_SYS_I2C0 (0)
// 0x00000020 [5] CLK_SYS_DMA (0)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
// 0x00000004 [2] CLK_SYS_ADC0 (0)
// 0x00000002 [1] CLK_ADC_ADC0 (0)
// 0x00000001 [0] CLK_SYS_CLOCKS_BANK_DEFAULT (0)
io_ro_32 enabled0;
_REG_(CLOCKS_ENABLED1_OFFSET) // CLOCKS_ENABLED1
// indicates the state of the clock enable
// 0x00004000 [14] CLK_SYS_XOSC (0)
// 0x00002000 [13] CLK_SYS_XIP (0)
// 0x00001000 [12] CLK_SYS_WATCHDOG (0)
// 0x00000800 [11] CLK_USB_USBCTRL (0)
// 0x00000400 [10] CLK_SYS_USBCTRL (0)
// 0x00000200 [9] CLK_SYS_UART1 (0)
// 0x00000100 [8] CLK_PERI_UART1 (0)
// 0x00000080 [7] CLK_SYS_UART0 (0)
// 0x00000040 [6] CLK_PERI_UART0 (0)
// 0x00000020 [5] CLK_SYS_TIMER (0)
// 0x00000010 [4] CLK_SYS_TBMAN (0)
// 0x00000008 [3] CLK_SYS_SYSINFO (0)
// 0x00000004 [2] CLK_SYS_SYSCFG (0)
// 0x00000002 [1] CLK_SYS_SRAM5 (0)
// 0x00000001 [0] CLK_SYS_SRAM4 (0)
io_ro_32 enabled1;
};
// (Description copied from array index 0 register CLOCKS_ENABLED0 applies similarly to other array indexes)
_REG_(CLOCKS_ENABLED0_OFFSET) // CLOCKS_ENABLED0
// indicates the state of the clock enable
// 0x80000000 [31] CLK_SYS_SRAM3 (0)
// 0x40000000 [30] CLK_SYS_SRAM2 (0)
// 0x20000000 [29] CLK_SYS_SRAM1 (0)
// 0x10000000 [28] CLK_SYS_SRAM0 (0)
// 0x08000000 [27] CLK_SYS_SPI1 (0)
// 0x04000000 [26] CLK_PERI_SPI1 (0)
// 0x02000000 [25] CLK_SYS_SPI0 (0)
// 0x01000000 [24] CLK_PERI_SPI0 (0)
// 0x00800000 [23] CLK_SYS_SIO (0)
// 0x00400000 [22] CLK_SYS_RTC (0)
// 0x00200000 [21] CLK_RTC_RTC (0)
// 0x00100000 [20] CLK_SYS_ROSC (0)
// 0x00080000 [19] CLK_SYS_ROM (0)
// 0x00040000 [18] CLK_SYS_RESETS (0)
// 0x00020000 [17] CLK_SYS_PWM (0)
// 0x00010000 [16] CLK_SYS_PSM (0)
// 0x00008000 [15] CLK_SYS_PLL_USB (0)
// 0x00004000 [14] CLK_SYS_PLL_SYS (0)
// 0x00002000 [13] CLK_SYS_PIO1 (0)
// 0x00001000 [12] CLK_SYS_PIO0 (0)
// 0x00000800 [11] CLK_SYS_PADS (0)
// 0x00000400 [10] CLK_SYS_VREG_AND_CHIP_RESET (0)
// 0x00000200 [9] CLK_SYS_JTAG (0)
// 0x00000100 [8] CLK_SYS_IO (0)
// 0x00000080 [7] CLK_SYS_I2C1 (0)
// 0x00000040 [6] CLK_SYS_I2C0 (0)
// 0x00000020 [5] CLK_SYS_DMA (0)
// 0x00000010 [4] CLK_SYS_BUSFABRIC (0)
// 0x00000008 [3] CLK_SYS_BUSCTRL (0)
// 0x00000004 [2] CLK_SYS_ADC (0)
// 0x00000002 [1] CLK_ADC_ADC (0)
// 0x00000001 [0] CLK_SYS_CLOCKS (0)
io_ro_32 enabled[2];
};
_REG_(CLOCKS_INTR_OFFSET) // CLOCKS_INTR
// Raw Interrupts
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 intr;
_REG_(CLOCKS_INTE_OFFSET) // CLOCKS_INTE
// Interrupt Enable
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 inte;
_REG_(CLOCKS_INTF_OFFSET) // CLOCKS_INTF
// Interrupt Force
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_rw_32 intf;
_REG_(CLOCKS_INTS_OFFSET) // CLOCKS_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] CLK_SYS_RESUS (0)
io_ro_32 ints;
} clocks_hw_t;
#define clocks_hw ((clocks_hw_t *)CLOCKS_BASE)
static_assert(sizeof (clocks_hw_t) == 0x00c8, "");
#endif // _HARDWARE_STRUCTS_CLOCKS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_H
#define _HARDWARE_STRUCTS_DMA_H
/**
* \file rp2040/dma.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
#include "hardware/structs/dma_debug.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_READ_ADDR_OFFSET) // DMA_CH0_READ_ADDR
// DMA Channel 0 Read Address pointer
// 0xffffffff [31:0] CH0_READ_ADDR (0x00000000) This register updates automatically each time a read completes
io_rw_32 read_addr;
_REG_(DMA_CH0_WRITE_ADDR_OFFSET) // DMA_CH0_WRITE_ADDR
// DMA Channel 0 Write Address pointer
// 0xffffffff [31:0] CH0_WRITE_ADDR (0x00000000) This register updates automatically each time a write completes
io_rw_32 write_addr;
_REG_(DMA_CH0_TRANS_COUNT_OFFSET) // DMA_CH0_TRANS_COUNT
// DMA Channel 0 Transfer Count
// 0xffffffff [31:0] CH0_TRANS_COUNT (0x00000000) Program the number of bus transfers a channel will...
io_rw_32 transfer_count;
_REG_(DMA_CH0_CTRL_TRIG_OFFSET) // DMA_CH0_CTRL_TRIG
// DMA Channel 0 Control and Status
// 0x80000000 [31] AHB_ERROR (0) Logical OR of the READ_ERROR and WRITE_ERROR flags
// 0x40000000 [30] READ_ERROR (0) If 1, the channel received a read bus error
// 0x20000000 [29] WRITE_ERROR (0) If 1, the channel received a write bus error
// 0x01000000 [24] BUSY (0) This flag goes high when the channel starts a new...
// 0x00800000 [23] SNIFF_EN (0) If 1, this channel's data transfers are visible to the...
// 0x00400000 [22] BSWAP (0) Apply byte-swap transformation to DMA data
// 0x00200000 [21] IRQ_QUIET (0) In QUIET mode, the channel does not generate IRQs at the...
// 0x001f8000 [20:15] TREQ_SEL (0x00) Select a Transfer Request signal
// 0x00007800 [14:11] CHAIN_TO (0x0) When this channel completes, it will trigger the channel...
// 0x00000400 [10] RING_SEL (0) Select whether RING_SIZE applies to read or write addresses
// 0x000003c0 [9:6] RING_SIZE (0x0) Size of address wrap region
// 0x00000020 [5] INCR_WRITE (0) If 1, the write address increments with each transfer
// 0x00000010 [4] INCR_READ (0) If 1, the read address increments with each transfer
// 0x0000000c [3:2] DATA_SIZE (0x0) Set the size of each bus transfer (byte/halfword/word)
// 0x00000002 [1] HIGH_PRIORITY (0) HIGH_PRIORITY gives a channel preferential treatment in...
// 0x00000001 [0] EN (0) DMA Channel Enable
io_rw_32 ctrl_trig;
_REG_(DMA_CH0_AL1_CTRL_OFFSET) // DMA_CH0_AL1_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL1_CTRL (-)
io_rw_32 al1_ctrl;
_REG_(DMA_CH0_AL1_READ_ADDR_OFFSET) // DMA_CH0_AL1_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL1_READ_ADDR (-)
io_rw_32 al1_read_addr;
_REG_(DMA_CH0_AL1_WRITE_ADDR_OFFSET) // DMA_CH0_AL1_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL1_WRITE_ADDR (-)
io_rw_32 al1_write_addr;
_REG_(DMA_CH0_AL1_TRANS_COUNT_TRIG_OFFSET) // DMA_CH0_AL1_TRANS_COUNT_TRIG
// Alias for channel 0 TRANS_COUNT register +
// 0xffffffff [31:0] CH0_AL1_TRANS_COUNT_TRIG (-)
io_rw_32 al1_transfer_count_trig;
_REG_(DMA_CH0_AL2_CTRL_OFFSET) // DMA_CH0_AL2_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL2_CTRL (-)
io_rw_32 al2_ctrl;
_REG_(DMA_CH0_AL2_TRANS_COUNT_OFFSET) // DMA_CH0_AL2_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL2_TRANS_COUNT (-)
io_rw_32 al2_transfer_count;
_REG_(DMA_CH0_AL2_READ_ADDR_OFFSET) // DMA_CH0_AL2_READ_ADDR
// Alias for channel 0 READ_ADDR register
// 0xffffffff [31:0] CH0_AL2_READ_ADDR (-)
io_rw_32 al2_read_addr;
_REG_(DMA_CH0_AL2_WRITE_ADDR_TRIG_OFFSET) // DMA_CH0_AL2_WRITE_ADDR_TRIG
// Alias for channel 0 WRITE_ADDR register +
// 0xffffffff [31:0] CH0_AL2_WRITE_ADDR_TRIG (-)
io_rw_32 al2_write_addr_trig;
_REG_(DMA_CH0_AL3_CTRL_OFFSET) // DMA_CH0_AL3_CTRL
// Alias for channel 0 CTRL register
// 0xffffffff [31:0] CH0_AL3_CTRL (-)
io_rw_32 al3_ctrl;
_REG_(DMA_CH0_AL3_WRITE_ADDR_OFFSET) // DMA_CH0_AL3_WRITE_ADDR
// Alias for channel 0 WRITE_ADDR register
// 0xffffffff [31:0] CH0_AL3_WRITE_ADDR (-)
io_rw_32 al3_write_addr;
_REG_(DMA_CH0_AL3_TRANS_COUNT_OFFSET) // DMA_CH0_AL3_TRANS_COUNT
// Alias for channel 0 TRANS_COUNT register
// 0xffffffff [31:0] CH0_AL3_TRANS_COUNT (-)
io_rw_32 al3_transfer_count;
_REG_(DMA_CH0_AL3_READ_ADDR_TRIG_OFFSET) // DMA_CH0_AL3_READ_ADDR_TRIG
// Alias for channel 0 READ_ADDR register +
// 0xffffffff [31:0] CH0_AL3_READ_ADDR_TRIG (-)
io_rw_32 al3_read_addr_trig;
} dma_channel_hw_t;
typedef struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
io_rw_32 intf;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints;
} dma_irq_ctrl_hw_t;
typedef struct {
dma_channel_hw_t ch[12];
uint32_t _pad0[64];
union {
struct {
_REG_(DMA_INTR_OFFSET) // DMA_INTR
// Interrupt Status (raw)
// 0x0000ffff [15:0] INTR (0x0000) Raw interrupt status for DMA Channels 0
io_rw_32 intr;
_REG_(DMA_INTE0_OFFSET) // DMA_INTE0
// Interrupt Enables for IRQ 0
// 0x0000ffff [15:0] INTE0 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 0
io_rw_32 inte0;
_REG_(DMA_INTF0_OFFSET) // DMA_INTF0
// Force Interrupts
// 0x0000ffff [15:0] INTF0 (0x0000) Write 1s to force the corresponding bits in INTE0
io_rw_32 intf0;
_REG_(DMA_INTS0_OFFSET) // DMA_INTS0
// Interrupt Status for IRQ 0
// 0x0000ffff [15:0] INTS0 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints0;
uint32_t __pad0;
_REG_(DMA_INTE1_OFFSET) // DMA_INTE1
// Interrupt Enables for IRQ 1
// 0x0000ffff [15:0] INTE1 (0x0000) Set bit n to pass interrupts from channel n to DMA IRQ 1
io_rw_32 inte1;
_REG_(DMA_INTF1_OFFSET) // DMA_INTF1
// Force Interrupts for IRQ 1
// 0x0000ffff [15:0] INTF1 (0x0000) Write 1s to force the corresponding bits in INTF1
io_rw_32 intf1;
_REG_(DMA_INTS1_OFFSET) // DMA_INTS1
// Interrupt Status (masked) for IRQ 1
// 0x0000ffff [15:0] INTS1 (0x0000) Indicates active channel interrupt requests which are...
io_rw_32 ints1;
};
dma_irq_ctrl_hw_t irq_ctrl[2];
};
// (Description copied from array index 0 register DMA_TIMER0 applies similarly to other array indexes)
_REG_(DMA_TIMER0_OFFSET) // DMA_TIMER0
// Pacing (X/Y) Fractional Timer +
// 0xffff0000 [31:16] X (0x0000) Pacing Timer Dividend
// 0x0000ffff [15:0] Y (0x0000) Pacing Timer Divisor
io_rw_32 timer[4];
_REG_(DMA_MULTI_CHAN_TRIGGER_OFFSET) // DMA_MULTI_CHAN_TRIGGER
// Trigger one or more channels simultaneously
// 0x0000ffff [15:0] MULTI_CHAN_TRIGGER (0x0000) Each bit in this register corresponds to a DMA channel
io_wo_32 multi_channel_trigger;
_REG_(DMA_SNIFF_CTRL_OFFSET) // DMA_SNIFF_CTRL
// Sniffer Control
// 0x00000800 [11] OUT_INV (0) If set, the result appears inverted (bitwise complement)...
// 0x00000400 [10] OUT_REV (0) If set, the result appears bit-reversed when read
// 0x00000200 [9] BSWAP (0) Locally perform a byte reverse on the sniffed data,...
// 0x000001e0 [8:5] CALC (0x0)
// 0x0000001e [4:1] DMACH (0x0) DMA channel for Sniffer to observe
// 0x00000001 [0] EN (0) Enable sniffer
io_rw_32 sniff_ctrl;
_REG_(DMA_SNIFF_DATA_OFFSET) // DMA_SNIFF_DATA
// Data accumulator for sniff hardware
// 0xffffffff [31:0] SNIFF_DATA (0x00000000) Write an initial seed value here before starting a DMA...
io_rw_32 sniff_data;
uint32_t _pad1;
_REG_(DMA_FIFO_LEVELS_OFFSET) // DMA_FIFO_LEVELS
// Debug RAF, WAF, TDF levels
// 0x00ff0000 [23:16] RAF_LVL (0x00) Current Read-Address-FIFO fill level
// 0x0000ff00 [15:8] WAF_LVL (0x00) Current Write-Address-FIFO fill level
// 0x000000ff [7:0] TDF_LVL (0x00) Current Transfer-Data-FIFO fill level
io_ro_32 fifo_levels;
_REG_(DMA_CHAN_ABORT_OFFSET) // DMA_CHAN_ABORT
// Abort an in-progress transfer sequence on one or more channels
// 0x0000ffff [15:0] CHAN_ABORT (0x0000) Each bit corresponds to a channel
io_wo_32 abort;
} dma_hw_t;
#define dma_hw ((dma_hw_t *)DMA_BASE)
static_assert(sizeof (dma_hw_t) == 0x0448, "");
#endif // _HARDWARE_STRUCTS_DMA_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_DMA_DEBUG_H
#define _HARDWARE_STRUCTS_DMA_DEBUG_H
/**
* \file rp2040/dma_debug.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/dma.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_dma
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/dma.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(DMA_CH0_DBG_CTDREQ_OFFSET) // DMA_CH0_DBG_CTDREQ
// Read: get channel DREQ counter (i
// 0x0000003f [5:0] CH0_DBG_CTDREQ (0x00)
io_rw_32 dbg_ctdreq;
_REG_(DMA_CH0_DBG_TCR_OFFSET) // DMA_CH0_DBG_TCR
// Read to get channel TRANS_COUNT reload value, i
// 0xffffffff [31:0] CH0_DBG_TCR (0x00000000)
io_ro_32 dbg_tcr;
uint32_t _pad0[14];
} dma_debug_channel_hw_t;
typedef struct {
dma_debug_channel_hw_t ch[12];
} dma_debug_hw_t;
#define dma_debug_hw ((dma_debug_hw_t *)(DMA_BASE + DMA_CH0_DBG_CTDREQ_OFFSET))
#endif // _HARDWARE_STRUCTS_DMA_DEBUG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_I2C_H
#define _HARDWARE_STRUCTS_I2C_H
/**
* \file rp2040/i2c.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/i2c.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_i2c
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/i2c.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(I2C_IC_CON_OFFSET) // I2C_IC_CON
// I2C Control Register
// 0x00000400 [10] STOP_DET_IF_MASTER_ACTIVE (0) Master issues the STOP_DET interrupt irrespective of...
// 0x00000200 [9] RX_FIFO_FULL_HLD_CTRL (0) This bit controls whether DW_apb_i2c should hold the bus...
// 0x00000100 [8] TX_EMPTY_CTRL (0) This bit controls the generation of the TX_EMPTY...
// 0x00000080 [7] STOP_DET_IFADDRESSED (0) In slave mode: - 1'b1: issues the STOP_DET interrupt...
// 0x00000040 [6] IC_SLAVE_DISABLE (1) This bit controls whether I2C has its slave disabled,...
// 0x00000020 [5] IC_RESTART_EN (1) Determines whether RESTART conditions may be sent when...
// 0x00000010 [4] IC_10BITADDR_MASTER (0) Controls whether the DW_apb_i2c starts its transfers in...
// 0x00000008 [3] IC_10BITADDR_SLAVE (0) When acting as a slave, this bit controls whether the...
// 0x00000006 [2:1] SPEED (0x2) These bits control at which speed the DW_apb_i2c...
// 0x00000001 [0] MASTER_MODE (1) This bit controls whether the DW_apb_i2c master is enabled
io_rw_32 con;
_REG_(I2C_IC_TAR_OFFSET) // I2C_IC_TAR
// I2C Target Address Register
// 0x00000800 [11] SPECIAL (0) This bit indicates whether software performs a Device-ID...
// 0x00000400 [10] GC_OR_START (0) If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is...
// 0x000003ff [9:0] IC_TAR (0x055) This is the target address for any master transaction
io_rw_32 tar;
_REG_(I2C_IC_SAR_OFFSET) // I2C_IC_SAR
// I2C Slave Address Register
// 0x000003ff [9:0] IC_SAR (0x055) The IC_SAR holds the slave address when the I2C is...
io_rw_32 sar;
uint32_t _pad0;
_REG_(I2C_IC_DATA_CMD_OFFSET) // I2C_IC_DATA_CMD
// I2C Rx/Tx Data Buffer and Command Register
// 0x00000800 [11] FIRST_DATA_BYTE (0) Indicates the first data byte received after the address...
// 0x00000400 [10] RESTART (0) This bit controls whether a RESTART is issued before the...
// 0x00000200 [9] STOP (0) This bit controls whether a STOP is issued after the...
// 0x00000100 [8] CMD (0) This bit controls whether a read or a write is performed
// 0x000000ff [7:0] DAT (0x00) This register contains the data to be transmitted or...
io_rw_32 data_cmd;
_REG_(I2C_IC_SS_SCL_HCNT_OFFSET) // I2C_IC_SS_SCL_HCNT
// Standard Speed I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_SS_SCL_HCNT (0x0028) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_hcnt;
_REG_(I2C_IC_SS_SCL_LCNT_OFFSET) // I2C_IC_SS_SCL_LCNT
// Standard Speed I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_SS_SCL_LCNT (0x002f) This register must be set before any I2C bus transaction...
io_rw_32 ss_scl_lcnt;
_REG_(I2C_IC_FS_SCL_HCNT_OFFSET) // I2C_IC_FS_SCL_HCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
// 0x0000ffff [15:0] IC_FS_SCL_HCNT (0x0006) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_hcnt;
_REG_(I2C_IC_FS_SCL_LCNT_OFFSET) // I2C_IC_FS_SCL_LCNT
// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
// 0x0000ffff [15:0] IC_FS_SCL_LCNT (0x000d) This register must be set before any I2C bus transaction...
io_rw_32 fs_scl_lcnt;
uint32_t _pad1[2];
_REG_(I2C_IC_INTR_STAT_OFFSET) // I2C_IC_INTR_STAT
// I2C Interrupt Status Register
// 0x00001000 [12] R_RESTART_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000800 [11] R_GEN_CALL (0) See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit
// 0x00000400 [10] R_START_DET (0) See IC_RAW_INTR_STAT for a detailed description of...
// 0x00000200 [9] R_STOP_DET (0) See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit
// 0x00000100 [8] R_ACTIVITY (0) See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit
// 0x00000080 [7] R_RX_DONE (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit
// 0x00000040 [6] R_TX_ABRT (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit
// 0x00000020 [5] R_RD_REQ (0) See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit
// 0x00000010 [4] R_TX_EMPTY (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit
// 0x00000008 [3] R_TX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit
// 0x00000004 [2] R_RX_FULL (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit
// 0x00000002 [1] R_RX_OVER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit
// 0x00000001 [0] R_RX_UNDER (0) See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit
io_ro_32 intr_stat;
_REG_(I2C_IC_INTR_MASK_OFFSET) // I2C_IC_INTR_MASK
// I2C Interrupt Mask Register
// 0x00001000 [12] M_RESTART_DET (0) This bit masks the R_RESTART_DET interrupt in...
// 0x00000800 [11] M_GEN_CALL (1) This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register
// 0x00000400 [10] M_START_DET (0) This bit masks the R_START_DET interrupt in IC_INTR_STAT register
// 0x00000200 [9] M_STOP_DET (0) This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register
// 0x00000100 [8] M_ACTIVITY (0) This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register
// 0x00000080 [7] M_RX_DONE (1) This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register
// 0x00000040 [6] M_TX_ABRT (1) This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register
// 0x00000020 [5] M_RD_REQ (1) This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register
// 0x00000010 [4] M_TX_EMPTY (1) This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register
// 0x00000008 [3] M_TX_OVER (1) This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register
// 0x00000004 [2] M_RX_FULL (1) This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register
// 0x00000002 [1] M_RX_OVER (1) This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register
// 0x00000001 [0] M_RX_UNDER (1) This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register
io_rw_32 intr_mask;
_REG_(I2C_IC_RAW_INTR_STAT_OFFSET) // I2C_IC_RAW_INTR_STAT
// I2C Raw Interrupt Status Register
// 0x00001000 [12] RESTART_DET (0) Indicates whether a RESTART condition has occurred on...
// 0x00000800 [11] GEN_CALL (0) Set only when a General Call address is received and it...
// 0x00000400 [10] START_DET (0) Indicates whether a START or RESTART condition has...
// 0x00000200 [9] STOP_DET (0) Indicates whether a STOP condition has occurred on the...
// 0x00000100 [8] ACTIVITY (0) This bit captures DW_apb_i2c activity and stays set...
// 0x00000080 [7] RX_DONE (0) When the DW_apb_i2c is acting as a slave-transmitter,...
// 0x00000040 [6] TX_ABRT (0) This bit indicates if DW_apb_i2c, as an I2C transmitter,...
// 0x00000020 [5] RD_REQ (0) This bit is set to 1 when DW_apb_i2c is acting as a...
// 0x00000010 [4] TX_EMPTY (0) The behavior of the TX_EMPTY interrupt status differs...
// 0x00000008 [3] TX_OVER (0) Set during transmit if the transmit buffer is filled to...
// 0x00000004 [2] RX_FULL (0) Set when the receive buffer reaches or goes above the...
// 0x00000002 [1] RX_OVER (0) Set if the receive buffer is completely filled to...
// 0x00000001 [0] RX_UNDER (0) Set if the processor attempts to read the receive buffer...
io_ro_32 raw_intr_stat;
_REG_(I2C_IC_RX_TL_OFFSET) // I2C_IC_RX_TL
// I2C Receive FIFO Threshold Register
// 0x000000ff [7:0] RX_TL (0x00) Receive FIFO Threshold Level
io_rw_32 rx_tl;
_REG_(I2C_IC_TX_TL_OFFSET) // I2C_IC_TX_TL
// I2C Transmit FIFO Threshold Register
// 0x000000ff [7:0] TX_TL (0x00) Transmit FIFO Threshold Level
io_rw_32 tx_tl;
_REG_(I2C_IC_CLR_INTR_OFFSET) // I2C_IC_CLR_INTR
// Clear Combined and Individual Interrupt Register
// 0x00000001 [0] CLR_INTR (0) Read this register to clear the combined interrupt, all...
io_ro_32 clr_intr;
_REG_(I2C_IC_CLR_RX_UNDER_OFFSET) // I2C_IC_CLR_RX_UNDER
// Clear RX_UNDER Interrupt Register
// 0x00000001 [0] CLR_RX_UNDER (0) Read this register to clear the RX_UNDER interrupt (bit...
io_ro_32 clr_rx_under;
_REG_(I2C_IC_CLR_RX_OVER_OFFSET) // I2C_IC_CLR_RX_OVER
// Clear RX_OVER Interrupt Register
// 0x00000001 [0] CLR_RX_OVER (0) Read this register to clear the RX_OVER interrupt (bit...
io_ro_32 clr_rx_over;
_REG_(I2C_IC_CLR_TX_OVER_OFFSET) // I2C_IC_CLR_TX_OVER
// Clear TX_OVER Interrupt Register
// 0x00000001 [0] CLR_TX_OVER (0) Read this register to clear the TX_OVER interrupt (bit...
io_ro_32 clr_tx_over;
_REG_(I2C_IC_CLR_RD_REQ_OFFSET) // I2C_IC_CLR_RD_REQ
// Clear RD_REQ Interrupt Register
// 0x00000001 [0] CLR_RD_REQ (0) Read this register to clear the RD_REQ interrupt (bit 5)...
io_ro_32 clr_rd_req;
_REG_(I2C_IC_CLR_TX_ABRT_OFFSET) // I2C_IC_CLR_TX_ABRT
// Clear TX_ABRT Interrupt Register
// 0x00000001 [0] CLR_TX_ABRT (0) Read this register to clear the TX_ABRT interrupt (bit...
io_ro_32 clr_tx_abrt;
_REG_(I2C_IC_CLR_RX_DONE_OFFSET) // I2C_IC_CLR_RX_DONE
// Clear RX_DONE Interrupt Register
// 0x00000001 [0] CLR_RX_DONE (0) Read this register to clear the RX_DONE interrupt (bit...
io_ro_32 clr_rx_done;
_REG_(I2C_IC_CLR_ACTIVITY_OFFSET) // I2C_IC_CLR_ACTIVITY
// Clear ACTIVITY Interrupt Register
// 0x00000001 [0] CLR_ACTIVITY (0) Reading this register clears the ACTIVITY interrupt if...
io_ro_32 clr_activity;
_REG_(I2C_IC_CLR_STOP_DET_OFFSET) // I2C_IC_CLR_STOP_DET
// Clear STOP_DET Interrupt Register
// 0x00000001 [0] CLR_STOP_DET (0) Read this register to clear the STOP_DET interrupt (bit...
io_ro_32 clr_stop_det;
_REG_(I2C_IC_CLR_START_DET_OFFSET) // I2C_IC_CLR_START_DET
// Clear START_DET Interrupt Register
// 0x00000001 [0] CLR_START_DET (0) Read this register to clear the START_DET interrupt (bit...
io_ro_32 clr_start_det;
_REG_(I2C_IC_CLR_GEN_CALL_OFFSET) // I2C_IC_CLR_GEN_CALL
// Clear GEN_CALL Interrupt Register
// 0x00000001 [0] CLR_GEN_CALL (0) Read this register to clear the GEN_CALL interrupt (bit...
io_ro_32 clr_gen_call;
_REG_(I2C_IC_ENABLE_OFFSET) // I2C_IC_ENABLE
// I2C ENABLE Register
// 0x00000004 [2] TX_CMD_BLOCK (0) In Master mode: - 1'b1: Blocks the transmission of data...
// 0x00000002 [1] ABORT (0) When set, the controller initiates the transfer abort
// 0x00000001 [0] ENABLE (0) Controls whether the DW_apb_i2c is enabled
io_rw_32 enable;
_REG_(I2C_IC_STATUS_OFFSET) // I2C_IC_STATUS
// I2C STATUS Register
// 0x00000040 [6] SLV_ACTIVITY (0) Slave FSM Activity Status
// 0x00000020 [5] MST_ACTIVITY (0) Master FSM Activity Status
// 0x00000010 [4] RFF (0) Receive FIFO Completely Full
// 0x00000008 [3] RFNE (0) Receive FIFO Not Empty
// 0x00000004 [2] TFE (1) Transmit FIFO Completely Empty
// 0x00000002 [1] TFNF (1) Transmit FIFO Not Full
// 0x00000001 [0] ACTIVITY (0) I2C Activity Status
io_ro_32 status;
_REG_(I2C_IC_TXFLR_OFFSET) // I2C_IC_TXFLR
// I2C Transmit FIFO Level Register
// 0x0000001f [4:0] TXFLR (0x00) Transmit FIFO Level
io_ro_32 txflr;
_REG_(I2C_IC_RXFLR_OFFSET) // I2C_IC_RXFLR
// I2C Receive FIFO Level Register
// 0x0000001f [4:0] RXFLR (0x00) Receive FIFO Level
io_ro_32 rxflr;
_REG_(I2C_IC_SDA_HOLD_OFFSET) // I2C_IC_SDA_HOLD
// I2C SDA Hold Time Length Register
// 0x00ff0000 [23:16] IC_SDA_RX_HOLD (0x00) Sets the required SDA hold time in units of ic_clk...
// 0x0000ffff [15:0] IC_SDA_TX_HOLD (0x0001) Sets the required SDA hold time in units of ic_clk...
io_rw_32 sda_hold;
_REG_(I2C_IC_TX_ABRT_SOURCE_OFFSET) // I2C_IC_TX_ABRT_SOURCE
// I2C Transmit Abort Source Register
// 0xff800000 [31:23] TX_FLUSH_CNT (0x000) This field indicates the number of Tx FIFO Data Commands...
// 0x00010000 [16] ABRT_USER_ABRT (0) This is a master-mode-only bit
// 0x00008000 [15] ABRT_SLVRD_INTX (0) 1: When the processor side responds to a slave mode...
// 0x00004000 [14] ABRT_SLV_ARBLOST (0) This field indicates that a Slave has lost the bus while...
// 0x00002000 [13] ABRT_SLVFLUSH_TXFIFO (0) This field specifies that the Slave has received a read...
// 0x00001000 [12] ARB_LOST (0) This field specifies that the Master has lost...
// 0x00000800 [11] ABRT_MASTER_DIS (0) This field indicates that the User tries to initiate a...
// 0x00000400 [10] ABRT_10B_RD_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000200 [9] ABRT_SBYTE_NORSTRT (0) To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT...
// 0x00000100 [8] ABRT_HS_NORSTRT (0) This field indicates that the restart is disabled...
// 0x00000080 [7] ABRT_SBYTE_ACKDET (0) This field indicates that the Master has sent a START...
// 0x00000040 [6] ABRT_HS_ACKDET (0) This field indicates that the Master is in High Speed...
// 0x00000020 [5] ABRT_GCALL_READ (0) This field indicates that DW_apb_i2c in the master mode...
// 0x00000010 [4] ABRT_GCALL_NOACK (0) This field indicates that DW_apb_i2c in master mode has...
// 0x00000008 [3] ABRT_TXDATA_NOACK (0) This field indicates the master-mode only bit
// 0x00000004 [2] ABRT_10ADDR2_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000002 [1] ABRT_10ADDR1_NOACK (0) This field indicates that the Master is in 10-bit...
// 0x00000001 [0] ABRT_7B_ADDR_NOACK (0) This field indicates that the Master is in 7-bit...
io_ro_32 tx_abrt_source;
_REG_(I2C_IC_SLV_DATA_NACK_ONLY_OFFSET) // I2C_IC_SLV_DATA_NACK_ONLY
// Generate Slave Data NACK Register
// 0x00000001 [0] NACK (0) Generate NACK
io_rw_32 slv_data_nack_only;
_REG_(I2C_IC_DMA_CR_OFFSET) // I2C_IC_DMA_CR
// DMA Control Register
// 0x00000002 [1] TDMAE (0) Transmit DMA Enable
// 0x00000001 [0] RDMAE (0) Receive DMA Enable
io_rw_32 dma_cr;
_REG_(I2C_IC_DMA_TDLR_OFFSET) // I2C_IC_DMA_TDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMATDL (0x0) Transmit Data Level
io_rw_32 dma_tdlr;
_REG_(I2C_IC_DMA_RDLR_OFFSET) // I2C_IC_DMA_RDLR
// DMA Transmit Data Level Register
// 0x0000000f [3:0] DMARDL (0x0) Receive Data Level
io_rw_32 dma_rdlr;
_REG_(I2C_IC_SDA_SETUP_OFFSET) // I2C_IC_SDA_SETUP
// I2C SDA Setup Register
// 0x000000ff [7:0] SDA_SETUP (0x64) SDA Setup
io_rw_32 sda_setup;
_REG_(I2C_IC_ACK_GENERAL_CALL_OFFSET) // I2C_IC_ACK_GENERAL_CALL
// I2C ACK General Call Register
// 0x00000001 [0] ACK_GEN_CALL (1) ACK General Call
io_rw_32 ack_general_call;
_REG_(I2C_IC_ENABLE_STATUS_OFFSET) // I2C_IC_ENABLE_STATUS
// I2C Enable Status Register
// 0x00000004 [2] SLV_RX_DATA_LOST (0) Slave Received Data Lost
// 0x00000002 [1] SLV_DISABLED_WHILE_BUSY (0) Slave Disabled While Busy (Transmit, Receive)
// 0x00000001 [0] IC_EN (0) ic_en Status
io_ro_32 enable_status;
_REG_(I2C_IC_FS_SPKLEN_OFFSET) // I2C_IC_FS_SPKLEN
// I2C SS, FS or FM+ spike suppression limit
// 0x000000ff [7:0] IC_FS_SPKLEN (0x07) This register must be set before any I2C bus transaction...
io_rw_32 fs_spklen;
uint32_t _pad2;
_REG_(I2C_IC_CLR_RESTART_DET_OFFSET) // I2C_IC_CLR_RESTART_DET
// Clear RESTART_DET Interrupt Register
// 0x00000001 [0] CLR_RESTART_DET (0) Read this register to clear the RESTART_DET interrupt...
io_ro_32 clr_restart_det;
uint32_t _pad3[18];
_REG_(I2C_IC_COMP_PARAM_1_OFFSET) // I2C_IC_COMP_PARAM_1
// Component Parameter Register 1
// 0x00ff0000 [23:16] TX_BUFFER_DEPTH (0x00) TX Buffer Depth = 16
// 0x0000ff00 [15:8] RX_BUFFER_DEPTH (0x00) RX Buffer Depth = 16
// 0x00000080 [7] ADD_ENCODED_PARAMS (0) Encoded parameters not visible
// 0x00000040 [6] HAS_DMA (0) DMA handshaking signals are enabled
// 0x00000020 [5] INTR_IO (0) COMBINED Interrupt outputs
// 0x00000010 [4] HC_COUNT_VALUES (0) Programmable count values for each mode
// 0x0000000c [3:2] MAX_SPEED_MODE (0x0) MAX SPEED MODE = FAST MODE
// 0x00000003 [1:0] APB_DATA_WIDTH (0x0) APB data bus width is 32 bits
io_ro_32 comp_param_1;
_REG_(I2C_IC_COMP_VERSION_OFFSET) // I2C_IC_COMP_VERSION
// I2C Component Version Register
// 0xffffffff [31:0] IC_COMP_VERSION (0x3230312a)
io_ro_32 comp_version;
_REG_(I2C_IC_COMP_TYPE_OFFSET) // I2C_IC_COMP_TYPE
// I2C Component Type Register
// 0xffffffff [31:0] IC_COMP_TYPE (0x44570140) Designware Component Type number = 0x44_57_01_40
io_ro_32 comp_type;
} i2c_hw_t;
#define i2c0_hw ((i2c_hw_t *)I2C0_BASE)
#define i2c1_hw ((i2c_hw_t *)I2C1_BASE)
static_assert(sizeof (i2c_hw_t) == 0x0100, "");
#endif // _HARDWARE_STRUCTS_I2C_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_INTERP_H
#define _HARDWARE_STRUCTS_INTERP_H
/**
* \file rp2040/interp.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_OFFSET) // SIO_INTERP0_ACCUM0
// Read/write access to accumulator 0
// 0xffffffff [31:0] INTERP0_ACCUM0 (0x00000000)
io_rw_32 accum[2];
// (Description copied from array index 0 register SIO_INTERP0_BASE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_BASE0_OFFSET) // SIO_INTERP0_BASE0
// Read/write access to BASE0 register
// 0xffffffff [31:0] INTERP0_BASE0 (0x00000000)
io_rw_32 base[3];
// (Description copied from array index 0 register SIO_INTERP0_POP_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_POP_LANE0_OFFSET) // SIO_INTERP0_POP_LANE0
// Read LANE0 result, and simultaneously write lane results to both accumulators (POP)
// 0xffffffff [31:0] INTERP0_POP_LANE0 (0x00000000)
io_ro_32 pop[3];
// (Description copied from array index 0 register SIO_INTERP0_PEEK_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_PEEK_LANE0_OFFSET) // SIO_INTERP0_PEEK_LANE0
// Read LANE0 result, without altering any internal state (PEEK)
// 0xffffffff [31:0] INTERP0_PEEK_LANE0 (0x00000000)
io_ro_32 peek[3];
// (Description copied from array index 0 register SIO_INTERP0_CTRL_LANE0 applies similarly to other array indexes)
_REG_(SIO_INTERP0_CTRL_LANE0_OFFSET) // SIO_INTERP0_CTRL_LANE0
// Control register for lane 0
// 0x02000000 [25] OVERF (0) Set if either OVERF0 or OVERF1 is set
// 0x01000000 [24] OVERF1 (0) Indicates if any masked-off MSBs in ACCUM1 are set
// 0x00800000 [23] OVERF0 (0) Indicates if any masked-off MSBs in ACCUM0 are set
// 0x00200000 [21] BLEND (0) Only present on INTERP0 on each core
// 0x00180000 [20:19] FORCE_MSB (0x0) ORed into bits 29:28 of the lane result presented to the...
// 0x00040000 [18] ADD_RAW (0) If 1, mask + shift is bypassed for LANE0 result
// 0x00020000 [17] CROSS_RESULT (0) If 1, feed the opposite lane's result into this lane's...
// 0x00010000 [16] CROSS_INPUT (0) If 1, feed the opposite lane's accumulator into this...
// 0x00008000 [15] SIGNED (0) If SIGNED is set, the shifted and masked accumulator...
// 0x00007c00 [14:10] MASK_MSB (0x00) The most-significant bit allowed to pass by the mask...
// 0x000003e0 [9:5] MASK_LSB (0x00) The least-significant bit allowed to pass by the mask (inclusive)
// 0x0000001f [4:0] SHIFT (0x00) Logical right-shift applied to accumulator before masking
io_rw_32 ctrl[2];
// (Description copied from array index 0 register SIO_INTERP0_ACCUM0_ADD applies similarly to other array indexes)
_REG_(SIO_INTERP0_ACCUM0_ADD_OFFSET) // SIO_INTERP0_ACCUM0_ADD
// Values written here are atomically added to ACCUM0
// 0x00ffffff [23:0] INTERP0_ACCUM0_ADD (0x000000)
io_rw_32 add_raw[2];
_REG_(SIO_INTERP0_BASE_1AND0_OFFSET) // SIO_INTERP0_BASE_1AND0
// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
// 0xffffffff [31:0] INTERP0_BASE_1AND0 (0x00000000)
io_wo_32 base01;
} interp_hw_t;
#define interp_hw_array ((interp_hw_t *)(SIO_BASE + SIO_INTERP0_ACCUM0_OFFSET))
static_assert(sizeof (interp_hw_t) == 0x0040, "");
#define interp0_hw (&interp_hw_array[0])
#define interp1_hw (&interp_hw_array[1])
#endif // _HARDWARE_STRUCTS_INTERP_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_BANK0_H
#define _HARDWARE_STRUCTS_IO_BANK0_H
/**
* \file rp2040/io_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief GPIO pin function selectors on RP2040 (used as typedef \ref gpio_function_t)
* \ingroup hardware_gpio
*/
typedef enum gpio_function_rp2040 {
GPIO_FUNC_XIP = 0, ///< Select XIP as GPIO pin function
GPIO_FUNC_SPI = 1, ///< Select SPI as GPIO pin function
GPIO_FUNC_UART = 2, ///< Select UART as GPIO pin function
GPIO_FUNC_I2C = 3, ///< Select I2C as GPIO pin function
GPIO_FUNC_PWM = 4, ///< Select PWM as GPIO pin function
GPIO_FUNC_SIO = 5, ///< Select SIO as GPIO pin function
GPIO_FUNC_PIO0 = 6, ///< Select PIO0 as GPIO pin function
GPIO_FUNC_PIO1 = 7, ///< Select PIO1 as GPIO pin function
GPIO_FUNC_GPCK = 8, ///< Select GPCK as GPIO pin function
GPIO_FUNC_USB = 9, ///< Select USB as GPIO pin function
GPIO_FUNC_NULL = 0x1f, ///< Select NULL as GPIO pin function
} gpio_function_t;
typedef struct {
_REG_(IO_BANK0_GPIO0_STATUS_OFFSET) // IO_BANK0_GPIO0_STATUS
// GPIO status
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
io_ro_32 status;
_REG_(IO_BANK0_GPIO0_CTRL_OFFSET) // IO_BANK0_GPIO0_CTRL
// GPIO control including function select and overrides
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x00003000 [13:12] OEOVER (0x0)
// 0x00000300 [9:8] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_bank0_status_ctrl_hw_t;
typedef struct {
// (Description copied from array index 0 register IO_BANK0_PROC0_INTE0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTE0_OFFSET) // IO_BANK0_PROC0_INTE0
// Interrupt Enable for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 inte[4];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTF0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTF0_OFFSET) // IO_BANK0_PROC0_INTF0
// Interrupt Force for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intf[4];
// (Description copied from array index 0 register IO_BANK0_PROC0_INTS0 applies similarly to other array indexes)
_REG_(IO_BANK0_PROC0_INTS0_OFFSET) // IO_BANK0_PROC0_INTS0
// Interrupt status after masking & forcing for proc0
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_ro_32 ints[4];
} io_bank0_irq_ctrl_hw_t;
/// \tag::io_bank0_hw[]
typedef struct {
io_bank0_status_ctrl_hw_t io[30];
// (Description copied from array index 0 register IO_BANK0_INTR0 applies similarly to other array indexes)
_REG_(IO_BANK0_INTR0_OFFSET) // IO_BANK0_INTR0
// Raw Interrupts
// 0x80000000 [31] GPIO7_EDGE_HIGH (0)
// 0x40000000 [30] GPIO7_EDGE_LOW (0)
// 0x20000000 [29] GPIO7_LEVEL_HIGH (0)
// 0x10000000 [28] GPIO7_LEVEL_LOW (0)
// 0x08000000 [27] GPIO6_EDGE_HIGH (0)
// 0x04000000 [26] GPIO6_EDGE_LOW (0)
// 0x02000000 [25] GPIO6_LEVEL_HIGH (0)
// 0x01000000 [24] GPIO6_LEVEL_LOW (0)
// 0x00800000 [23] GPIO5_EDGE_HIGH (0)
// 0x00400000 [22] GPIO5_EDGE_LOW (0)
// 0x00200000 [21] GPIO5_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO5_LEVEL_LOW (0)
// 0x00080000 [19] GPIO4_EDGE_HIGH (0)
// 0x00040000 [18] GPIO4_EDGE_LOW (0)
// 0x00020000 [17] GPIO4_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO4_LEVEL_LOW (0)
// 0x00008000 [15] GPIO3_EDGE_HIGH (0)
// 0x00004000 [14] GPIO3_EDGE_LOW (0)
// 0x00002000 [13] GPIO3_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO3_LEVEL_LOW (0)
// 0x00000800 [11] GPIO2_EDGE_HIGH (0)
// 0x00000400 [10] GPIO2_EDGE_LOW (0)
// 0x00000200 [9] GPIO2_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO2_LEVEL_LOW (0)
// 0x00000080 [7] GPIO1_EDGE_HIGH (0)
// 0x00000040 [6] GPIO1_EDGE_LOW (0)
// 0x00000020 [5] GPIO1_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO1_LEVEL_LOW (0)
// 0x00000008 [3] GPIO0_EDGE_HIGH (0)
// 0x00000004 [2] GPIO0_EDGE_LOW (0)
// 0x00000002 [1] GPIO0_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO0_LEVEL_LOW (0)
io_rw_32 intr[4];
union {
struct {
io_bank0_irq_ctrl_hw_t proc0_irq_ctrl;
io_bank0_irq_ctrl_hw_t proc1_irq_ctrl;
io_bank0_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_bank0_irq_ctrl_hw_t irq_ctrl[3];
};
} io_bank0_hw_t;
/// \end::io_bank0_hw[]
#define io_bank0_hw ((io_bank0_hw_t *)IO_BANK0_BASE)
static_assert(sizeof (io_bank0_hw_t) == 0x0190, "");
#endif // _HARDWARE_STRUCTS_IO_BANK0_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_IO_QSPI_H
#define _HARDWARE_STRUCTS_IO_QSPI_H
/**
* \file rp2040/io_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/io_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_io_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/io_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/**
* \brief QSPI pin function selectors on RP2040 (used as typedef \ref gpio_function1_t)
*/
typedef enum gpio_function1_rp2040 {
GPIO_FUNC1_XIP = 0, ///< Select XIP as QSPI pin function
GPIO_FUNC1_SIO = 5, ///< Select SIO as QSPI pin function
GPIO_FUNC1_NULL = 0x1f, ///< Select NULL as QSPI pin function
} gpio_function1_t;
typedef struct {
_REG_(IO_QSPI_GPIO_QSPI_SCLK_STATUS_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_STATUS
// GPIO status
// 0x04000000 [26] IRQTOPROC (0) interrupt to processors, after override is applied
// 0x01000000 [24] IRQFROMPAD (0) interrupt from pad before override is applied
// 0x00080000 [19] INTOPERI (0) input signal to peripheral, after override is applied
// 0x00020000 [17] INFROMPAD (0) input signal from pad, before override is applied
// 0x00002000 [13] OETOPAD (0) output enable to pad after register override is applied
// 0x00001000 [12] OEFROMPERI (0) output enable from selected peripheral, before register...
// 0x00000200 [9] OUTTOPAD (0) output signal to pad after register override is applied
// 0x00000100 [8] OUTFROMPERI (0) output signal from selected peripheral, before register...
io_ro_32 status;
_REG_(IO_QSPI_GPIO_QSPI_SCLK_CTRL_OFFSET) // IO_QSPI_GPIO_QSPI_SCLK_CTRL
// GPIO control including function select and overrides
// 0x30000000 [29:28] IRQOVER (0x0)
// 0x00030000 [17:16] INOVER (0x0)
// 0x00003000 [13:12] OEOVER (0x0)
// 0x00000300 [9:8] OUTOVER (0x0)
// 0x0000001f [4:0] FUNCSEL (0x1f) 0-31 -> selects pin function according to the gpio table +
io_rw_32 ctrl;
} io_qspi_status_ctrl_hw_t;
typedef struct {
_REG_(IO_QSPI_PROC0_INTE_OFFSET) // IO_QSPI_PROC0_INTE
// Interrupt Enable for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 inte;
_REG_(IO_QSPI_PROC0_INTF_OFFSET) // IO_QSPI_PROC0_INTF
// Interrupt Force for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 intf;
_REG_(IO_QSPI_PROC0_INTS_OFFSET) // IO_QSPI_PROC0_INTS
// Interrupt status after masking & forcing for proc0
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_ro_32 ints;
} io_qspi_irq_ctrl_hw_t;
typedef struct {
io_qspi_status_ctrl_hw_t io[6];
_REG_(IO_QSPI_INTR_OFFSET) // IO_QSPI_INTR
// Raw Interrupts
// 0x00800000 [23] GPIO_QSPI_SD3_EDGE_HIGH (0)
// 0x00400000 [22] GPIO_QSPI_SD3_EDGE_LOW (0)
// 0x00200000 [21] GPIO_QSPI_SD3_LEVEL_HIGH (0)
// 0x00100000 [20] GPIO_QSPI_SD3_LEVEL_LOW (0)
// 0x00080000 [19] GPIO_QSPI_SD2_EDGE_HIGH (0)
// 0x00040000 [18] GPIO_QSPI_SD2_EDGE_LOW (0)
// 0x00020000 [17] GPIO_QSPI_SD2_LEVEL_HIGH (0)
// 0x00010000 [16] GPIO_QSPI_SD2_LEVEL_LOW (0)
// 0x00008000 [15] GPIO_QSPI_SD1_EDGE_HIGH (0)
// 0x00004000 [14] GPIO_QSPI_SD1_EDGE_LOW (0)
// 0x00002000 [13] GPIO_QSPI_SD1_LEVEL_HIGH (0)
// 0x00001000 [12] GPIO_QSPI_SD1_LEVEL_LOW (0)
// 0x00000800 [11] GPIO_QSPI_SD0_EDGE_HIGH (0)
// 0x00000400 [10] GPIO_QSPI_SD0_EDGE_LOW (0)
// 0x00000200 [9] GPIO_QSPI_SD0_LEVEL_HIGH (0)
// 0x00000100 [8] GPIO_QSPI_SD0_LEVEL_LOW (0)
// 0x00000080 [7] GPIO_QSPI_SS_EDGE_HIGH (0)
// 0x00000040 [6] GPIO_QSPI_SS_EDGE_LOW (0)
// 0x00000020 [5] GPIO_QSPI_SS_LEVEL_HIGH (0)
// 0x00000010 [4] GPIO_QSPI_SS_LEVEL_LOW (0)
// 0x00000008 [3] GPIO_QSPI_SCLK_EDGE_HIGH (0)
// 0x00000004 [2] GPIO_QSPI_SCLK_EDGE_LOW (0)
// 0x00000002 [1] GPIO_QSPI_SCLK_LEVEL_HIGH (0)
// 0x00000001 [0] GPIO_QSPI_SCLK_LEVEL_LOW (0)
io_rw_32 intr;
union {
struct {
io_qspi_irq_ctrl_hw_t proc0_irq_ctrl;
io_qspi_irq_ctrl_hw_t proc1_irq_ctrl;
io_qspi_irq_ctrl_hw_t dormant_wake_irq_ctrl;
};
io_qspi_irq_ctrl_hw_t irq_ctrl[3];
};
} io_qspi_hw_t;
#define io_qspi_hw ((io_qspi_hw_t *)IO_QSPI_BASE)
static_assert(sizeof (io_qspi_hw_t) == 0x0058, "");
#endif // _HARDWARE_STRUCTS_IO_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_bank0.h"
#define iobank0_hw io_bank0_hw

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/io_qspi.h"
#define ioqspi_hw io_qspi_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_M0PLUS_H
#define _HARDWARE_STRUCTS_M0PLUS_H
/**
* \file rp2040/m0plus.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
uint32_t _pad0[14340];
_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
// SysTick Control and Status Register
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
io_rw_32 syst_csr;
_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
// SysTick Reload Value Register
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
io_rw_32 syst_rvr;
_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
// SysTick Current Value Register
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
io_rw_32 syst_cvr;
_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
// SysTick Calibration Value Register
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
io_ro_32 syst_calib;
uint32_t _pad1[56];
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
// Interrupt Set-Enable Register
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
io_rw_32 nvic_iser;
uint32_t _pad2[31];
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
// Interrupt Clear-Enable Register
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
io_rw_32 nvic_icer;
uint32_t _pad3[31];
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
// Interrupt Set-Pending Register
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
io_rw_32 nvic_ispr;
uint32_t _pad4[31];
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
// Interrupt Clear-Pending Register
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
io_rw_32 nvic_icpr;
uint32_t _pad5[95];
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
// Interrupt Priority Register 0
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
io_rw_32 nvic_ipr[8];
uint32_t _pad6[568];
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
// CPUID Base Register
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
io_ro_32 cpuid;
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
// Interrupt Control and State Register
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
io_rw_32 icsr;
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
// Vector Table Offset Register
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
io_rw_32 vtor;
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
// Application Interrupt and Reset Control Register
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
io_rw_32 aircr;
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
// System Control Register
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
io_rw_32 scr;
_REG_(M0PLUS_CCR_OFFSET) // M0PLUS_CCR
// Configuration and Control Register
// 0x00000200 [9] STKALIGN (0) Always reads as one, indicates 8-byte stack alignment on...
// 0x00000008 [3] UNALIGN_TRP (0) Always reads as one, indicates that all unaligned...
io_ro_32 ccr;
uint32_t _pad7;
// (Description copied from array index 0 register M0PLUS_SHPR2 applies similarly to other array indexes)
_REG_(M0PLUS_SHPR2_OFFSET) // M0PLUS_SHPR2
// System Handler Priority Register 2
// 0xc0000000 [31:30] PRI_11 (0x0) Priority of system handler 11, SVCall
io_rw_32 shpr[2];
_REG_(M0PLUS_SHCSR_OFFSET) // M0PLUS_SHCSR
// System Handler Control and State Register
// 0x00008000 [15] SVCALLPENDED (0) Reads as 1 if SVCall is Pending
io_rw_32 shcsr;
uint32_t _pad8[26];
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
// MPU Type Register
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
io_ro_32 mpu_type;
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
// MPU Control Register
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
// 0x00000001 [0] ENABLE (0) Enables the MPU
io_rw_32 mpu_ctrl;
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
// MPU Region Number Register
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
io_rw_32 mpu_rnr;
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
// MPU Region Base Address Register
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
io_rw_32 mpu_rbar;
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
// MPU Region Attribute and Size Register
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
// 0x00000001 [0] ENABLE (0) Enables the region
io_rw_32 mpu_rasr;
} m0plus_hw_t;
#define ppb_hw ((m0plus_hw_t *)PPB_BASE)
static_assert(sizeof (m0plus_hw_t) == 0xeda4, "");
#endif // _HARDWARE_STRUCTS_M0PLUS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_MPU_H
#define _HARDWARE_STRUCTS_MPU_H
/**
* \file rp2040/mpu.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_MPU_TYPE_OFFSET) // M0PLUS_MPU_TYPE
// MPU Type Register
// 0x00ff0000 [23:16] IREGION (0x00) Instruction region
// 0x0000ff00 [15:8] DREGION (0x08) Number of regions supported by the MPU
// 0x00000001 [0] SEPARATE (0) Indicates support for separate instruction and data address maps
io_ro_32 type;
_REG_(M0PLUS_MPU_CTRL_OFFSET) // M0PLUS_MPU_CTRL
// MPU Control Register
// 0x00000004 [2] PRIVDEFENA (0) Controls whether the default memory map is enabled as a...
// 0x00000002 [1] HFNMIENA (0) Controls the use of the MPU for HardFaults and NMIs
// 0x00000001 [0] ENABLE (0) Enables the MPU
io_rw_32 ctrl;
_REG_(M0PLUS_MPU_RNR_OFFSET) // M0PLUS_MPU_RNR
// MPU Region Number Register
// 0x0000000f [3:0] REGION (0x0) Indicates the MPU region referenced by the MPU_RBAR and...
io_rw_32 rnr;
_REG_(M0PLUS_MPU_RBAR_OFFSET) // M0PLUS_MPU_RBAR
// MPU Region Base Address Register
// 0xffffff00 [31:8] ADDR (0x000000) Base address of the region
// 0x00000010 [4] VALID (0) On writes, indicates whether the write must update the...
// 0x0000000f [3:0] REGION (0x0) On writes, specifies the number of the region whose base...
io_rw_32 rbar;
_REG_(M0PLUS_MPU_RASR_OFFSET) // M0PLUS_MPU_RASR
// MPU Region Attribute and Size Register
// 0xffff0000 [31:16] ATTRS (0x0000) The MPU Region Attribute field
// 0x0000ff00 [15:8] SRD (0x00) Subregion Disable
// 0x0000003e [5:1] SIZE (0x00) Indicates the region size
// 0x00000001 [0] ENABLE (0) Enables the region
io_rw_32 rasr;
} mpu_hw_t;
#define mpu_hw ((mpu_hw_t *)(PPB_BASE + M0PLUS_MPU_TYPE_OFFSET))
static_assert(sizeof (mpu_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_MPU_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_NVIC_H
#define _HARDWARE_STRUCTS_NVIC_H
/**
* \file rp2040/nvic.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_NVIC_ISER_OFFSET) // M0PLUS_NVIC_ISER
// Interrupt Set-Enable Register
// 0xffffffff [31:0] SETENA (0x00000000) Interrupt set-enable bits
io_rw_32 iser;
uint32_t _pad0[31];
_REG_(M0PLUS_NVIC_ICER_OFFSET) // M0PLUS_NVIC_ICER
// Interrupt Clear-Enable Register
// 0xffffffff [31:0] CLRENA (0x00000000) Interrupt clear-enable bits
io_rw_32 icer;
uint32_t _pad1[31];
_REG_(M0PLUS_NVIC_ISPR_OFFSET) // M0PLUS_NVIC_ISPR
// Interrupt Set-Pending Register
// 0xffffffff [31:0] SETPEND (0x00000000) Interrupt set-pending bits
io_rw_32 ispr;
uint32_t _pad2[31];
_REG_(M0PLUS_NVIC_ICPR_OFFSET) // M0PLUS_NVIC_ICPR
// Interrupt Clear-Pending Register
// 0xffffffff [31:0] CLRPEND (0x00000000) Interrupt clear-pending bits
io_rw_32 icpr;
uint32_t _pad3[95];
// (Description copied from array index 0 register M0PLUS_NVIC_IPR0 applies similarly to other array indexes)
_REG_(M0PLUS_NVIC_IPR0_OFFSET) // M0PLUS_NVIC_IPR0
// Interrupt Priority Register 0
// 0xc0000000 [31:30] IP_3 (0x0) Priority of interrupt 3
// 0x00c00000 [23:22] IP_2 (0x0) Priority of interrupt 2
// 0x0000c000 [15:14] IP_1 (0x0) Priority of interrupt 1
// 0x000000c0 [7:6] IP_0 (0x0) Priority of interrupt 0
io_rw_32 ipr[8];
} nvic_hw_t;
#define nvic_hw ((nvic_hw_t *)(PPB_BASE + M0PLUS_NVIC_ISER_OFFSET))
static_assert(sizeof (nvic_hw_t) == 0x0320, "");
#endif // _HARDWARE_STRUCTS_NVIC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_BANK0_H
#define _HARDWARE_STRUCTS_PADS_BANK0_H
/**
* \file rp2040/pads_bank0.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_bank0.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_bank0
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_bank0.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_BANK0_VOLTAGE_SELECT_OFFSET) // PADS_BANK0_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_BANK0_GPIO0 applies similarly to other array indexes)
_REG_(PADS_BANK0_GPIO0_OFFSET) // PADS_BANK0_GPIO0
// Pad control register
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (1) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[30];
} pads_bank0_hw_t;
#define pads_bank0_hw ((pads_bank0_hw_t *)PADS_BANK0_BASE)
static_assert(sizeof (pads_bank0_hw_t) == 0x007c, "");
#endif // _HARDWARE_STRUCTS_PADS_BANK0_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PADS_QSPI_H
#define _HARDWARE_STRUCTS_PADS_QSPI_H
/**
* \file rp2040/pads_qspi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pads_qspi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pads_qspi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pads_qspi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PADS_QSPI_VOLTAGE_SELECT_OFFSET) // PADS_QSPI_VOLTAGE_SELECT
// Voltage select
// 0x00000001 [0] VOLTAGE_SELECT (0)
io_rw_32 voltage_select;
// (Description copied from array index 0 register PADS_QSPI_GPIO_QSPI_SCLK applies similarly to other array indexes)
_REG_(PADS_QSPI_GPIO_QSPI_SCLK_OFFSET) // PADS_QSPI_GPIO_QSPI_SCLK
// Pad control register
// 0x00000080 [7] OD (0) Output disable
// 0x00000040 [6] IE (1) Input enable
// 0x00000030 [5:4] DRIVE (0x1) Drive strength
// 0x00000008 [3] PUE (0) Pull up enable
// 0x00000004 [2] PDE (1) Pull down enable
// 0x00000002 [1] SCHMITT (1) Enable schmitt trigger
// 0x00000001 [0] SLEWFAST (0) Slew rate control
io_rw_32 io[6];
} pads_qspi_hw_t;
#define pads_qspi_hw ((pads_qspi_hw_t *)PADS_QSPI_BASE)
static_assert(sizeof (pads_qspi_hw_t) == 0x001c, "");
#endif // _HARDWARE_STRUCTS_PADS_QSPI_H

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/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/pads_bank0.h"
#define padsbank0_hw pads_bank0_hw

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PIO_H
#define _HARDWARE_STRUCTS_PIO_H
/**
* \file rp2040/pio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pio.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PIO_SM0_CLKDIV_OFFSET) // PIO_SM0_CLKDIV
// Clock divisor register for state machine 0 +
// 0xffff0000 [31:16] INT (0x0001) Effective frequency is sysclk/(int + frac/256)
// 0x0000ff00 [15:8] FRAC (0x00) Fractional part of clock divisor
io_rw_32 clkdiv;
_REG_(PIO_SM0_EXECCTRL_OFFSET) // PIO_SM0_EXECCTRL
// Execution/behavioural settings for state machine 0
// 0x80000000 [31] EXEC_STALLED (0) If 1, an instruction written to SMx_INSTR is stalled,...
// 0x40000000 [30] SIDE_EN (0) If 1, the MSB of the Delay/Side-set instruction field is...
// 0x20000000 [29] SIDE_PINDIR (0) If 1, side-set data is asserted to pin directions,...
// 0x1f000000 [28:24] JMP_PIN (0x00) The GPIO number to use as condition for JMP PIN
// 0x00f80000 [23:19] OUT_EN_SEL (0x00) Which data bit to use for inline OUT enable
// 0x00040000 [18] INLINE_OUT_EN (0) If 1, use a bit of OUT data as an auxiliary write enable +
// 0x00020000 [17] OUT_STICKY (0) Continuously assert the most recent OUT/SET to the pins
// 0x0001f000 [16:12] WRAP_TOP (0x1f) After reaching this address, execution is wrapped to wrap_bottom
// 0x00000f80 [11:7] WRAP_BOTTOM (0x00) After reaching wrap_top, execution is wrapped to this address
// 0x00000010 [4] STATUS_SEL (0) Comparison used for the MOV x, STATUS instruction
// 0x0000000f [3:0] STATUS_N (0x0) Comparison level for the MOV x, STATUS instruction
io_rw_32 execctrl;
_REG_(PIO_SM0_SHIFTCTRL_OFFSET) // PIO_SM0_SHIFTCTRL
// Control behaviour of the input/output shift registers for state machine 0
// 0x80000000 [31] FJOIN_RX (0) When 1, RX FIFO steals the TX FIFO's storage, and...
// 0x40000000 [30] FJOIN_TX (0) When 1, TX FIFO steals the RX FIFO's storage, and...
// 0x3e000000 [29:25] PULL_THRESH (0x00) Number of bits shifted out of OSR before autopull, or...
// 0x01f00000 [24:20] PUSH_THRESH (0x00) Number of bits shifted into ISR before autopush, or...
// 0x00080000 [19] OUT_SHIFTDIR (1) 1 = shift out of output shift register to right
// 0x00040000 [18] IN_SHIFTDIR (1) 1 = shift input shift register to right (data enters from left)
// 0x00020000 [17] AUTOPULL (0) Pull automatically when the output shift register is emptied, i
// 0x00010000 [16] AUTOPUSH (0) Push automatically when the input shift register is filled, i
io_rw_32 shiftctrl;
_REG_(PIO_SM0_ADDR_OFFSET) // PIO_SM0_ADDR
// Current instruction address of state machine 0
// 0x0000001f [4:0] SM0_ADDR (0x00)
io_ro_32 addr;
_REG_(PIO_SM0_INSTR_OFFSET) // PIO_SM0_INSTR
// Read to see the instruction currently addressed by state machine 0's program counter +
// 0x0000ffff [15:0] SM0_INSTR (-)
io_rw_32 instr;
_REG_(PIO_SM0_PINCTRL_OFFSET) // PIO_SM0_PINCTRL
// State machine pin control
// 0xe0000000 [31:29] SIDESET_COUNT (0x0) The number of MSBs of the Delay/Side-set instruction...
// 0x1c000000 [28:26] SET_COUNT (0x5) The number of pins asserted by a SET
// 0x03f00000 [25:20] OUT_COUNT (0x00) The number of pins asserted by an OUT PINS, OUT PINDIRS...
// 0x000f8000 [19:15] IN_BASE (0x00) The pin which is mapped to the least-significant bit of...
// 0x00007c00 [14:10] SIDESET_BASE (0x00) The lowest-numbered pin that will be affected by a...
// 0x000003e0 [9:5] SET_BASE (0x00) The lowest-numbered pin that will be affected by a SET...
// 0x0000001f [4:0] OUT_BASE (0x00) The lowest-numbered pin that will be affected by an OUT...
io_rw_32 pinctrl;
} pio_sm_hw_t;
typedef struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints;
} pio_irq_ctrl_hw_t;
typedef struct {
_REG_(PIO_CTRL_OFFSET) // PIO_CTRL
// PIO control register
// 0x00000f00 [11:8] CLKDIV_RESTART (0x0) Restart a state machine's clock divider from an initial...
// 0x000000f0 [7:4] SM_RESTART (0x0) Write 1 to instantly clear internal SM state which may...
// 0x0000000f [3:0] SM_ENABLE (0x0) Enable/disable each of the four state machines by...
io_rw_32 ctrl;
_REG_(PIO_FSTAT_OFFSET) // PIO_FSTAT
// FIFO status register
// 0x0f000000 [27:24] TXEMPTY (0xf) State machine TX FIFO is empty
// 0x000f0000 [19:16] TXFULL (0x0) State machine TX FIFO is full
// 0x00000f00 [11:8] RXEMPTY (0xf) State machine RX FIFO is empty
// 0x0000000f [3:0] RXFULL (0x0) State machine RX FIFO is full
io_ro_32 fstat;
_REG_(PIO_FDEBUG_OFFSET) // PIO_FDEBUG
// FIFO debug register
// 0x0f000000 [27:24] TXSTALL (0x0) State machine has stalled on empty TX FIFO during a...
// 0x000f0000 [19:16] TXOVER (0x0) TX FIFO overflow (i
// 0x00000f00 [11:8] RXUNDER (0x0) RX FIFO underflow (i
// 0x0000000f [3:0] RXSTALL (0x0) State machine has stalled on full RX FIFO during a...
io_rw_32 fdebug;
_REG_(PIO_FLEVEL_OFFSET) // PIO_FLEVEL
// FIFO levels
// 0xf0000000 [31:28] RX3 (0x0)
// 0x0f000000 [27:24] TX3 (0x0)
// 0x00f00000 [23:20] RX2 (0x0)
// 0x000f0000 [19:16] TX2 (0x0)
// 0x0000f000 [15:12] RX1 (0x0)
// 0x00000f00 [11:8] TX1 (0x0)
// 0x000000f0 [7:4] RX0 (0x0)
// 0x0000000f [3:0] TX0 (0x0)
io_ro_32 flevel;
// (Description copied from array index 0 register PIO_TXF0 applies similarly to other array indexes)
_REG_(PIO_TXF0_OFFSET) // PIO_TXF0
// Direct write access to the TX FIFO for this state machine
// 0xffffffff [31:0] TXF0 (0x00000000)
io_wo_32 txf[4];
// (Description copied from array index 0 register PIO_RXF0 applies similarly to other array indexes)
_REG_(PIO_RXF0_OFFSET) // PIO_RXF0
// Direct read access to the RX FIFO for this state machine
// 0xffffffff [31:0] RXF0 (-)
io_ro_32 rxf[4];
_REG_(PIO_IRQ_OFFSET) // PIO_IRQ
// State machine IRQ flags register
// 0x000000ff [7:0] IRQ (0x00)
io_rw_32 irq;
_REG_(PIO_IRQ_FORCE_OFFSET) // PIO_IRQ_FORCE
// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ
// 0x000000ff [7:0] IRQ_FORCE (0x00)
io_wo_32 irq_force;
_REG_(PIO_INPUT_SYNC_BYPASS_OFFSET) // PIO_INPUT_SYNC_BYPASS
// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities
// 0xffffffff [31:0] INPUT_SYNC_BYPASS (0x00000000)
io_rw_32 input_sync_bypass;
_REG_(PIO_DBG_PADOUT_OFFSET) // PIO_DBG_PADOUT
// Read to sample the pad output values PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOUT (0x00000000)
io_ro_32 dbg_padout;
_REG_(PIO_DBG_PADOE_OFFSET) // PIO_DBG_PADOE
// Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs
// 0xffffffff [31:0] DBG_PADOE (0x00000000)
io_ro_32 dbg_padoe;
_REG_(PIO_DBG_CFGINFO_OFFSET) // PIO_DBG_CFGINFO
// The PIO hardware has some free parameters that may vary between chip products
// 0x003f0000 [21:16] IMEM_SIZE (-) The size of the instruction memory, measured in units of...
// 0x00000f00 [11:8] SM_COUNT (-) The number of state machines this PIO instance is equipped with
// 0x0000003f [5:0] FIFO_DEPTH (-) The depth of the state machine TX/RX FIFOs, measured in words
io_ro_32 dbg_cfginfo;
// (Description copied from array index 0 register PIO_INSTR_MEM0 applies similarly to other array indexes)
_REG_(PIO_INSTR_MEM0_OFFSET) // PIO_INSTR_MEM0
// Write-only access to instruction memory location 0
// 0x0000ffff [15:0] INSTR_MEM0 (0x0000)
io_wo_32 instr_mem[32];
pio_sm_hw_t sm[4];
_REG_(PIO_INTR_OFFSET) // PIO_INTR
// Raw Interrupts
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 intr;
union {
struct {
_REG_(PIO_IRQ0_INTE_OFFSET) // PIO_IRQ0_INTE
// Interrupt Enable for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte0;
_REG_(PIO_IRQ0_INTF_OFFSET) // PIO_IRQ0_INTF
// Interrupt Force for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf0;
_REG_(PIO_IRQ0_INTS_OFFSET) // PIO_IRQ0_INTS
// Interrupt status after masking & forcing for irq0
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints0;
_REG_(PIO_IRQ1_INTE_OFFSET) // PIO_IRQ1_INTE
// Interrupt Enable for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 inte1;
_REG_(PIO_IRQ1_INTF_OFFSET) // PIO_IRQ1_INTF
// Interrupt Force for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_rw_32 intf1;
_REG_(PIO_IRQ1_INTS_OFFSET) // PIO_IRQ1_INTS
// Interrupt status after masking & forcing for irq1
// 0x00000800 [11] SM3 (0)
// 0x00000400 [10] SM2 (0)
// 0x00000200 [9] SM1 (0)
// 0x00000100 [8] SM0 (0)
// 0x00000080 [7] SM3_TXNFULL (0)
// 0x00000040 [6] SM2_TXNFULL (0)
// 0x00000020 [5] SM1_TXNFULL (0)
// 0x00000010 [4] SM0_TXNFULL (0)
// 0x00000008 [3] SM3_RXNEMPTY (0)
// 0x00000004 [2] SM2_RXNEMPTY (0)
// 0x00000002 [1] SM1_RXNEMPTY (0)
// 0x00000001 [0] SM0_RXNEMPTY (0)
io_ro_32 ints1;
};
pio_irq_ctrl_hw_t irq_ctrl[2];
};
} pio_hw_t;
#define pio0_hw ((pio_hw_t *)PIO0_BASE)
#define pio1_hw ((pio_hw_t *)PIO1_BASE)
static_assert(sizeof (pio_hw_t) == 0x0144, "");
#endif // _HARDWARE_STRUCTS_PIO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PLL_H
#define _HARDWARE_STRUCTS_PLL_H
/**
* \file rp2040/pll.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pll.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pll
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pll.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/// \tag::pll_hw[]
typedef struct {
_REG_(PLL_CS_OFFSET) // PLL_CS
// Control and Status
// 0x80000000 [31] LOCK (0) PLL is locked
// 0x00000100 [8] BYPASS (0) Passes the reference clock to the output instead of the...
// 0x0000003f [5:0] REFDIV (0x01) Divides the PLL input reference clock
io_rw_32 cs;
_REG_(PLL_PWR_OFFSET) // PLL_PWR
// Controls the PLL power modes
// 0x00000020 [5] VCOPD (1) PLL VCO powerdown +
// 0x00000008 [3] POSTDIVPD (1) PLL post divider powerdown +
// 0x00000004 [2] DSMPD (1) PLL DSM powerdown +
// 0x00000001 [0] PD (1) PLL powerdown +
io_rw_32 pwr;
_REG_(PLL_FBDIV_INT_OFFSET) // PLL_FBDIV_INT
// Feedback divisor
// 0x00000fff [11:0] FBDIV_INT (0x000) see ctrl reg description for constraints
io_rw_32 fbdiv_int;
_REG_(PLL_PRIM_OFFSET) // PLL_PRIM
// Controls the PLL post dividers for the primary output
// 0x00070000 [18:16] POSTDIV1 (0x7) divide by 1-7
// 0x00007000 [14:12] POSTDIV2 (0x7) divide by 1-7
io_rw_32 prim;
} pll_hw_t;
/// \end::pll_hw[]
#define pll_sys_hw ((pll_hw_t *)PLL_SYS_BASE)
#define pll_usb_hw ((pll_hw_t *)PLL_USB_BASE)
static_assert(sizeof (pll_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_PLL_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PSM_H
#define _HARDWARE_STRUCTS_PSM_H
/**
* \file rp2040/psm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/psm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_psm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/psm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PSM_FRCE_ON_OFFSET) // PSM_FRCE_ON
// Force block out of reset (i
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 frce_on;
_REG_(PSM_FRCE_OFF_OFFSET) // PSM_FRCE_OFF
// Force into reset (i
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 frce_off;
_REG_(PSM_WDSEL_OFFSET) // PSM_WDSEL
// Set to 1 if this peripheral should be reset when the watchdog fires
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_rw_32 wdsel;
_REG_(PSM_DONE_OFFSET) // PSM_DONE
// Indicates the peripheral's registers are ready to access
// 0x00010000 [16] PROC1 (0)
// 0x00008000 [15] PROC0 (0)
// 0x00004000 [14] SIO (0)
// 0x00002000 [13] VREG_AND_CHIP_RESET (0)
// 0x00001000 [12] XIP (0)
// 0x00000800 [11] SRAM5 (0)
// 0x00000400 [10] SRAM4 (0)
// 0x00000200 [9] SRAM3 (0)
// 0x00000100 [8] SRAM2 (0)
// 0x00000080 [7] SRAM1 (0)
// 0x00000040 [6] SRAM0 (0)
// 0x00000020 [5] ROM (0)
// 0x00000010 [4] BUSFABRIC (0)
// 0x00000008 [3] RESETS (0)
// 0x00000004 [2] CLOCKS (0)
// 0x00000002 [1] XOSC (0)
// 0x00000001 [0] ROSC (0)
io_ro_32 done;
} psm_hw_t;
#define psm_hw ((psm_hw_t *)PSM_BASE)
static_assert(sizeof (psm_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_PSM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_PWM_H
#define _HARDWARE_STRUCTS_PWM_H
/**
* \file rp2040/pwm.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/pwm.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_pwm
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/pwm.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(PWM_CH0_CSR_OFFSET) // PWM_CH0_CSR
// Control and status register
// 0x00000080 [7] PH_ADV (0) Advance the phase of the counter by 1 count, while it is running
// 0x00000040 [6] PH_RET (0) Retard the phase of the counter by 1 count, while it is running
// 0x00000030 [5:4] DIVMODE (0x0)
// 0x00000008 [3] B_INV (0) Invert output B
// 0x00000004 [2] A_INV (0) Invert output A
// 0x00000002 [1] PH_CORRECT (0) 1: Enable phase-correct modulation
// 0x00000001 [0] EN (0) Enable the PWM channel
io_rw_32 csr;
_REG_(PWM_CH0_DIV_OFFSET) // PWM_CH0_DIV
// INT and FRAC form a fixed-point fractional number
// 0x00000ff0 [11:4] INT (0x01)
// 0x0000000f [3:0] FRAC (0x0)
io_rw_32 div;
_REG_(PWM_CH0_CTR_OFFSET) // PWM_CH0_CTR
// Direct access to the PWM counter
// 0x0000ffff [15:0] CH0_CTR (0x0000)
io_rw_32 ctr;
_REG_(PWM_CH0_CC_OFFSET) // PWM_CH0_CC
// Counter compare values
// 0xffff0000 [31:16] B (0x0000)
// 0x0000ffff [15:0] A (0x0000)
io_rw_32 cc;
_REG_(PWM_CH0_TOP_OFFSET) // PWM_CH0_TOP
// Counter wrap value
// 0x0000ffff [15:0] CH0_TOP (0xffff)
io_rw_32 top;
} pwm_slice_hw_t;
typedef struct {
_REG_(PWM_INTE_OFFSET) // PWM_INTE
// Interrupt Enable
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_INTF_OFFSET) // PWM_INTF
// Interrupt Force
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_INTS_OFFSET) // PWM_INTS
// Interrupt status after masking & forcing
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_ro_32 ints;
} pwm_irq_ctrl_hw_t;
typedef struct {
pwm_slice_hw_t slice[8];
_REG_(PWM_EN_OFFSET) // PWM_EN
// This register aliases the CSR_EN bits for all channels
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 en;
_REG_(PWM_INTR_OFFSET) // PWM_INTR
// Raw Interrupts
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intr;
union {
struct {
_REG_(PWM_INTE_OFFSET) // PWM_INTE
// Interrupt Enable
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 inte;
_REG_(PWM_INTF_OFFSET) // PWM_INTF
// Interrupt Force
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 intf;
_REG_(PWM_INTS_OFFSET) // PWM_INTS
// Interrupt status after masking & forcing
// 0x00000080 [7] CH7 (0)
// 0x00000040 [6] CH6 (0)
// 0x00000020 [5] CH5 (0)
// 0x00000010 [4] CH4 (0)
// 0x00000008 [3] CH3 (0)
// 0x00000004 [2] CH2 (0)
// 0x00000002 [1] CH1 (0)
// 0x00000001 [0] CH0 (0)
io_rw_32 ints;
};
pwm_irq_ctrl_hw_t irq_ctrl[1];
};
} pwm_hw_t;
#define pwm_hw ((pwm_hw_t *)PWM_BASE)
static_assert(sizeof (pwm_hw_t) == 0x00b4, "");
#endif // _HARDWARE_STRUCTS_PWM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RESETS_H
#define _HARDWARE_STRUCTS_RESETS_H
/**
* \file rp2040/resets.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/resets.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_resets
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/resets.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/** \brief Resettable component numbers on RP2040 (used as typedef \ref reset_num_t)
* \ingroup hardware_resets
*/
typedef enum reset_num_rp2040 {
RESET_ADC = 0, ///< Select ADC to be reset
RESET_BUSCTRL = 1, ///< Select BUSCTRL to be reset
RESET_DMA = 2, ///< Select DMA to be reset
RESET_I2C0 = 3, ///< Select I2C0 to be reset
RESET_I2C1 = 4, ///< Select I2C1 to be reset
RESET_IO_BANK0 = 5, ///< Select IO_BANK0 to be reset
RESET_IO_QSPI = 6, ///< Select IO_QSPI to be reset
RESET_JTAG = 7, ///< Select JTAG to be reset
RESET_PADS_BANK0 = 8, ///< Select PADS_BANK0 to be reset
RESET_PADS_QSPI = 9, ///< Select PADS_QSPI to be reset
RESET_PIO0 = 10, ///< Select PIO0 to be reset
RESET_PIO1 = 11, ///< Select PIO1 to be reset
RESET_PLL_SYS = 12, ///< Select PLL_SYS to be reset
RESET_PLL_USB = 13, ///< Select PLL_USB to be reset
RESET_PWM = 14, ///< Select PWM to be reset
RESET_RTC = 15, ///< Select RTC to be reset
RESET_SPI0 = 16, ///< Select SPI0 to be reset
RESET_SPI1 = 17, ///< Select SPI1 to be reset
RESET_SYSCFG = 18, ///< Select SYSCFG to be reset
RESET_SYSINFO = 19, ///< Select SYSINFO to be reset
RESET_TBMAN = 20, ///< Select TBMAN to be reset
RESET_TIMER = 21, ///< Select TIMER to be reset
RESET_UART0 = 22, ///< Select UART0 to be reset
RESET_UART1 = 23, ///< Select UART1 to be reset
RESET_USBCTRL = 24, ///< Select USBCTRL to be reset
RESET_COUNT
} reset_num_t;
/// \tag::resets_hw[]
typedef struct {
_REG_(RESETS_RESET_OFFSET) // RESETS_RESET
// Reset control.
// 0x01000000 [24] USBCTRL (1)
// 0x00800000 [23] UART1 (1)
// 0x00400000 [22] UART0 (1)
// 0x00200000 [21] TIMER (1)
// 0x00100000 [20] TBMAN (1)
// 0x00080000 [19] SYSINFO (1)
// 0x00040000 [18] SYSCFG (1)
// 0x00020000 [17] SPI1 (1)
// 0x00010000 [16] SPI0 (1)
// 0x00008000 [15] RTC (1)
// 0x00004000 [14] PWM (1)
// 0x00002000 [13] PLL_USB (1)
// 0x00001000 [12] PLL_SYS (1)
// 0x00000800 [11] PIO1 (1)
// 0x00000400 [10] PIO0 (1)
// 0x00000200 [9] PADS_QSPI (1)
// 0x00000100 [8] PADS_BANK0 (1)
// 0x00000080 [7] JTAG (1)
// 0x00000040 [6] IO_QSPI (1)
// 0x00000020 [5] IO_BANK0 (1)
// 0x00000010 [4] I2C1 (1)
// 0x00000008 [3] I2C0 (1)
// 0x00000004 [2] DMA (1)
// 0x00000002 [1] BUSCTRL (1)
// 0x00000001 [0] ADC (1)
io_rw_32 reset;
_REG_(RESETS_WDSEL_OFFSET) // RESETS_WDSEL
// Watchdog select.
// 0x01000000 [24] USBCTRL (0)
// 0x00800000 [23] UART1 (0)
// 0x00400000 [22] UART0 (0)
// 0x00200000 [21] TIMER (0)
// 0x00100000 [20] TBMAN (0)
// 0x00080000 [19] SYSINFO (0)
// 0x00040000 [18] SYSCFG (0)
// 0x00020000 [17] SPI1 (0)
// 0x00010000 [16] SPI0 (0)
// 0x00008000 [15] RTC (0)
// 0x00004000 [14] PWM (0)
// 0x00002000 [13] PLL_USB (0)
// 0x00001000 [12] PLL_SYS (0)
// 0x00000800 [11] PIO1 (0)
// 0x00000400 [10] PIO0 (0)
// 0x00000200 [9] PADS_QSPI (0)
// 0x00000100 [8] PADS_BANK0 (0)
// 0x00000080 [7] JTAG (0)
// 0x00000040 [6] IO_QSPI (0)
// 0x00000020 [5] IO_BANK0 (0)
// 0x00000010 [4] I2C1 (0)
// 0x00000008 [3] I2C0 (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_rw_32 wdsel;
_REG_(RESETS_RESET_DONE_OFFSET) // RESETS_RESET_DONE
// Reset done.
// 0x01000000 [24] USBCTRL (0)
// 0x00800000 [23] UART1 (0)
// 0x00400000 [22] UART0 (0)
// 0x00200000 [21] TIMER (0)
// 0x00100000 [20] TBMAN (0)
// 0x00080000 [19] SYSINFO (0)
// 0x00040000 [18] SYSCFG (0)
// 0x00020000 [17] SPI1 (0)
// 0x00010000 [16] SPI0 (0)
// 0x00008000 [15] RTC (0)
// 0x00004000 [14] PWM (0)
// 0x00002000 [13] PLL_USB (0)
// 0x00001000 [12] PLL_SYS (0)
// 0x00000800 [11] PIO1 (0)
// 0x00000400 [10] PIO0 (0)
// 0x00000200 [9] PADS_QSPI (0)
// 0x00000100 [8] PADS_BANK0 (0)
// 0x00000080 [7] JTAG (0)
// 0x00000040 [6] IO_QSPI (0)
// 0x00000020 [5] IO_BANK0 (0)
// 0x00000010 [4] I2C1 (0)
// 0x00000008 [3] I2C0 (0)
// 0x00000004 [2] DMA (0)
// 0x00000002 [1] BUSCTRL (0)
// 0x00000001 [0] ADC (0)
io_ro_32 reset_done;
} resets_hw_t;
/// \end::resets_hw[]
#define resets_hw ((resets_hw_t *)RESETS_BASE)
static_assert(sizeof (resets_hw_t) == 0x000c, "");
#endif // _HARDWARE_STRUCTS_RESETS_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_ROSC_H
#define _HARDWARE_STRUCTS_ROSC_H
/**
* \file rp2040/rosc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/rosc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rosc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/rosc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(ROSC_CTRL_OFFSET) // ROSC_CTRL
// Ring Oscillator control
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to ENABLE +
// 0x00000fff [11:0] FREQ_RANGE (0xaa0) Controls the number of delay stages in the ROSC ring +
io_rw_32 ctrl;
_REG_(ROSC_FREQA_OFFSET) // ROSC_FREQA
// Ring Oscillator frequency control A
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS3 (0x0) Stage 3 drive strength
// 0x00000700 [10:8] DS2 (0x0) Stage 2 drive strength
// 0x00000070 [6:4] DS1 (0x0) Stage 1 drive strength
// 0x00000007 [2:0] DS0 (0x0) Stage 0 drive strength
io_rw_32 freqa;
_REG_(ROSC_FREQB_OFFSET) // ROSC_FREQB
// Ring Oscillator frequency control B
// 0xffff0000 [31:16] PASSWD (0x0000) Set to 0x9696 to apply the settings +
// 0x00007000 [14:12] DS7 (0x0) Stage 7 drive strength
// 0x00000700 [10:8] DS6 (0x0) Stage 6 drive strength
// 0x00000070 [6:4] DS5 (0x0) Stage 5 drive strength
// 0x00000007 [2:0] DS4 (0x0) Stage 4 drive strength
io_rw_32 freqb;
_REG_(ROSC_DORMANT_OFFSET) // ROSC_DORMANT
// Ring Oscillator pause control
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the ROSC +
io_rw_32 dormant;
_REG_(ROSC_DIV_OFFSET) // ROSC_DIV
// Controls the output divider
// 0x00000fff [11:0] DIV (-) set to 0xaa0 + div where +
io_rw_32 div;
_REG_(ROSC_PHASE_OFFSET) // ROSC_PHASE
// Controls the phase shifted output
// 0x00000ff0 [11:4] PASSWD (0x00) set to 0xaa +
// 0x00000008 [3] ENABLE (1) enable the phase-shifted output +
// 0x00000004 [2] FLIP (0) invert the phase-shifted output +
// 0x00000003 [1:0] SHIFT (0x0) phase shift the phase-shifted output by SHIFT input clocks +
io_rw_32 phase;
_REG_(ROSC_STATUS_OFFSET) // ROSC_STATUS
// Ring Oscillator Status
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
// 0x00010000 [16] DIV_RUNNING (-) post-divider is running +
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and stable +
io_rw_32 status;
_REG_(ROSC_RANDOMBIT_OFFSET) // ROSC_RANDOMBIT
// Returns a 1 bit random value
// 0x00000001 [0] RANDOMBIT (1)
io_ro_32 randombit;
_REG_(ROSC_COUNT_OFFSET) // ROSC_COUNT
// A down counter running at the ROSC frequency which counts to zero and stops.
// 0x000000ff [7:0] COUNT (0x00)
io_rw_32 count;
} rosc_hw_t;
#define rosc_hw ((rosc_hw_t *)ROSC_BASE)
static_assert(sizeof (rosc_hw_t) == 0x0024, "");
#endif // _HARDWARE_STRUCTS_ROSC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_RTC_H
#define _HARDWARE_STRUCTS_RTC_H
/**
* \file rp2040/rtc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/rtc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_rtc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/rtc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(RTC_CLKDIV_M1_OFFSET) // RTC_CLKDIV_M1
// Divider minus 1 for the 1 second counter
// 0x0000ffff [15:0] CLKDIV_M1 (0x0000)
io_rw_32 clkdiv_m1;
_REG_(RTC_SETUP_0_OFFSET) // RTC_SETUP_0
// RTC setup register 0
// 0x00fff000 [23:12] YEAR (0x000) Year
// 0x00000f00 [11:8] MONTH (0x0) Month (1
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
io_rw_32 setup_0;
_REG_(RTC_SETUP_1_OFFSET) // RTC_SETUP_1
// RTC setup register 1
// 0x07000000 [26:24] DOTW (0x0) Day of the week: 1-Monday
// 0x001f0000 [20:16] HOUR (0x00) Hours
// 0x00003f00 [13:8] MIN (0x00) Minutes
// 0x0000003f [5:0] SEC (0x00) Seconds
io_rw_32 setup_1;
_REG_(RTC_CTRL_OFFSET) // RTC_CTRL
// RTC Control and status
// 0x00000100 [8] FORCE_NOTLEAPYEAR (0) If set, leapyear is forced off
// 0x00000010 [4] LOAD (0) Load RTC
// 0x00000002 [1] RTC_ACTIVE (-) RTC enabled (running)
// 0x00000001 [0] RTC_ENABLE (0) Enable RTC
io_rw_32 ctrl;
_REG_(RTC_IRQ_SETUP_0_OFFSET) // RTC_IRQ_SETUP_0
// Interrupt setup register 0
// 0x20000000 [29] MATCH_ACTIVE (-)
// 0x10000000 [28] MATCH_ENA (0) Global match enable
// 0x04000000 [26] YEAR_ENA (0) Enable year matching
// 0x02000000 [25] MONTH_ENA (0) Enable month matching
// 0x01000000 [24] DAY_ENA (0) Enable day matching
// 0x00fff000 [23:12] YEAR (0x000) Year
// 0x00000f00 [11:8] MONTH (0x0) Month (1
// 0x0000001f [4:0] DAY (0x00) Day of the month (1
io_rw_32 irq_setup_0;
_REG_(RTC_IRQ_SETUP_1_OFFSET) // RTC_IRQ_SETUP_1
// Interrupt setup register 1
// 0x80000000 [31] DOTW_ENA (0) Enable day of the week matching
// 0x40000000 [30] HOUR_ENA (0) Enable hour matching
// 0x20000000 [29] MIN_ENA (0) Enable minute matching
// 0x10000000 [28] SEC_ENA (0) Enable second matching
// 0x07000000 [26:24] DOTW (0x0) Day of the week
// 0x001f0000 [20:16] HOUR (0x00) Hours
// 0x00003f00 [13:8] MIN (0x00) Minutes
// 0x0000003f [5:0] SEC (0x00) Seconds
io_rw_32 irq_setup_1;
_REG_(RTC_RTC_1_OFFSET) // RTC_RTC_1
// RTC register 1
// 0x00fff000 [23:12] YEAR (-) Year
// 0x00000f00 [11:8] MONTH (-) Month (1
// 0x0000001f [4:0] DAY (-) Day of the month (1
io_ro_32 rtc_1;
_REG_(RTC_RTC_0_OFFSET) // RTC_RTC_0
// RTC register 0 +
// 0x07000000 [26:24] DOTW (-) Day of the week
// 0x001f0000 [20:16] HOUR (-) Hours
// 0x00003f00 [13:8] MIN (-) Minutes
// 0x0000003f [5:0] SEC (-) Seconds
io_ro_32 rtc_0;
_REG_(RTC_INTR_OFFSET) // RTC_INTR
// Raw Interrupts
// 0x00000001 [0] RTC (0)
io_ro_32 intr;
_REG_(RTC_INTE_OFFSET) // RTC_INTE
// Interrupt Enable
// 0x00000001 [0] RTC (0)
io_rw_32 inte;
_REG_(RTC_INTF_OFFSET) // RTC_INTF
// Interrupt Force
// 0x00000001 [0] RTC (0)
io_rw_32 intf;
_REG_(RTC_INTS_OFFSET) // RTC_INTS
// Interrupt status after masking & forcing
// 0x00000001 [0] RTC (0)
io_ro_32 ints;
} rtc_hw_t;
#define rtc_hw ((rtc_hw_t *)RTC_BASE)
static_assert(sizeof (rtc_hw_t) == 0x0030, "");
#endif // _HARDWARE_STRUCTS_RTC_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SCB_H
#define _HARDWARE_STRUCTS_SCB_H
/**
* \file rp2040/scb.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_CPUID_OFFSET) // M0PLUS_CPUID
// CPUID Base Register
// 0xff000000 [31:24] IMPLEMENTER (0x41) Implementor code: 0x41 = ARM
// 0x00f00000 [23:20] VARIANT (0x0) Major revision number n in the rnpm revision status: +
// 0x000f0000 [19:16] ARCHITECTURE (0xc) Constant that defines the architecture of the processor: +
// 0x0000fff0 [15:4] PARTNO (0xc60) Number of processor within family: 0xC60 = Cortex-M0+
// 0x0000000f [3:0] REVISION (0x1) Minor revision number m in the rnpm revision status: +
io_ro_32 cpuid;
_REG_(M0PLUS_ICSR_OFFSET) // M0PLUS_ICSR
// Interrupt Control and State Register
// 0x80000000 [31] NMIPENDSET (0) Setting this bit will activate an NMI
// 0x10000000 [28] PENDSVSET (0) PendSV set-pending bit
// 0x08000000 [27] PENDSVCLR (0) PendSV clear-pending bit
// 0x04000000 [26] PENDSTSET (0) SysTick exception set-pending bit
// 0x02000000 [25] PENDSTCLR (0) SysTick exception clear-pending bit
// 0x00800000 [23] ISRPREEMPT (0) The system can only access this bit when the core is halted
// 0x00400000 [22] ISRPENDING (0) External interrupt pending flag
// 0x001ff000 [20:12] VECTPENDING (0x000) Indicates the exception number for the highest priority...
// 0x000001ff [8:0] VECTACTIVE (0x000) Active exception number field
io_rw_32 icsr;
_REG_(M0PLUS_VTOR_OFFSET) // M0PLUS_VTOR
// Vector Table Offset Register
// 0xffffff00 [31:8] TBLOFF (0x000000) Bits [31:8] of the indicate the vector table offset address
io_rw_32 vtor;
_REG_(M0PLUS_AIRCR_OFFSET) // M0PLUS_AIRCR
// Application Interrupt and Reset Control Register
// 0xffff0000 [31:16] VECTKEY (0x0000) Register key: +
// 0x00008000 [15] ENDIANESS (0) Data endianness implemented: +
// 0x00000004 [2] SYSRESETREQ (0) Writing 1 to this bit causes the SYSRESETREQ signal to...
// 0x00000002 [1] VECTCLRACTIVE (0) Clears all active state information for fixed and...
io_rw_32 aircr;
_REG_(M0PLUS_SCR_OFFSET) // M0PLUS_SCR
// System Control Register
// 0x00000010 [4] SEVONPEND (0) Send Event on Pending bit: +
// 0x00000004 [2] SLEEPDEEP (0) Controls whether the processor uses sleep or deep sleep...
// 0x00000002 [1] SLEEPONEXIT (0) Indicates sleep-on-exit when returning from Handler mode...
io_rw_32 scr;
} armv6m_scb_hw_t;
#define scb_hw ((armv6m_scb_hw_t *)(PPB_BASE + M0PLUS_CPUID_OFFSET))
static_assert(sizeof (armv6m_scb_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_SCB_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SIO_H
#define _HARDWARE_STRUCTS_SIO_H
/**
* \file rp2040/sio.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sio.h"
#include "hardware/structs/interp.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sio
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sio.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SIO_CPUID_OFFSET) // SIO_CPUID
// Processor core identifier
// 0xffffffff [31:0] CPUID (-) Value is 0 when read from processor core 0, and 1 when...
io_ro_32 cpuid;
_REG_(SIO_GPIO_IN_OFFSET) // SIO_GPIO_IN
// Input value for GPIO pins
// 0x3fffffff [29:0] GPIO_IN (0x00000000) Input value for GPIO0
io_ro_32 gpio_in;
_REG_(SIO_GPIO_HI_IN_OFFSET) // SIO_GPIO_HI_IN
// Input value for QSPI pins
// 0x0000003f [5:0] GPIO_HI_IN (0x00) Input value on QSPI IO in order 0
io_ro_32 gpio_hi_in;
uint32_t _pad0;
_REG_(SIO_GPIO_OUT_OFFSET) // SIO_GPIO_OUT
// GPIO output value
// 0x3fffffff [29:0] GPIO_OUT (0x00000000) Set output level (1/0 -> high/low) for GPIO0
io_rw_32 gpio_out;
_REG_(SIO_GPIO_OUT_SET_OFFSET) // SIO_GPIO_OUT_SET
// GPIO output value set
// 0x3fffffff [29:0] GPIO_OUT_SET (0x00000000) Perform an atomic bit-set on GPIO_OUT, i
io_wo_32 gpio_set;
_REG_(SIO_GPIO_OUT_CLR_OFFSET) // SIO_GPIO_OUT_CLR
// GPIO output value clear
// 0x3fffffff [29:0] GPIO_OUT_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OUT, i
io_wo_32 gpio_clr;
_REG_(SIO_GPIO_OUT_XOR_OFFSET) // SIO_GPIO_OUT_XOR
// GPIO output value XOR
// 0x3fffffff [29:0] GPIO_OUT_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OUT, i
io_wo_32 gpio_togl;
_REG_(SIO_GPIO_OE_OFFSET) // SIO_GPIO_OE
// GPIO output enable
// 0x3fffffff [29:0] GPIO_OE (0x00000000) Set output enable (1/0 -> output/input) for GPIO0
io_rw_32 gpio_oe;
_REG_(SIO_GPIO_OE_SET_OFFSET) // SIO_GPIO_OE_SET
// GPIO output enable set
// 0x3fffffff [29:0] GPIO_OE_SET (0x00000000) Perform an atomic bit-set on GPIO_OE, i
io_wo_32 gpio_oe_set;
_REG_(SIO_GPIO_OE_CLR_OFFSET) // SIO_GPIO_OE_CLR
// GPIO output enable clear
// 0x3fffffff [29:0] GPIO_OE_CLR (0x00000000) Perform an atomic bit-clear on GPIO_OE, i
io_wo_32 gpio_oe_clr;
_REG_(SIO_GPIO_OE_XOR_OFFSET) // SIO_GPIO_OE_XOR
// GPIO output enable XOR
// 0x3fffffff [29:0] GPIO_OE_XOR (0x00000000) Perform an atomic bitwise XOR on GPIO_OE, i
io_wo_32 gpio_oe_togl;
_REG_(SIO_GPIO_HI_OUT_OFFSET) // SIO_GPIO_HI_OUT
// QSPI output value
// 0x0000003f [5:0] GPIO_HI_OUT (0x00) Set output level (1/0 -> high/low) for QSPI IO0
io_rw_32 gpio_hi_out;
_REG_(SIO_GPIO_HI_OUT_SET_OFFSET) // SIO_GPIO_HI_OUT_SET
// QSPI output value set
// 0x0000003f [5:0] GPIO_HI_OUT_SET (0x00) Perform an atomic bit-set on GPIO_HI_OUT, i
io_wo_32 gpio_hi_set;
_REG_(SIO_GPIO_HI_OUT_CLR_OFFSET) // SIO_GPIO_HI_OUT_CLR
// QSPI output value clear
// 0x0000003f [5:0] GPIO_HI_OUT_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OUT, i
io_wo_32 gpio_hi_clr;
_REG_(SIO_GPIO_HI_OUT_XOR_OFFSET) // SIO_GPIO_HI_OUT_XOR
// QSPI output value XOR
// 0x0000003f [5:0] GPIO_HI_OUT_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OUT, i
io_wo_32 gpio_hi_togl;
_REG_(SIO_GPIO_HI_OE_OFFSET) // SIO_GPIO_HI_OE
// QSPI output enable
// 0x0000003f [5:0] GPIO_HI_OE (0x00) Set output enable (1/0 -> output/input) for QSPI IO0
io_rw_32 gpio_hi_oe;
_REG_(SIO_GPIO_HI_OE_SET_OFFSET) // SIO_GPIO_HI_OE_SET
// QSPI output enable set
// 0x0000003f [5:0] GPIO_HI_OE_SET (0x00) Perform an atomic bit-set on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_set;
_REG_(SIO_GPIO_HI_OE_CLR_OFFSET) // SIO_GPIO_HI_OE_CLR
// QSPI output enable clear
// 0x0000003f [5:0] GPIO_HI_OE_CLR (0x00) Perform an atomic bit-clear on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_clr;
_REG_(SIO_GPIO_HI_OE_XOR_OFFSET) // SIO_GPIO_HI_OE_XOR
// QSPI output enable XOR
// 0x0000003f [5:0] GPIO_HI_OE_XOR (0x00) Perform an atomic bitwise XOR on GPIO_HI_OE, i
io_wo_32 gpio_hi_oe_togl;
_REG_(SIO_FIFO_ST_OFFSET) // SIO_FIFO_ST
// Status register for inter-core FIFOs (mailboxes).
// 0x00000008 [3] ROE (0) Sticky flag indicating the RX FIFO was read when empty
// 0x00000004 [2] WOF (0) Sticky flag indicating the TX FIFO was written when full
// 0x00000002 [1] RDY (1) Value is 1 if this core's TX FIFO is not full (i
// 0x00000001 [0] VLD (0) Value is 1 if this core's RX FIFO is not empty (i
io_rw_32 fifo_st;
_REG_(SIO_FIFO_WR_OFFSET) // SIO_FIFO_WR
// Write access to this core's TX FIFO
// 0xffffffff [31:0] FIFO_WR (0x00000000)
io_wo_32 fifo_wr;
_REG_(SIO_FIFO_RD_OFFSET) // SIO_FIFO_RD
// Read access to this core's RX FIFO
// 0xffffffff [31:0] FIFO_RD (-)
io_ro_32 fifo_rd;
_REG_(SIO_SPINLOCK_ST_OFFSET) // SIO_SPINLOCK_ST
// Spinlock state
// 0xffffffff [31:0] SPINLOCK_ST (0x00000000)
io_ro_32 spinlock_st;
_REG_(SIO_DIV_UDIVIDEND_OFFSET) // SIO_DIV_UDIVIDEND
// Divider unsigned dividend
// 0xffffffff [31:0] DIV_UDIVIDEND (0x00000000)
io_rw_32 div_udividend;
_REG_(SIO_DIV_UDIVISOR_OFFSET) // SIO_DIV_UDIVISOR
// Divider unsigned divisor
// 0xffffffff [31:0] DIV_UDIVISOR (0x00000000)
io_rw_32 div_udivisor;
_REG_(SIO_DIV_SDIVIDEND_OFFSET) // SIO_DIV_SDIVIDEND
// Divider signed dividend
// 0xffffffff [31:0] DIV_SDIVIDEND (0x00000000)
io_rw_32 div_sdividend;
_REG_(SIO_DIV_SDIVISOR_OFFSET) // SIO_DIV_SDIVISOR
// Divider signed divisor
// 0xffffffff [31:0] DIV_SDIVISOR (0x00000000)
io_rw_32 div_sdivisor;
_REG_(SIO_DIV_QUOTIENT_OFFSET) // SIO_DIV_QUOTIENT
// Divider result quotient
// 0xffffffff [31:0] DIV_QUOTIENT (0x00000000)
io_rw_32 div_quotient;
_REG_(SIO_DIV_REMAINDER_OFFSET) // SIO_DIV_REMAINDER
// Divider result remainder
// 0xffffffff [31:0] DIV_REMAINDER (0x00000000)
io_rw_32 div_remainder;
_REG_(SIO_DIV_CSR_OFFSET) // SIO_DIV_CSR
// Control and status register for divider
// 0x00000002 [1] DIRTY (0) Changes to 1 when any register is written, and back to 0...
// 0x00000001 [0] READY (1) Reads as 0 when a calculation is in progress, 1 otherwise
io_ro_32 div_csr;
uint32_t _pad1;
interp_hw_t interp[2];
// (Description copied from array index 0 register SIO_SPINLOCK0 applies similarly to other array indexes)
_REG_(SIO_SPINLOCK0_OFFSET) // SIO_SPINLOCK0
// Spinlock register 0
// 0xffffffff [31:0] SPINLOCK0 (0x00000000)
io_rw_32 spinlock[32];
} sio_hw_t;
#define sio_hw ((sio_hw_t *)SIO_BASE)
static_assert(sizeof (sio_hw_t) == 0x0180, "");
#endif // _HARDWARE_STRUCTS_SIO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SPI_H
#define _HARDWARE_STRUCTS_SPI_H
/**
* \file rp2040/spi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/spi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_spi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/spi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SPI_SSPCR0_OFFSET) // SPI_SSPCR0
// Control register 0, SSPCR0 on page 3-4
// 0x0000ff00 [15:8] SCR (0x00) Serial clock rate
// 0x00000080 [7] SPH (0) SSPCLKOUT phase, applicable to Motorola SPI frame format only
// 0x00000040 [6] SPO (0) SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// 0x00000030 [5:4] FRF (0x0) Frame format: 00 Motorola SPI frame format
// 0x0000000f [3:0] DSS (0x0) Data Size Select: 0000 Reserved, undefined operation
io_rw_32 cr0;
_REG_(SPI_SSPCR1_OFFSET) // SPI_SSPCR1
// Control register 1, SSPCR1 on page 3-5
// 0x00000008 [3] SOD (0) Slave-mode output disable
// 0x00000004 [2] MS (0) Master or slave mode select
// 0x00000002 [1] SSE (0) Synchronous serial port enable: 0 SSP operation disabled
// 0x00000001 [0] LBM (0) Loop back mode: 0 Normal serial port operation enabled
io_rw_32 cr1;
_REG_(SPI_SSPDR_OFFSET) // SPI_SSPDR
// Data register, SSPDR on page 3-6
// 0x0000ffff [15:0] DATA (-) Transmit/Receive FIFO: Read Receive FIFO
io_rw_32 dr;
_REG_(SPI_SSPSR_OFFSET) // SPI_SSPSR
// Status register, SSPSR on page 3-7
// 0x00000010 [4] BSY (0) PrimeCell SSP busy flag, RO: 0 SSP is idle
// 0x00000008 [3] RFF (0) Receive FIFO full, RO: 0 Receive FIFO is not full
// 0x00000004 [2] RNE (0) Receive FIFO not empty, RO: 0 Receive FIFO is empty
// 0x00000002 [1] TNF (1) Transmit FIFO not full, RO: 0 Transmit FIFO is full
// 0x00000001 [0] TFE (1) Transmit FIFO empty, RO: 0 Transmit FIFO is not empty
io_ro_32 sr;
_REG_(SPI_SSPCPSR_OFFSET) // SPI_SSPCPSR
// Clock prescale register, SSPCPSR on page 3-8
// 0x000000ff [7:0] CPSDVSR (0x00) Clock prescale divisor
io_rw_32 cpsr;
_REG_(SPI_SSPIMSC_OFFSET) // SPI_SSPIMSC
// Interrupt mask set or clear register, SSPIMSC on page 3-9
// 0x00000008 [3] TXIM (0) Transmit FIFO interrupt mask: 0 Transmit FIFO half empty...
// 0x00000004 [2] RXIM (0) Receive FIFO interrupt mask: 0 Receive FIFO half full or...
// 0x00000002 [1] RTIM (0) Receive timeout interrupt mask: 0 Receive FIFO not empty...
// 0x00000001 [0] RORIM (0) Receive overrun interrupt mask: 0 Receive FIFO written...
io_rw_32 imsc;
_REG_(SPI_SSPRIS_OFFSET) // SPI_SSPRIS
// Raw interrupt status register, SSPRIS on page 3-10
// 0x00000008 [3] TXRIS (1) Gives the raw interrupt state, prior to masking, of the...
// 0x00000004 [2] RXRIS (0) Gives the raw interrupt state, prior to masking, of the...
// 0x00000002 [1] RTRIS (0) Gives the raw interrupt state, prior to masking, of the...
// 0x00000001 [0] RORRIS (0) Gives the raw interrupt state, prior to masking, of the...
io_ro_32 ris;
_REG_(SPI_SSPMIS_OFFSET) // SPI_SSPMIS
// Masked interrupt status register, SSPMIS on page 3-11
// 0x00000008 [3] TXMIS (0) Gives the transmit FIFO masked interrupt state, after...
// 0x00000004 [2] RXMIS (0) Gives the receive FIFO masked interrupt state, after...
// 0x00000002 [1] RTMIS (0) Gives the receive timeout masked interrupt state, after...
// 0x00000001 [0] RORMIS (0) Gives the receive over run masked interrupt status,...
io_ro_32 mis;
_REG_(SPI_SSPICR_OFFSET) // SPI_SSPICR
// Interrupt clear register, SSPICR on page 3-11
// 0x00000002 [1] RTIC (0) Clears the SSPRTINTR interrupt
// 0x00000001 [0] RORIC (0) Clears the SSPRORINTR interrupt
io_rw_32 icr;
_REG_(SPI_SSPDMACR_OFFSET) // SPI_SSPDMACR
// DMA control register, SSPDMACR on page 3-12
// 0x00000002 [1] TXDMAE (0) Transmit DMA Enable
// 0x00000001 [0] RXDMAE (0) Receive DMA Enable
io_rw_32 dmacr;
} spi_hw_t;
#define spi0_hw ((spi_hw_t *)SPI0_BASE)
#define spi1_hw ((spi_hw_t *)SPI1_BASE)
static_assert(sizeof (spi_hw_t) == 0x0028, "");
#endif // _HARDWARE_STRUCTS_SPI_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SSI_H
#define _HARDWARE_STRUCTS_SSI_H
/**
* \file rp2040/ssi.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/ssi.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_ssi
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/ssi.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SSI_CTRLR0_OFFSET) // SSI_CTRLR0
// Control register 0
// 0x01000000 [24] SSTE (0) Slave select toggle enable
// 0x00600000 [22:21] SPI_FRF (0x0) SPI frame format
// 0x001f0000 [20:16] DFS_32 (0x00) Data frame size in 32b transfer mode +
// 0x0000f000 [15:12] CFS (0x0) Control frame size +
// 0x00000800 [11] SRL (0) Shift register loop (test mode)
// 0x00000400 [10] SLV_OE (0) Slave output enable
// 0x00000300 [9:8] TMOD (0x0) Transfer mode
// 0x00000080 [7] SCPOL (0) Serial clock polarity
// 0x00000040 [6] SCPH (0) Serial clock phase
// 0x00000030 [5:4] FRF (0x0) Frame format
// 0x0000000f [3:0] DFS (0x0) Data frame size
io_rw_32 ctrlr0;
_REG_(SSI_CTRLR1_OFFSET) // SSI_CTRLR1
// Master Control register 1
// 0x0000ffff [15:0] NDF (0x0000) Number of data frames
io_rw_32 ctrlr1;
_REG_(SSI_SSIENR_OFFSET) // SSI_SSIENR
// SSI Enable
// 0x00000001 [0] SSI_EN (0) SSI enable
io_rw_32 ssienr;
_REG_(SSI_MWCR_OFFSET) // SSI_MWCR
// Microwire Control
// 0x00000004 [2] MHS (0) Microwire handshaking
// 0x00000002 [1] MDD (0) Microwire control
// 0x00000001 [0] MWMOD (0) Microwire transfer mode
io_rw_32 mwcr;
_REG_(SSI_SER_OFFSET) // SSI_SER
// Slave enable
// 0x00000001 [0] SER (0) For each bit: +
io_rw_32 ser;
_REG_(SSI_BAUDR_OFFSET) // SSI_BAUDR
// Baud rate
// 0x0000ffff [15:0] SCKDV (0x0000) SSI clock divider
io_rw_32 baudr;
_REG_(SSI_TXFTLR_OFFSET) // SSI_TXFTLR
// TX FIFO threshold level
// 0x000000ff [7:0] TFT (0x00) Transmit FIFO threshold
io_rw_32 txftlr;
_REG_(SSI_RXFTLR_OFFSET) // SSI_RXFTLR
// RX FIFO threshold level
// 0x000000ff [7:0] RFT (0x00) Receive FIFO threshold
io_rw_32 rxftlr;
_REG_(SSI_TXFLR_OFFSET) // SSI_TXFLR
// TX FIFO level
// 0x000000ff [7:0] TFTFL (0x00) Transmit FIFO level
io_ro_32 txflr;
_REG_(SSI_RXFLR_OFFSET) // SSI_RXFLR
// RX FIFO level
// 0x000000ff [7:0] RXTFL (0x00) Receive FIFO level
io_ro_32 rxflr;
_REG_(SSI_SR_OFFSET) // SSI_SR
// Status register
// 0x00000040 [6] DCOL (0) Data collision error
// 0x00000020 [5] TXE (0) Transmission error
// 0x00000010 [4] RFF (0) Receive FIFO full
// 0x00000008 [3] RFNE (0) Receive FIFO not empty
// 0x00000004 [2] TFE (0) Transmit FIFO empty
// 0x00000002 [1] TFNF (0) Transmit FIFO not full
// 0x00000001 [0] BUSY (0) SSI busy flag
io_ro_32 sr;
_REG_(SSI_IMR_OFFSET) // SSI_IMR
// Interrupt mask
// 0x00000020 [5] MSTIM (0) Multi-master contention interrupt mask
// 0x00000010 [4] RXFIM (0) Receive FIFO full interrupt mask
// 0x00000008 [3] RXOIM (0) Receive FIFO overflow interrupt mask
// 0x00000004 [2] RXUIM (0) Receive FIFO underflow interrupt mask
// 0x00000002 [1] TXOIM (0) Transmit FIFO overflow interrupt mask
// 0x00000001 [0] TXEIM (0) Transmit FIFO empty interrupt mask
io_rw_32 imr;
_REG_(SSI_ISR_OFFSET) // SSI_ISR
// Interrupt status
// 0x00000020 [5] MSTIS (0) Multi-master contention interrupt status
// 0x00000010 [4] RXFIS (0) Receive FIFO full interrupt status
// 0x00000008 [3] RXOIS (0) Receive FIFO overflow interrupt status
// 0x00000004 [2] RXUIS (0) Receive FIFO underflow interrupt status
// 0x00000002 [1] TXOIS (0) Transmit FIFO overflow interrupt status
// 0x00000001 [0] TXEIS (0) Transmit FIFO empty interrupt status
io_ro_32 isr;
_REG_(SSI_RISR_OFFSET) // SSI_RISR
// Raw interrupt status
// 0x00000020 [5] MSTIR (0) Multi-master contention raw interrupt status
// 0x00000010 [4] RXFIR (0) Receive FIFO full raw interrupt status
// 0x00000008 [3] RXOIR (0) Receive FIFO overflow raw interrupt status
// 0x00000004 [2] RXUIR (0) Receive FIFO underflow raw interrupt status
// 0x00000002 [1] TXOIR (0) Transmit FIFO overflow raw interrupt status
// 0x00000001 [0] TXEIR (0) Transmit FIFO empty raw interrupt status
io_ro_32 risr;
_REG_(SSI_TXOICR_OFFSET) // SSI_TXOICR
// TX FIFO overflow interrupt clear
// 0x00000001 [0] TXOICR (0) Clear-on-read transmit FIFO overflow interrupt
io_ro_32 txoicr;
_REG_(SSI_RXOICR_OFFSET) // SSI_RXOICR
// RX FIFO overflow interrupt clear
// 0x00000001 [0] RXOICR (0) Clear-on-read receive FIFO overflow interrupt
io_ro_32 rxoicr;
_REG_(SSI_RXUICR_OFFSET) // SSI_RXUICR
// RX FIFO underflow interrupt clear
// 0x00000001 [0] RXUICR (0) Clear-on-read receive FIFO underflow interrupt
io_ro_32 rxuicr;
_REG_(SSI_MSTICR_OFFSET) // SSI_MSTICR
// Multi-master interrupt clear
// 0x00000001 [0] MSTICR (0) Clear-on-read multi-master contention interrupt
io_ro_32 msticr;
_REG_(SSI_ICR_OFFSET) // SSI_ICR
// Interrupt clear
// 0x00000001 [0] ICR (0) Clear-on-read all active interrupts
io_ro_32 icr;
_REG_(SSI_DMACR_OFFSET) // SSI_DMACR
// DMA control
// 0x00000002 [1] TDMAE (0) Transmit DMA enable
// 0x00000001 [0] RDMAE (0) Receive DMA enable
io_rw_32 dmacr;
_REG_(SSI_DMATDLR_OFFSET) // SSI_DMATDLR
// DMA TX data level
// 0x000000ff [7:0] DMATDL (0x00) Transmit data watermark level
io_rw_32 dmatdlr;
_REG_(SSI_DMARDLR_OFFSET) // SSI_DMARDLR
// DMA RX data level
// 0x000000ff [7:0] DMARDL (0x00) Receive data watermark level (DMARDLR+1)
io_rw_32 dmardlr;
_REG_(SSI_IDR_OFFSET) // SSI_IDR
// Identification register
// 0xffffffff [31:0] IDCODE (0x51535049) Peripheral dentification code
io_ro_32 idr;
_REG_(SSI_SSI_VERSION_ID_OFFSET) // SSI_SSI_VERSION_ID
// Version ID
// 0xffffffff [31:0] SSI_COMP_VERSION (0x3430312a) SNPS component version (format X
io_ro_32 ssi_version_id;
_REG_(SSI_DR0_OFFSET) // SSI_DR0
// Data Register 0 (of 36)
// 0xffffffff [31:0] DR (0x00000000) First data register of 36
io_rw_32 dr0;
uint32_t _pad0[35];
_REG_(SSI_RX_SAMPLE_DLY_OFFSET) // SSI_RX_SAMPLE_DLY
// RX sample delay
// 0x000000ff [7:0] RSD (0x00) RXD sample delay (in SCLK cycles)
io_rw_32 rx_sample_dly;
_REG_(SSI_SPI_CTRLR0_OFFSET) // SSI_SPI_CTRLR0
// SPI control
// 0xff000000 [31:24] XIP_CMD (0x03) SPI Command to send in XIP mode (INST_L = 8-bit) or to...
// 0x00040000 [18] SPI_RXDS_EN (0) Read data strobe enable
// 0x00020000 [17] INST_DDR_EN (0) Instruction DDR transfer enable
// 0x00010000 [16] SPI_DDR_EN (0) SPI DDR transfer enable
// 0x0000f800 [15:11] WAIT_CYCLES (0x00) Wait cycles between control frame transmit and data...
// 0x00000300 [9:8] INST_L (0x0) Instruction length (0/4/8/16b)
// 0x0000003c [5:2] ADDR_L (0x0) Address length (0b-60b in 4b increments)
// 0x00000003 [1:0] TRANS_TYPE (0x0) Address and instruction transfer format
io_rw_32 spi_ctrlr0;
_REG_(SSI_TXD_DRIVE_EDGE_OFFSET) // SSI_TXD_DRIVE_EDGE
// TX drive edge
// 0x000000ff [7:0] TDE (0x00) TXD drive edge
io_rw_32 txd_drive_edge;
} ssi_hw_t;
#define ssi_hw ((ssi_hw_t *)XIP_SSI_BASE)
static_assert(sizeof (ssi_hw_t) == 0x00fc, "");
#endif // _HARDWARE_STRUCTS_SSI_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSCFG_H
#define _HARDWARE_STRUCTS_SYSCFG_H
/**
* \file rp2040/syscfg.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/syscfg.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_syscfg
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/syscfg.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SYSCFG_PROC0_NMI_MASK_OFFSET) // SYSCFG_PROC0_NMI_MASK
// Processor core 0 NMI source mask
// 0xffffffff [31:0] PROC0_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ
io_rw_32 proc0_nmi_mask;
_REG_(SYSCFG_PROC1_NMI_MASK_OFFSET) // SYSCFG_PROC1_NMI_MASK
// Processor core 1 NMI source mask
// 0xffffffff [31:0] PROC1_NMI_MASK (0x00000000) Set a bit high to enable NMI from that IRQ
io_rw_32 proc1_nmi_mask;
_REG_(SYSCFG_PROC_CONFIG_OFFSET) // SYSCFG_PROC_CONFIG
// Configuration for processors
// 0xf0000000 [31:28] PROC1_DAP_INSTID (0x1) Configure proc1 DAP instance ID
// 0x0f000000 [27:24] PROC0_DAP_INSTID (0x0) Configure proc0 DAP instance ID
// 0x00000002 [1] PROC1_HALTED (0) Indication that proc1 has halted
// 0x00000001 [0] PROC0_HALTED (0) Indication that proc0 has halted
io_rw_32 proc_config;
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS
// For each bit, if 1, bypass the input synchronizer between that GPIO +
// 0x3fffffff [29:0] PROC_IN_SYNC_BYPASS (0x00000000)
io_rw_32 proc_in_sync_bypass;
_REG_(SYSCFG_PROC_IN_SYNC_BYPASS_HI_OFFSET) // SYSCFG_PROC_IN_SYNC_BYPASS_HI
// For each bit, if 1, bypass the input synchronizer between that GPIO +
// 0x0000003f [5:0] PROC_IN_SYNC_BYPASS_HI (0x00)
io_rw_32 proc_in_sync_bypass_hi;
_REG_(SYSCFG_DBGFORCE_OFFSET) // SYSCFG_DBGFORCE
// Directly control the SWD debug port of either processor
// 0x00000080 [7] PROC1_ATTACH (0) Attach processor 1 debug port to syscfg controls, and...
// 0x00000040 [6] PROC1_SWCLK (1) Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
// 0x00000020 [5] PROC1_SWDI (1) Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
// 0x00000010 [4] PROC1_SWDO (-) Observe the value of processor 1 SWDIO output
// 0x00000008 [3] PROC0_ATTACH (0) Attach processor 0 debug port to syscfg controls, and...
// 0x00000004 [2] PROC0_SWCLK (1) Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
// 0x00000002 [1] PROC0_SWDI (1) Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
// 0x00000001 [0] PROC0_SWDO (-) Observe the value of processor 0 SWDIO output
io_rw_32 dbgforce;
_REG_(SYSCFG_MEMPOWERDOWN_OFFSET) // SYSCFG_MEMPOWERDOWN
// Control power downs to memories
// 0x00000080 [7] ROM (0)
// 0x00000040 [6] USB (0)
// 0x00000020 [5] SRAM5 (0)
// 0x00000010 [4] SRAM4 (0)
// 0x00000008 [3] SRAM3 (0)
// 0x00000004 [2] SRAM2 (0)
// 0x00000002 [1] SRAM1 (0)
// 0x00000001 [0] SRAM0 (0)
io_rw_32 mempowerdown;
} syscfg_hw_t;
#define syscfg_hw ((syscfg_hw_t *)SYSCFG_BASE)
static_assert(sizeof (syscfg_hw_t) == 0x001c, "");
#endif // _HARDWARE_STRUCTS_SYSCFG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSINFO_H
#define _HARDWARE_STRUCTS_SYSINFO_H
/**
* \file rp2040/sysinfo.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/sysinfo.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_sysinfo
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/sysinfo.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(SYSINFO_CHIP_ID_OFFSET) // SYSINFO_CHIP_ID
// JEDEC JEP-106 compliant chip identifier
// 0xf0000000 [31:28] REVISION (-)
// 0x0ffff000 [27:12] PART (-)
// 0x00000fff [11:0] MANUFACTURER (-)
io_ro_32 chip_id;
_REG_(SYSINFO_PLATFORM_OFFSET) // SYSINFO_PLATFORM
// Platform register
// 0x00000002 [1] ASIC (0)
// 0x00000001 [0] FPGA (0)
io_ro_32 platform;
uint32_t _pad0[2];
_REG_(SYSINFO_GITREF_RP2040_OFFSET) // SYSINFO_GITREF_RP2040
// Git hash of the chip source
// 0xffffffff [31:0] GITREF_RP2040 (-)
io_ro_32 gitref_rp2040;
} sysinfo_hw_t;
#define sysinfo_hw ((sysinfo_hw_t *)SYSINFO_BASE)
static_assert(sizeof (sysinfo_hw_t) == 0x0014, "");
#endif // _HARDWARE_STRUCTS_SYSINFO_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_SYSTICK_H
#define _HARDWARE_STRUCTS_SYSTICK_H
/**
* \file rp2040/systick.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/m0plus.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_m0plus
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/m0plus.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(M0PLUS_SYST_CSR_OFFSET) // M0PLUS_SYST_CSR
// SysTick Control and Status Register
// 0x00010000 [16] COUNTFLAG (0) Returns 1 if timer counted to 0 since last time this was read
// 0x00000004 [2] CLKSOURCE (0) SysTick clock source
// 0x00000002 [1] TICKINT (0) Enables SysTick exception request: +
// 0x00000001 [0] ENABLE (0) Enable SysTick counter: +
io_rw_32 csr;
_REG_(M0PLUS_SYST_RVR_OFFSET) // M0PLUS_SYST_RVR
// SysTick Reload Value Register
// 0x00ffffff [23:0] RELOAD (0x000000) Value to load into the SysTick Current Value Register...
io_rw_32 rvr;
_REG_(M0PLUS_SYST_CVR_OFFSET) // M0PLUS_SYST_CVR
// SysTick Current Value Register
// 0x00ffffff [23:0] CURRENT (0x000000) Reads return the current value of the SysTick counter
io_rw_32 cvr;
_REG_(M0PLUS_SYST_CALIB_OFFSET) // M0PLUS_SYST_CALIB
// SysTick Calibration Value Register
// 0x80000000 [31] NOREF (0) If reads as 1, the Reference clock is not provided - the...
// 0x40000000 [30] SKEW (0) If reads as 1, the calibration value for 10ms is inexact...
// 0x00ffffff [23:0] TENMS (0x000000) An optional Reload value to be used for 10ms (100Hz)...
io_ro_32 calib;
} systick_hw_t;
#define systick_hw ((systick_hw_t *)(PPB_BASE + M0PLUS_SYST_CSR_OFFSET))
static_assert(sizeof (systick_hw_t) == 0x0010, "");
#endif // _HARDWARE_STRUCTS_SYSTICK_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TBMAN_H
#define _HARDWARE_STRUCTS_TBMAN_H
/**
* \file rp2040/tbman.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/tbman.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_tbman
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/tbman.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(TBMAN_PLATFORM_OFFSET) // TBMAN_PLATFORM
// Indicates the type of platform in use
// 0x00000002 [1] FPGA (0) Indicates the platform is an FPGA
// 0x00000001 [0] ASIC (1) Indicates the platform is an ASIC
io_ro_32 platform;
} tbman_hw_t;
#define tbman_hw ((tbman_hw_t *)TBMAN_BASE)
static_assert(sizeof (tbman_hw_t) == 0x0004, "");
#endif // _HARDWARE_STRUCTS_TBMAN_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_TIMER_H
#define _HARDWARE_STRUCTS_TIMER_H
/**
* \file rp2040/timer.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/timer.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_timer
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/timer.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(TIMER_TIMEHW_OFFSET) // TIMER_TIMEHW
// Write to bits 63:32 of time +
// 0xffffffff [31:0] TIMEHW (0x00000000)
io_wo_32 timehw;
_REG_(TIMER_TIMELW_OFFSET) // TIMER_TIMELW
// Write to bits 31:0 of time +
// 0xffffffff [31:0] TIMELW (0x00000000)
io_wo_32 timelw;
_REG_(TIMER_TIMEHR_OFFSET) // TIMER_TIMEHR
// Read from bits 63:32 of time +
// 0xffffffff [31:0] TIMEHR (0x00000000)
io_ro_32 timehr;
_REG_(TIMER_TIMELR_OFFSET) // TIMER_TIMELR
// Read from bits 31:0 of time
// 0xffffffff [31:0] TIMELR (0x00000000)
io_ro_32 timelr;
// (Description copied from array index 0 register TIMER_ALARM0 applies similarly to other array indexes)
_REG_(TIMER_ALARM0_OFFSET) // TIMER_ALARM0
// Arm alarm 0, and configure the time it will fire
// 0xffffffff [31:0] ALARM0 (0x00000000)
io_rw_32 alarm[4];
_REG_(TIMER_ARMED_OFFSET) // TIMER_ARMED
// Indicates the armed/disarmed status of each alarm
// 0x0000000f [3:0] ARMED (0x0)
io_rw_32 armed;
_REG_(TIMER_TIMERAWH_OFFSET) // TIMER_TIMERAWH
// Raw read from bits 63:32 of time (no side effects)
// 0xffffffff [31:0] TIMERAWH (0x00000000)
io_ro_32 timerawh;
_REG_(TIMER_TIMERAWL_OFFSET) // TIMER_TIMERAWL
// Raw read from bits 31:0 of time (no side effects)
// 0xffffffff [31:0] TIMERAWL (0x00000000)
io_ro_32 timerawl;
_REG_(TIMER_DBGPAUSE_OFFSET) // TIMER_DBGPAUSE
// Set bits high to enable pause when the corresponding debug ports are active
// 0x00000004 [2] DBG1 (1) Pause when processor 1 is in debug mode
// 0x00000002 [1] DBG0 (1) Pause when processor 0 is in debug mode
io_rw_32 dbgpause;
_REG_(TIMER_PAUSE_OFFSET) // TIMER_PAUSE
// Set high to pause the timer
// 0x00000001 [0] PAUSE (0)
io_rw_32 pause;
_REG_(TIMER_INTR_OFFSET) // TIMER_INTR
// Raw Interrupts
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 intr;
_REG_(TIMER_INTE_OFFSET) // TIMER_INTE
// Interrupt Enable
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 inte;
_REG_(TIMER_INTF_OFFSET) // TIMER_INTF
// Interrupt Force
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_rw_32 intf;
_REG_(TIMER_INTS_OFFSET) // TIMER_INTS
// Interrupt status after masking & forcing
// 0x00000008 [3] ALARM_3 (0)
// 0x00000004 [2] ALARM_2 (0)
// 0x00000002 [1] ALARM_1 (0)
// 0x00000001 [0] ALARM_0 (0)
io_ro_32 ints;
} timer_hw_t;
#define timer_hw ((timer_hw_t *)TIMER_BASE)
static_assert(sizeof (timer_hw_t) == 0x0044, "");
#endif // _HARDWARE_STRUCTS_TIMER_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_UART_H
#define _HARDWARE_STRUCTS_UART_H
/**
* \file rp2040/uart.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/uart.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_uart
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/uart.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(UART_UARTDR_OFFSET) // UART_UARTDR
// Data Register, UARTDR
// 0x00000800 [11] OE (-) Overrun error
// 0x00000400 [10] BE (-) Break error
// 0x00000200 [9] PE (-) Parity error
// 0x00000100 [8] FE (-) Framing error
// 0x000000ff [7:0] DATA (-) Receive (read) data character
io_rw_32 dr;
_REG_(UART_UARTRSR_OFFSET) // UART_UARTRSR
// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
// 0x00000008 [3] OE (0) Overrun error
// 0x00000004 [2] BE (0) Break error
// 0x00000002 [1] PE (0) Parity error
// 0x00000001 [0] FE (0) Framing error
io_rw_32 rsr;
uint32_t _pad0[4];
_REG_(UART_UARTFR_OFFSET) // UART_UARTFR
// Flag Register, UARTFR
// 0x00000100 [8] RI (-) Ring indicator
// 0x00000080 [7] TXFE (1) Transmit FIFO empty
// 0x00000040 [6] RXFF (0) Receive FIFO full
// 0x00000020 [5] TXFF (0) Transmit FIFO full
// 0x00000010 [4] RXFE (1) Receive FIFO empty
// 0x00000008 [3] BUSY (0) UART busy
// 0x00000004 [2] DCD (-) Data carrier detect
// 0x00000002 [1] DSR (-) Data set ready
// 0x00000001 [0] CTS (-) Clear to send
io_ro_32 fr;
uint32_t _pad1;
_REG_(UART_UARTILPR_OFFSET) // UART_UARTILPR
// IrDA Low-Power Counter Register, UARTILPR
// 0x000000ff [7:0] ILPDVSR (0x00) 8-bit low-power divisor value
io_rw_32 ilpr;
_REG_(UART_UARTIBRD_OFFSET) // UART_UARTIBRD
// Integer Baud Rate Register, UARTIBRD
// 0x0000ffff [15:0] BAUD_DIVINT (0x0000) The integer baud rate divisor
io_rw_32 ibrd;
_REG_(UART_UARTFBRD_OFFSET) // UART_UARTFBRD
// Fractional Baud Rate Register, UARTFBRD
// 0x0000003f [5:0] BAUD_DIVFRAC (0x00) The fractional baud rate divisor
io_rw_32 fbrd;
_REG_(UART_UARTLCR_H_OFFSET) // UART_UARTLCR_H
// Line Control Register, UARTLCR_H
// 0x00000080 [7] SPS (0) Stick parity select
// 0x00000060 [6:5] WLEN (0x0) Word length
// 0x00000010 [4] FEN (0) Enable FIFOs: 0 = FIFOs are disabled (character mode)...
// 0x00000008 [3] STP2 (0) Two stop bits select
// 0x00000004 [2] EPS (0) Even parity select
// 0x00000002 [1] PEN (0) Parity enable: 0 = parity is disabled and no parity bit...
// 0x00000001 [0] BRK (0) Send break
io_rw_32 lcr_h;
_REG_(UART_UARTCR_OFFSET) // UART_UARTCR
// Control Register, UARTCR
// 0x00008000 [15] CTSEN (0) CTS hardware flow control enable
// 0x00004000 [14] RTSEN (0) RTS hardware flow control enable
// 0x00002000 [13] OUT2 (0) This bit is the complement of the UART Out2 (nUARTOut2)...
// 0x00001000 [12] OUT1 (0) This bit is the complement of the UART Out1 (nUARTOut1)...
// 0x00000800 [11] RTS (0) Request to send
// 0x00000400 [10] DTR (0) Data transmit ready
// 0x00000200 [9] RXE (1) Receive enable
// 0x00000100 [8] TXE (1) Transmit enable
// 0x00000080 [7] LBE (0) Loopback enable
// 0x00000004 [2] SIRLP (0) SIR low-power IrDA mode
// 0x00000002 [1] SIREN (0) SIR enable: 0 = IrDA SIR ENDEC is disabled
// 0x00000001 [0] UARTEN (0) UART enable: 0 = UART is disabled
io_rw_32 cr;
_REG_(UART_UARTIFLS_OFFSET) // UART_UARTIFLS
// Interrupt FIFO Level Select Register, UARTIFLS
// 0x00000038 [5:3] RXIFLSEL (0x2) Receive interrupt FIFO level select
// 0x00000007 [2:0] TXIFLSEL (0x2) Transmit interrupt FIFO level select
io_rw_32 ifls;
_REG_(UART_UARTIMSC_OFFSET) // UART_UARTIMSC
// Interrupt Mask Set/Clear Register, UARTIMSC
// 0x00000400 [10] OEIM (0) Overrun error interrupt mask
// 0x00000200 [9] BEIM (0) Break error interrupt mask
// 0x00000100 [8] PEIM (0) Parity error interrupt mask
// 0x00000080 [7] FEIM (0) Framing error interrupt mask
// 0x00000040 [6] RTIM (0) Receive timeout interrupt mask
// 0x00000020 [5] TXIM (0) Transmit interrupt mask
// 0x00000010 [4] RXIM (0) Receive interrupt mask
// 0x00000008 [3] DSRMIM (0) nUARTDSR modem interrupt mask
// 0x00000004 [2] DCDMIM (0) nUARTDCD modem interrupt mask
// 0x00000002 [1] CTSMIM (0) nUARTCTS modem interrupt mask
// 0x00000001 [0] RIMIM (0) nUARTRI modem interrupt mask
io_rw_32 imsc;
_REG_(UART_UARTRIS_OFFSET) // UART_UARTRIS
// Raw Interrupt Status Register, UARTRIS
// 0x00000400 [10] OERIS (0) Overrun error interrupt status
// 0x00000200 [9] BERIS (0) Break error interrupt status
// 0x00000100 [8] PERIS (0) Parity error interrupt status
// 0x00000080 [7] FERIS (0) Framing error interrupt status
// 0x00000040 [6] RTRIS (0) Receive timeout interrupt status
// 0x00000020 [5] TXRIS (0) Transmit interrupt status
// 0x00000010 [4] RXRIS (0) Receive interrupt status
// 0x00000008 [3] DSRRMIS (-) nUARTDSR modem interrupt status
// 0x00000004 [2] DCDRMIS (-) nUARTDCD modem interrupt status
// 0x00000002 [1] CTSRMIS (-) nUARTCTS modem interrupt status
// 0x00000001 [0] RIRMIS (-) nUARTRI modem interrupt status
io_ro_32 ris;
_REG_(UART_UARTMIS_OFFSET) // UART_UARTMIS
// Masked Interrupt Status Register, UARTMIS
// 0x00000400 [10] OEMIS (0) Overrun error masked interrupt status
// 0x00000200 [9] BEMIS (0) Break error masked interrupt status
// 0x00000100 [8] PEMIS (0) Parity error masked interrupt status
// 0x00000080 [7] FEMIS (0) Framing error masked interrupt status
// 0x00000040 [6] RTMIS (0) Receive timeout masked interrupt status
// 0x00000020 [5] TXMIS (0) Transmit masked interrupt status
// 0x00000010 [4] RXMIS (0) Receive masked interrupt status
// 0x00000008 [3] DSRMMIS (-) nUARTDSR modem masked interrupt status
// 0x00000004 [2] DCDMMIS (-) nUARTDCD modem masked interrupt status
// 0x00000002 [1] CTSMMIS (-) nUARTCTS modem masked interrupt status
// 0x00000001 [0] RIMMIS (-) nUARTRI modem masked interrupt status
io_ro_32 mis;
_REG_(UART_UARTICR_OFFSET) // UART_UARTICR
// Interrupt Clear Register, UARTICR
// 0x00000400 [10] OEIC (-) Overrun error interrupt clear
// 0x00000200 [9] BEIC (-) Break error interrupt clear
// 0x00000100 [8] PEIC (-) Parity error interrupt clear
// 0x00000080 [7] FEIC (-) Framing error interrupt clear
// 0x00000040 [6] RTIC (-) Receive timeout interrupt clear
// 0x00000020 [5] TXIC (-) Transmit interrupt clear
// 0x00000010 [4] RXIC (-) Receive interrupt clear
// 0x00000008 [3] DSRMIC (-) nUARTDSR modem interrupt clear
// 0x00000004 [2] DCDMIC (-) nUARTDCD modem interrupt clear
// 0x00000002 [1] CTSMIC (-) nUARTCTS modem interrupt clear
// 0x00000001 [0] RIMIC (-) nUARTRI modem interrupt clear
io_rw_32 icr;
_REG_(UART_UARTDMACR_OFFSET) // UART_UARTDMACR
// DMA Control Register, UARTDMACR
// 0x00000004 [2] DMAONERR (0) DMA on error
// 0x00000002 [1] TXDMAE (0) Transmit DMA enable
// 0x00000001 [0] RXDMAE (0) Receive DMA enable
io_rw_32 dmacr;
} uart_hw_t;
#define uart0_hw ((uart_hw_t *)UART0_BASE)
#define uart1_hw ((uart_hw_t *)UART1_BASE)
static_assert(sizeof (uart_hw_t) == 0x004c, "");
#endif // _HARDWARE_STRUCTS_UART_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_USB_H
#define _HARDWARE_STRUCTS_USB_H
/**
* \file rp2040/usb.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/usb.h"
#include "hardware/structs/usb_dpram.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_usb
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(USB_ADDR_ENDP_OFFSET) // USB_ADDR_ENDP
// Device address and endpoint control
// 0x000f0000 [19:16] ENDPOINT (0x0) Device endpoint to send data to
// 0x0000007f [6:0] ADDRESS (0x00) In device mode, the address that the device should respond to
io_rw_32 dev_addr_ctrl;
// (Description copied from array index 0 register USB_ADDR_ENDP1 applies similarly to other array indexes)
_REG_(USB_ADDR_ENDP1_OFFSET) // USB_ADDR_ENDP1
// Interrupt endpoint 1
// 0x04000000 [26] INTEP_PREAMBLE (0) Interrupt EP requires preamble (is a low speed device on...
// 0x02000000 [25] INTEP_DIR (0) Direction of the interrupt endpoint
// 0x000f0000 [19:16] ENDPOINT (0x0) Endpoint number of the interrupt endpoint
// 0x0000007f [6:0] ADDRESS (0x00) Device address
io_rw_32 int_ep_addr_ctrl[15];
_REG_(USB_MAIN_CTRL_OFFSET) // USB_MAIN_CTRL
// Main control register
// 0x80000000 [31] SIM_TIMING (0) Reduced timings for simulation
// 0x00000002 [1] HOST_NDEVICE (0) Device mode = 0, Host mode = 1
// 0x00000001 [0] CONTROLLER_EN (0) Enable controller
io_rw_32 main_ctrl;
_REG_(USB_SOF_WR_OFFSET) // USB_SOF_WR
// Set the SOF (Start of Frame) frame number in the host controller
// 0x000007ff [10:0] COUNT (0x000)
io_wo_32 sof_wr;
_REG_(USB_SOF_RD_OFFSET) // USB_SOF_RD
// Read the last SOF (Start of Frame) frame number seen
// 0x000007ff [10:0] COUNT (0x000)
io_ro_32 sof_rd;
_REG_(USB_SIE_CTRL_OFFSET) // USB_SIE_CTRL
// SIE control register
// 0x80000000 [31] EP0_INT_STALL (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
// 0x40000000 [30] EP0_DOUBLE_BUF (0) Device: EP0 single buffered = 0, double buffered = 1
// 0x20000000 [29] EP0_INT_1BUF (0) Device: Set bit in BUFF_STATUS for every buffer completed on EP0
// 0x10000000 [28] EP0_INT_2BUF (0) Device: Set bit in BUFF_STATUS for every 2 buffers...
// 0x08000000 [27] EP0_INT_NAK (0) Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
// 0x04000000 [26] DIRECT_EN (0) Direct bus drive enable
// 0x02000000 [25] DIRECT_DP (0) Direct control of DP
// 0x01000000 [24] DIRECT_DM (0) Direct control of DM
// 0x00040000 [18] TRANSCEIVER_PD (0) Power down bus transceiver
// 0x00020000 [17] RPU_OPT (0) Device: Pull-up strength (0=1K2, 1=2k3)
// 0x00010000 [16] PULLUP_EN (0) Device: Enable pull up resistor
// 0x00008000 [15] PULLDOWN_EN (0) Host: Enable pull down resistors
// 0x00002000 [13] RESET_BUS (0) Host: Reset bus
// 0x00001000 [12] RESUME (0) Device: Remote wakeup
// 0x00000800 [11] VBUS_EN (0) Host: Enable VBUS
// 0x00000400 [10] KEEP_ALIVE_EN (0) Host: Enable keep alive packet (for low speed bus)
// 0x00000200 [9] SOF_EN (0) Host: Enable SOF generation (for full speed bus)
// 0x00000100 [8] SOF_SYNC (0) Host: Delay packet(s) until after SOF
// 0x00000040 [6] PREAMBLE_EN (0) Host: Preable enable for LS device on FS hub
// 0x00000010 [4] STOP_TRANS (0) Host: Stop transaction
// 0x00000008 [3] RECEIVE_DATA (0) Host: Receive transaction (IN to host)
// 0x00000004 [2] SEND_DATA (0) Host: Send transaction (OUT from host)
// 0x00000002 [1] SEND_SETUP (0) Host: Send Setup packet
// 0x00000001 [0] START_TRANS (0) Host: Start transaction
io_rw_32 sie_ctrl;
_REG_(USB_SIE_STATUS_OFFSET) // USB_SIE_STATUS
// SIE status register
// 0x80000000 [31] DATA_SEQ_ERROR (0) Data Sequence Error
// 0x40000000 [30] ACK_REC (0) ACK received
// 0x20000000 [29] STALL_REC (0) Host: STALL received
// 0x10000000 [28] NAK_REC (0) Host: NAK received
// 0x08000000 [27] RX_TIMEOUT (0) RX timeout is raised by both the host and device if an...
// 0x04000000 [26] RX_OVERFLOW (0) RX overflow is raised by the Serial RX engine if the...
// 0x02000000 [25] BIT_STUFF_ERROR (0) Bit Stuff Error
// 0x01000000 [24] CRC_ERROR (0) CRC Error
// 0x00080000 [19] BUS_RESET (0) Device: bus reset received
// 0x00040000 [18] TRANS_COMPLETE (0) Transaction complete
// 0x00020000 [17] SETUP_REC (0) Device: Setup packet received
// 0x00010000 [16] CONNECTED (0) Device: connected
// 0x00000800 [11] RESUME (0) Host: Device has initiated a remote resume
// 0x00000400 [10] VBUS_OVER_CURR (0) VBUS over current detected
// 0x00000300 [9:8] SPEED (0x0) Host: device speed
// 0x00000010 [4] SUSPENDED (0) Bus in suspended state
// 0x0000000c [3:2] LINE_STATE (0x0) USB bus line state
// 0x00000001 [0] VBUS_DETECTED (0) Device: VBUS Detected
io_rw_32 sie_status;
_REG_(USB_INT_EP_CTRL_OFFSET) // USB_INT_EP_CTRL
// interrupt endpoint control register
// 0x0000fffe [15:1] INT_EP_ACTIVE (0x0000) Host: Enable interrupt endpoint 1 => 15
io_rw_32 int_ep_ctrl;
_REG_(USB_BUFF_STATUS_OFFSET) // USB_BUFF_STATUS
// Buffer status register
// 0x80000000 [31] EP15_OUT (0)
// 0x40000000 [30] EP15_IN (0)
// 0x20000000 [29] EP14_OUT (0)
// 0x10000000 [28] EP14_IN (0)
// 0x08000000 [27] EP13_OUT (0)
// 0x04000000 [26] EP13_IN (0)
// 0x02000000 [25] EP12_OUT (0)
// 0x01000000 [24] EP12_IN (0)
// 0x00800000 [23] EP11_OUT (0)
// 0x00400000 [22] EP11_IN (0)
// 0x00200000 [21] EP10_OUT (0)
// 0x00100000 [20] EP10_IN (0)
// 0x00080000 [19] EP9_OUT (0)
// 0x00040000 [18] EP9_IN (0)
// 0x00020000 [17] EP8_OUT (0)
// 0x00010000 [16] EP8_IN (0)
// 0x00008000 [15] EP7_OUT (0)
// 0x00004000 [14] EP7_IN (0)
// 0x00002000 [13] EP6_OUT (0)
// 0x00001000 [12] EP6_IN (0)
// 0x00000800 [11] EP5_OUT (0)
// 0x00000400 [10] EP5_IN (0)
// 0x00000200 [9] EP4_OUT (0)
// 0x00000100 [8] EP4_IN (0)
// 0x00000080 [7] EP3_OUT (0)
// 0x00000040 [6] EP3_IN (0)
// 0x00000020 [5] EP2_OUT (0)
// 0x00000010 [4] EP2_IN (0)
// 0x00000008 [3] EP1_OUT (0)
// 0x00000004 [2] EP1_IN (0)
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_rw_32 buf_status;
_REG_(USB_BUFF_CPU_SHOULD_HANDLE_OFFSET) // USB_BUFF_CPU_SHOULD_HANDLE
// Which of the double buffers should be handled
// 0x80000000 [31] EP15_OUT (0)
// 0x40000000 [30] EP15_IN (0)
// 0x20000000 [29] EP14_OUT (0)
// 0x10000000 [28] EP14_IN (0)
// 0x08000000 [27] EP13_OUT (0)
// 0x04000000 [26] EP13_IN (0)
// 0x02000000 [25] EP12_OUT (0)
// 0x01000000 [24] EP12_IN (0)
// 0x00800000 [23] EP11_OUT (0)
// 0x00400000 [22] EP11_IN (0)
// 0x00200000 [21] EP10_OUT (0)
// 0x00100000 [20] EP10_IN (0)
// 0x00080000 [19] EP9_OUT (0)
// 0x00040000 [18] EP9_IN (0)
// 0x00020000 [17] EP8_OUT (0)
// 0x00010000 [16] EP8_IN (0)
// 0x00008000 [15] EP7_OUT (0)
// 0x00004000 [14] EP7_IN (0)
// 0x00002000 [13] EP6_OUT (0)
// 0x00001000 [12] EP6_IN (0)
// 0x00000800 [11] EP5_OUT (0)
// 0x00000400 [10] EP5_IN (0)
// 0x00000200 [9] EP4_OUT (0)
// 0x00000100 [8] EP4_IN (0)
// 0x00000080 [7] EP3_OUT (0)
// 0x00000040 [6] EP3_IN (0)
// 0x00000020 [5] EP2_OUT (0)
// 0x00000010 [4] EP2_IN (0)
// 0x00000008 [3] EP1_OUT (0)
// 0x00000004 [2] EP1_IN (0)
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_ro_32 buf_cpu_should_handle;
_REG_(USB_EP_ABORT_OFFSET) // USB_EP_ABORT
// Device only: Can be set to ignore the buffer control register for this endpoint in case you...
// 0x80000000 [31] EP15_OUT (0)
// 0x40000000 [30] EP15_IN (0)
// 0x20000000 [29] EP14_OUT (0)
// 0x10000000 [28] EP14_IN (0)
// 0x08000000 [27] EP13_OUT (0)
// 0x04000000 [26] EP13_IN (0)
// 0x02000000 [25] EP12_OUT (0)
// 0x01000000 [24] EP12_IN (0)
// 0x00800000 [23] EP11_OUT (0)
// 0x00400000 [22] EP11_IN (0)
// 0x00200000 [21] EP10_OUT (0)
// 0x00100000 [20] EP10_IN (0)
// 0x00080000 [19] EP9_OUT (0)
// 0x00040000 [18] EP9_IN (0)
// 0x00020000 [17] EP8_OUT (0)
// 0x00010000 [16] EP8_IN (0)
// 0x00008000 [15] EP7_OUT (0)
// 0x00004000 [14] EP7_IN (0)
// 0x00002000 [13] EP6_OUT (0)
// 0x00001000 [12] EP6_IN (0)
// 0x00000800 [11] EP5_OUT (0)
// 0x00000400 [10] EP5_IN (0)
// 0x00000200 [9] EP4_OUT (0)
// 0x00000100 [8] EP4_IN (0)
// 0x00000080 [7] EP3_OUT (0)
// 0x00000040 [6] EP3_IN (0)
// 0x00000020 [5] EP2_OUT (0)
// 0x00000010 [4] EP2_IN (0)
// 0x00000008 [3] EP1_OUT (0)
// 0x00000004 [2] EP1_IN (0)
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_rw_32 abort;
_REG_(USB_EP_ABORT_DONE_OFFSET) // USB_EP_ABORT_DONE
// Device only: Used in conjunction with `EP_ABORT`
// 0x80000000 [31] EP15_OUT (0)
// 0x40000000 [30] EP15_IN (0)
// 0x20000000 [29] EP14_OUT (0)
// 0x10000000 [28] EP14_IN (0)
// 0x08000000 [27] EP13_OUT (0)
// 0x04000000 [26] EP13_IN (0)
// 0x02000000 [25] EP12_OUT (0)
// 0x01000000 [24] EP12_IN (0)
// 0x00800000 [23] EP11_OUT (0)
// 0x00400000 [22] EP11_IN (0)
// 0x00200000 [21] EP10_OUT (0)
// 0x00100000 [20] EP10_IN (0)
// 0x00080000 [19] EP9_OUT (0)
// 0x00040000 [18] EP9_IN (0)
// 0x00020000 [17] EP8_OUT (0)
// 0x00010000 [16] EP8_IN (0)
// 0x00008000 [15] EP7_OUT (0)
// 0x00004000 [14] EP7_IN (0)
// 0x00002000 [13] EP6_OUT (0)
// 0x00001000 [12] EP6_IN (0)
// 0x00000800 [11] EP5_OUT (0)
// 0x00000400 [10] EP5_IN (0)
// 0x00000200 [9] EP4_OUT (0)
// 0x00000100 [8] EP4_IN (0)
// 0x00000080 [7] EP3_OUT (0)
// 0x00000040 [6] EP3_IN (0)
// 0x00000020 [5] EP2_OUT (0)
// 0x00000010 [4] EP2_IN (0)
// 0x00000008 [3] EP1_OUT (0)
// 0x00000004 [2] EP1_IN (0)
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_rw_32 abort_done;
_REG_(USB_EP_STALL_ARM_OFFSET) // USB_EP_STALL_ARM
// Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register...
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_rw_32 ep_stall_arm;
_REG_(USB_NAK_POLL_OFFSET) // USB_NAK_POLL
// Used by the host controller
// 0x03ff0000 [25:16] DELAY_FS (0x010) NAK polling interval for a full speed device
// 0x000003ff [9:0] DELAY_LS (0x010) NAK polling interval for a low speed device
io_rw_32 nak_poll;
_REG_(USB_EP_STATUS_STALL_NAK_OFFSET) // USB_EP_STATUS_STALL_NAK
// Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set
// 0x80000000 [31] EP15_OUT (0)
// 0x40000000 [30] EP15_IN (0)
// 0x20000000 [29] EP14_OUT (0)
// 0x10000000 [28] EP14_IN (0)
// 0x08000000 [27] EP13_OUT (0)
// 0x04000000 [26] EP13_IN (0)
// 0x02000000 [25] EP12_OUT (0)
// 0x01000000 [24] EP12_IN (0)
// 0x00800000 [23] EP11_OUT (0)
// 0x00400000 [22] EP11_IN (0)
// 0x00200000 [21] EP10_OUT (0)
// 0x00100000 [20] EP10_IN (0)
// 0x00080000 [19] EP9_OUT (0)
// 0x00040000 [18] EP9_IN (0)
// 0x00020000 [17] EP8_OUT (0)
// 0x00010000 [16] EP8_IN (0)
// 0x00008000 [15] EP7_OUT (0)
// 0x00004000 [14] EP7_IN (0)
// 0x00002000 [13] EP6_OUT (0)
// 0x00001000 [12] EP6_IN (0)
// 0x00000800 [11] EP5_OUT (0)
// 0x00000400 [10] EP5_IN (0)
// 0x00000200 [9] EP4_OUT (0)
// 0x00000100 [8] EP4_IN (0)
// 0x00000080 [7] EP3_OUT (0)
// 0x00000040 [6] EP3_IN (0)
// 0x00000020 [5] EP2_OUT (0)
// 0x00000010 [4] EP2_IN (0)
// 0x00000008 [3] EP1_OUT (0)
// 0x00000004 [2] EP1_IN (0)
// 0x00000002 [1] EP0_OUT (0)
// 0x00000001 [0] EP0_IN (0)
io_rw_32 ep_nak_stall_status;
_REG_(USB_USB_MUXING_OFFSET) // USB_USB_MUXING
// Where to connect the USB controller
// 0x00000008 [3] SOFTCON (0)
// 0x00000004 [2] TO_DIGITAL_PAD (0)
// 0x00000002 [1] TO_EXTPHY (0)
// 0x00000001 [0] TO_PHY (0)
io_rw_32 muxing;
_REG_(USB_USB_PWR_OFFSET) // USB_USB_PWR
// Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO
// 0x00000020 [5] OVERCURR_DETECT_EN (0)
// 0x00000010 [4] OVERCURR_DETECT (0)
// 0x00000008 [3] VBUS_DETECT_OVERRIDE_EN (0)
// 0x00000004 [2] VBUS_DETECT (0)
// 0x00000002 [1] VBUS_EN_OVERRIDE_EN (0)
// 0x00000001 [0] VBUS_EN (0)
io_rw_32 pwr;
_REG_(USB_USBPHY_DIRECT_OFFSET) // USB_USBPHY_DIRECT
// Note that most functions are driven directly from usb_fsls controller
// 0x00400000 [22] DM_OVV (0) Status bit from USB PHY
// 0x00200000 [21] DP_OVV (0) Status bit from USB PHY
// 0x00100000 [20] DM_OVCN (0) Status bit from USB PHY
// 0x00080000 [19] DP_OVCN (0) Status bit from USB PHY
// 0x00040000 [18] RX_DM (0) Status bit from USB PHY +
// 0x00020000 [17] RX_DP (0) Status bit from USB PHY +
// 0x00010000 [16] RX_DD (0) Status bit from USB PHY +
// 0x00008000 [15] TX_DIFFMODE (0)
// 0x00004000 [14] TX_FSSLEW (0)
// 0x00002000 [13] TX_PD (0)
// 0x00001000 [12] RX_PD (0)
// 0x00000800 [11] TX_DM (0) Value to drive to USB PHY when override enable is set...
// 0x00000400 [10] TX_DP (0) Value to drive to USB PHY when override enable is set...
// 0x00000200 [9] TX_DM_OE (0) Value to drive to USB PHY when override enable is set...
// 0x00000100 [8] TX_DP_OE (0) Value to drive to USB PHY when override enable is set...
// 0x00000040 [6] DM_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
// 0x00000020 [5] DM_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
// 0x00000010 [4] DM_PULLUP_HISEL (0) when dm_pullup_en is set high, this enables second resistor
// 0x00000004 [2] DP_PULLDN_EN (0) Value to drive to USB PHY when override enable is set...
// 0x00000002 [1] DP_PULLUP_EN (0) Value to drive to USB PHY when override enable is set...
// 0x00000001 [0] DP_PULLUP_HISEL (0) when dp_pullup_en is set high, this enables second resistor
io_rw_32 phy_direct;
_REG_(USB_USBPHY_DIRECT_OVERRIDE_OFFSET) // USB_USBPHY_DIRECT_OVERRIDE
// 0x00008000 [15] TX_DIFFMODE_OVERRIDE_EN (0)
// 0x00001000 [12] DM_PULLUP_OVERRIDE_EN (0)
// 0x00000800 [11] TX_FSSLEW_OVERRIDE_EN (0)
// 0x00000400 [10] TX_PD_OVERRIDE_EN (0)
// 0x00000200 [9] RX_PD_OVERRIDE_EN (0)
// 0x00000100 [8] TX_DM_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000080 [7] TX_DP_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000040 [6] TX_DM_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000020 [5] TX_DP_OE_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000010 [4] DM_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000008 [3] DP_PULLDN_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000004 [2] DP_PULLUP_EN_OVERRIDE_EN (0) Override default value or value driven from USB Controller to PHY
// 0x00000002 [1] DM_PULLUP_HISEL_OVERRIDE_EN (0)
// 0x00000001 [0] DP_PULLUP_HISEL_OVERRIDE_EN (0)
io_rw_32 phy_direct_override;
_REG_(USB_USBPHY_TRIM_OFFSET) // USB_USBPHY_TRIM
// Note that most functions are driven directly from usb_fsls controller
// 0x00001f00 [12:8] DM_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
// 0x0000001f [4:0] DP_PULLDN_TRIM (0x1f) Value to drive to USB PHY +
io_rw_32 phy_trim;
uint32_t _pad0;
_REG_(USB_INTR_OFFSET) // USB_INTR
// Raw Interrupts
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
// 0x00010000 [16] SETUP_REQ (0) Device
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
io_ro_32 intr;
_REG_(USB_INTE_OFFSET) // USB_INTE
// Interrupt Enable
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
// 0x00010000 [16] SETUP_REQ (0) Device
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
io_rw_32 inte;
_REG_(USB_INTF_OFFSET) // USB_INTF
// Interrupt Force
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
// 0x00010000 [16] SETUP_REQ (0) Device
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
io_rw_32 intf;
_REG_(USB_INTS_OFFSET) // USB_INTS
// Interrupt status after masking & forcing
// 0x00080000 [19] EP_STALL_NAK (0) Raised when any bit in EP_STATUS_STALL_NAK is set
// 0x00040000 [18] ABORT_DONE (0) Raised when any bit in ABORT_DONE is set
// 0x00020000 [17] DEV_SOF (0) Set every time the device receives a SOF (Start of Frame) packet
// 0x00010000 [16] SETUP_REQ (0) Device
// 0x00008000 [15] DEV_RESUME_FROM_HOST (0) Set when the device receives a resume from the host
// 0x00004000 [14] DEV_SUSPEND (0) Set when the device suspend state changes
// 0x00002000 [13] DEV_CONN_DIS (0) Set when the device connection state changes
// 0x00001000 [12] BUS_RESET (0) Source: SIE_STATUS
// 0x00000800 [11] VBUS_DETECT (0) Source: SIE_STATUS
// 0x00000400 [10] STALL (0) Source: SIE_STATUS
// 0x00000200 [9] ERROR_CRC (0) Source: SIE_STATUS
// 0x00000100 [8] ERROR_BIT_STUFF (0) Source: SIE_STATUS
// 0x00000080 [7] ERROR_RX_OVERFLOW (0) Source: SIE_STATUS
// 0x00000040 [6] ERROR_RX_TIMEOUT (0) Source: SIE_STATUS
// 0x00000020 [5] ERROR_DATA_SEQ (0) Source: SIE_STATUS
// 0x00000010 [4] BUFF_STATUS (0) Raised when any bit in BUFF_STATUS is set
// 0x00000008 [3] TRANS_COMPLETE (0) Raised every time SIE_STATUS
// 0x00000004 [2] HOST_SOF (0) Host: raised every time the host sends a SOF (Start of Frame)
// 0x00000002 [1] HOST_RESUME (0) Host: raised when a device wakes up the host
// 0x00000001 [0] HOST_CONN_DIS (0) Host: raised when a device is connected or disconnected (i
io_ro_32 ints;
} usb_hw_t;
#define usb_hw ((usb_hw_t *)USBCTRL_REGS_BASE)
static_assert(sizeof (usb_hw_t) == 0x009c, "");
#endif // _HARDWARE_STRUCTS_USB_H

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/**
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_USB_DPRAM_H
#define _HARDWARE_STRUCTS_USB_DPRAM_H
#include "hardware/address_mapped.h"
#include "hardware/regs/usb.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2350/rp2350-datasheet.pdf#tab-registerlist_usb
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/usb.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
// 0-15
#define USB_NUM_ENDPOINTS 16
// allow user to restrict number of endpoints available to save RAN
#ifndef USB_MAX_ENDPOINTS
#define USB_MAX_ENDPOINTS USB_NUM_ENDPOINTS
#endif
// 1-15
#define USB_HOST_INTERRUPT_ENDPOINTS (USB_NUM_ENDPOINTS - 1)
// Endpoint buffer control bits
#define USB_BUF_CTRL_FULL 0x00008000u
#define USB_BUF_CTRL_LAST 0x00004000u
#define USB_BUF_CTRL_DATA0_PID 0x00000000u
#define USB_BUF_CTRL_DATA1_PID 0x00002000u
#define USB_BUF_CTRL_SEL 0x00001000u
#define USB_BUF_CTRL_STALL 0x00000800u
#define USB_BUF_CTRL_AVAIL 0x00000400u
#define USB_BUF_CTRL_LEN_MASK 0x000003FFu
#define USB_BUF_CTRL_LEN_LSB 0
// ep_inout_ctrl bits
#define EP_CTRL_ENABLE_BITS (1u << 31u)
#define EP_CTRL_DOUBLE_BUFFERED_BITS (1u << 30)
#define EP_CTRL_INTERRUPT_PER_BUFFER (1u << 29)
#define EP_CTRL_INTERRUPT_PER_DOUBLE_BUFFER (1u << 28)
#define EP_CTRL_INTERRUPT_ON_NAK (1u << 16)
#define EP_CTRL_INTERRUPT_ON_STALL (1u << 17)
#define EP_CTRL_BUFFER_TYPE_LSB 26u
#define EP_CTRL_HOST_INTERRUPT_INTERVAL_LSB 16u
#define USB_DPRAM_SIZE 4096u
// PICO_CONFIG: USB_DPRAM_MAX, Set amount of USB RAM used by USB system, min=0, max=4096, default=4096, group=hardware_usb
// Allow user to claim some of the USB RAM for themselves
#ifndef USB_DPRAM_MAX
#define USB_DPRAM_MAX USB_DPRAM_SIZE
#endif
// Define maximum packet sizes
#define USB_MAX_ISO_PACKET_SIZE 1023
#define USB_MAX_PACKET_SIZE 64
typedef struct {
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
// Starts at ep1
struct usb_device_dpram_ep_ctrl {
io_rw_32 in;
io_rw_32 out;
} ep_ctrl[USB_NUM_ENDPOINTS - 1];
// Starts at ep0
struct usb_device_dpram_ep_buf_ctrl {
io_rw_32 in;
io_rw_32 out;
} ep_buf_ctrl[USB_NUM_ENDPOINTS];
// EP0 buffers are fixed. Assumes single buffered mode for EP0
uint8_t ep0_buf_a[0x40];
uint8_t ep0_buf_b[0x40];
// Rest of DPRAM can be carved up as needed
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
} usb_device_dpram_t;
static_assert(sizeof(usb_device_dpram_t) == USB_DPRAM_MAX, "");
static_assert(offsetof(usb_device_dpram_t, epx_data) == 0x180, "");
typedef struct {
// 4K of DPSRAM at beginning. Note this supports 8, 16, and 32 bit accesses
volatile uint8_t setup_packet[8]; // First 8 bytes are always for setup packets
// Interrupt endpoint control 1 -> 15
struct usb_host_dpram_ep_ctrl {
io_rw_32 ctrl;
io_rw_32 spare;
} int_ep_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
io_rw_32 epx_buf_ctrl;
io_rw_32 _spare0;
// Interrupt endpoint buffer control
struct usb_host_dpram_ep_buf_ctrl {
io_rw_32 ctrl;
io_rw_32 spare;
} int_ep_buffer_ctrl[USB_HOST_INTERRUPT_ENDPOINTS];
io_rw_32 epx_ctrl;
uint8_t _spare1[124];
// Should start at 0x180
uint8_t epx_data[USB_DPRAM_MAX - 0x180];
} usb_host_dpram_t;
static_assert(sizeof(usb_host_dpram_t) == USB_DPRAM_MAX, "");
static_assert(offsetof(usb_host_dpram_t, epx_data) == 0x180, "");
#define usb_dpram ((usb_device_dpram_t *)USBCTRL_DPRAM_BASE)
#define usbh_dpram ((usb_host_dpram_t *)USBCTRL_DPRAM_BASE)
static_assert( USB_HOST_INTERRUPT_ENDPOINTS == 15, "");
#endif // _HARDWARE_STRUCTS_USB_DPRAM_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
#define _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H
/**
* \file rp2040/vreg_and_chip_reset.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/vreg_and_chip_reset.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_vreg_and_chip_reset
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/vreg_and_chip_reset.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(VREG_AND_CHIP_RESET_VREG_OFFSET) // VREG_AND_CHIP_RESET_VREG
// Voltage regulator control and status
// 0x00001000 [12] ROK (0) regulation status +
// 0x000000f0 [7:4] VSEL (0xb) output voltage select +
// 0x00000002 [1] HIZ (0) high impedance mode select +
// 0x00000001 [0] EN (1) enable +
io_rw_32 vreg;
_REG_(VREG_AND_CHIP_RESET_BOD_OFFSET) // VREG_AND_CHIP_RESET_BOD
// brown-out detection control
// 0x000000f0 [7:4] VSEL (0x9) threshold select +
// 0x00000001 [0] EN (1) enable +
io_rw_32 bod;
_REG_(VREG_AND_CHIP_RESET_CHIP_RESET_OFFSET) // VREG_AND_CHIP_RESET_CHIP_RESET
// Chip reset control and status
// 0x01000000 [24] PSM_RESTART_FLAG (0) This is set by psm_restart from the debugger
// 0x00100000 [20] HAD_PSM_RESTART (0) Last reset was from the debug port
// 0x00010000 [16] HAD_RUN (0) Last reset was from the RUN pin
// 0x00000100 [8] HAD_POR (0) Last reset was from the power-on reset or brown-out...
io_rw_32 chip_reset;
} vreg_and_chip_reset_hw_t;
#define vreg_and_chip_reset_hw ((vreg_and_chip_reset_hw_t *)VREG_AND_CHIP_RESET_BASE)
static_assert(sizeof (vreg_and_chip_reset_hw_t) == 0x000c, "");
#endif // _HARDWARE_STRUCTS_VREG_AND_CHIP_RESET_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_WATCHDOG_H
#define _HARDWARE_STRUCTS_WATCHDOG_H
/**
* \file rp2040/watchdog.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/watchdog.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_watchdog
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/watchdog.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(WATCHDOG_CTRL_OFFSET) // WATCHDOG_CTRL
// Watchdog control
// 0x80000000 [31] TRIGGER (0) Trigger a watchdog reset
// 0x40000000 [30] ENABLE (0) When not enabled the watchdog timer is paused
// 0x04000000 [26] PAUSE_DBG1 (1) Pause the watchdog timer when processor 1 is in debug mode
// 0x02000000 [25] PAUSE_DBG0 (1) Pause the watchdog timer when processor 0 is in debug mode
// 0x01000000 [24] PAUSE_JTAG (1) Pause the watchdog timer when JTAG is accessing the bus fabric
// 0x00ffffff [23:0] TIME (0x000000) Indicates the number of ticks / 2 (see errata RP2040-E1)...
io_rw_32 ctrl;
_REG_(WATCHDOG_LOAD_OFFSET) // WATCHDOG_LOAD
// Load the watchdog timer.
// 0x00ffffff [23:0] LOAD (0x000000)
io_wo_32 load;
_REG_(WATCHDOG_REASON_OFFSET) // WATCHDOG_REASON
// Logs the reason for the last reset.
// 0x00000002 [1] FORCE (0)
// 0x00000001 [0] TIMER (0)
io_ro_32 reason;
// (Description copied from array index 0 register WATCHDOG_SCRATCH0 applies similarly to other array indexes)
_REG_(WATCHDOG_SCRATCH0_OFFSET) // WATCHDOG_SCRATCH0
// Scratch register
// 0xffffffff [31:0] SCRATCH0 (0x00000000)
io_rw_32 scratch[8];
_REG_(WATCHDOG_TICK_OFFSET) // WATCHDOG_TICK
// Controls the tick generator
// 0x000ff800 [19:11] COUNT (-) Count down timer: the remaining number clk_tick cycles...
// 0x00000400 [10] RUNNING (-) Is the tick generator running?
// 0x00000200 [9] ENABLE (1) start / stop tick generation
// 0x000001ff [8:0] CYCLES (0x000) Total number of clk_tick cycles before the next tick
io_rw_32 tick;
} watchdog_hw_t;
#define watchdog_hw ((watchdog_hw_t *)WATCHDOG_BASE)
static_assert(sizeof (watchdog_hw_t) == 0x0030, "");
#endif // _HARDWARE_STRUCTS_WATCHDOG_H

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_XIP_H
#define _HARDWARE_STRUCTS_XIP_H
/**
* \file rp2040/xip.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/xip.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xip
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/xip.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
typedef struct {
_REG_(XIP_CTRL_OFFSET) // XIP_CTRL
// Cache control
// 0x00000008 [3] POWER_DOWN (0) When 1, the cache memories are powered down
// 0x00000002 [1] ERR_BADWRITE (1) When 1, writes to any alias other than 0x0 (caching,...
// 0x00000001 [0] EN (1) When 1, enable the cache
io_rw_32 ctrl;
_REG_(XIP_FLUSH_OFFSET) // XIP_FLUSH
// Cache Flush control
// 0x00000001 [0] FLUSH (0) Write 1 to flush the cache
io_wo_32 flush;
_REG_(XIP_STAT_OFFSET) // XIP_STAT
// Cache Status
// 0x00000004 [2] FIFO_FULL (0) When 1, indicates the XIP streaming FIFO is completely full
// 0x00000002 [1] FIFO_EMPTY (1) When 1, indicates the XIP streaming FIFO is completely empty
// 0x00000001 [0] FLUSH_READY (0) Reads as 0 while a cache flush is in progress, and 1 otherwise
io_ro_32 stat;
_REG_(XIP_CTR_HIT_OFFSET) // XIP_CTR_HIT
// Cache Hit counter
// 0xffffffff [31:0] CTR_HIT (0x00000000) A 32 bit saturating counter that increments upon each...
io_rw_32 ctr_hit;
_REG_(XIP_CTR_ACC_OFFSET) // XIP_CTR_ACC
// Cache Access counter
// 0xffffffff [31:0] CTR_ACC (0x00000000) A 32 bit saturating counter that increments upon each...
io_rw_32 ctr_acc;
_REG_(XIP_STREAM_ADDR_OFFSET) // XIP_STREAM_ADDR
// FIFO stream address
// 0xfffffffc [31:2] STREAM_ADDR (0x00000000) The address of the next word to be streamed from flash...
io_rw_32 stream_addr;
_REG_(XIP_STREAM_CTR_OFFSET) // XIP_STREAM_CTR
// FIFO stream control
// 0x003fffff [21:0] STREAM_CTR (0x000000) Write a nonzero value to start a streaming read
io_rw_32 stream_ctr;
_REG_(XIP_STREAM_FIFO_OFFSET) // XIP_STREAM_FIFO
// FIFO stream data
// 0xffffffff [31:0] STREAM_FIFO (0x00000000) Streamed data is buffered here, for retrieval by the system DMA
io_ro_32 stream_fifo;
} xip_ctrl_hw_t;
#define xip_ctrl_hw ((xip_ctrl_hw_t *)XIP_CTRL_BASE)
static_assert(sizeof (xip_ctrl_hw_t) == 0x0020, "");
#endif // _HARDWARE_STRUCTS_XIP_H

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/**
* Copyright (c) 2024 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// Support old header for compatibility (and if included, support old variable name)
#include "hardware/structs/xip.h"
#define XIP_STAT_FIFO_FULL XIP_STAT_FIFO_FULL_BITS
#define XIP_STAT_FIFO_EMPTY XIP_STAT_FIFO_EMPTY_BITS
#define XIP_STAT_FLUSH_RDY XIP_STAT_FLUSH_READY_BITS

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// THIS HEADER FILE IS AUTOMATICALLY GENERATED -- DO NOT EDIT
/**
* Copyright (c) 2024 Raspberry Pi Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HARDWARE_STRUCTS_XOSC_H
#define _HARDWARE_STRUCTS_XOSC_H
/**
* \file rp2040/xosc.h
*/
#include "hardware/address_mapped.h"
#include "hardware/regs/xosc.h"
// Reference to datasheet: https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf#tab-registerlist_xosc
//
// The _REG_ macro is intended to help make the register navigable in your IDE (for example, using the "Go to Definition" feature)
// _REG_(x) will link to the corresponding register in hardware/regs/xosc.h.
//
// Bit-field descriptions are of the form:
// BITMASK [BITRANGE] FIELDNAME (RESETVALUE) DESCRIPTION
/// \tag::xosc_hw[]
typedef struct {
_REG_(XOSC_CTRL_OFFSET) // XOSC_CTRL
// Crystal Oscillator Control
// 0x00fff000 [23:12] ENABLE (-) On power-up this field is initialised to DISABLE and the...
// 0x00000fff [11:0] FREQ_RANGE (-) Frequency range
io_rw_32 ctrl;
_REG_(XOSC_STATUS_OFFSET) // XOSC_STATUS
// Crystal Oscillator Status
// 0x80000000 [31] STABLE (0) Oscillator is running and stable
// 0x01000000 [24] BADWRITE (0) An invalid value has been written to CTRL_ENABLE or...
// 0x00001000 [12] ENABLED (-) Oscillator is enabled but not necessarily running and...
// 0x00000003 [1:0] FREQ_RANGE (-) The current frequency range setting, always reads 0
io_rw_32 status;
_REG_(XOSC_DORMANT_OFFSET) // XOSC_DORMANT
// Crystal Oscillator pause control
// 0xffffffff [31:0] DORMANT (-) This is used to save power by pausing the XOSC +
io_rw_32 dormant;
_REG_(XOSC_STARTUP_OFFSET) // XOSC_STARTUP
// Controls the startup delay
// 0x00100000 [20] X4 (-) Multiplies the startup_delay by 4
// 0x00003fff [13:0] DELAY (-) in multiples of 256*xtal_period
io_rw_32 startup;
uint32_t _pad0[3];
_REG_(XOSC_COUNT_OFFSET) // XOSC_COUNT
// A down counter running at the XOSC frequency which counts to zero and stops.
// 0x000000ff [7:0] COUNT (0x00)
io_rw_32 count;
} xosc_hw_t;
/// \end::xosc_hw[]
#define xosc_hw ((xosc_hw_t *)XOSC_BASE)
static_assert(sizeof (xosc_hw_t) == 0x0020, "");
#endif // _HARDWARE_STRUCTS_XOSC_H