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stm32: Allow external crystal speed to be customized in Kconfig

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2019-11-25 14:00:30 -05:00
parent 0b0e5a911e
commit bd6c25c9f8
4 changed files with 60 additions and 55 deletions
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14
src/stm32/stm32f0.c
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@ -4,7 +4,7 @@
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h" // CONFIG_CLOCK_REF_8M
#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
#include "board/armcm_boot.h" // armcm_main
#include "board/irq.h" // irq_disable
#include "command.h" // DECL_CONSTANT_STR
@ -99,7 +99,7 @@ usb_request_bootloader(void)
NVIC_SystemReset();
}
#if CONFIG_CLOCK_REF_8M
#if !CONFIG_STM32_CLOCK_REF_INTERNAL
DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PF0,PF1");
#endif
@ -108,13 +108,15 @@ static void
pll_setup(void)
{
uint32_t cfgr;
if (CONFIG_CLOCK_REF_8M) {
// Configure 48Mhz PLL from external 8Mhz crystal (HSE)
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 48Mhz PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ;
RCC->CR |= RCC_CR_HSEON;
cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((6 - 2) << RCC_CFGR_PLLMUL_Pos);
cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((div - 2) << RCC_CFGR_PLLMUL_Pos);
} else {
// Configure 48Mhz PLL from internal 8Mhz oscillator (HSI)
cfgr = RCC_CFGR_PLLSRC_HSI_DIV2 | ((12 - 2) << RCC_CFGR_PLLMUL_Pos);
uint32_t div2 = (CONFIG_CLOCK_FREQ / 8000000) * 2;
cfgr = RCC_CFGR_PLLSRC_HSI_DIV2 | ((div2 - 2) << RCC_CFGR_PLLMUL_Pos);
}
RCC->CFGR = cfgr;
RCC->CR |= RCC_CR_PLLON;