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ldc1612: enable frequency div to reduce noise
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BTT Eddy uses 12MHz clock in frequency.
Coil is oscillating at 3+MHz.
Which is out of spec for LDC1612 sensors.
Division of coil frequency seems to reduce output noise.

Signed-off-by: Timofey Titovets <nefelim4ag@gmail.com>
This commit is contained in:
Timofey Titovets 2026-01-02 23:44:43 +01:00 • committed by KevinOConnor
parent e60fe3d99b
commit abda66d6ef
1 changed files with 11 additions and 7 deletions
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18
klippy/extras/ldc1612.py
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@ -87,8 +87,12 @@ class LDC1612:
self.oid = oid = mcu.create_oid()
self.query_ldc1612_cmd = None
self.ldc1612_setup_home_cmd = self.query_ldc1612_home_state_cmd = None
self.frequency = config.getint("frequency", DEFAULT_LDC1612_FREQ,
2000000, 40000000)
self.clock_freq = config.getint("frequency", DEFAULT_LDC1612_FREQ,
2000000, 40000000)
# Coil frequency divider, assume 12MHz is BTT Eddy
# BTT Eddy's coil frequency is > 1/4 of reference clock
self.sensor_div = 1 if self.clock_freq != DEFAULT_LDC1612_FREQ else 2
self.freq_conv = float(self.clock_freq * self.sensor_div) / (1<<28)
if config.get('intb_pin', None) is not None:
ppins = config.get_printer().lookup_object("pins")
pin_params = ppins.lookup_pin(config.get('intb_pin'))
@ -143,7 +147,7 @@ class LDC1612:
def setup_home(self, print_time, trigger_freq,
trsync_oid, hit_reason, err_reason):
clock = self.mcu.print_time_to_clock(print_time)
tfreq = int(trigger_freq * (1<<28) / float(self.frequency) + 0.5)
tfreq = int(trigger_freq / self.freq_conv + 0.5)
self.ldc1612_setup_home_cmd.send(
[self.oid, clock, tfreq, trsync_oid, hit_reason, err_reason])
def clear_home(self):
@ -155,7 +159,7 @@ class LDC1612:
return self.mcu.clock_to_print_time(tclock)
# Measurement decoding
def _convert_samples(self, samples):
freq_conv = float(self.frequency) / (1<<28)
freq_conv = self.freq_conv
count = 0
for ptime, val in samples:
mv = val & 0x0fffffff
@ -176,11 +180,11 @@ class LDC1612:
"(e.g. faulty wiring) or a faulty ldc1612 chip."
% (manuf_id, dev_id, LDC1612_MANUF_ID, LDC1612_DEV_ID))
# Setup chip in requested query rate
rcount0 = self.frequency / (16. * self.data_rate)
rcount0 = self.clock_freq / (16. * self.data_rate)
self.set_reg(REG_RCOUNT0, int(rcount0 + 0.5))
self.set_reg(REG_OFFSET0, 0)
self.set_reg(REG_SETTLECOUNT0, int(SETTLETIME*self.frequency/16. + .5))
self.set_reg(REG_CLOCK_DIVIDERS0, (1 << 12) | 1)
self.set_reg(REG_SETTLECOUNT0, int(SETTLETIME*self.clock_freq/16. + .5))
self.set_reg(REG_CLOCK_DIVIDERS0, (self.sensor_div << 12) | 1)
self.set_reg(REG_ERROR_CONFIG, (0x1f << 11) | 1)
self.set_reg(REG_MUX_CONFIG, 0x0208 | DEGLITCH)
self.set_reg(REG_CONFIG, 0x001 | (1<<12) | (1<<10) | (1<<9))