From a0615e5e17d701ada93acd59031193a1b231dd7c Mon Sep 17 00:00:00 2001
From: Eric Callahan <arksine.code@gmail.com>
Date: Sat, 6 Nov 2021 11:17:08 -0400
Subject: [PATCH] stm32f4: reset peripherals in enable_pcclock()

Reset peripherals to after enabling to clear stale
registers set by the bootloader.

Signed-off-by:  Eric Callahan <arksine.code@gmail.com>
---
 src/stm32/stm32f4.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/src/stm32/stm32f4.c b/src/stm32/stm32f4.c
index b185d9835..3e5fc2d21 100644
--- a/src/stm32/stm32f4.c
+++ b/src/stm32/stm32f4.c
@@ -24,10 +24,17 @@ enable_pclock(uint32_t periph_base)
         uint32_t pos = (periph_base - APB1PERIPH_BASE) / 0x400;
         RCC->APB1ENR |= (1<<pos);
         RCC->APB1ENR;
+        RCC->APB1RSTR |= (1<<pos);
+        RCC->APB1RSTR &= ~(1<<pos);
     } else if (periph_base < AHB1PERIPH_BASE) {
         uint32_t pos = (periph_base - APB2PERIPH_BASE) / 0x400;
         RCC->APB2ENR |= (1<<pos);
         RCC->APB2ENR;
+        // Skip ADC peripheral reset as they share a bit
+        if (pos < 8 || pos > 10) {
+            RCC->APB2RSTR |= (1<<pos);
+            RCC->APB2RSTR &= ~(1<<pos);
+        }
     } else if (periph_base < AHB2PERIPH_BASE) {
         uint32_t pos = (periph_base - AHB1PERIPH_BASE) / 0x400;
         RCC->AHB1ENR |= (1<<pos);