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lib: Add Atmel SAM E70 headers
Signed-off-by: Alex Maclean <monkeh@monkeh.net>
This commit is contained in:
Alex Maclean
Kevin O'Connor
parent
befb503cf0
commit
99c2bf0ded
127 changed files with 77351 additions and 0 deletions
73
lib/same70b/include/instance/acc.h
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73
lib/same70b/include/instance/acc.h
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/**
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* \file
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*
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* \brief Instance description for ACC
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_ACC_INSTANCE_H_
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#define _SAME70_ACC_INSTANCE_H_
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/* ========== Register definition for ACC peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_ACC_CR (0x40044000) /**< (ACC) Control Register */
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#define REG_ACC_MR (0x40044004) /**< (ACC) Mode Register */
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#define REG_ACC_IER (0x40044024) /**< (ACC) Interrupt Enable Register */
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#define REG_ACC_IDR (0x40044028) /**< (ACC) Interrupt Disable Register */
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#define REG_ACC_IMR (0x4004402C) /**< (ACC) Interrupt Mask Register */
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#define REG_ACC_ISR (0x40044030) /**< (ACC) Interrupt Status Register */
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#define REG_ACC_ACR (0x40044094) /**< (ACC) Analog Control Register */
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#define REG_ACC_WPMR (0x400440E4) /**< (ACC) Write Protection Mode Register */
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#define REG_ACC_WPSR (0x400440E8) /**< (ACC) Write Protection Status Register */
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#else
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#define REG_ACC_CR (*(__O uint32_t*)0x40044000U) /**< (ACC) Control Register */
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#define REG_ACC_MR (*(__IO uint32_t*)0x40044004U) /**< (ACC) Mode Register */
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#define REG_ACC_IER (*(__O uint32_t*)0x40044024U) /**< (ACC) Interrupt Enable Register */
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#define REG_ACC_IDR (*(__O uint32_t*)0x40044028U) /**< (ACC) Interrupt Disable Register */
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#define REG_ACC_IMR (*(__I uint32_t*)0x4004402CU) /**< (ACC) Interrupt Mask Register */
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#define REG_ACC_ISR (*(__I uint32_t*)0x40044030U) /**< (ACC) Interrupt Status Register */
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#define REG_ACC_ACR (*(__IO uint32_t*)0x40044094U) /**< (ACC) Analog Control Register */
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#define REG_ACC_WPMR (*(__IO uint32_t*)0x400440E4U) /**< (ACC) Write Protection Mode Register */
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#define REG_ACC_WPSR (*(__I uint32_t*)0x400440E8U) /**< (ACC) Write Protection Status Register */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for ACC peripheral ========== */
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#define ACC_INSTANCE_ID 33
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#define ACC_CLOCK_ID 33
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#define ACC_HAS_PLUS_COMPARATOR_SELECTION 1
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#define ACC_HAS_MINUS_COMPARATOR_SELECTION 1
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#define ACC_HAS_INVERTED_COMPARATOR 1
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#define ACC_HAS_EDGETYPE_SELECTION 1
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#define ACC_HAS_INTERRUPTS 1
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#define ACC_HAS_CURRENT_SELECTION 1
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#define ACC_HAS_HYSTERESIS 1
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#define ACC_HAS_FAULT_ENABLE 1
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#endif /* _SAME70_ACC_INSTANCE_ */
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145
lib/same70b/include/instance/aes.h
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145
lib/same70b/include/instance/aes.h
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/**
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* \file
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*
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* \brief Instance description for AES
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_AES_INSTANCE_H_
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#define _SAME70_AES_INSTANCE_H_
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/* ========== Register definition for AES peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_AES_CR (0x4006C000) /**< (AES) Control Register */
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#define REG_AES_MR (0x4006C004) /**< (AES) Mode Register */
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#define REG_AES_IER (0x4006C010) /**< (AES) Interrupt Enable Register */
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#define REG_AES_IDR (0x4006C014) /**< (AES) Interrupt Disable Register */
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#define REG_AES_IMR (0x4006C018) /**< (AES) Interrupt Mask Register */
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#define REG_AES_ISR (0x4006C01C) /**< (AES) Interrupt Status Register */
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#define REG_AES_KEYWR (0x4006C020) /**< (AES) Key Word Register */
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#define REG_AES_KEYWR0 (0x4006C020) /**< (AES) Key Word Register 0 */
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#define REG_AES_KEYWR1 (0x4006C024) /**< (AES) Key Word Register 1 */
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#define REG_AES_KEYWR2 (0x4006C028) /**< (AES) Key Word Register 2 */
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#define REG_AES_KEYWR3 (0x4006C02C) /**< (AES) Key Word Register 3 */
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#define REG_AES_KEYWR4 (0x4006C030) /**< (AES) Key Word Register 4 */
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#define REG_AES_KEYWR5 (0x4006C034) /**< (AES) Key Word Register 5 */
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#define REG_AES_KEYWR6 (0x4006C038) /**< (AES) Key Word Register 6 */
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#define REG_AES_KEYWR7 (0x4006C03C) /**< (AES) Key Word Register 7 */
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#define REG_AES_IDATAR (0x4006C040) /**< (AES) Input Data Register */
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#define REG_AES_IDATAR0 (0x4006C040) /**< (AES) Input Data Register 0 */
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#define REG_AES_IDATAR1 (0x4006C044) /**< (AES) Input Data Register 1 */
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#define REG_AES_IDATAR2 (0x4006C048) /**< (AES) Input Data Register 2 */
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#define REG_AES_IDATAR3 (0x4006C04C) /**< (AES) Input Data Register 3 */
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#define REG_AES_ODATAR (0x4006C050) /**< (AES) Output Data Register */
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#define REG_AES_ODATAR0 (0x4006C050) /**< (AES) Output Data Register 0 */
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#define REG_AES_ODATAR1 (0x4006C054) /**< (AES) Output Data Register 1 */
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#define REG_AES_ODATAR2 (0x4006C058) /**< (AES) Output Data Register 2 */
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#define REG_AES_ODATAR3 (0x4006C05C) /**< (AES) Output Data Register 3 */
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#define REG_AES_IVR (0x4006C060) /**< (AES) Initialization Vector Register */
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#define REG_AES_IVR0 (0x4006C060) /**< (AES) Initialization Vector Register 0 */
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#define REG_AES_IVR1 (0x4006C064) /**< (AES) Initialization Vector Register 1 */
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#define REG_AES_IVR2 (0x4006C068) /**< (AES) Initialization Vector Register 2 */
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#define REG_AES_IVR3 (0x4006C06C) /**< (AES) Initialization Vector Register 3 */
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#define REG_AES_AADLENR (0x4006C070) /**< (AES) Additional Authenticated Data Length Register */
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#define REG_AES_CLENR (0x4006C074) /**< (AES) Plaintext/Ciphertext Length Register */
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#define REG_AES_GHASHR (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register */
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#define REG_AES_GHASHR0 (0x4006C078) /**< (AES) GCM Intermediate Hash Word Register 0 */
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#define REG_AES_GHASHR1 (0x4006C07C) /**< (AES) GCM Intermediate Hash Word Register 1 */
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#define REG_AES_GHASHR2 (0x4006C080) /**< (AES) GCM Intermediate Hash Word Register 2 */
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#define REG_AES_GHASHR3 (0x4006C084) /**< (AES) GCM Intermediate Hash Word Register 3 */
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#define REG_AES_TAGR (0x4006C088) /**< (AES) GCM Authentication Tag Word Register */
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#define REG_AES_TAGR0 (0x4006C088) /**< (AES) GCM Authentication Tag Word Register 0 */
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#define REG_AES_TAGR1 (0x4006C08C) /**< (AES) GCM Authentication Tag Word Register 1 */
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#define REG_AES_TAGR2 (0x4006C090) /**< (AES) GCM Authentication Tag Word Register 2 */
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#define REG_AES_TAGR3 (0x4006C094) /**< (AES) GCM Authentication Tag Word Register 3 */
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#define REG_AES_CTRR (0x4006C098) /**< (AES) GCM Encryption Counter Value Register */
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#define REG_AES_GCMHR (0x4006C09C) /**< (AES) GCM H Word Register */
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#define REG_AES_GCMHR0 (0x4006C09C) /**< (AES) GCM H Word Register 0 */
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#define REG_AES_GCMHR1 (0x4006C0A0) /**< (AES) GCM H Word Register 1 */
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#define REG_AES_GCMHR2 (0x4006C0A4) /**< (AES) GCM H Word Register 2 */
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#define REG_AES_GCMHR3 (0x4006C0A8) /**< (AES) GCM H Word Register 3 */
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#else
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#define REG_AES_CR (*(__O uint32_t*)0x4006C000U) /**< (AES) Control Register */
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#define REG_AES_MR (*(__IO uint32_t*)0x4006C004U) /**< (AES) Mode Register */
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#define REG_AES_IER (*(__O uint32_t*)0x4006C010U) /**< (AES) Interrupt Enable Register */
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#define REG_AES_IDR (*(__O uint32_t*)0x4006C014U) /**< (AES) Interrupt Disable Register */
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#define REG_AES_IMR (*(__I uint32_t*)0x4006C018U) /**< (AES) Interrupt Mask Register */
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#define REG_AES_ISR (*(__I uint32_t*)0x4006C01CU) /**< (AES) Interrupt Status Register */
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#define REG_AES_KEYWR (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register */
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#define REG_AES_KEYWR0 (*(__O uint32_t*)0x4006C020U) /**< (AES) Key Word Register 0 */
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#define REG_AES_KEYWR1 (*(__O uint32_t*)0x4006C024U) /**< (AES) Key Word Register 1 */
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#define REG_AES_KEYWR2 (*(__O uint32_t*)0x4006C028U) /**< (AES) Key Word Register 2 */
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#define REG_AES_KEYWR3 (*(__O uint32_t*)0x4006C02CU) /**< (AES) Key Word Register 3 */
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#define REG_AES_KEYWR4 (*(__O uint32_t*)0x4006C030U) /**< (AES) Key Word Register 4 */
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#define REG_AES_KEYWR5 (*(__O uint32_t*)0x4006C034U) /**< (AES) Key Word Register 5 */
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#define REG_AES_KEYWR6 (*(__O uint32_t*)0x4006C038U) /**< (AES) Key Word Register 6 */
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#define REG_AES_KEYWR7 (*(__O uint32_t*)0x4006C03CU) /**< (AES) Key Word Register 7 */
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#define REG_AES_IDATAR (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register */
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#define REG_AES_IDATAR0 (*(__O uint32_t*)0x4006C040U) /**< (AES) Input Data Register 0 */
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#define REG_AES_IDATAR1 (*(__O uint32_t*)0x4006C044U) /**< (AES) Input Data Register 1 */
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#define REG_AES_IDATAR2 (*(__O uint32_t*)0x4006C048U) /**< (AES) Input Data Register 2 */
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#define REG_AES_IDATAR3 (*(__O uint32_t*)0x4006C04CU) /**< (AES) Input Data Register 3 */
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#define REG_AES_ODATAR (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register */
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#define REG_AES_ODATAR0 (*(__I uint32_t*)0x4006C050U) /**< (AES) Output Data Register 0 */
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#define REG_AES_ODATAR1 (*(__I uint32_t*)0x4006C054U) /**< (AES) Output Data Register 1 */
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#define REG_AES_ODATAR2 (*(__I uint32_t*)0x4006C058U) /**< (AES) Output Data Register 2 */
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#define REG_AES_ODATAR3 (*(__I uint32_t*)0x4006C05CU) /**< (AES) Output Data Register 3 */
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#define REG_AES_IVR (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register */
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#define REG_AES_IVR0 (*(__O uint32_t*)0x4006C060U) /**< (AES) Initialization Vector Register 0 */
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#define REG_AES_IVR1 (*(__O uint32_t*)0x4006C064U) /**< (AES) Initialization Vector Register 1 */
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#define REG_AES_IVR2 (*(__O uint32_t*)0x4006C068U) /**< (AES) Initialization Vector Register 2 */
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#define REG_AES_IVR3 (*(__O uint32_t*)0x4006C06CU) /**< (AES) Initialization Vector Register 3 */
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#define REG_AES_AADLENR (*(__IO uint32_t*)0x4006C070U) /**< (AES) Additional Authenticated Data Length Register */
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#define REG_AES_CLENR (*(__IO uint32_t*)0x4006C074U) /**< (AES) Plaintext/Ciphertext Length Register */
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#define REG_AES_GHASHR (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register */
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#define REG_AES_GHASHR0 (*(__IO uint32_t*)0x4006C078U) /**< (AES) GCM Intermediate Hash Word Register 0 */
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#define REG_AES_GHASHR1 (*(__IO uint32_t*)0x4006C07CU) /**< (AES) GCM Intermediate Hash Word Register 1 */
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#define REG_AES_GHASHR2 (*(__IO uint32_t*)0x4006C080U) /**< (AES) GCM Intermediate Hash Word Register 2 */
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#define REG_AES_GHASHR3 (*(__IO uint32_t*)0x4006C084U) /**< (AES) GCM Intermediate Hash Word Register 3 */
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#define REG_AES_TAGR (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register */
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#define REG_AES_TAGR0 (*(__I uint32_t*)0x4006C088U) /**< (AES) GCM Authentication Tag Word Register 0 */
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#define REG_AES_TAGR1 (*(__I uint32_t*)0x4006C08CU) /**< (AES) GCM Authentication Tag Word Register 1 */
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#define REG_AES_TAGR2 (*(__I uint32_t*)0x4006C090U) /**< (AES) GCM Authentication Tag Word Register 2 */
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#define REG_AES_TAGR3 (*(__I uint32_t*)0x4006C094U) /**< (AES) GCM Authentication Tag Word Register 3 */
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#define REG_AES_CTRR (*(__I uint32_t*)0x4006C098U) /**< (AES) GCM Encryption Counter Value Register */
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#define REG_AES_GCMHR (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register */
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#define REG_AES_GCMHR0 (*(__IO uint32_t*)0x4006C09CU) /**< (AES) GCM H Word Register 0 */
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#define REG_AES_GCMHR1 (*(__IO uint32_t*)0x4006C0A0U) /**< (AES) GCM H Word Register 1 */
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#define REG_AES_GCMHR2 (*(__IO uint32_t*)0x4006C0A4U) /**< (AES) GCM H Word Register 2 */
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#define REG_AES_GCMHR3 (*(__IO uint32_t*)0x4006C0A8U) /**< (AES) GCM H Word Register 3 */
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#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
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/* ========== Instance Parameter definitions for AES peripheral ========== */
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#define AES_DMAC_ID_TX 37
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#define AES_DMAC_ID_RX 38
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#define AES_INSTANCE_ID 56
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#define AES_CLOCK_ID 56
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#endif /* _SAME70_AES_INSTANCE_ */
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113
lib/same70b/include/instance/afec0.h
Normal file
113
lib/same70b/include/instance/afec0.h
Normal file
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@ -0,0 +1,113 @@
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/**
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* \file
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*
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* \brief Instance description for AFEC0
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*
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* Copyright (c) 2019 Microchip Technology Inc.
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*
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* \license_start
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*
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* \page License
|
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
|
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*
|
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS,
|
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
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* limitations under the License.
|
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*
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* \license_stop
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*
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*/
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/* file generated from device description version 2019-01-18T21:19:59Z */
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#ifndef _SAME70_AFEC0_INSTANCE_H_
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#define _SAME70_AFEC0_INSTANCE_H_
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/* ========== Register definition for AFEC0 peripheral ========== */
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#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
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#define REG_AFEC0_CR (0x4003C000) /**< (AFEC0) AFEC Control Register */
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#define REG_AFEC0_MR (0x4003C004) /**< (AFEC0) AFEC Mode Register */
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#define REG_AFEC0_EMR (0x4003C008) /**< (AFEC0) AFEC Extended Mode Register */
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#define REG_AFEC0_SEQ1R (0x4003C00C) /**< (AFEC0) AFEC Channel Sequence 1 Register */
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#define REG_AFEC0_SEQ2R (0x4003C010) /**< (AFEC0) AFEC Channel Sequence 2 Register */
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#define REG_AFEC0_CHER (0x4003C014) /**< (AFEC0) AFEC Channel Enable Register */
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#define REG_AFEC0_CHDR (0x4003C018) /**< (AFEC0) AFEC Channel Disable Register */
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#define REG_AFEC0_CHSR (0x4003C01C) /**< (AFEC0) AFEC Channel Status Register */
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#define REG_AFEC0_LCDR (0x4003C020) /**< (AFEC0) AFEC Last Converted Data Register */
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#define REG_AFEC0_IER (0x4003C024) /**< (AFEC0) AFEC Interrupt Enable Register */
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#define REG_AFEC0_IDR (0x4003C028) /**< (AFEC0) AFEC Interrupt Disable Register */
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#define REG_AFEC0_IMR (0x4003C02C) /**< (AFEC0) AFEC Interrupt Mask Register */
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#define REG_AFEC0_ISR (0x4003C030) /**< (AFEC0) AFEC Interrupt Status Register */
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#define REG_AFEC0_OVER (0x4003C04C) /**< (AFEC0) AFEC Overrun Status Register */
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#define REG_AFEC0_CWR (0x4003C050) /**< (AFEC0) AFEC Compare Window Register */
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#define REG_AFEC0_CGR (0x4003C054) /**< (AFEC0) AFEC Channel Gain Register */
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#define REG_AFEC0_DIFFR (0x4003C060) /**< (AFEC0) AFEC Channel Differential Register */
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#define REG_AFEC0_CSELR (0x4003C064) /**< (AFEC0) AFEC Channel Selection Register */
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#define REG_AFEC0_CDR (0x4003C068) /**< (AFEC0) AFEC Channel Data Register */
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#define REG_AFEC0_COCR (0x4003C06C) /**< (AFEC0) AFEC Channel Offset Compensation Register */
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#define REG_AFEC0_TEMPMR (0x4003C070) /**< (AFEC0) AFEC Temperature Sensor Mode Register */
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#define REG_AFEC0_TEMPCWR (0x4003C074) /**< (AFEC0) AFEC Temperature Compare Window Register */
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#define REG_AFEC0_ACR (0x4003C094) /**< (AFEC0) AFEC Analog Control Register */
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#define REG_AFEC0_SHMR (0x4003C0A0) /**< (AFEC0) AFEC Sample & Hold Mode Register */
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#define REG_AFEC0_COSR (0x4003C0D0) /**< (AFEC0) AFEC Correction Select Register */
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#define REG_AFEC0_CVR (0x4003C0D4) /**< (AFEC0) AFEC Correction Values Register */
|
||||
#define REG_AFEC0_CECR (0x4003C0D8) /**< (AFEC0) AFEC Channel Error Correction Register */
|
||||
#define REG_AFEC0_WPMR (0x4003C0E4) /**< (AFEC0) AFEC Write Protection Mode Register */
|
||||
#define REG_AFEC0_WPSR (0x4003C0E8) /**< (AFEC0) AFEC Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_AFEC0_CR (*(__O uint32_t*)0x4003C000U) /**< (AFEC0) AFEC Control Register */
|
||||
#define REG_AFEC0_MR (*(__IO uint32_t*)0x4003C004U) /**< (AFEC0) AFEC Mode Register */
|
||||
#define REG_AFEC0_EMR (*(__IO uint32_t*)0x4003C008U) /**< (AFEC0) AFEC Extended Mode Register */
|
||||
#define REG_AFEC0_SEQ1R (*(__IO uint32_t*)0x4003C00CU) /**< (AFEC0) AFEC Channel Sequence 1 Register */
|
||||
#define REG_AFEC0_SEQ2R (*(__IO uint32_t*)0x4003C010U) /**< (AFEC0) AFEC Channel Sequence 2 Register */
|
||||
#define REG_AFEC0_CHER (*(__O uint32_t*)0x4003C014U) /**< (AFEC0) AFEC Channel Enable Register */
|
||||
#define REG_AFEC0_CHDR (*(__O uint32_t*)0x4003C018U) /**< (AFEC0) AFEC Channel Disable Register */
|
||||
#define REG_AFEC0_CHSR (*(__I uint32_t*)0x4003C01CU) /**< (AFEC0) AFEC Channel Status Register */
|
||||
#define REG_AFEC0_LCDR (*(__I uint32_t*)0x4003C020U) /**< (AFEC0) AFEC Last Converted Data Register */
|
||||
#define REG_AFEC0_IER (*(__O uint32_t*)0x4003C024U) /**< (AFEC0) AFEC Interrupt Enable Register */
|
||||
#define REG_AFEC0_IDR (*(__O uint32_t*)0x4003C028U) /**< (AFEC0) AFEC Interrupt Disable Register */
|
||||
#define REG_AFEC0_IMR (*(__I uint32_t*)0x4003C02CU) /**< (AFEC0) AFEC Interrupt Mask Register */
|
||||
#define REG_AFEC0_ISR (*(__I uint32_t*)0x4003C030U) /**< (AFEC0) AFEC Interrupt Status Register */
|
||||
#define REG_AFEC0_OVER (*(__I uint32_t*)0x4003C04CU) /**< (AFEC0) AFEC Overrun Status Register */
|
||||
#define REG_AFEC0_CWR (*(__IO uint32_t*)0x4003C050U) /**< (AFEC0) AFEC Compare Window Register */
|
||||
#define REG_AFEC0_CGR (*(__IO uint32_t*)0x4003C054U) /**< (AFEC0) AFEC Channel Gain Register */
|
||||
#define REG_AFEC0_DIFFR (*(__IO uint32_t*)0x4003C060U) /**< (AFEC0) AFEC Channel Differential Register */
|
||||
#define REG_AFEC0_CSELR (*(__IO uint32_t*)0x4003C064U) /**< (AFEC0) AFEC Channel Selection Register */
|
||||
#define REG_AFEC0_CDR (*(__I uint32_t*)0x4003C068U) /**< (AFEC0) AFEC Channel Data Register */
|
||||
#define REG_AFEC0_COCR (*(__IO uint32_t*)0x4003C06CU) /**< (AFEC0) AFEC Channel Offset Compensation Register */
|
||||
#define REG_AFEC0_TEMPMR (*(__IO uint32_t*)0x4003C070U) /**< (AFEC0) AFEC Temperature Sensor Mode Register */
|
||||
#define REG_AFEC0_TEMPCWR (*(__IO uint32_t*)0x4003C074U) /**< (AFEC0) AFEC Temperature Compare Window Register */
|
||||
#define REG_AFEC0_ACR (*(__IO uint32_t*)0x4003C094U) /**< (AFEC0) AFEC Analog Control Register */
|
||||
#define REG_AFEC0_SHMR (*(__IO uint32_t*)0x4003C0A0U) /**< (AFEC0) AFEC Sample & Hold Mode Register */
|
||||
#define REG_AFEC0_COSR (*(__IO uint32_t*)0x4003C0D0U) /**< (AFEC0) AFEC Correction Select Register */
|
||||
#define REG_AFEC0_CVR (*(__IO uint32_t*)0x4003C0D4U) /**< (AFEC0) AFEC Correction Values Register */
|
||||
#define REG_AFEC0_CECR (*(__IO uint32_t*)0x4003C0D8U) /**< (AFEC0) AFEC Channel Error Correction Register */
|
||||
#define REG_AFEC0_WPMR (*(__IO uint32_t*)0x4003C0E4U) /**< (AFEC0) AFEC Write Protection Mode Register */
|
||||
#define REG_AFEC0_WPSR (*(__I uint32_t*)0x4003C0E8U) /**< (AFEC0) AFEC Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for AFEC0 peripheral ========== */
|
||||
#define AFEC0_DMAC_ID_RX 35
|
||||
#define AFEC0_INSTANCE_ID 29
|
||||
#define AFEC0_CLOCK_ID 29
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG0 0x0 /* External ADC Trigger Input (AFE0_ADTRG pin) */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG1 0x1 /* TC0 Channel 0 Output (TIOA0) */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG2 0x2 /* TC0 Channel 1 Output (TIOA1) */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG3 0x3 /* TC0 Channel 2 Output (TIOA2) */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG4 0x4 /* PWM0 event line 0 */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG5 0x5 /* PWM0 event line 1 */
|
||||
#define AFEC0_TRGSEL_AFEC_TRIG6 0x6 /* Analog Comparator Fault Output */
|
||||
|
||||
#endif /* _SAME70_AFEC0_INSTANCE_ */
|
||||
113
lib/same70b/include/instance/afec1.h
Normal file
113
lib/same70b/include/instance/afec1.h
Normal file
|
|
@ -0,0 +1,113 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for AFEC1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_AFEC1_INSTANCE_H_
|
||||
#define _SAME70_AFEC1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for AFEC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_AFEC1_CR (0x40064000) /**< (AFEC1) AFEC Control Register */
|
||||
#define REG_AFEC1_MR (0x40064004) /**< (AFEC1) AFEC Mode Register */
|
||||
#define REG_AFEC1_EMR (0x40064008) /**< (AFEC1) AFEC Extended Mode Register */
|
||||
#define REG_AFEC1_SEQ1R (0x4006400C) /**< (AFEC1) AFEC Channel Sequence 1 Register */
|
||||
#define REG_AFEC1_SEQ2R (0x40064010) /**< (AFEC1) AFEC Channel Sequence 2 Register */
|
||||
#define REG_AFEC1_CHER (0x40064014) /**< (AFEC1) AFEC Channel Enable Register */
|
||||
#define REG_AFEC1_CHDR (0x40064018) /**< (AFEC1) AFEC Channel Disable Register */
|
||||
#define REG_AFEC1_CHSR (0x4006401C) /**< (AFEC1) AFEC Channel Status Register */
|
||||
#define REG_AFEC1_LCDR (0x40064020) /**< (AFEC1) AFEC Last Converted Data Register */
|
||||
#define REG_AFEC1_IER (0x40064024) /**< (AFEC1) AFEC Interrupt Enable Register */
|
||||
#define REG_AFEC1_IDR (0x40064028) /**< (AFEC1) AFEC Interrupt Disable Register */
|
||||
#define REG_AFEC1_IMR (0x4006402C) /**< (AFEC1) AFEC Interrupt Mask Register */
|
||||
#define REG_AFEC1_ISR (0x40064030) /**< (AFEC1) AFEC Interrupt Status Register */
|
||||
#define REG_AFEC1_OVER (0x4006404C) /**< (AFEC1) AFEC Overrun Status Register */
|
||||
#define REG_AFEC1_CWR (0x40064050) /**< (AFEC1) AFEC Compare Window Register */
|
||||
#define REG_AFEC1_CGR (0x40064054) /**< (AFEC1) AFEC Channel Gain Register */
|
||||
#define REG_AFEC1_DIFFR (0x40064060) /**< (AFEC1) AFEC Channel Differential Register */
|
||||
#define REG_AFEC1_CSELR (0x40064064) /**< (AFEC1) AFEC Channel Selection Register */
|
||||
#define REG_AFEC1_CDR (0x40064068) /**< (AFEC1) AFEC Channel Data Register */
|
||||
#define REG_AFEC1_COCR (0x4006406C) /**< (AFEC1) AFEC Channel Offset Compensation Register */
|
||||
#define REG_AFEC1_TEMPMR (0x40064070) /**< (AFEC1) AFEC Temperature Sensor Mode Register */
|
||||
#define REG_AFEC1_TEMPCWR (0x40064074) /**< (AFEC1) AFEC Temperature Compare Window Register */
|
||||
#define REG_AFEC1_ACR (0x40064094) /**< (AFEC1) AFEC Analog Control Register */
|
||||
#define REG_AFEC1_SHMR (0x400640A0) /**< (AFEC1) AFEC Sample & Hold Mode Register */
|
||||
#define REG_AFEC1_COSR (0x400640D0) /**< (AFEC1) AFEC Correction Select Register */
|
||||
#define REG_AFEC1_CVR (0x400640D4) /**< (AFEC1) AFEC Correction Values Register */
|
||||
#define REG_AFEC1_CECR (0x400640D8) /**< (AFEC1) AFEC Channel Error Correction Register */
|
||||
#define REG_AFEC1_WPMR (0x400640E4) /**< (AFEC1) AFEC Write Protection Mode Register */
|
||||
#define REG_AFEC1_WPSR (0x400640E8) /**< (AFEC1) AFEC Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_AFEC1_CR (*(__O uint32_t*)0x40064000U) /**< (AFEC1) AFEC Control Register */
|
||||
#define REG_AFEC1_MR (*(__IO uint32_t*)0x40064004U) /**< (AFEC1) AFEC Mode Register */
|
||||
#define REG_AFEC1_EMR (*(__IO uint32_t*)0x40064008U) /**< (AFEC1) AFEC Extended Mode Register */
|
||||
#define REG_AFEC1_SEQ1R (*(__IO uint32_t*)0x4006400CU) /**< (AFEC1) AFEC Channel Sequence 1 Register */
|
||||
#define REG_AFEC1_SEQ2R (*(__IO uint32_t*)0x40064010U) /**< (AFEC1) AFEC Channel Sequence 2 Register */
|
||||
#define REG_AFEC1_CHER (*(__O uint32_t*)0x40064014U) /**< (AFEC1) AFEC Channel Enable Register */
|
||||
#define REG_AFEC1_CHDR (*(__O uint32_t*)0x40064018U) /**< (AFEC1) AFEC Channel Disable Register */
|
||||
#define REG_AFEC1_CHSR (*(__I uint32_t*)0x4006401CU) /**< (AFEC1) AFEC Channel Status Register */
|
||||
#define REG_AFEC1_LCDR (*(__I uint32_t*)0x40064020U) /**< (AFEC1) AFEC Last Converted Data Register */
|
||||
#define REG_AFEC1_IER (*(__O uint32_t*)0x40064024U) /**< (AFEC1) AFEC Interrupt Enable Register */
|
||||
#define REG_AFEC1_IDR (*(__O uint32_t*)0x40064028U) /**< (AFEC1) AFEC Interrupt Disable Register */
|
||||
#define REG_AFEC1_IMR (*(__I uint32_t*)0x4006402CU) /**< (AFEC1) AFEC Interrupt Mask Register */
|
||||
#define REG_AFEC1_ISR (*(__I uint32_t*)0x40064030U) /**< (AFEC1) AFEC Interrupt Status Register */
|
||||
#define REG_AFEC1_OVER (*(__I uint32_t*)0x4006404CU) /**< (AFEC1) AFEC Overrun Status Register */
|
||||
#define REG_AFEC1_CWR (*(__IO uint32_t*)0x40064050U) /**< (AFEC1) AFEC Compare Window Register */
|
||||
#define REG_AFEC1_CGR (*(__IO uint32_t*)0x40064054U) /**< (AFEC1) AFEC Channel Gain Register */
|
||||
#define REG_AFEC1_DIFFR (*(__IO uint32_t*)0x40064060U) /**< (AFEC1) AFEC Channel Differential Register */
|
||||
#define REG_AFEC1_CSELR (*(__IO uint32_t*)0x40064064U) /**< (AFEC1) AFEC Channel Selection Register */
|
||||
#define REG_AFEC1_CDR (*(__I uint32_t*)0x40064068U) /**< (AFEC1) AFEC Channel Data Register */
|
||||
#define REG_AFEC1_COCR (*(__IO uint32_t*)0x4006406CU) /**< (AFEC1) AFEC Channel Offset Compensation Register */
|
||||
#define REG_AFEC1_TEMPMR (*(__IO uint32_t*)0x40064070U) /**< (AFEC1) AFEC Temperature Sensor Mode Register */
|
||||
#define REG_AFEC1_TEMPCWR (*(__IO uint32_t*)0x40064074U) /**< (AFEC1) AFEC Temperature Compare Window Register */
|
||||
#define REG_AFEC1_ACR (*(__IO uint32_t*)0x40064094U) /**< (AFEC1) AFEC Analog Control Register */
|
||||
#define REG_AFEC1_SHMR (*(__IO uint32_t*)0x400640A0U) /**< (AFEC1) AFEC Sample & Hold Mode Register */
|
||||
#define REG_AFEC1_COSR (*(__IO uint32_t*)0x400640D0U) /**< (AFEC1) AFEC Correction Select Register */
|
||||
#define REG_AFEC1_CVR (*(__IO uint32_t*)0x400640D4U) /**< (AFEC1) AFEC Correction Values Register */
|
||||
#define REG_AFEC1_CECR (*(__IO uint32_t*)0x400640D8U) /**< (AFEC1) AFEC Channel Error Correction Register */
|
||||
#define REG_AFEC1_WPMR (*(__IO uint32_t*)0x400640E4U) /**< (AFEC1) AFEC Write Protection Mode Register */
|
||||
#define REG_AFEC1_WPSR (*(__I uint32_t*)0x400640E8U) /**< (AFEC1) AFEC Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for AFEC1 peripheral ========== */
|
||||
#define AFEC1_DMAC_ID_RX 36
|
||||
#define AFEC1_INSTANCE_ID 40
|
||||
#define AFEC1_CLOCK_ID 40
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG0 0x0 /* External ADC Trigger Input (AFE1_ADTRG Pin) */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG1 0x1 /* TC1 Channel 0 Output (TIOA3) */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG2 0x2 /* TC1 Channel 1 Output (TIOA4) */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG3 0x3 /* TC1 Channel 2 Output (TIOA5) */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG4 0x4 /* PWM1 event line 0 */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG5 0x5 /* PWM1 event line 1 */
|
||||
#define AFEC1_TRGSEL_AFEC_TRIG6 0x6 /* Analog Comparator Fault Output */
|
||||
|
||||
#endif /* _SAME70_AFEC1_INSTANCE_ */
|
||||
46
lib/same70b/include/instance/chipid.h
Normal file
46
lib/same70b/include/instance/chipid.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for CHIPID
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_CHIPID_INSTANCE_H_
|
||||
#define _SAME70_CHIPID_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for CHIPID peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_CHIPID_CIDR (0x400E0940) /**< (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID (0x400E0944) /**< (CHIPID) Chip ID Extension Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_CHIPID_CIDR (*(__I uint32_t*)0x400E0940U) /**< (CHIPID) Chip ID Register */
|
||||
#define REG_CHIPID_EXID (*(__I uint32_t*)0x400E0944U) /**< (CHIPID) Chip ID Extension Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_CHIPID_INSTANCE_ */
|
||||
80
lib/same70b/include/instance/dacc.h
Normal file
80
lib/same70b/include/instance/dacc.h
Normal file
|
|
@ -0,0 +1,80 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for DACC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_DACC_INSTANCE_H_
|
||||
#define _SAME70_DACC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for DACC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_DACC_CR (0x40040000) /**< (DACC) Control Register */
|
||||
#define REG_DACC_MR (0x40040004) /**< (DACC) Mode Register */
|
||||
#define REG_DACC_TRIGR (0x40040008) /**< (DACC) Trigger Register */
|
||||
#define REG_DACC_CHER (0x40040010) /**< (DACC) Channel Enable Register */
|
||||
#define REG_DACC_CHDR (0x40040014) /**< (DACC) Channel Disable Register */
|
||||
#define REG_DACC_CHSR (0x40040018) /**< (DACC) Channel Status Register */
|
||||
#define REG_DACC_CDR (0x4004001C) /**< (DACC) Conversion Data Register 0 */
|
||||
#define REG_DACC_CDR0 (0x4004001C) /**< (DACC) Conversion Data Register 0 */
|
||||
#define REG_DACC_CDR1 (0x40040020) /**< (DACC) Conversion Data Register 1 */
|
||||
#define REG_DACC_IER (0x40040024) /**< (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR (0x40040028) /**< (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR (0x4004002C) /**< (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR (0x40040030) /**< (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_ACR (0x40040094) /**< (DACC) Analog Current Register */
|
||||
#define REG_DACC_WPMR (0x400400E4) /**< (DACC) Write Protection Mode Register */
|
||||
#define REG_DACC_WPSR (0x400400E8) /**< (DACC) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_DACC_CR (*(__O uint32_t*)0x40040000U) /**< (DACC) Control Register */
|
||||
#define REG_DACC_MR (*(__IO uint32_t*)0x40040004U) /**< (DACC) Mode Register */
|
||||
#define REG_DACC_TRIGR (*(__IO uint32_t*)0x40040008U) /**< (DACC) Trigger Register */
|
||||
#define REG_DACC_CHER (*(__O uint32_t*)0x40040010U) /**< (DACC) Channel Enable Register */
|
||||
#define REG_DACC_CHDR (*(__O uint32_t*)0x40040014U) /**< (DACC) Channel Disable Register */
|
||||
#define REG_DACC_CHSR (*(__I uint32_t*)0x40040018U) /**< (DACC) Channel Status Register */
|
||||
#define REG_DACC_CDR (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */
|
||||
#define REG_DACC_CDR0 (*(__O uint32_t*)0x4004001CU) /**< (DACC) Conversion Data Register 0 */
|
||||
#define REG_DACC_CDR1 (*(__O uint32_t*)0x40040020U) /**< (DACC) Conversion Data Register 1 */
|
||||
#define REG_DACC_IER (*(__O uint32_t*)0x40040024U) /**< (DACC) Interrupt Enable Register */
|
||||
#define REG_DACC_IDR (*(__O uint32_t*)0x40040028U) /**< (DACC) Interrupt Disable Register */
|
||||
#define REG_DACC_IMR (*(__I uint32_t*)0x4004002CU) /**< (DACC) Interrupt Mask Register */
|
||||
#define REG_DACC_ISR (*(__I uint32_t*)0x40040030U) /**< (DACC) Interrupt Status Register */
|
||||
#define REG_DACC_ACR (*(__IO uint32_t*)0x40040094U) /**< (DACC) Analog Current Register */
|
||||
#define REG_DACC_WPMR (*(__IO uint32_t*)0x400400E4U) /**< (DACC) Write Protection Mode Register */
|
||||
#define REG_DACC_WPSR (*(__I uint32_t*)0x400400E8U) /**< (DACC) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for DACC peripheral ========== */
|
||||
#define DACC_DMAC_ID_TX 30
|
||||
#define DACC_INSTANCE_ID 30
|
||||
#define DACC_CLOCK_ID 30
|
||||
|
||||
#endif /* _SAME70_DACC_INSTANCE_ */
|
||||
59
lib/same70b/include/instance/efc.h
Normal file
59
lib/same70b/include/instance/efc.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for EFC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_EFC_INSTANCE_H_
|
||||
#define _SAME70_EFC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for EFC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_EEFC_FMR (0x400E0C00) /**< (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EEFC_FCR (0x400E0C04) /**< (EFC) EEFC Flash Command Register */
|
||||
#define REG_EEFC_FSR (0x400E0C08) /**< (EFC) EEFC Flash Status Register */
|
||||
#define REG_EEFC_FRR (0x400E0C0C) /**< (EFC) EEFC Flash Result Register */
|
||||
#define REG_EEFC_WPMR (0x400E0CE4) /**< (EFC) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_EEFC_FMR (*(__IO uint32_t*)0x400E0C00U) /**< (EFC) EEFC Flash Mode Register */
|
||||
#define REG_EEFC_FCR (*(__O uint32_t*)0x400E0C04U) /**< (EFC) EEFC Flash Command Register */
|
||||
#define REG_EEFC_FSR (*(__I uint32_t*)0x400E0C08U) /**< (EFC) EEFC Flash Status Register */
|
||||
#define REG_EEFC_FRR (*(__I uint32_t*)0x400E0C0CU) /**< (EFC) EEFC Flash Result Register */
|
||||
#define REG_EEFC_WPMR (*(__IO uint32_t*)0x400E0CE4U) /**< (EFC) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for EFC peripheral ========== */
|
||||
#define EFC_FLASH_SIZE 2097152
|
||||
#define EFC_PAGE_SIZE 512
|
||||
#define EFC_INSTANCE_ID 6
|
||||
#define EFC_PAGES_PR_REGION 32
|
||||
|
||||
#endif /* _SAME70_EFC_INSTANCE_ */
|
||||
489
lib/same70b/include/instance/gmac.h
Normal file
489
lib/same70b/include/instance/gmac.h
Normal file
|
|
@ -0,0 +1,489 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for GMAC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_GMAC_INSTANCE_H_
|
||||
#define _SAME70_GMAC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for GMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_GMAC_SAB1 (0x40050088) /**< (GMAC) Specific Address 1 Bottom Register 0 */
|
||||
#define REG_GMAC_SAT1 (0x4005008C) /**< (GMAC) Specific Address 1 Top Register 0 */
|
||||
#define REG_GMAC_SAB2 (0x40050090) /**< (GMAC) Specific Address 1 Bottom Register 1 */
|
||||
#define REG_GMAC_SAT2 (0x40050094) /**< (GMAC) Specific Address 1 Top Register 1 */
|
||||
#define REG_GMAC_SAB3 (0x40050098) /**< (GMAC) Specific Address 1 Bottom Register 2 */
|
||||
#define REG_GMAC_SAT3 (0x4005009C) /**< (GMAC) Specific Address 1 Top Register 2 */
|
||||
#define REG_GMAC_SAB4 (0x400500A0) /**< (GMAC) Specific Address 1 Bottom Register 3 */
|
||||
#define REG_GMAC_SAT4 (0x400500A4) /**< (GMAC) Specific Address 1 Top Register 3 */
|
||||
#define REG_GMAC_ST2CW00 (0x40050700) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */
|
||||
#define REG_GMAC_ST2CW10 (0x40050704) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */
|
||||
#define REG_GMAC_ST2CW01 (0x40050708) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */
|
||||
#define REG_GMAC_ST2CW11 (0x4005070C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */
|
||||
#define REG_GMAC_ST2CW02 (0x40050710) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */
|
||||
#define REG_GMAC_ST2CW12 (0x40050714) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */
|
||||
#define REG_GMAC_ST2CW03 (0x40050718) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */
|
||||
#define REG_GMAC_ST2CW13 (0x4005071C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */
|
||||
#define REG_GMAC_ST2CW04 (0x40050720) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */
|
||||
#define REG_GMAC_ST2CW14 (0x40050724) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */
|
||||
#define REG_GMAC_ST2CW05 (0x40050728) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */
|
||||
#define REG_GMAC_ST2CW15 (0x4005072C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */
|
||||
#define REG_GMAC_ST2CW06 (0x40050730) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */
|
||||
#define REG_GMAC_ST2CW16 (0x40050734) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */
|
||||
#define REG_GMAC_ST2CW07 (0x40050738) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */
|
||||
#define REG_GMAC_ST2CW17 (0x4005073C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */
|
||||
#define REG_GMAC_ST2CW08 (0x40050740) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */
|
||||
#define REG_GMAC_ST2CW18 (0x40050744) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */
|
||||
#define REG_GMAC_ST2CW09 (0x40050748) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */
|
||||
#define REG_GMAC_ST2CW19 (0x4005074C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */
|
||||
#define REG_GMAC_ST2CW010 (0x40050750) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */
|
||||
#define REG_GMAC_ST2CW110 (0x40050754) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */
|
||||
#define REG_GMAC_ST2CW011 (0x40050758) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */
|
||||
#define REG_GMAC_ST2CW111 (0x4005075C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */
|
||||
#define REG_GMAC_ST2CW012 (0x40050760) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */
|
||||
#define REG_GMAC_ST2CW112 (0x40050764) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */
|
||||
#define REG_GMAC_ST2CW013 (0x40050768) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */
|
||||
#define REG_GMAC_ST2CW113 (0x4005076C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */
|
||||
#define REG_GMAC_ST2CW014 (0x40050770) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */
|
||||
#define REG_GMAC_ST2CW114 (0x40050774) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */
|
||||
#define REG_GMAC_ST2CW015 (0x40050778) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */
|
||||
#define REG_GMAC_ST2CW115 (0x4005077C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */
|
||||
#define REG_GMAC_ST2CW016 (0x40050780) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */
|
||||
#define REG_GMAC_ST2CW116 (0x40050784) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */
|
||||
#define REG_GMAC_ST2CW017 (0x40050788) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */
|
||||
#define REG_GMAC_ST2CW117 (0x4005078C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */
|
||||
#define REG_GMAC_ST2CW018 (0x40050790) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */
|
||||
#define REG_GMAC_ST2CW118 (0x40050794) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */
|
||||
#define REG_GMAC_ST2CW019 (0x40050798) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */
|
||||
#define REG_GMAC_ST2CW119 (0x4005079C) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */
|
||||
#define REG_GMAC_ST2CW020 (0x400507A0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */
|
||||
#define REG_GMAC_ST2CW120 (0x400507A4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */
|
||||
#define REG_GMAC_ST2CW021 (0x400507A8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */
|
||||
#define REG_GMAC_ST2CW121 (0x400507AC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */
|
||||
#define REG_GMAC_ST2CW022 (0x400507B0) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */
|
||||
#define REG_GMAC_ST2CW122 (0x400507B4) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */
|
||||
#define REG_GMAC_ST2CW023 (0x400507B8) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */
|
||||
#define REG_GMAC_ST2CW123 (0x400507BC) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */
|
||||
#define REG_GMAC_NCR (0x40050000) /**< (GMAC) Network Control Register */
|
||||
#define REG_GMAC_NCFGR (0x40050004) /**< (GMAC) Network Configuration Register */
|
||||
#define REG_GMAC_NSR (0x40050008) /**< (GMAC) Network Status Register */
|
||||
#define REG_GMAC_UR (0x4005000C) /**< (GMAC) User Register */
|
||||
#define REG_GMAC_DCFGR (0x40050010) /**< (GMAC) DMA Configuration Register */
|
||||
#define REG_GMAC_TSR (0x40050014) /**< (GMAC) Transmit Status Register */
|
||||
#define REG_GMAC_RBQB (0x40050018) /**< (GMAC) Receive Buffer Queue Base Address Register */
|
||||
#define REG_GMAC_TBQB (0x4005001C) /**< (GMAC) Transmit Buffer Queue Base Address Register */
|
||||
#define REG_GMAC_RSR (0x40050020) /**< (GMAC) Receive Status Register */
|
||||
#define REG_GMAC_ISR (0x40050024) /**< (GMAC) Interrupt Status Register */
|
||||
#define REG_GMAC_IER (0x40050028) /**< (GMAC) Interrupt Enable Register */
|
||||
#define REG_GMAC_IDR (0x4005002C) /**< (GMAC) Interrupt Disable Register */
|
||||
#define REG_GMAC_IMR (0x40050030) /**< (GMAC) Interrupt Mask Register */
|
||||
#define REG_GMAC_MAN (0x40050034) /**< (GMAC) PHY Maintenance Register */
|
||||
#define REG_GMAC_RPQ (0x40050038) /**< (GMAC) Received Pause Quantum Register */
|
||||
#define REG_GMAC_TPQ (0x4005003C) /**< (GMAC) Transmit Pause Quantum Register */
|
||||
#define REG_GMAC_TPSF (0x40050040) /**< (GMAC) TX Partial Store and Forward Register */
|
||||
#define REG_GMAC_RPSF (0x40050044) /**< (GMAC) RX Partial Store and Forward Register */
|
||||
#define REG_GMAC_RJFML (0x40050048) /**< (GMAC) RX Jumbo Frame Max Length Register */
|
||||
#define REG_GMAC_HRB (0x40050080) /**< (GMAC) Hash Register Bottom */
|
||||
#define REG_GMAC_HRT (0x40050084) /**< (GMAC) Hash Register Top */
|
||||
#define REG_GMAC_TIDM1 (0x400500A8) /**< (GMAC) Type ID Match 1 Register */
|
||||
#define REG_GMAC_TIDM2 (0x400500AC) /**< (GMAC) Type ID Match 2 Register */
|
||||
#define REG_GMAC_TIDM3 (0x400500B0) /**< (GMAC) Type ID Match 3 Register */
|
||||
#define REG_GMAC_TIDM4 (0x400500B4) /**< (GMAC) Type ID Match 4 Register */
|
||||
#define REG_GMAC_WOL (0x400500B8) /**< (GMAC) Wake on LAN Register */
|
||||
#define REG_GMAC_IPGS (0x400500BC) /**< (GMAC) IPG Stretch Register */
|
||||
#define REG_GMAC_SVLAN (0x400500C0) /**< (GMAC) Stacked VLAN Register */
|
||||
#define REG_GMAC_TPFCP (0x400500C4) /**< (GMAC) Transmit PFC Pause Register */
|
||||
#define REG_GMAC_SAMB1 (0x400500C8) /**< (GMAC) Specific Address 1 Mask Bottom Register */
|
||||
#define REG_GMAC_SAMT1 (0x400500CC) /**< (GMAC) Specific Address 1 Mask Top Register */
|
||||
#define REG_GMAC_NSC (0x400500DC) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */
|
||||
#define REG_GMAC_SCL (0x400500E0) /**< (GMAC) 1588 Timer Second Comparison Low Register */
|
||||
#define REG_GMAC_SCH (0x400500E4) /**< (GMAC) 1588 Timer Second Comparison High Register */
|
||||
#define REG_GMAC_EFTSH (0x400500E8) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_EFRSH (0x400500EC) /**< (GMAC) PTP Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_PEFTSH (0x400500F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_PEFRSH (0x400500F4) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_OTLO (0x40050100) /**< (GMAC) Octets Transmitted Low Register */
|
||||
#define REG_GMAC_OTHI (0x40050104) /**< (GMAC) Octets Transmitted High Register */
|
||||
#define REG_GMAC_FT (0x40050108) /**< (GMAC) Frames Transmitted Register */
|
||||
#define REG_GMAC_BCFT (0x4005010C) /**< (GMAC) Broadcast Frames Transmitted Register */
|
||||
#define REG_GMAC_MFT (0x40050110) /**< (GMAC) Multicast Frames Transmitted Register */
|
||||
#define REG_GMAC_PFT (0x40050114) /**< (GMAC) Pause Frames Transmitted Register */
|
||||
#define REG_GMAC_BFT64 (0x40050118) /**< (GMAC) 64 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT127 (0x4005011C) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT255 (0x40050120) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT511 (0x40050124) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1023 (0x40050128) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1518 (0x4005012C) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_GTBFT1518 (0x40050130) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TUR (0x40050134) /**< (GMAC) Transmit Underruns Register */
|
||||
#define REG_GMAC_SCF (0x40050138) /**< (GMAC) Single Collision Frames Register */
|
||||
#define REG_GMAC_MCF (0x4005013C) /**< (GMAC) Multiple Collision Frames Register */
|
||||
#define REG_GMAC_EC (0x40050140) /**< (GMAC) Excessive Collisions Register */
|
||||
#define REG_GMAC_LC (0x40050144) /**< (GMAC) Late Collisions Register */
|
||||
#define REG_GMAC_DTF (0x40050148) /**< (GMAC) Deferred Transmission Frames Register */
|
||||
#define REG_GMAC_CSE (0x4005014C) /**< (GMAC) Carrier Sense Errors Register */
|
||||
#define REG_GMAC_ORLO (0x40050150) /**< (GMAC) Octets Received Low Received Register */
|
||||
#define REG_GMAC_ORHI (0x40050154) /**< (GMAC) Octets Received High Received Register */
|
||||
#define REG_GMAC_FR (0x40050158) /**< (GMAC) Frames Received Register */
|
||||
#define REG_GMAC_BCFR (0x4005015C) /**< (GMAC) Broadcast Frames Received Register */
|
||||
#define REG_GMAC_MFR (0x40050160) /**< (GMAC) Multicast Frames Received Register */
|
||||
#define REG_GMAC_PFR (0x40050164) /**< (GMAC) Pause Frames Received Register */
|
||||
#define REG_GMAC_BFR64 (0x40050168) /**< (GMAC) 64 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR127 (0x4005016C) /**< (GMAC) 65 to 127 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR255 (0x40050170) /**< (GMAC) 128 to 255 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR511 (0x40050174) /**< (GMAC) 256 to 511 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1023 (0x40050178) /**< (GMAC) 512 to 1023 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1518 (0x4005017C) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */
|
||||
#define REG_GMAC_TMXBFR (0x40050180) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */
|
||||
#define REG_GMAC_UFR (0x40050184) /**< (GMAC) Undersize Frames Received Register */
|
||||
#define REG_GMAC_OFR (0x40050188) /**< (GMAC) Oversize Frames Received Register */
|
||||
#define REG_GMAC_JR (0x4005018C) /**< (GMAC) Jabbers Received Register */
|
||||
#define REG_GMAC_FCSE (0x40050190) /**< (GMAC) Frame Check Sequence Errors Register */
|
||||
#define REG_GMAC_LFFE (0x40050194) /**< (GMAC) Length Field Frame Errors Register */
|
||||
#define REG_GMAC_RSE (0x40050198) /**< (GMAC) Receive Symbol Errors Register */
|
||||
#define REG_GMAC_AE (0x4005019C) /**< (GMAC) Alignment Errors Register */
|
||||
#define REG_GMAC_RRE (0x400501A0) /**< (GMAC) Receive Resource Errors Register */
|
||||
#define REG_GMAC_ROE (0x400501A4) /**< (GMAC) Receive Overrun Register */
|
||||
#define REG_GMAC_IHCE (0x400501A8) /**< (GMAC) IP Header Checksum Errors Register */
|
||||
#define REG_GMAC_TCE (0x400501AC) /**< (GMAC) TCP Checksum Errors Register */
|
||||
#define REG_GMAC_UCE (0x400501B0) /**< (GMAC) UDP Checksum Errors Register */
|
||||
#define REG_GMAC_TISUBN (0x400501BC) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
|
||||
#define REG_GMAC_TSH (0x400501C0) /**< (GMAC) 1588 Timer Seconds High Register */
|
||||
#define REG_GMAC_TSL (0x400501D0) /**< (GMAC) 1588 Timer Seconds Low Register */
|
||||
#define REG_GMAC_TN (0x400501D4) /**< (GMAC) 1588 Timer Nanoseconds Register */
|
||||
#define REG_GMAC_TA (0x400501D8) /**< (GMAC) 1588 Timer Adjust Register */
|
||||
#define REG_GMAC_TI (0x400501DC) /**< (GMAC) 1588 Timer Increment Register */
|
||||
#define REG_GMAC_EFTSL (0x400501E0) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_EFTN (0x400501E4) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
|
||||
#define REG_GMAC_EFRSL (0x400501E8) /**< (GMAC) PTP Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_EFRN (0x400501EC) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */
|
||||
#define REG_GMAC_PEFTSL (0x400501F0) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_PEFTN (0x400501F4) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
|
||||
#define REG_GMAC_PEFRSL (0x400501F8) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_PEFRN (0x400501FC) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
|
||||
#define REG_GMAC_RXLPI (0x40050270) /**< (GMAC) Received LPI Transitions */
|
||||
#define REG_GMAC_RXLPITIME (0x40050274) /**< (GMAC) Received LPI Time */
|
||||
#define REG_GMAC_TXLPI (0x40050278) /**< (GMAC) Transmit LPI Transitions */
|
||||
#define REG_GMAC_TXLPITIME (0x4005027C) /**< (GMAC) Transmit LPI Time */
|
||||
#define REG_GMAC_ISRPQ (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_ISRPQ0 (0x40050400) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_ISRPQ1 (0x40050404) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_ISRPQ2 (0x40050408) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_ISRPQ3 (0x4005040C) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_ISRPQ4 (0x40050410) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_TBQBAPQ (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_TBQBAPQ0 (0x40050440) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_TBQBAPQ1 (0x40050444) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_TBQBAPQ2 (0x40050448) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_TBQBAPQ3 (0x4005044C) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_TBQBAPQ4 (0x40050450) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_RBQBAPQ (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_RBQBAPQ0 (0x40050480) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_RBQBAPQ1 (0x40050484) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_RBQBAPQ2 (0x40050488) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_RBQBAPQ3 (0x4005048C) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_RBQBAPQ4 (0x40050490) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_RBSRPQ (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_RBSRPQ0 (0x400504A0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_RBSRPQ1 (0x400504A4) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_RBSRPQ2 (0x400504A8) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_RBSRPQ3 (0x400504AC) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_RBSRPQ4 (0x400504B0) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_CBSCR (0x400504BC) /**< (GMAC) Credit-Based Shaping Control Register */
|
||||
#define REG_GMAC_CBSISQA (0x400504C0) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
|
||||
#define REG_GMAC_CBSISQB (0x400504C4) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
|
||||
#define REG_GMAC_ST1RPQ (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue */
|
||||
#define REG_GMAC_ST1RPQ0 (0x40050500) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */
|
||||
#define REG_GMAC_ST1RPQ1 (0x40050504) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */
|
||||
#define REG_GMAC_ST1RPQ2 (0x40050508) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */
|
||||
#define REG_GMAC_ST1RPQ3 (0x4005050C) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */
|
||||
#define REG_GMAC_ST2RPQ (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue */
|
||||
#define REG_GMAC_ST2RPQ0 (0x40050540) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */
|
||||
#define REG_GMAC_ST2RPQ1 (0x40050544) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */
|
||||
#define REG_GMAC_ST2RPQ2 (0x40050548) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */
|
||||
#define REG_GMAC_ST2RPQ3 (0x4005054C) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */
|
||||
#define REG_GMAC_ST2RPQ4 (0x40050550) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */
|
||||
#define REG_GMAC_ST2RPQ5 (0x40050554) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */
|
||||
#define REG_GMAC_ST2RPQ6 (0x40050558) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */
|
||||
#define REG_GMAC_ST2RPQ7 (0x4005055C) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */
|
||||
#define REG_GMAC_IERPQ (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IERPQ0 (0x40050600) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IERPQ1 (0x40050604) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IERPQ2 (0x40050608) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IERPQ3 (0x4005060C) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IERPQ4 (0x40050610) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_IDRPQ (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IDRPQ0 (0x40050620) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IDRPQ1 (0x40050624) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IDRPQ2 (0x40050628) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IDRPQ3 (0x4005062C) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IDRPQ4 (0x40050630) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_IMRPQ (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IMRPQ0 (0x40050640) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IMRPQ1 (0x40050644) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IMRPQ2 (0x40050648) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IMRPQ3 (0x4005064C) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IMRPQ4 (0x40050650) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_ST2ER (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register */
|
||||
#define REG_GMAC_ST2ER0 (0x400506E0) /**< (GMAC) Screening Type 2 Ethertype Register 0 */
|
||||
#define REG_GMAC_ST2ER1 (0x400506E4) /**< (GMAC) Screening Type 2 Ethertype Register 1 */
|
||||
#define REG_GMAC_ST2ER2 (0x400506E8) /**< (GMAC) Screening Type 2 Ethertype Register 2 */
|
||||
#define REG_GMAC_ST2ER3 (0x400506EC) /**< (GMAC) Screening Type 2 Ethertype Register 3 */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_GMAC_SAB1 (*(__IO uint32_t*)0x40050088U) /**< (GMAC) Specific Address 1 Bottom Register 0 */
|
||||
#define REG_GMAC_SAT1 (*(__IO uint32_t*)0x4005008CU) /**< (GMAC) Specific Address 1 Top Register 0 */
|
||||
#define REG_GMAC_SAB2 (*(__IO uint32_t*)0x40050090U) /**< (GMAC) Specific Address 1 Bottom Register 1 */
|
||||
#define REG_GMAC_SAT2 (*(__IO uint32_t*)0x40050094U) /**< (GMAC) Specific Address 1 Top Register 1 */
|
||||
#define REG_GMAC_SAB3 (*(__IO uint32_t*)0x40050098U) /**< (GMAC) Specific Address 1 Bottom Register 2 */
|
||||
#define REG_GMAC_SAT3 (*(__IO uint32_t*)0x4005009CU) /**< (GMAC) Specific Address 1 Top Register 2 */
|
||||
#define REG_GMAC_SAB4 (*(__IO uint32_t*)0x400500A0U) /**< (GMAC) Specific Address 1 Bottom Register 3 */
|
||||
#define REG_GMAC_SAT4 (*(__IO uint32_t*)0x400500A4U) /**< (GMAC) Specific Address 1 Top Register 3 */
|
||||
#define REG_GMAC_ST2CW00 (*(__IO uint32_t*)0x40050700U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 0 */
|
||||
#define REG_GMAC_ST2CW10 (*(__IO uint32_t*)0x40050704U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 0 */
|
||||
#define REG_GMAC_ST2CW01 (*(__IO uint32_t*)0x40050708U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 1 */
|
||||
#define REG_GMAC_ST2CW11 (*(__IO uint32_t*)0x4005070CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 1 */
|
||||
#define REG_GMAC_ST2CW02 (*(__IO uint32_t*)0x40050710U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 2 */
|
||||
#define REG_GMAC_ST2CW12 (*(__IO uint32_t*)0x40050714U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 2 */
|
||||
#define REG_GMAC_ST2CW03 (*(__IO uint32_t*)0x40050718U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 3 */
|
||||
#define REG_GMAC_ST2CW13 (*(__IO uint32_t*)0x4005071CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 3 */
|
||||
#define REG_GMAC_ST2CW04 (*(__IO uint32_t*)0x40050720U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 4 */
|
||||
#define REG_GMAC_ST2CW14 (*(__IO uint32_t*)0x40050724U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 4 */
|
||||
#define REG_GMAC_ST2CW05 (*(__IO uint32_t*)0x40050728U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 5 */
|
||||
#define REG_GMAC_ST2CW15 (*(__IO uint32_t*)0x4005072CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 5 */
|
||||
#define REG_GMAC_ST2CW06 (*(__IO uint32_t*)0x40050730U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 6 */
|
||||
#define REG_GMAC_ST2CW16 (*(__IO uint32_t*)0x40050734U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 6 */
|
||||
#define REG_GMAC_ST2CW07 (*(__IO uint32_t*)0x40050738U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 7 */
|
||||
#define REG_GMAC_ST2CW17 (*(__IO uint32_t*)0x4005073CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 7 */
|
||||
#define REG_GMAC_ST2CW08 (*(__IO uint32_t*)0x40050740U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 8 */
|
||||
#define REG_GMAC_ST2CW18 (*(__IO uint32_t*)0x40050744U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 8 */
|
||||
#define REG_GMAC_ST2CW09 (*(__IO uint32_t*)0x40050748U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 9 */
|
||||
#define REG_GMAC_ST2CW19 (*(__IO uint32_t*)0x4005074CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 9 */
|
||||
#define REG_GMAC_ST2CW010 (*(__IO uint32_t*)0x40050750U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 10 */
|
||||
#define REG_GMAC_ST2CW110 (*(__IO uint32_t*)0x40050754U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 10 */
|
||||
#define REG_GMAC_ST2CW011 (*(__IO uint32_t*)0x40050758U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 11 */
|
||||
#define REG_GMAC_ST2CW111 (*(__IO uint32_t*)0x4005075CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 11 */
|
||||
#define REG_GMAC_ST2CW012 (*(__IO uint32_t*)0x40050760U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 12 */
|
||||
#define REG_GMAC_ST2CW112 (*(__IO uint32_t*)0x40050764U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 12 */
|
||||
#define REG_GMAC_ST2CW013 (*(__IO uint32_t*)0x40050768U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 13 */
|
||||
#define REG_GMAC_ST2CW113 (*(__IO uint32_t*)0x4005076CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 13 */
|
||||
#define REG_GMAC_ST2CW014 (*(__IO uint32_t*)0x40050770U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 14 */
|
||||
#define REG_GMAC_ST2CW114 (*(__IO uint32_t*)0x40050774U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 14 */
|
||||
#define REG_GMAC_ST2CW015 (*(__IO uint32_t*)0x40050778U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 15 */
|
||||
#define REG_GMAC_ST2CW115 (*(__IO uint32_t*)0x4005077CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 15 */
|
||||
#define REG_GMAC_ST2CW016 (*(__IO uint32_t*)0x40050780U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 16 */
|
||||
#define REG_GMAC_ST2CW116 (*(__IO uint32_t*)0x40050784U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 16 */
|
||||
#define REG_GMAC_ST2CW017 (*(__IO uint32_t*)0x40050788U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 17 */
|
||||
#define REG_GMAC_ST2CW117 (*(__IO uint32_t*)0x4005078CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 17 */
|
||||
#define REG_GMAC_ST2CW018 (*(__IO uint32_t*)0x40050790U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 18 */
|
||||
#define REG_GMAC_ST2CW118 (*(__IO uint32_t*)0x40050794U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 18 */
|
||||
#define REG_GMAC_ST2CW019 (*(__IO uint32_t*)0x40050798U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 19 */
|
||||
#define REG_GMAC_ST2CW119 (*(__IO uint32_t*)0x4005079CU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 19 */
|
||||
#define REG_GMAC_ST2CW020 (*(__IO uint32_t*)0x400507A0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 20 */
|
||||
#define REG_GMAC_ST2CW120 (*(__IO uint32_t*)0x400507A4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 20 */
|
||||
#define REG_GMAC_ST2CW021 (*(__IO uint32_t*)0x400507A8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 21 */
|
||||
#define REG_GMAC_ST2CW121 (*(__IO uint32_t*)0x400507ACU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 21 */
|
||||
#define REG_GMAC_ST2CW022 (*(__IO uint32_t*)0x400507B0U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 22 */
|
||||
#define REG_GMAC_ST2CW122 (*(__IO uint32_t*)0x400507B4U) /**< (GMAC) Screening Type 2 Compare Word 1 Register 22 */
|
||||
#define REG_GMAC_ST2CW023 (*(__IO uint32_t*)0x400507B8U) /**< (GMAC) Screening Type 2 Compare Word 0 Register 23 */
|
||||
#define REG_GMAC_ST2CW123 (*(__IO uint32_t*)0x400507BCU) /**< (GMAC) Screening Type 2 Compare Word 1 Register 23 */
|
||||
#define REG_GMAC_NCR (*(__IO uint32_t*)0x40050000U) /**< (GMAC) Network Control Register */
|
||||
#define REG_GMAC_NCFGR (*(__IO uint32_t*)0x40050004U) /**< (GMAC) Network Configuration Register */
|
||||
#define REG_GMAC_NSR (*(__I uint32_t*)0x40050008U) /**< (GMAC) Network Status Register */
|
||||
#define REG_GMAC_UR (*(__IO uint32_t*)0x4005000CU) /**< (GMAC) User Register */
|
||||
#define REG_GMAC_DCFGR (*(__IO uint32_t*)0x40050010U) /**< (GMAC) DMA Configuration Register */
|
||||
#define REG_GMAC_TSR (*(__IO uint32_t*)0x40050014U) /**< (GMAC) Transmit Status Register */
|
||||
#define REG_GMAC_RBQB (*(__IO uint32_t*)0x40050018U) /**< (GMAC) Receive Buffer Queue Base Address Register */
|
||||
#define REG_GMAC_TBQB (*(__IO uint32_t*)0x4005001CU) /**< (GMAC) Transmit Buffer Queue Base Address Register */
|
||||
#define REG_GMAC_RSR (*(__IO uint32_t*)0x40050020U) /**< (GMAC) Receive Status Register */
|
||||
#define REG_GMAC_ISR (*(__I uint32_t*)0x40050024U) /**< (GMAC) Interrupt Status Register */
|
||||
#define REG_GMAC_IER (*(__O uint32_t*)0x40050028U) /**< (GMAC) Interrupt Enable Register */
|
||||
#define REG_GMAC_IDR (*(__O uint32_t*)0x4005002CU) /**< (GMAC) Interrupt Disable Register */
|
||||
#define REG_GMAC_IMR (*(__IO uint32_t*)0x40050030U) /**< (GMAC) Interrupt Mask Register */
|
||||
#define REG_GMAC_MAN (*(__IO uint32_t*)0x40050034U) /**< (GMAC) PHY Maintenance Register */
|
||||
#define REG_GMAC_RPQ (*(__I uint32_t*)0x40050038U) /**< (GMAC) Received Pause Quantum Register */
|
||||
#define REG_GMAC_TPQ (*(__IO uint32_t*)0x4005003CU) /**< (GMAC) Transmit Pause Quantum Register */
|
||||
#define REG_GMAC_TPSF (*(__IO uint32_t*)0x40050040U) /**< (GMAC) TX Partial Store and Forward Register */
|
||||
#define REG_GMAC_RPSF (*(__IO uint32_t*)0x40050044U) /**< (GMAC) RX Partial Store and Forward Register */
|
||||
#define REG_GMAC_RJFML (*(__IO uint32_t*)0x40050048U) /**< (GMAC) RX Jumbo Frame Max Length Register */
|
||||
#define REG_GMAC_HRB (*(__IO uint32_t*)0x40050080U) /**< (GMAC) Hash Register Bottom */
|
||||
#define REG_GMAC_HRT (*(__IO uint32_t*)0x40050084U) /**< (GMAC) Hash Register Top */
|
||||
#define REG_GMAC_TIDM1 (*(__IO uint32_t*)0x400500A8U) /**< (GMAC) Type ID Match 1 Register */
|
||||
#define REG_GMAC_TIDM2 (*(__IO uint32_t*)0x400500ACU) /**< (GMAC) Type ID Match 2 Register */
|
||||
#define REG_GMAC_TIDM3 (*(__IO uint32_t*)0x400500B0U) /**< (GMAC) Type ID Match 3 Register */
|
||||
#define REG_GMAC_TIDM4 (*(__IO uint32_t*)0x400500B4U) /**< (GMAC) Type ID Match 4 Register */
|
||||
#define REG_GMAC_WOL (*(__IO uint32_t*)0x400500B8U) /**< (GMAC) Wake on LAN Register */
|
||||
#define REG_GMAC_IPGS (*(__IO uint32_t*)0x400500BCU) /**< (GMAC) IPG Stretch Register */
|
||||
#define REG_GMAC_SVLAN (*(__IO uint32_t*)0x400500C0U) /**< (GMAC) Stacked VLAN Register */
|
||||
#define REG_GMAC_TPFCP (*(__IO uint32_t*)0x400500C4U) /**< (GMAC) Transmit PFC Pause Register */
|
||||
#define REG_GMAC_SAMB1 (*(__IO uint32_t*)0x400500C8U) /**< (GMAC) Specific Address 1 Mask Bottom Register */
|
||||
#define REG_GMAC_SAMT1 (*(__IO uint32_t*)0x400500CCU) /**< (GMAC) Specific Address 1 Mask Top Register */
|
||||
#define REG_GMAC_NSC (*(__IO uint32_t*)0x400500DCU) /**< (GMAC) 1588 Timer Nanosecond Comparison Register */
|
||||
#define REG_GMAC_SCL (*(__IO uint32_t*)0x400500E0U) /**< (GMAC) 1588 Timer Second Comparison Low Register */
|
||||
#define REG_GMAC_SCH (*(__IO uint32_t*)0x400500E4U) /**< (GMAC) 1588 Timer Second Comparison High Register */
|
||||
#define REG_GMAC_EFTSH (*(__I uint32_t*)0x400500E8U) /**< (GMAC) PTP Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_EFRSH (*(__I uint32_t*)0x400500ECU) /**< (GMAC) PTP Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_PEFTSH (*(__I uint32_t*)0x400500F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds High Register */
|
||||
#define REG_GMAC_PEFRSH (*(__I uint32_t*)0x400500F4U) /**< (GMAC) PTP Peer Event Frame Received Seconds High Register */
|
||||
#define REG_GMAC_OTLO (*(__I uint32_t*)0x40050100U) /**< (GMAC) Octets Transmitted Low Register */
|
||||
#define REG_GMAC_OTHI (*(__I uint32_t*)0x40050104U) /**< (GMAC) Octets Transmitted High Register */
|
||||
#define REG_GMAC_FT (*(__I uint32_t*)0x40050108U) /**< (GMAC) Frames Transmitted Register */
|
||||
#define REG_GMAC_BCFT (*(__I uint32_t*)0x4005010CU) /**< (GMAC) Broadcast Frames Transmitted Register */
|
||||
#define REG_GMAC_MFT (*(__I uint32_t*)0x40050110U) /**< (GMAC) Multicast Frames Transmitted Register */
|
||||
#define REG_GMAC_PFT (*(__I uint32_t*)0x40050114U) /**< (GMAC) Pause Frames Transmitted Register */
|
||||
#define REG_GMAC_BFT64 (*(__I uint32_t*)0x40050118U) /**< (GMAC) 64 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT127 (*(__I uint32_t*)0x4005011CU) /**< (GMAC) 65 to 127 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT255 (*(__I uint32_t*)0x40050120U) /**< (GMAC) 128 to 255 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT511 (*(__I uint32_t*)0x40050124U) /**< (GMAC) 256 to 511 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1023 (*(__I uint32_t*)0x40050128U) /**< (GMAC) 512 to 1023 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TBFT1518 (*(__I uint32_t*)0x4005012CU) /**< (GMAC) 1024 to 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_GTBFT1518 (*(__I uint32_t*)0x40050130U) /**< (GMAC) Greater Than 1518 Byte Frames Transmitted Register */
|
||||
#define REG_GMAC_TUR (*(__I uint32_t*)0x40050134U) /**< (GMAC) Transmit Underruns Register */
|
||||
#define REG_GMAC_SCF (*(__I uint32_t*)0x40050138U) /**< (GMAC) Single Collision Frames Register */
|
||||
#define REG_GMAC_MCF (*(__I uint32_t*)0x4005013CU) /**< (GMAC) Multiple Collision Frames Register */
|
||||
#define REG_GMAC_EC (*(__I uint32_t*)0x40050140U) /**< (GMAC) Excessive Collisions Register */
|
||||
#define REG_GMAC_LC (*(__I uint32_t*)0x40050144U) /**< (GMAC) Late Collisions Register */
|
||||
#define REG_GMAC_DTF (*(__I uint32_t*)0x40050148U) /**< (GMAC) Deferred Transmission Frames Register */
|
||||
#define REG_GMAC_CSE (*(__I uint32_t*)0x4005014CU) /**< (GMAC) Carrier Sense Errors Register */
|
||||
#define REG_GMAC_ORLO (*(__I uint32_t*)0x40050150U) /**< (GMAC) Octets Received Low Received Register */
|
||||
#define REG_GMAC_ORHI (*(__I uint32_t*)0x40050154U) /**< (GMAC) Octets Received High Received Register */
|
||||
#define REG_GMAC_FR (*(__I uint32_t*)0x40050158U) /**< (GMAC) Frames Received Register */
|
||||
#define REG_GMAC_BCFR (*(__I uint32_t*)0x4005015CU) /**< (GMAC) Broadcast Frames Received Register */
|
||||
#define REG_GMAC_MFR (*(__I uint32_t*)0x40050160U) /**< (GMAC) Multicast Frames Received Register */
|
||||
#define REG_GMAC_PFR (*(__I uint32_t*)0x40050164U) /**< (GMAC) Pause Frames Received Register */
|
||||
#define REG_GMAC_BFR64 (*(__I uint32_t*)0x40050168U) /**< (GMAC) 64 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR127 (*(__I uint32_t*)0x4005016CU) /**< (GMAC) 65 to 127 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR255 (*(__I uint32_t*)0x40050170U) /**< (GMAC) 128 to 255 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR511 (*(__I uint32_t*)0x40050174U) /**< (GMAC) 256 to 511 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1023 (*(__I uint32_t*)0x40050178U) /**< (GMAC) 512 to 1023 Byte Frames Received Register */
|
||||
#define REG_GMAC_TBFR1518 (*(__I uint32_t*)0x4005017CU) /**< (GMAC) 1024 to 1518 Byte Frames Received Register */
|
||||
#define REG_GMAC_TMXBFR (*(__I uint32_t*)0x40050180U) /**< (GMAC) 1519 to Maximum Byte Frames Received Register */
|
||||
#define REG_GMAC_UFR (*(__I uint32_t*)0x40050184U) /**< (GMAC) Undersize Frames Received Register */
|
||||
#define REG_GMAC_OFR (*(__I uint32_t*)0x40050188U) /**< (GMAC) Oversize Frames Received Register */
|
||||
#define REG_GMAC_JR (*(__I uint32_t*)0x4005018CU) /**< (GMAC) Jabbers Received Register */
|
||||
#define REG_GMAC_FCSE (*(__I uint32_t*)0x40050190U) /**< (GMAC) Frame Check Sequence Errors Register */
|
||||
#define REG_GMAC_LFFE (*(__I uint32_t*)0x40050194U) /**< (GMAC) Length Field Frame Errors Register */
|
||||
#define REG_GMAC_RSE (*(__I uint32_t*)0x40050198U) /**< (GMAC) Receive Symbol Errors Register */
|
||||
#define REG_GMAC_AE (*(__I uint32_t*)0x4005019CU) /**< (GMAC) Alignment Errors Register */
|
||||
#define REG_GMAC_RRE (*(__I uint32_t*)0x400501A0U) /**< (GMAC) Receive Resource Errors Register */
|
||||
#define REG_GMAC_ROE (*(__I uint32_t*)0x400501A4U) /**< (GMAC) Receive Overrun Register */
|
||||
#define REG_GMAC_IHCE (*(__I uint32_t*)0x400501A8U) /**< (GMAC) IP Header Checksum Errors Register */
|
||||
#define REG_GMAC_TCE (*(__I uint32_t*)0x400501ACU) /**< (GMAC) TCP Checksum Errors Register */
|
||||
#define REG_GMAC_UCE (*(__I uint32_t*)0x400501B0U) /**< (GMAC) UDP Checksum Errors Register */
|
||||
#define REG_GMAC_TISUBN (*(__IO uint32_t*)0x400501BCU) /**< (GMAC) 1588 Timer Increment Sub-nanoseconds Register */
|
||||
#define REG_GMAC_TSH (*(__IO uint32_t*)0x400501C0U) /**< (GMAC) 1588 Timer Seconds High Register */
|
||||
#define REG_GMAC_TSL (*(__IO uint32_t*)0x400501D0U) /**< (GMAC) 1588 Timer Seconds Low Register */
|
||||
#define REG_GMAC_TN (*(__IO uint32_t*)0x400501D4U) /**< (GMAC) 1588 Timer Nanoseconds Register */
|
||||
#define REG_GMAC_TA (*(__O uint32_t*)0x400501D8U) /**< (GMAC) 1588 Timer Adjust Register */
|
||||
#define REG_GMAC_TI (*(__IO uint32_t*)0x400501DCU) /**< (GMAC) 1588 Timer Increment Register */
|
||||
#define REG_GMAC_EFTSL (*(__I uint32_t*)0x400501E0U) /**< (GMAC) PTP Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_EFTN (*(__I uint32_t*)0x400501E4U) /**< (GMAC) PTP Event Frame Transmitted Nanoseconds Register */
|
||||
#define REG_GMAC_EFRSL (*(__I uint32_t*)0x400501E8U) /**< (GMAC) PTP Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_EFRN (*(__I uint32_t*)0x400501ECU) /**< (GMAC) PTP Event Frame Received Nanoseconds Register */
|
||||
#define REG_GMAC_PEFTSL (*(__I uint32_t*)0x400501F0U) /**< (GMAC) PTP Peer Event Frame Transmitted Seconds Low Register */
|
||||
#define REG_GMAC_PEFTN (*(__I uint32_t*)0x400501F4U) /**< (GMAC) PTP Peer Event Frame Transmitted Nanoseconds Register */
|
||||
#define REG_GMAC_PEFRSL (*(__I uint32_t*)0x400501F8U) /**< (GMAC) PTP Peer Event Frame Received Seconds Low Register */
|
||||
#define REG_GMAC_PEFRN (*(__I uint32_t*)0x400501FCU) /**< (GMAC) PTP Peer Event Frame Received Nanoseconds Register */
|
||||
#define REG_GMAC_RXLPI (*(__I uint32_t*)0x40050270U) /**< (GMAC) Received LPI Transitions */
|
||||
#define REG_GMAC_RXLPITIME (*(__I uint32_t*)0x40050274U) /**< (GMAC) Received LPI Time */
|
||||
#define REG_GMAC_TXLPI (*(__I uint32_t*)0x40050278U) /**< (GMAC) Transmit LPI Transitions */
|
||||
#define REG_GMAC_TXLPITIME (*(__I uint32_t*)0x4005027CU) /**< (GMAC) Transmit LPI Time */
|
||||
#define REG_GMAC_ISRPQ (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_ISRPQ0 (*(__I uint32_t*)0x40050400U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_ISRPQ1 (*(__I uint32_t*)0x40050404U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_ISRPQ2 (*(__I uint32_t*)0x40050408U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_ISRPQ3 (*(__I uint32_t*)0x4005040CU) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_ISRPQ4 (*(__I uint32_t*)0x40050410U) /**< (GMAC) Interrupt Status Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_TBQBAPQ (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_TBQBAPQ0 (*(__IO uint32_t*)0x40050440U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_TBQBAPQ1 (*(__IO uint32_t*)0x40050444U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_TBQBAPQ2 (*(__IO uint32_t*)0x40050448U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_TBQBAPQ3 (*(__IO uint32_t*)0x4005044CU) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_TBQBAPQ4 (*(__IO uint32_t*)0x40050450U) /**< (GMAC) Transmit Buffer Queue Base Address Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_RBQBAPQ (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_RBQBAPQ0 (*(__IO uint32_t*)0x40050480U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_RBQBAPQ1 (*(__IO uint32_t*)0x40050484U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_RBQBAPQ2 (*(__IO uint32_t*)0x40050488U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_RBQBAPQ3 (*(__IO uint32_t*)0x4005048CU) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_RBQBAPQ4 (*(__IO uint32_t*)0x40050490U) /**< (GMAC) Receive Buffer Queue Base Address Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_RBSRPQ (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_RBSRPQ0 (*(__IO uint32_t*)0x400504A0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_RBSRPQ1 (*(__IO uint32_t*)0x400504A4U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_RBSRPQ2 (*(__IO uint32_t*)0x400504A8U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_RBSRPQ3 (*(__IO uint32_t*)0x400504ACU) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_RBSRPQ4 (*(__IO uint32_t*)0x400504B0U) /**< (GMAC) Receive Buffer Size Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_CBSCR (*(__IO uint32_t*)0x400504BCU) /**< (GMAC) Credit-Based Shaping Control Register */
|
||||
#define REG_GMAC_CBSISQA (*(__IO uint32_t*)0x400504C0U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue A */
|
||||
#define REG_GMAC_CBSISQB (*(__IO uint32_t*)0x400504C4U) /**< (GMAC) Credit-Based Shaping IdleSlope Register for Queue B */
|
||||
#define REG_GMAC_ST1RPQ (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue */
|
||||
#define REG_GMAC_ST1RPQ0 (*(__IO uint32_t*)0x40050500U) /**< (GMAC) Screening Type 1 Register Priority Queue 0 */
|
||||
#define REG_GMAC_ST1RPQ1 (*(__IO uint32_t*)0x40050504U) /**< (GMAC) Screening Type 1 Register Priority Queue 1 */
|
||||
#define REG_GMAC_ST1RPQ2 (*(__IO uint32_t*)0x40050508U) /**< (GMAC) Screening Type 1 Register Priority Queue 2 */
|
||||
#define REG_GMAC_ST1RPQ3 (*(__IO uint32_t*)0x4005050CU) /**< (GMAC) Screening Type 1 Register Priority Queue 3 */
|
||||
#define REG_GMAC_ST2RPQ (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue */
|
||||
#define REG_GMAC_ST2RPQ0 (*(__IO uint32_t*)0x40050540U) /**< (GMAC) Screening Type 2 Register Priority Queue 0 */
|
||||
#define REG_GMAC_ST2RPQ1 (*(__IO uint32_t*)0x40050544U) /**< (GMAC) Screening Type 2 Register Priority Queue 1 */
|
||||
#define REG_GMAC_ST2RPQ2 (*(__IO uint32_t*)0x40050548U) /**< (GMAC) Screening Type 2 Register Priority Queue 2 */
|
||||
#define REG_GMAC_ST2RPQ3 (*(__IO uint32_t*)0x4005054CU) /**< (GMAC) Screening Type 2 Register Priority Queue 3 */
|
||||
#define REG_GMAC_ST2RPQ4 (*(__IO uint32_t*)0x40050550U) /**< (GMAC) Screening Type 2 Register Priority Queue 4 */
|
||||
#define REG_GMAC_ST2RPQ5 (*(__IO uint32_t*)0x40050554U) /**< (GMAC) Screening Type 2 Register Priority Queue 5 */
|
||||
#define REG_GMAC_ST2RPQ6 (*(__IO uint32_t*)0x40050558U) /**< (GMAC) Screening Type 2 Register Priority Queue 6 */
|
||||
#define REG_GMAC_ST2RPQ7 (*(__IO uint32_t*)0x4005055CU) /**< (GMAC) Screening Type 2 Register Priority Queue 7 */
|
||||
#define REG_GMAC_IERPQ (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IERPQ0 (*(__O uint32_t*)0x40050600U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IERPQ1 (*(__O uint32_t*)0x40050604U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IERPQ2 (*(__O uint32_t*)0x40050608U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IERPQ3 (*(__O uint32_t*)0x4005060CU) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IERPQ4 (*(__O uint32_t*)0x40050610U) /**< (GMAC) Interrupt Enable Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_IDRPQ (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IDRPQ0 (*(__O uint32_t*)0x40050620U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IDRPQ1 (*(__O uint32_t*)0x40050624U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IDRPQ2 (*(__O uint32_t*)0x40050628U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IDRPQ3 (*(__O uint32_t*)0x4005062CU) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IDRPQ4 (*(__O uint32_t*)0x40050630U) /**< (GMAC) Interrupt Disable Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_IMRPQ (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) */
|
||||
#define REG_GMAC_IMRPQ0 (*(__IO uint32_t*)0x40050640U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 0 */
|
||||
#define REG_GMAC_IMRPQ1 (*(__IO uint32_t*)0x40050644U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 1 */
|
||||
#define REG_GMAC_IMRPQ2 (*(__IO uint32_t*)0x40050648U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 2 */
|
||||
#define REG_GMAC_IMRPQ3 (*(__IO uint32_t*)0x4005064CU) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 3 */
|
||||
#define REG_GMAC_IMRPQ4 (*(__IO uint32_t*)0x40050650U) /**< (GMAC) Interrupt Mask Register Priority Queue (1..5) 4 */
|
||||
#define REG_GMAC_ST2ER (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register */
|
||||
#define REG_GMAC_ST2ER0 (*(__IO uint32_t*)0x400506E0U) /**< (GMAC) Screening Type 2 Ethertype Register 0 */
|
||||
#define REG_GMAC_ST2ER1 (*(__IO uint32_t*)0x400506E4U) /**< (GMAC) Screening Type 2 Ethertype Register 1 */
|
||||
#define REG_GMAC_ST2ER2 (*(__IO uint32_t*)0x400506E8U) /**< (GMAC) Screening Type 2 Ethertype Register 2 */
|
||||
#define REG_GMAC_ST2ER3 (*(__IO uint32_t*)0x400506ECU) /**< (GMAC) Screening Type 2 Ethertype Register 3 */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for GMAC peripheral ========== */
|
||||
#define GMAC_INSTANCE_ID 39
|
||||
#define GMAC_CLOCK_ID 39
|
||||
|
||||
#endif /* _SAME70_GMAC_INSTANCE_ */
|
||||
60
lib/same70b/include/instance/gpbr.h
Normal file
60
lib/same70b/include/instance/gpbr.h
Normal file
|
|
@ -0,0 +1,60 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for GPBR
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_GPBR_INSTANCE_H_
|
||||
#define _SAME70_GPBR_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for GPBR peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_GPBR_SYS_GPBR (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */
|
||||
#define REG_GPBR_SYS_GPBR0 (0x400E1890) /**< (GPBR) General Purpose Backup Register 0 */
|
||||
#define REG_GPBR_SYS_GPBR1 (0x400E1894) /**< (GPBR) General Purpose Backup Register 1 */
|
||||
#define REG_GPBR_SYS_GPBR2 (0x400E1898) /**< (GPBR) General Purpose Backup Register 2 */
|
||||
#define REG_GPBR_SYS_GPBR3 (0x400E189C) /**< (GPBR) General Purpose Backup Register 3 */
|
||||
#define REG_GPBR_SYS_GPBR4 (0x400E18A0) /**< (GPBR) General Purpose Backup Register 4 */
|
||||
#define REG_GPBR_SYS_GPBR5 (0x400E18A4) /**< (GPBR) General Purpose Backup Register 5 */
|
||||
#define REG_GPBR_SYS_GPBR6 (0x400E18A8) /**< (GPBR) General Purpose Backup Register 6 */
|
||||
#define REG_GPBR_SYS_GPBR7 (0x400E18AC) /**< (GPBR) General Purpose Backup Register 7 */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_GPBR_SYS_GPBR (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */
|
||||
#define REG_GPBR_SYS_GPBR0 (*(__IO uint32_t*)0x400E1890U) /**< (GPBR) General Purpose Backup Register 0 */
|
||||
#define REG_GPBR_SYS_GPBR1 (*(__IO uint32_t*)0x400E1894U) /**< (GPBR) General Purpose Backup Register 1 */
|
||||
#define REG_GPBR_SYS_GPBR2 (*(__IO uint32_t*)0x400E1898U) /**< (GPBR) General Purpose Backup Register 2 */
|
||||
#define REG_GPBR_SYS_GPBR3 (*(__IO uint32_t*)0x400E189CU) /**< (GPBR) General Purpose Backup Register 3 */
|
||||
#define REG_GPBR_SYS_GPBR4 (*(__IO uint32_t*)0x400E18A0U) /**< (GPBR) General Purpose Backup Register 4 */
|
||||
#define REG_GPBR_SYS_GPBR5 (*(__IO uint32_t*)0x400E18A4U) /**< (GPBR) General Purpose Backup Register 5 */
|
||||
#define REG_GPBR_SYS_GPBR6 (*(__IO uint32_t*)0x400E18A8U) /**< (GPBR) General Purpose Backup Register 6 */
|
||||
#define REG_GPBR_SYS_GPBR7 (*(__IO uint32_t*)0x400E18ACU) /**< (GPBR) General Purpose Backup Register 7 */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_GPBR_INSTANCE_ */
|
||||
609
lib/same70b/include/instance/hsmci.h
Normal file
609
lib/same70b/include/instance/hsmci.h
Normal file
|
|
@ -0,0 +1,609 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for HSMCI
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_HSMCI_INSTANCE_H_
|
||||
#define _SAME70_HSMCI_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for HSMCI peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_HSMCI_CR (0x40000000) /**< (HSMCI) Control Register */
|
||||
#define REG_HSMCI_MR (0x40000004) /**< (HSMCI) Mode Register */
|
||||
#define REG_HSMCI_DTOR (0x40000008) /**< (HSMCI) Data Timeout Register */
|
||||
#define REG_HSMCI_SDCR (0x4000000C) /**< (HSMCI) SD/SDIO Card Register */
|
||||
#define REG_HSMCI_ARGR (0x40000010) /**< (HSMCI) Argument Register */
|
||||
#define REG_HSMCI_CMDR (0x40000014) /**< (HSMCI) Command Register */
|
||||
#define REG_HSMCI_BLKR (0x40000018) /**< (HSMCI) Block Register */
|
||||
#define REG_HSMCI_CSTOR (0x4000001C) /**< (HSMCI) Completion Signal Timeout Register */
|
||||
#define REG_HSMCI_RSPR (0x40000020) /**< (HSMCI) Response Register 0 */
|
||||
#define REG_HSMCI_RSPR0 (0x40000020) /**< (HSMCI) Response Register 0 */
|
||||
#define REG_HSMCI_RSPR1 (0x40000024) /**< (HSMCI) Response Register 1 */
|
||||
#define REG_HSMCI_RSPR2 (0x40000028) /**< (HSMCI) Response Register 2 */
|
||||
#define REG_HSMCI_RSPR3 (0x4000002C) /**< (HSMCI) Response Register 3 */
|
||||
#define REG_HSMCI_RDR (0x40000030) /**< (HSMCI) Receive Data Register */
|
||||
#define REG_HSMCI_TDR (0x40000034) /**< (HSMCI) Transmit Data Register */
|
||||
#define REG_HSMCI_SR (0x40000040) /**< (HSMCI) Status Register */
|
||||
#define REG_HSMCI_IER (0x40000044) /**< (HSMCI) Interrupt Enable Register */
|
||||
#define REG_HSMCI_IDR (0x40000048) /**< (HSMCI) Interrupt Disable Register */
|
||||
#define REG_HSMCI_IMR (0x4000004C) /**< (HSMCI) Interrupt Mask Register */
|
||||
#define REG_HSMCI_DMA (0x40000050) /**< (HSMCI) DMA Configuration Register */
|
||||
#define REG_HSMCI_CFG (0x40000054) /**< (HSMCI) Configuration Register */
|
||||
#define REG_HSMCI_WPMR (0x400000E4) /**< (HSMCI) Write Protection Mode Register */
|
||||
#define REG_HSMCI_WPSR (0x400000E8) /**< (HSMCI) Write Protection Status Register */
|
||||
#define REG_HSMCI_FIFO (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */
|
||||
#define REG_HSMCI_FIFO0 (0x40000200) /**< (HSMCI) FIFO Memory Aperture0 0 */
|
||||
#define REG_HSMCI_FIFO1 (0x40000204) /**< (HSMCI) FIFO Memory Aperture0 1 */
|
||||
#define REG_HSMCI_FIFO2 (0x40000208) /**< (HSMCI) FIFO Memory Aperture0 2 */
|
||||
#define REG_HSMCI_FIFO3 (0x4000020C) /**< (HSMCI) FIFO Memory Aperture0 3 */
|
||||
#define REG_HSMCI_FIFO4 (0x40000210) /**< (HSMCI) FIFO Memory Aperture0 4 */
|
||||
#define REG_HSMCI_FIFO5 (0x40000214) /**< (HSMCI) FIFO Memory Aperture0 5 */
|
||||
#define REG_HSMCI_FIFO6 (0x40000218) /**< (HSMCI) FIFO Memory Aperture0 6 */
|
||||
#define REG_HSMCI_FIFO7 (0x4000021C) /**< (HSMCI) FIFO Memory Aperture0 7 */
|
||||
#define REG_HSMCI_FIFO8 (0x40000220) /**< (HSMCI) FIFO Memory Aperture0 8 */
|
||||
#define REG_HSMCI_FIFO9 (0x40000224) /**< (HSMCI) FIFO Memory Aperture0 9 */
|
||||
#define REG_HSMCI_FIFO10 (0x40000228) /**< (HSMCI) FIFO Memory Aperture0 10 */
|
||||
#define REG_HSMCI_FIFO11 (0x4000022C) /**< (HSMCI) FIFO Memory Aperture0 11 */
|
||||
#define REG_HSMCI_FIFO12 (0x40000230) /**< (HSMCI) FIFO Memory Aperture0 12 */
|
||||
#define REG_HSMCI_FIFO13 (0x40000234) /**< (HSMCI) FIFO Memory Aperture0 13 */
|
||||
#define REG_HSMCI_FIFO14 (0x40000238) /**< (HSMCI) FIFO Memory Aperture0 14 */
|
||||
#define REG_HSMCI_FIFO15 (0x4000023C) /**< (HSMCI) FIFO Memory Aperture0 15 */
|
||||
#define REG_HSMCI_FIFO16 (0x40000240) /**< (HSMCI) FIFO Memory Aperture0 16 */
|
||||
#define REG_HSMCI_FIFO17 (0x40000244) /**< (HSMCI) FIFO Memory Aperture0 17 */
|
||||
#define REG_HSMCI_FIFO18 (0x40000248) /**< (HSMCI) FIFO Memory Aperture0 18 */
|
||||
#define REG_HSMCI_FIFO19 (0x4000024C) /**< (HSMCI) FIFO Memory Aperture0 19 */
|
||||
#define REG_HSMCI_FIFO20 (0x40000250) /**< (HSMCI) FIFO Memory Aperture0 20 */
|
||||
#define REG_HSMCI_FIFO21 (0x40000254) /**< (HSMCI) FIFO Memory Aperture0 21 */
|
||||
#define REG_HSMCI_FIFO22 (0x40000258) /**< (HSMCI) FIFO Memory Aperture0 22 */
|
||||
#define REG_HSMCI_FIFO23 (0x4000025C) /**< (HSMCI) FIFO Memory Aperture0 23 */
|
||||
#define REG_HSMCI_FIFO24 (0x40000260) /**< (HSMCI) FIFO Memory Aperture0 24 */
|
||||
#define REG_HSMCI_FIFO25 (0x40000264) /**< (HSMCI) FIFO Memory Aperture0 25 */
|
||||
#define REG_HSMCI_FIFO26 (0x40000268) /**< (HSMCI) FIFO Memory Aperture0 26 */
|
||||
#define REG_HSMCI_FIFO27 (0x4000026C) /**< (HSMCI) FIFO Memory Aperture0 27 */
|
||||
#define REG_HSMCI_FIFO28 (0x40000270) /**< (HSMCI) FIFO Memory Aperture0 28 */
|
||||
#define REG_HSMCI_FIFO29 (0x40000274) /**< (HSMCI) FIFO Memory Aperture0 29 */
|
||||
#define REG_HSMCI_FIFO30 (0x40000278) /**< (HSMCI) FIFO Memory Aperture0 30 */
|
||||
#define REG_HSMCI_FIFO31 (0x4000027C) /**< (HSMCI) FIFO Memory Aperture0 31 */
|
||||
#define REG_HSMCI_FIFO32 (0x40000280) /**< (HSMCI) FIFO Memory Aperture0 32 */
|
||||
#define REG_HSMCI_FIFO33 (0x40000284) /**< (HSMCI) FIFO Memory Aperture0 33 */
|
||||
#define REG_HSMCI_FIFO34 (0x40000288) /**< (HSMCI) FIFO Memory Aperture0 34 */
|
||||
#define REG_HSMCI_FIFO35 (0x4000028C) /**< (HSMCI) FIFO Memory Aperture0 35 */
|
||||
#define REG_HSMCI_FIFO36 (0x40000290) /**< (HSMCI) FIFO Memory Aperture0 36 */
|
||||
#define REG_HSMCI_FIFO37 (0x40000294) /**< (HSMCI) FIFO Memory Aperture0 37 */
|
||||
#define REG_HSMCI_FIFO38 (0x40000298) /**< (HSMCI) FIFO Memory Aperture0 38 */
|
||||
#define REG_HSMCI_FIFO39 (0x4000029C) /**< (HSMCI) FIFO Memory Aperture0 39 */
|
||||
#define REG_HSMCI_FIFO40 (0x400002A0) /**< (HSMCI) FIFO Memory Aperture0 40 */
|
||||
#define REG_HSMCI_FIFO41 (0x400002A4) /**< (HSMCI) FIFO Memory Aperture0 41 */
|
||||
#define REG_HSMCI_FIFO42 (0x400002A8) /**< (HSMCI) FIFO Memory Aperture0 42 */
|
||||
#define REG_HSMCI_FIFO43 (0x400002AC) /**< (HSMCI) FIFO Memory Aperture0 43 */
|
||||
#define REG_HSMCI_FIFO44 (0x400002B0) /**< (HSMCI) FIFO Memory Aperture0 44 */
|
||||
#define REG_HSMCI_FIFO45 (0x400002B4) /**< (HSMCI) FIFO Memory Aperture0 45 */
|
||||
#define REG_HSMCI_FIFO46 (0x400002B8) /**< (HSMCI) FIFO Memory Aperture0 46 */
|
||||
#define REG_HSMCI_FIFO47 (0x400002BC) /**< (HSMCI) FIFO Memory Aperture0 47 */
|
||||
#define REG_HSMCI_FIFO48 (0x400002C0) /**< (HSMCI) FIFO Memory Aperture0 48 */
|
||||
#define REG_HSMCI_FIFO49 (0x400002C4) /**< (HSMCI) FIFO Memory Aperture0 49 */
|
||||
#define REG_HSMCI_FIFO50 (0x400002C8) /**< (HSMCI) FIFO Memory Aperture0 50 */
|
||||
#define REG_HSMCI_FIFO51 (0x400002CC) /**< (HSMCI) FIFO Memory Aperture0 51 */
|
||||
#define REG_HSMCI_FIFO52 (0x400002D0) /**< (HSMCI) FIFO Memory Aperture0 52 */
|
||||
#define REG_HSMCI_FIFO53 (0x400002D4) /**< (HSMCI) FIFO Memory Aperture0 53 */
|
||||
#define REG_HSMCI_FIFO54 (0x400002D8) /**< (HSMCI) FIFO Memory Aperture0 54 */
|
||||
#define REG_HSMCI_FIFO55 (0x400002DC) /**< (HSMCI) FIFO Memory Aperture0 55 */
|
||||
#define REG_HSMCI_FIFO56 (0x400002E0) /**< (HSMCI) FIFO Memory Aperture0 56 */
|
||||
#define REG_HSMCI_FIFO57 (0x400002E4) /**< (HSMCI) FIFO Memory Aperture0 57 */
|
||||
#define REG_HSMCI_FIFO58 (0x400002E8) /**< (HSMCI) FIFO Memory Aperture0 58 */
|
||||
#define REG_HSMCI_FIFO59 (0x400002EC) /**< (HSMCI) FIFO Memory Aperture0 59 */
|
||||
#define REG_HSMCI_FIFO60 (0x400002F0) /**< (HSMCI) FIFO Memory Aperture0 60 */
|
||||
#define REG_HSMCI_FIFO61 (0x400002F4) /**< (HSMCI) FIFO Memory Aperture0 61 */
|
||||
#define REG_HSMCI_FIFO62 (0x400002F8) /**< (HSMCI) FIFO Memory Aperture0 62 */
|
||||
#define REG_HSMCI_FIFO63 (0x400002FC) /**< (HSMCI) FIFO Memory Aperture0 63 */
|
||||
#define REG_HSMCI_FIFO64 (0x40000300) /**< (HSMCI) FIFO Memory Aperture0 64 */
|
||||
#define REG_HSMCI_FIFO65 (0x40000304) /**< (HSMCI) FIFO Memory Aperture0 65 */
|
||||
#define REG_HSMCI_FIFO66 (0x40000308) /**< (HSMCI) FIFO Memory Aperture0 66 */
|
||||
#define REG_HSMCI_FIFO67 (0x4000030C) /**< (HSMCI) FIFO Memory Aperture0 67 */
|
||||
#define REG_HSMCI_FIFO68 (0x40000310) /**< (HSMCI) FIFO Memory Aperture0 68 */
|
||||
#define REG_HSMCI_FIFO69 (0x40000314) /**< (HSMCI) FIFO Memory Aperture0 69 */
|
||||
#define REG_HSMCI_FIFO70 (0x40000318) /**< (HSMCI) FIFO Memory Aperture0 70 */
|
||||
#define REG_HSMCI_FIFO71 (0x4000031C) /**< (HSMCI) FIFO Memory Aperture0 71 */
|
||||
#define REG_HSMCI_FIFO72 (0x40000320) /**< (HSMCI) FIFO Memory Aperture0 72 */
|
||||
#define REG_HSMCI_FIFO73 (0x40000324) /**< (HSMCI) FIFO Memory Aperture0 73 */
|
||||
#define REG_HSMCI_FIFO74 (0x40000328) /**< (HSMCI) FIFO Memory Aperture0 74 */
|
||||
#define REG_HSMCI_FIFO75 (0x4000032C) /**< (HSMCI) FIFO Memory Aperture0 75 */
|
||||
#define REG_HSMCI_FIFO76 (0x40000330) /**< (HSMCI) FIFO Memory Aperture0 76 */
|
||||
#define REG_HSMCI_FIFO77 (0x40000334) /**< (HSMCI) FIFO Memory Aperture0 77 */
|
||||
#define REG_HSMCI_FIFO78 (0x40000338) /**< (HSMCI) FIFO Memory Aperture0 78 */
|
||||
#define REG_HSMCI_FIFO79 (0x4000033C) /**< (HSMCI) FIFO Memory Aperture0 79 */
|
||||
#define REG_HSMCI_FIFO80 (0x40000340) /**< (HSMCI) FIFO Memory Aperture0 80 */
|
||||
#define REG_HSMCI_FIFO81 (0x40000344) /**< (HSMCI) FIFO Memory Aperture0 81 */
|
||||
#define REG_HSMCI_FIFO82 (0x40000348) /**< (HSMCI) FIFO Memory Aperture0 82 */
|
||||
#define REG_HSMCI_FIFO83 (0x4000034C) /**< (HSMCI) FIFO Memory Aperture0 83 */
|
||||
#define REG_HSMCI_FIFO84 (0x40000350) /**< (HSMCI) FIFO Memory Aperture0 84 */
|
||||
#define REG_HSMCI_FIFO85 (0x40000354) /**< (HSMCI) FIFO Memory Aperture0 85 */
|
||||
#define REG_HSMCI_FIFO86 (0x40000358) /**< (HSMCI) FIFO Memory Aperture0 86 */
|
||||
#define REG_HSMCI_FIFO87 (0x4000035C) /**< (HSMCI) FIFO Memory Aperture0 87 */
|
||||
#define REG_HSMCI_FIFO88 (0x40000360) /**< (HSMCI) FIFO Memory Aperture0 88 */
|
||||
#define REG_HSMCI_FIFO89 (0x40000364) /**< (HSMCI) FIFO Memory Aperture0 89 */
|
||||
#define REG_HSMCI_FIFO90 (0x40000368) /**< (HSMCI) FIFO Memory Aperture0 90 */
|
||||
#define REG_HSMCI_FIFO91 (0x4000036C) /**< (HSMCI) FIFO Memory Aperture0 91 */
|
||||
#define REG_HSMCI_FIFO92 (0x40000370) /**< (HSMCI) FIFO Memory Aperture0 92 */
|
||||
#define REG_HSMCI_FIFO93 (0x40000374) /**< (HSMCI) FIFO Memory Aperture0 93 */
|
||||
#define REG_HSMCI_FIFO94 (0x40000378) /**< (HSMCI) FIFO Memory Aperture0 94 */
|
||||
#define REG_HSMCI_FIFO95 (0x4000037C) /**< (HSMCI) FIFO Memory Aperture0 95 */
|
||||
#define REG_HSMCI_FIFO96 (0x40000380) /**< (HSMCI) FIFO Memory Aperture0 96 */
|
||||
#define REG_HSMCI_FIFO97 (0x40000384) /**< (HSMCI) FIFO Memory Aperture0 97 */
|
||||
#define REG_HSMCI_FIFO98 (0x40000388) /**< (HSMCI) FIFO Memory Aperture0 98 */
|
||||
#define REG_HSMCI_FIFO99 (0x4000038C) /**< (HSMCI) FIFO Memory Aperture0 99 */
|
||||
#define REG_HSMCI_FIFO100 (0x40000390) /**< (HSMCI) FIFO Memory Aperture0 100 */
|
||||
#define REG_HSMCI_FIFO101 (0x40000394) /**< (HSMCI) FIFO Memory Aperture0 101 */
|
||||
#define REG_HSMCI_FIFO102 (0x40000398) /**< (HSMCI) FIFO Memory Aperture0 102 */
|
||||
#define REG_HSMCI_FIFO103 (0x4000039C) /**< (HSMCI) FIFO Memory Aperture0 103 */
|
||||
#define REG_HSMCI_FIFO104 (0x400003A0) /**< (HSMCI) FIFO Memory Aperture0 104 */
|
||||
#define REG_HSMCI_FIFO105 (0x400003A4) /**< (HSMCI) FIFO Memory Aperture0 105 */
|
||||
#define REG_HSMCI_FIFO106 (0x400003A8) /**< (HSMCI) FIFO Memory Aperture0 106 */
|
||||
#define REG_HSMCI_FIFO107 (0x400003AC) /**< (HSMCI) FIFO Memory Aperture0 107 */
|
||||
#define REG_HSMCI_FIFO108 (0x400003B0) /**< (HSMCI) FIFO Memory Aperture0 108 */
|
||||
#define REG_HSMCI_FIFO109 (0x400003B4) /**< (HSMCI) FIFO Memory Aperture0 109 */
|
||||
#define REG_HSMCI_FIFO110 (0x400003B8) /**< (HSMCI) FIFO Memory Aperture0 110 */
|
||||
#define REG_HSMCI_FIFO111 (0x400003BC) /**< (HSMCI) FIFO Memory Aperture0 111 */
|
||||
#define REG_HSMCI_FIFO112 (0x400003C0) /**< (HSMCI) FIFO Memory Aperture0 112 */
|
||||
#define REG_HSMCI_FIFO113 (0x400003C4) /**< (HSMCI) FIFO Memory Aperture0 113 */
|
||||
#define REG_HSMCI_FIFO114 (0x400003C8) /**< (HSMCI) FIFO Memory Aperture0 114 */
|
||||
#define REG_HSMCI_FIFO115 (0x400003CC) /**< (HSMCI) FIFO Memory Aperture0 115 */
|
||||
#define REG_HSMCI_FIFO116 (0x400003D0) /**< (HSMCI) FIFO Memory Aperture0 116 */
|
||||
#define REG_HSMCI_FIFO117 (0x400003D4) /**< (HSMCI) FIFO Memory Aperture0 117 */
|
||||
#define REG_HSMCI_FIFO118 (0x400003D8) /**< (HSMCI) FIFO Memory Aperture0 118 */
|
||||
#define REG_HSMCI_FIFO119 (0x400003DC) /**< (HSMCI) FIFO Memory Aperture0 119 */
|
||||
#define REG_HSMCI_FIFO120 (0x400003E0) /**< (HSMCI) FIFO Memory Aperture0 120 */
|
||||
#define REG_HSMCI_FIFO121 (0x400003E4) /**< (HSMCI) FIFO Memory Aperture0 121 */
|
||||
#define REG_HSMCI_FIFO122 (0x400003E8) /**< (HSMCI) FIFO Memory Aperture0 122 */
|
||||
#define REG_HSMCI_FIFO123 (0x400003EC) /**< (HSMCI) FIFO Memory Aperture0 123 */
|
||||
#define REG_HSMCI_FIFO124 (0x400003F0) /**< (HSMCI) FIFO Memory Aperture0 124 */
|
||||
#define REG_HSMCI_FIFO125 (0x400003F4) /**< (HSMCI) FIFO Memory Aperture0 125 */
|
||||
#define REG_HSMCI_FIFO126 (0x400003F8) /**< (HSMCI) FIFO Memory Aperture0 126 */
|
||||
#define REG_HSMCI_FIFO127 (0x400003FC) /**< (HSMCI) FIFO Memory Aperture0 127 */
|
||||
#define REG_HSMCI_FIFO128 (0x40000400) /**< (HSMCI) FIFO Memory Aperture0 128 */
|
||||
#define REG_HSMCI_FIFO129 (0x40000404) /**< (HSMCI) FIFO Memory Aperture0 129 */
|
||||
#define REG_HSMCI_FIFO130 (0x40000408) /**< (HSMCI) FIFO Memory Aperture0 130 */
|
||||
#define REG_HSMCI_FIFO131 (0x4000040C) /**< (HSMCI) FIFO Memory Aperture0 131 */
|
||||
#define REG_HSMCI_FIFO132 (0x40000410) /**< (HSMCI) FIFO Memory Aperture0 132 */
|
||||
#define REG_HSMCI_FIFO133 (0x40000414) /**< (HSMCI) FIFO Memory Aperture0 133 */
|
||||
#define REG_HSMCI_FIFO134 (0x40000418) /**< (HSMCI) FIFO Memory Aperture0 134 */
|
||||
#define REG_HSMCI_FIFO135 (0x4000041C) /**< (HSMCI) FIFO Memory Aperture0 135 */
|
||||
#define REG_HSMCI_FIFO136 (0x40000420) /**< (HSMCI) FIFO Memory Aperture0 136 */
|
||||
#define REG_HSMCI_FIFO137 (0x40000424) /**< (HSMCI) FIFO Memory Aperture0 137 */
|
||||
#define REG_HSMCI_FIFO138 (0x40000428) /**< (HSMCI) FIFO Memory Aperture0 138 */
|
||||
#define REG_HSMCI_FIFO139 (0x4000042C) /**< (HSMCI) FIFO Memory Aperture0 139 */
|
||||
#define REG_HSMCI_FIFO140 (0x40000430) /**< (HSMCI) FIFO Memory Aperture0 140 */
|
||||
#define REG_HSMCI_FIFO141 (0x40000434) /**< (HSMCI) FIFO Memory Aperture0 141 */
|
||||
#define REG_HSMCI_FIFO142 (0x40000438) /**< (HSMCI) FIFO Memory Aperture0 142 */
|
||||
#define REG_HSMCI_FIFO143 (0x4000043C) /**< (HSMCI) FIFO Memory Aperture0 143 */
|
||||
#define REG_HSMCI_FIFO144 (0x40000440) /**< (HSMCI) FIFO Memory Aperture0 144 */
|
||||
#define REG_HSMCI_FIFO145 (0x40000444) /**< (HSMCI) FIFO Memory Aperture0 145 */
|
||||
#define REG_HSMCI_FIFO146 (0x40000448) /**< (HSMCI) FIFO Memory Aperture0 146 */
|
||||
#define REG_HSMCI_FIFO147 (0x4000044C) /**< (HSMCI) FIFO Memory Aperture0 147 */
|
||||
#define REG_HSMCI_FIFO148 (0x40000450) /**< (HSMCI) FIFO Memory Aperture0 148 */
|
||||
#define REG_HSMCI_FIFO149 (0x40000454) /**< (HSMCI) FIFO Memory Aperture0 149 */
|
||||
#define REG_HSMCI_FIFO150 (0x40000458) /**< (HSMCI) FIFO Memory Aperture0 150 */
|
||||
#define REG_HSMCI_FIFO151 (0x4000045C) /**< (HSMCI) FIFO Memory Aperture0 151 */
|
||||
#define REG_HSMCI_FIFO152 (0x40000460) /**< (HSMCI) FIFO Memory Aperture0 152 */
|
||||
#define REG_HSMCI_FIFO153 (0x40000464) /**< (HSMCI) FIFO Memory Aperture0 153 */
|
||||
#define REG_HSMCI_FIFO154 (0x40000468) /**< (HSMCI) FIFO Memory Aperture0 154 */
|
||||
#define REG_HSMCI_FIFO155 (0x4000046C) /**< (HSMCI) FIFO Memory Aperture0 155 */
|
||||
#define REG_HSMCI_FIFO156 (0x40000470) /**< (HSMCI) FIFO Memory Aperture0 156 */
|
||||
#define REG_HSMCI_FIFO157 (0x40000474) /**< (HSMCI) FIFO Memory Aperture0 157 */
|
||||
#define REG_HSMCI_FIFO158 (0x40000478) /**< (HSMCI) FIFO Memory Aperture0 158 */
|
||||
#define REG_HSMCI_FIFO159 (0x4000047C) /**< (HSMCI) FIFO Memory Aperture0 159 */
|
||||
#define REG_HSMCI_FIFO160 (0x40000480) /**< (HSMCI) FIFO Memory Aperture0 160 */
|
||||
#define REG_HSMCI_FIFO161 (0x40000484) /**< (HSMCI) FIFO Memory Aperture0 161 */
|
||||
#define REG_HSMCI_FIFO162 (0x40000488) /**< (HSMCI) FIFO Memory Aperture0 162 */
|
||||
#define REG_HSMCI_FIFO163 (0x4000048C) /**< (HSMCI) FIFO Memory Aperture0 163 */
|
||||
#define REG_HSMCI_FIFO164 (0x40000490) /**< (HSMCI) FIFO Memory Aperture0 164 */
|
||||
#define REG_HSMCI_FIFO165 (0x40000494) /**< (HSMCI) FIFO Memory Aperture0 165 */
|
||||
#define REG_HSMCI_FIFO166 (0x40000498) /**< (HSMCI) FIFO Memory Aperture0 166 */
|
||||
#define REG_HSMCI_FIFO167 (0x4000049C) /**< (HSMCI) FIFO Memory Aperture0 167 */
|
||||
#define REG_HSMCI_FIFO168 (0x400004A0) /**< (HSMCI) FIFO Memory Aperture0 168 */
|
||||
#define REG_HSMCI_FIFO169 (0x400004A4) /**< (HSMCI) FIFO Memory Aperture0 169 */
|
||||
#define REG_HSMCI_FIFO170 (0x400004A8) /**< (HSMCI) FIFO Memory Aperture0 170 */
|
||||
#define REG_HSMCI_FIFO171 (0x400004AC) /**< (HSMCI) FIFO Memory Aperture0 171 */
|
||||
#define REG_HSMCI_FIFO172 (0x400004B0) /**< (HSMCI) FIFO Memory Aperture0 172 */
|
||||
#define REG_HSMCI_FIFO173 (0x400004B4) /**< (HSMCI) FIFO Memory Aperture0 173 */
|
||||
#define REG_HSMCI_FIFO174 (0x400004B8) /**< (HSMCI) FIFO Memory Aperture0 174 */
|
||||
#define REG_HSMCI_FIFO175 (0x400004BC) /**< (HSMCI) FIFO Memory Aperture0 175 */
|
||||
#define REG_HSMCI_FIFO176 (0x400004C0) /**< (HSMCI) FIFO Memory Aperture0 176 */
|
||||
#define REG_HSMCI_FIFO177 (0x400004C4) /**< (HSMCI) FIFO Memory Aperture0 177 */
|
||||
#define REG_HSMCI_FIFO178 (0x400004C8) /**< (HSMCI) FIFO Memory Aperture0 178 */
|
||||
#define REG_HSMCI_FIFO179 (0x400004CC) /**< (HSMCI) FIFO Memory Aperture0 179 */
|
||||
#define REG_HSMCI_FIFO180 (0x400004D0) /**< (HSMCI) FIFO Memory Aperture0 180 */
|
||||
#define REG_HSMCI_FIFO181 (0x400004D4) /**< (HSMCI) FIFO Memory Aperture0 181 */
|
||||
#define REG_HSMCI_FIFO182 (0x400004D8) /**< (HSMCI) FIFO Memory Aperture0 182 */
|
||||
#define REG_HSMCI_FIFO183 (0x400004DC) /**< (HSMCI) FIFO Memory Aperture0 183 */
|
||||
#define REG_HSMCI_FIFO184 (0x400004E0) /**< (HSMCI) FIFO Memory Aperture0 184 */
|
||||
#define REG_HSMCI_FIFO185 (0x400004E4) /**< (HSMCI) FIFO Memory Aperture0 185 */
|
||||
#define REG_HSMCI_FIFO186 (0x400004E8) /**< (HSMCI) FIFO Memory Aperture0 186 */
|
||||
#define REG_HSMCI_FIFO187 (0x400004EC) /**< (HSMCI) FIFO Memory Aperture0 187 */
|
||||
#define REG_HSMCI_FIFO188 (0x400004F0) /**< (HSMCI) FIFO Memory Aperture0 188 */
|
||||
#define REG_HSMCI_FIFO189 (0x400004F4) /**< (HSMCI) FIFO Memory Aperture0 189 */
|
||||
#define REG_HSMCI_FIFO190 (0x400004F8) /**< (HSMCI) FIFO Memory Aperture0 190 */
|
||||
#define REG_HSMCI_FIFO191 (0x400004FC) /**< (HSMCI) FIFO Memory Aperture0 191 */
|
||||
#define REG_HSMCI_FIFO192 (0x40000500) /**< (HSMCI) FIFO Memory Aperture0 192 */
|
||||
#define REG_HSMCI_FIFO193 (0x40000504) /**< (HSMCI) FIFO Memory Aperture0 193 */
|
||||
#define REG_HSMCI_FIFO194 (0x40000508) /**< (HSMCI) FIFO Memory Aperture0 194 */
|
||||
#define REG_HSMCI_FIFO195 (0x4000050C) /**< (HSMCI) FIFO Memory Aperture0 195 */
|
||||
#define REG_HSMCI_FIFO196 (0x40000510) /**< (HSMCI) FIFO Memory Aperture0 196 */
|
||||
#define REG_HSMCI_FIFO197 (0x40000514) /**< (HSMCI) FIFO Memory Aperture0 197 */
|
||||
#define REG_HSMCI_FIFO198 (0x40000518) /**< (HSMCI) FIFO Memory Aperture0 198 */
|
||||
#define REG_HSMCI_FIFO199 (0x4000051C) /**< (HSMCI) FIFO Memory Aperture0 199 */
|
||||
#define REG_HSMCI_FIFO200 (0x40000520) /**< (HSMCI) FIFO Memory Aperture0 200 */
|
||||
#define REG_HSMCI_FIFO201 (0x40000524) /**< (HSMCI) FIFO Memory Aperture0 201 */
|
||||
#define REG_HSMCI_FIFO202 (0x40000528) /**< (HSMCI) FIFO Memory Aperture0 202 */
|
||||
#define REG_HSMCI_FIFO203 (0x4000052C) /**< (HSMCI) FIFO Memory Aperture0 203 */
|
||||
#define REG_HSMCI_FIFO204 (0x40000530) /**< (HSMCI) FIFO Memory Aperture0 204 */
|
||||
#define REG_HSMCI_FIFO205 (0x40000534) /**< (HSMCI) FIFO Memory Aperture0 205 */
|
||||
#define REG_HSMCI_FIFO206 (0x40000538) /**< (HSMCI) FIFO Memory Aperture0 206 */
|
||||
#define REG_HSMCI_FIFO207 (0x4000053C) /**< (HSMCI) FIFO Memory Aperture0 207 */
|
||||
#define REG_HSMCI_FIFO208 (0x40000540) /**< (HSMCI) FIFO Memory Aperture0 208 */
|
||||
#define REG_HSMCI_FIFO209 (0x40000544) /**< (HSMCI) FIFO Memory Aperture0 209 */
|
||||
#define REG_HSMCI_FIFO210 (0x40000548) /**< (HSMCI) FIFO Memory Aperture0 210 */
|
||||
#define REG_HSMCI_FIFO211 (0x4000054C) /**< (HSMCI) FIFO Memory Aperture0 211 */
|
||||
#define REG_HSMCI_FIFO212 (0x40000550) /**< (HSMCI) FIFO Memory Aperture0 212 */
|
||||
#define REG_HSMCI_FIFO213 (0x40000554) /**< (HSMCI) FIFO Memory Aperture0 213 */
|
||||
#define REG_HSMCI_FIFO214 (0x40000558) /**< (HSMCI) FIFO Memory Aperture0 214 */
|
||||
#define REG_HSMCI_FIFO215 (0x4000055C) /**< (HSMCI) FIFO Memory Aperture0 215 */
|
||||
#define REG_HSMCI_FIFO216 (0x40000560) /**< (HSMCI) FIFO Memory Aperture0 216 */
|
||||
#define REG_HSMCI_FIFO217 (0x40000564) /**< (HSMCI) FIFO Memory Aperture0 217 */
|
||||
#define REG_HSMCI_FIFO218 (0x40000568) /**< (HSMCI) FIFO Memory Aperture0 218 */
|
||||
#define REG_HSMCI_FIFO219 (0x4000056C) /**< (HSMCI) FIFO Memory Aperture0 219 */
|
||||
#define REG_HSMCI_FIFO220 (0x40000570) /**< (HSMCI) FIFO Memory Aperture0 220 */
|
||||
#define REG_HSMCI_FIFO221 (0x40000574) /**< (HSMCI) FIFO Memory Aperture0 221 */
|
||||
#define REG_HSMCI_FIFO222 (0x40000578) /**< (HSMCI) FIFO Memory Aperture0 222 */
|
||||
#define REG_HSMCI_FIFO223 (0x4000057C) /**< (HSMCI) FIFO Memory Aperture0 223 */
|
||||
#define REG_HSMCI_FIFO224 (0x40000580) /**< (HSMCI) FIFO Memory Aperture0 224 */
|
||||
#define REG_HSMCI_FIFO225 (0x40000584) /**< (HSMCI) FIFO Memory Aperture0 225 */
|
||||
#define REG_HSMCI_FIFO226 (0x40000588) /**< (HSMCI) FIFO Memory Aperture0 226 */
|
||||
#define REG_HSMCI_FIFO227 (0x4000058C) /**< (HSMCI) FIFO Memory Aperture0 227 */
|
||||
#define REG_HSMCI_FIFO228 (0x40000590) /**< (HSMCI) FIFO Memory Aperture0 228 */
|
||||
#define REG_HSMCI_FIFO229 (0x40000594) /**< (HSMCI) FIFO Memory Aperture0 229 */
|
||||
#define REG_HSMCI_FIFO230 (0x40000598) /**< (HSMCI) FIFO Memory Aperture0 230 */
|
||||
#define REG_HSMCI_FIFO231 (0x4000059C) /**< (HSMCI) FIFO Memory Aperture0 231 */
|
||||
#define REG_HSMCI_FIFO232 (0x400005A0) /**< (HSMCI) FIFO Memory Aperture0 232 */
|
||||
#define REG_HSMCI_FIFO233 (0x400005A4) /**< (HSMCI) FIFO Memory Aperture0 233 */
|
||||
#define REG_HSMCI_FIFO234 (0x400005A8) /**< (HSMCI) FIFO Memory Aperture0 234 */
|
||||
#define REG_HSMCI_FIFO235 (0x400005AC) /**< (HSMCI) FIFO Memory Aperture0 235 */
|
||||
#define REG_HSMCI_FIFO236 (0x400005B0) /**< (HSMCI) FIFO Memory Aperture0 236 */
|
||||
#define REG_HSMCI_FIFO237 (0x400005B4) /**< (HSMCI) FIFO Memory Aperture0 237 */
|
||||
#define REG_HSMCI_FIFO238 (0x400005B8) /**< (HSMCI) FIFO Memory Aperture0 238 */
|
||||
#define REG_HSMCI_FIFO239 (0x400005BC) /**< (HSMCI) FIFO Memory Aperture0 239 */
|
||||
#define REG_HSMCI_FIFO240 (0x400005C0) /**< (HSMCI) FIFO Memory Aperture0 240 */
|
||||
#define REG_HSMCI_FIFO241 (0x400005C4) /**< (HSMCI) FIFO Memory Aperture0 241 */
|
||||
#define REG_HSMCI_FIFO242 (0x400005C8) /**< (HSMCI) FIFO Memory Aperture0 242 */
|
||||
#define REG_HSMCI_FIFO243 (0x400005CC) /**< (HSMCI) FIFO Memory Aperture0 243 */
|
||||
#define REG_HSMCI_FIFO244 (0x400005D0) /**< (HSMCI) FIFO Memory Aperture0 244 */
|
||||
#define REG_HSMCI_FIFO245 (0x400005D4) /**< (HSMCI) FIFO Memory Aperture0 245 */
|
||||
#define REG_HSMCI_FIFO246 (0x400005D8) /**< (HSMCI) FIFO Memory Aperture0 246 */
|
||||
#define REG_HSMCI_FIFO247 (0x400005DC) /**< (HSMCI) FIFO Memory Aperture0 247 */
|
||||
#define REG_HSMCI_FIFO248 (0x400005E0) /**< (HSMCI) FIFO Memory Aperture0 248 */
|
||||
#define REG_HSMCI_FIFO249 (0x400005E4) /**< (HSMCI) FIFO Memory Aperture0 249 */
|
||||
#define REG_HSMCI_FIFO250 (0x400005E8) /**< (HSMCI) FIFO Memory Aperture0 250 */
|
||||
#define REG_HSMCI_FIFO251 (0x400005EC) /**< (HSMCI) FIFO Memory Aperture0 251 */
|
||||
#define REG_HSMCI_FIFO252 (0x400005F0) /**< (HSMCI) FIFO Memory Aperture0 252 */
|
||||
#define REG_HSMCI_FIFO253 (0x400005F4) /**< (HSMCI) FIFO Memory Aperture0 253 */
|
||||
#define REG_HSMCI_FIFO254 (0x400005F8) /**< (HSMCI) FIFO Memory Aperture0 254 */
|
||||
#define REG_HSMCI_FIFO255 (0x400005FC) /**< (HSMCI) FIFO Memory Aperture0 255 */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_HSMCI_CR (*(__O uint32_t*)0x40000000U) /**< (HSMCI) Control Register */
|
||||
#define REG_HSMCI_MR (*(__IO uint32_t*)0x40000004U) /**< (HSMCI) Mode Register */
|
||||
#define REG_HSMCI_DTOR (*(__IO uint32_t*)0x40000008U) /**< (HSMCI) Data Timeout Register */
|
||||
#define REG_HSMCI_SDCR (*(__IO uint32_t*)0x4000000CU) /**< (HSMCI) SD/SDIO Card Register */
|
||||
#define REG_HSMCI_ARGR (*(__IO uint32_t*)0x40000010U) /**< (HSMCI) Argument Register */
|
||||
#define REG_HSMCI_CMDR (*(__O uint32_t*)0x40000014U) /**< (HSMCI) Command Register */
|
||||
#define REG_HSMCI_BLKR (*(__IO uint32_t*)0x40000018U) /**< (HSMCI) Block Register */
|
||||
#define REG_HSMCI_CSTOR (*(__IO uint32_t*)0x4000001CU) /**< (HSMCI) Completion Signal Timeout Register */
|
||||
#define REG_HSMCI_RSPR (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */
|
||||
#define REG_HSMCI_RSPR0 (*(__I uint32_t*)0x40000020U) /**< (HSMCI) Response Register 0 */
|
||||
#define REG_HSMCI_RSPR1 (*(__I uint32_t*)0x40000024U) /**< (HSMCI) Response Register 1 */
|
||||
#define REG_HSMCI_RSPR2 (*(__I uint32_t*)0x40000028U) /**< (HSMCI) Response Register 2 */
|
||||
#define REG_HSMCI_RSPR3 (*(__I uint32_t*)0x4000002CU) /**< (HSMCI) Response Register 3 */
|
||||
#define REG_HSMCI_RDR (*(__I uint32_t*)0x40000030U) /**< (HSMCI) Receive Data Register */
|
||||
#define REG_HSMCI_TDR (*(__O uint32_t*)0x40000034U) /**< (HSMCI) Transmit Data Register */
|
||||
#define REG_HSMCI_SR (*(__I uint32_t*)0x40000040U) /**< (HSMCI) Status Register */
|
||||
#define REG_HSMCI_IER (*(__O uint32_t*)0x40000044U) /**< (HSMCI) Interrupt Enable Register */
|
||||
#define REG_HSMCI_IDR (*(__O uint32_t*)0x40000048U) /**< (HSMCI) Interrupt Disable Register */
|
||||
#define REG_HSMCI_IMR (*(__I uint32_t*)0x4000004CU) /**< (HSMCI) Interrupt Mask Register */
|
||||
#define REG_HSMCI_DMA (*(__IO uint32_t*)0x40000050U) /**< (HSMCI) DMA Configuration Register */
|
||||
#define REG_HSMCI_CFG (*(__IO uint32_t*)0x40000054U) /**< (HSMCI) Configuration Register */
|
||||
#define REG_HSMCI_WPMR (*(__IO uint32_t*)0x400000E4U) /**< (HSMCI) Write Protection Mode Register */
|
||||
#define REG_HSMCI_WPSR (*(__I uint32_t*)0x400000E8U) /**< (HSMCI) Write Protection Status Register */
|
||||
#define REG_HSMCI_FIFO (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */
|
||||
#define REG_HSMCI_FIFO0 (*(__IO uint32_t*)0x40000200U) /**< (HSMCI) FIFO Memory Aperture0 0 */
|
||||
#define REG_HSMCI_FIFO1 (*(__IO uint32_t*)0x40000204U) /**< (HSMCI) FIFO Memory Aperture0 1 */
|
||||
#define REG_HSMCI_FIFO2 (*(__IO uint32_t*)0x40000208U) /**< (HSMCI) FIFO Memory Aperture0 2 */
|
||||
#define REG_HSMCI_FIFO3 (*(__IO uint32_t*)0x4000020CU) /**< (HSMCI) FIFO Memory Aperture0 3 */
|
||||
#define REG_HSMCI_FIFO4 (*(__IO uint32_t*)0x40000210U) /**< (HSMCI) FIFO Memory Aperture0 4 */
|
||||
#define REG_HSMCI_FIFO5 (*(__IO uint32_t*)0x40000214U) /**< (HSMCI) FIFO Memory Aperture0 5 */
|
||||
#define REG_HSMCI_FIFO6 (*(__IO uint32_t*)0x40000218U) /**< (HSMCI) FIFO Memory Aperture0 6 */
|
||||
#define REG_HSMCI_FIFO7 (*(__IO uint32_t*)0x4000021CU) /**< (HSMCI) FIFO Memory Aperture0 7 */
|
||||
#define REG_HSMCI_FIFO8 (*(__IO uint32_t*)0x40000220U) /**< (HSMCI) FIFO Memory Aperture0 8 */
|
||||
#define REG_HSMCI_FIFO9 (*(__IO uint32_t*)0x40000224U) /**< (HSMCI) FIFO Memory Aperture0 9 */
|
||||
#define REG_HSMCI_FIFO10 (*(__IO uint32_t*)0x40000228U) /**< (HSMCI) FIFO Memory Aperture0 10 */
|
||||
#define REG_HSMCI_FIFO11 (*(__IO uint32_t*)0x4000022CU) /**< (HSMCI) FIFO Memory Aperture0 11 */
|
||||
#define REG_HSMCI_FIFO12 (*(__IO uint32_t*)0x40000230U) /**< (HSMCI) FIFO Memory Aperture0 12 */
|
||||
#define REG_HSMCI_FIFO13 (*(__IO uint32_t*)0x40000234U) /**< (HSMCI) FIFO Memory Aperture0 13 */
|
||||
#define REG_HSMCI_FIFO14 (*(__IO uint32_t*)0x40000238U) /**< (HSMCI) FIFO Memory Aperture0 14 */
|
||||
#define REG_HSMCI_FIFO15 (*(__IO uint32_t*)0x4000023CU) /**< (HSMCI) FIFO Memory Aperture0 15 */
|
||||
#define REG_HSMCI_FIFO16 (*(__IO uint32_t*)0x40000240U) /**< (HSMCI) FIFO Memory Aperture0 16 */
|
||||
#define REG_HSMCI_FIFO17 (*(__IO uint32_t*)0x40000244U) /**< (HSMCI) FIFO Memory Aperture0 17 */
|
||||
#define REG_HSMCI_FIFO18 (*(__IO uint32_t*)0x40000248U) /**< (HSMCI) FIFO Memory Aperture0 18 */
|
||||
#define REG_HSMCI_FIFO19 (*(__IO uint32_t*)0x4000024CU) /**< (HSMCI) FIFO Memory Aperture0 19 */
|
||||
#define REG_HSMCI_FIFO20 (*(__IO uint32_t*)0x40000250U) /**< (HSMCI) FIFO Memory Aperture0 20 */
|
||||
#define REG_HSMCI_FIFO21 (*(__IO uint32_t*)0x40000254U) /**< (HSMCI) FIFO Memory Aperture0 21 */
|
||||
#define REG_HSMCI_FIFO22 (*(__IO uint32_t*)0x40000258U) /**< (HSMCI) FIFO Memory Aperture0 22 */
|
||||
#define REG_HSMCI_FIFO23 (*(__IO uint32_t*)0x4000025CU) /**< (HSMCI) FIFO Memory Aperture0 23 */
|
||||
#define REG_HSMCI_FIFO24 (*(__IO uint32_t*)0x40000260U) /**< (HSMCI) FIFO Memory Aperture0 24 */
|
||||
#define REG_HSMCI_FIFO25 (*(__IO uint32_t*)0x40000264U) /**< (HSMCI) FIFO Memory Aperture0 25 */
|
||||
#define REG_HSMCI_FIFO26 (*(__IO uint32_t*)0x40000268U) /**< (HSMCI) FIFO Memory Aperture0 26 */
|
||||
#define REG_HSMCI_FIFO27 (*(__IO uint32_t*)0x4000026CU) /**< (HSMCI) FIFO Memory Aperture0 27 */
|
||||
#define REG_HSMCI_FIFO28 (*(__IO uint32_t*)0x40000270U) /**< (HSMCI) FIFO Memory Aperture0 28 */
|
||||
#define REG_HSMCI_FIFO29 (*(__IO uint32_t*)0x40000274U) /**< (HSMCI) FIFO Memory Aperture0 29 */
|
||||
#define REG_HSMCI_FIFO30 (*(__IO uint32_t*)0x40000278U) /**< (HSMCI) FIFO Memory Aperture0 30 */
|
||||
#define REG_HSMCI_FIFO31 (*(__IO uint32_t*)0x4000027CU) /**< (HSMCI) FIFO Memory Aperture0 31 */
|
||||
#define REG_HSMCI_FIFO32 (*(__IO uint32_t*)0x40000280U) /**< (HSMCI) FIFO Memory Aperture0 32 */
|
||||
#define REG_HSMCI_FIFO33 (*(__IO uint32_t*)0x40000284U) /**< (HSMCI) FIFO Memory Aperture0 33 */
|
||||
#define REG_HSMCI_FIFO34 (*(__IO uint32_t*)0x40000288U) /**< (HSMCI) FIFO Memory Aperture0 34 */
|
||||
#define REG_HSMCI_FIFO35 (*(__IO uint32_t*)0x4000028CU) /**< (HSMCI) FIFO Memory Aperture0 35 */
|
||||
#define REG_HSMCI_FIFO36 (*(__IO uint32_t*)0x40000290U) /**< (HSMCI) FIFO Memory Aperture0 36 */
|
||||
#define REG_HSMCI_FIFO37 (*(__IO uint32_t*)0x40000294U) /**< (HSMCI) FIFO Memory Aperture0 37 */
|
||||
#define REG_HSMCI_FIFO38 (*(__IO uint32_t*)0x40000298U) /**< (HSMCI) FIFO Memory Aperture0 38 */
|
||||
#define REG_HSMCI_FIFO39 (*(__IO uint32_t*)0x4000029CU) /**< (HSMCI) FIFO Memory Aperture0 39 */
|
||||
#define REG_HSMCI_FIFO40 (*(__IO uint32_t*)0x400002A0U) /**< (HSMCI) FIFO Memory Aperture0 40 */
|
||||
#define REG_HSMCI_FIFO41 (*(__IO uint32_t*)0x400002A4U) /**< (HSMCI) FIFO Memory Aperture0 41 */
|
||||
#define REG_HSMCI_FIFO42 (*(__IO uint32_t*)0x400002A8U) /**< (HSMCI) FIFO Memory Aperture0 42 */
|
||||
#define REG_HSMCI_FIFO43 (*(__IO uint32_t*)0x400002ACU) /**< (HSMCI) FIFO Memory Aperture0 43 */
|
||||
#define REG_HSMCI_FIFO44 (*(__IO uint32_t*)0x400002B0U) /**< (HSMCI) FIFO Memory Aperture0 44 */
|
||||
#define REG_HSMCI_FIFO45 (*(__IO uint32_t*)0x400002B4U) /**< (HSMCI) FIFO Memory Aperture0 45 */
|
||||
#define REG_HSMCI_FIFO46 (*(__IO uint32_t*)0x400002B8U) /**< (HSMCI) FIFO Memory Aperture0 46 */
|
||||
#define REG_HSMCI_FIFO47 (*(__IO uint32_t*)0x400002BCU) /**< (HSMCI) FIFO Memory Aperture0 47 */
|
||||
#define REG_HSMCI_FIFO48 (*(__IO uint32_t*)0x400002C0U) /**< (HSMCI) FIFO Memory Aperture0 48 */
|
||||
#define REG_HSMCI_FIFO49 (*(__IO uint32_t*)0x400002C4U) /**< (HSMCI) FIFO Memory Aperture0 49 */
|
||||
#define REG_HSMCI_FIFO50 (*(__IO uint32_t*)0x400002C8U) /**< (HSMCI) FIFO Memory Aperture0 50 */
|
||||
#define REG_HSMCI_FIFO51 (*(__IO uint32_t*)0x400002CCU) /**< (HSMCI) FIFO Memory Aperture0 51 */
|
||||
#define REG_HSMCI_FIFO52 (*(__IO uint32_t*)0x400002D0U) /**< (HSMCI) FIFO Memory Aperture0 52 */
|
||||
#define REG_HSMCI_FIFO53 (*(__IO uint32_t*)0x400002D4U) /**< (HSMCI) FIFO Memory Aperture0 53 */
|
||||
#define REG_HSMCI_FIFO54 (*(__IO uint32_t*)0x400002D8U) /**< (HSMCI) FIFO Memory Aperture0 54 */
|
||||
#define REG_HSMCI_FIFO55 (*(__IO uint32_t*)0x400002DCU) /**< (HSMCI) FIFO Memory Aperture0 55 */
|
||||
#define REG_HSMCI_FIFO56 (*(__IO uint32_t*)0x400002E0U) /**< (HSMCI) FIFO Memory Aperture0 56 */
|
||||
#define REG_HSMCI_FIFO57 (*(__IO uint32_t*)0x400002E4U) /**< (HSMCI) FIFO Memory Aperture0 57 */
|
||||
#define REG_HSMCI_FIFO58 (*(__IO uint32_t*)0x400002E8U) /**< (HSMCI) FIFO Memory Aperture0 58 */
|
||||
#define REG_HSMCI_FIFO59 (*(__IO uint32_t*)0x400002ECU) /**< (HSMCI) FIFO Memory Aperture0 59 */
|
||||
#define REG_HSMCI_FIFO60 (*(__IO uint32_t*)0x400002F0U) /**< (HSMCI) FIFO Memory Aperture0 60 */
|
||||
#define REG_HSMCI_FIFO61 (*(__IO uint32_t*)0x400002F4U) /**< (HSMCI) FIFO Memory Aperture0 61 */
|
||||
#define REG_HSMCI_FIFO62 (*(__IO uint32_t*)0x400002F8U) /**< (HSMCI) FIFO Memory Aperture0 62 */
|
||||
#define REG_HSMCI_FIFO63 (*(__IO uint32_t*)0x400002FCU) /**< (HSMCI) FIFO Memory Aperture0 63 */
|
||||
#define REG_HSMCI_FIFO64 (*(__IO uint32_t*)0x40000300U) /**< (HSMCI) FIFO Memory Aperture0 64 */
|
||||
#define REG_HSMCI_FIFO65 (*(__IO uint32_t*)0x40000304U) /**< (HSMCI) FIFO Memory Aperture0 65 */
|
||||
#define REG_HSMCI_FIFO66 (*(__IO uint32_t*)0x40000308U) /**< (HSMCI) FIFO Memory Aperture0 66 */
|
||||
#define REG_HSMCI_FIFO67 (*(__IO uint32_t*)0x4000030CU) /**< (HSMCI) FIFO Memory Aperture0 67 */
|
||||
#define REG_HSMCI_FIFO68 (*(__IO uint32_t*)0x40000310U) /**< (HSMCI) FIFO Memory Aperture0 68 */
|
||||
#define REG_HSMCI_FIFO69 (*(__IO uint32_t*)0x40000314U) /**< (HSMCI) FIFO Memory Aperture0 69 */
|
||||
#define REG_HSMCI_FIFO70 (*(__IO uint32_t*)0x40000318U) /**< (HSMCI) FIFO Memory Aperture0 70 */
|
||||
#define REG_HSMCI_FIFO71 (*(__IO uint32_t*)0x4000031CU) /**< (HSMCI) FIFO Memory Aperture0 71 */
|
||||
#define REG_HSMCI_FIFO72 (*(__IO uint32_t*)0x40000320U) /**< (HSMCI) FIFO Memory Aperture0 72 */
|
||||
#define REG_HSMCI_FIFO73 (*(__IO uint32_t*)0x40000324U) /**< (HSMCI) FIFO Memory Aperture0 73 */
|
||||
#define REG_HSMCI_FIFO74 (*(__IO uint32_t*)0x40000328U) /**< (HSMCI) FIFO Memory Aperture0 74 */
|
||||
#define REG_HSMCI_FIFO75 (*(__IO uint32_t*)0x4000032CU) /**< (HSMCI) FIFO Memory Aperture0 75 */
|
||||
#define REG_HSMCI_FIFO76 (*(__IO uint32_t*)0x40000330U) /**< (HSMCI) FIFO Memory Aperture0 76 */
|
||||
#define REG_HSMCI_FIFO77 (*(__IO uint32_t*)0x40000334U) /**< (HSMCI) FIFO Memory Aperture0 77 */
|
||||
#define REG_HSMCI_FIFO78 (*(__IO uint32_t*)0x40000338U) /**< (HSMCI) FIFO Memory Aperture0 78 */
|
||||
#define REG_HSMCI_FIFO79 (*(__IO uint32_t*)0x4000033CU) /**< (HSMCI) FIFO Memory Aperture0 79 */
|
||||
#define REG_HSMCI_FIFO80 (*(__IO uint32_t*)0x40000340U) /**< (HSMCI) FIFO Memory Aperture0 80 */
|
||||
#define REG_HSMCI_FIFO81 (*(__IO uint32_t*)0x40000344U) /**< (HSMCI) FIFO Memory Aperture0 81 */
|
||||
#define REG_HSMCI_FIFO82 (*(__IO uint32_t*)0x40000348U) /**< (HSMCI) FIFO Memory Aperture0 82 */
|
||||
#define REG_HSMCI_FIFO83 (*(__IO uint32_t*)0x4000034CU) /**< (HSMCI) FIFO Memory Aperture0 83 */
|
||||
#define REG_HSMCI_FIFO84 (*(__IO uint32_t*)0x40000350U) /**< (HSMCI) FIFO Memory Aperture0 84 */
|
||||
#define REG_HSMCI_FIFO85 (*(__IO uint32_t*)0x40000354U) /**< (HSMCI) FIFO Memory Aperture0 85 */
|
||||
#define REG_HSMCI_FIFO86 (*(__IO uint32_t*)0x40000358U) /**< (HSMCI) FIFO Memory Aperture0 86 */
|
||||
#define REG_HSMCI_FIFO87 (*(__IO uint32_t*)0x4000035CU) /**< (HSMCI) FIFO Memory Aperture0 87 */
|
||||
#define REG_HSMCI_FIFO88 (*(__IO uint32_t*)0x40000360U) /**< (HSMCI) FIFO Memory Aperture0 88 */
|
||||
#define REG_HSMCI_FIFO89 (*(__IO uint32_t*)0x40000364U) /**< (HSMCI) FIFO Memory Aperture0 89 */
|
||||
#define REG_HSMCI_FIFO90 (*(__IO uint32_t*)0x40000368U) /**< (HSMCI) FIFO Memory Aperture0 90 */
|
||||
#define REG_HSMCI_FIFO91 (*(__IO uint32_t*)0x4000036CU) /**< (HSMCI) FIFO Memory Aperture0 91 */
|
||||
#define REG_HSMCI_FIFO92 (*(__IO uint32_t*)0x40000370U) /**< (HSMCI) FIFO Memory Aperture0 92 */
|
||||
#define REG_HSMCI_FIFO93 (*(__IO uint32_t*)0x40000374U) /**< (HSMCI) FIFO Memory Aperture0 93 */
|
||||
#define REG_HSMCI_FIFO94 (*(__IO uint32_t*)0x40000378U) /**< (HSMCI) FIFO Memory Aperture0 94 */
|
||||
#define REG_HSMCI_FIFO95 (*(__IO uint32_t*)0x4000037CU) /**< (HSMCI) FIFO Memory Aperture0 95 */
|
||||
#define REG_HSMCI_FIFO96 (*(__IO uint32_t*)0x40000380U) /**< (HSMCI) FIFO Memory Aperture0 96 */
|
||||
#define REG_HSMCI_FIFO97 (*(__IO uint32_t*)0x40000384U) /**< (HSMCI) FIFO Memory Aperture0 97 */
|
||||
#define REG_HSMCI_FIFO98 (*(__IO uint32_t*)0x40000388U) /**< (HSMCI) FIFO Memory Aperture0 98 */
|
||||
#define REG_HSMCI_FIFO99 (*(__IO uint32_t*)0x4000038CU) /**< (HSMCI) FIFO Memory Aperture0 99 */
|
||||
#define REG_HSMCI_FIFO100 (*(__IO uint32_t*)0x40000390U) /**< (HSMCI) FIFO Memory Aperture0 100 */
|
||||
#define REG_HSMCI_FIFO101 (*(__IO uint32_t*)0x40000394U) /**< (HSMCI) FIFO Memory Aperture0 101 */
|
||||
#define REG_HSMCI_FIFO102 (*(__IO uint32_t*)0x40000398U) /**< (HSMCI) FIFO Memory Aperture0 102 */
|
||||
#define REG_HSMCI_FIFO103 (*(__IO uint32_t*)0x4000039CU) /**< (HSMCI) FIFO Memory Aperture0 103 */
|
||||
#define REG_HSMCI_FIFO104 (*(__IO uint32_t*)0x400003A0U) /**< (HSMCI) FIFO Memory Aperture0 104 */
|
||||
#define REG_HSMCI_FIFO105 (*(__IO uint32_t*)0x400003A4U) /**< (HSMCI) FIFO Memory Aperture0 105 */
|
||||
#define REG_HSMCI_FIFO106 (*(__IO uint32_t*)0x400003A8U) /**< (HSMCI) FIFO Memory Aperture0 106 */
|
||||
#define REG_HSMCI_FIFO107 (*(__IO uint32_t*)0x400003ACU) /**< (HSMCI) FIFO Memory Aperture0 107 */
|
||||
#define REG_HSMCI_FIFO108 (*(__IO uint32_t*)0x400003B0U) /**< (HSMCI) FIFO Memory Aperture0 108 */
|
||||
#define REG_HSMCI_FIFO109 (*(__IO uint32_t*)0x400003B4U) /**< (HSMCI) FIFO Memory Aperture0 109 */
|
||||
#define REG_HSMCI_FIFO110 (*(__IO uint32_t*)0x400003B8U) /**< (HSMCI) FIFO Memory Aperture0 110 */
|
||||
#define REG_HSMCI_FIFO111 (*(__IO uint32_t*)0x400003BCU) /**< (HSMCI) FIFO Memory Aperture0 111 */
|
||||
#define REG_HSMCI_FIFO112 (*(__IO uint32_t*)0x400003C0U) /**< (HSMCI) FIFO Memory Aperture0 112 */
|
||||
#define REG_HSMCI_FIFO113 (*(__IO uint32_t*)0x400003C4U) /**< (HSMCI) FIFO Memory Aperture0 113 */
|
||||
#define REG_HSMCI_FIFO114 (*(__IO uint32_t*)0x400003C8U) /**< (HSMCI) FIFO Memory Aperture0 114 */
|
||||
#define REG_HSMCI_FIFO115 (*(__IO uint32_t*)0x400003CCU) /**< (HSMCI) FIFO Memory Aperture0 115 */
|
||||
#define REG_HSMCI_FIFO116 (*(__IO uint32_t*)0x400003D0U) /**< (HSMCI) FIFO Memory Aperture0 116 */
|
||||
#define REG_HSMCI_FIFO117 (*(__IO uint32_t*)0x400003D4U) /**< (HSMCI) FIFO Memory Aperture0 117 */
|
||||
#define REG_HSMCI_FIFO118 (*(__IO uint32_t*)0x400003D8U) /**< (HSMCI) FIFO Memory Aperture0 118 */
|
||||
#define REG_HSMCI_FIFO119 (*(__IO uint32_t*)0x400003DCU) /**< (HSMCI) FIFO Memory Aperture0 119 */
|
||||
#define REG_HSMCI_FIFO120 (*(__IO uint32_t*)0x400003E0U) /**< (HSMCI) FIFO Memory Aperture0 120 */
|
||||
#define REG_HSMCI_FIFO121 (*(__IO uint32_t*)0x400003E4U) /**< (HSMCI) FIFO Memory Aperture0 121 */
|
||||
#define REG_HSMCI_FIFO122 (*(__IO uint32_t*)0x400003E8U) /**< (HSMCI) FIFO Memory Aperture0 122 */
|
||||
#define REG_HSMCI_FIFO123 (*(__IO uint32_t*)0x400003ECU) /**< (HSMCI) FIFO Memory Aperture0 123 */
|
||||
#define REG_HSMCI_FIFO124 (*(__IO uint32_t*)0x400003F0U) /**< (HSMCI) FIFO Memory Aperture0 124 */
|
||||
#define REG_HSMCI_FIFO125 (*(__IO uint32_t*)0x400003F4U) /**< (HSMCI) FIFO Memory Aperture0 125 */
|
||||
#define REG_HSMCI_FIFO126 (*(__IO uint32_t*)0x400003F8U) /**< (HSMCI) FIFO Memory Aperture0 126 */
|
||||
#define REG_HSMCI_FIFO127 (*(__IO uint32_t*)0x400003FCU) /**< (HSMCI) FIFO Memory Aperture0 127 */
|
||||
#define REG_HSMCI_FIFO128 (*(__IO uint32_t*)0x40000400U) /**< (HSMCI) FIFO Memory Aperture0 128 */
|
||||
#define REG_HSMCI_FIFO129 (*(__IO uint32_t*)0x40000404U) /**< (HSMCI) FIFO Memory Aperture0 129 */
|
||||
#define REG_HSMCI_FIFO130 (*(__IO uint32_t*)0x40000408U) /**< (HSMCI) FIFO Memory Aperture0 130 */
|
||||
#define REG_HSMCI_FIFO131 (*(__IO uint32_t*)0x4000040CU) /**< (HSMCI) FIFO Memory Aperture0 131 */
|
||||
#define REG_HSMCI_FIFO132 (*(__IO uint32_t*)0x40000410U) /**< (HSMCI) FIFO Memory Aperture0 132 */
|
||||
#define REG_HSMCI_FIFO133 (*(__IO uint32_t*)0x40000414U) /**< (HSMCI) FIFO Memory Aperture0 133 */
|
||||
#define REG_HSMCI_FIFO134 (*(__IO uint32_t*)0x40000418U) /**< (HSMCI) FIFO Memory Aperture0 134 */
|
||||
#define REG_HSMCI_FIFO135 (*(__IO uint32_t*)0x4000041CU) /**< (HSMCI) FIFO Memory Aperture0 135 */
|
||||
#define REG_HSMCI_FIFO136 (*(__IO uint32_t*)0x40000420U) /**< (HSMCI) FIFO Memory Aperture0 136 */
|
||||
#define REG_HSMCI_FIFO137 (*(__IO uint32_t*)0x40000424U) /**< (HSMCI) FIFO Memory Aperture0 137 */
|
||||
#define REG_HSMCI_FIFO138 (*(__IO uint32_t*)0x40000428U) /**< (HSMCI) FIFO Memory Aperture0 138 */
|
||||
#define REG_HSMCI_FIFO139 (*(__IO uint32_t*)0x4000042CU) /**< (HSMCI) FIFO Memory Aperture0 139 */
|
||||
#define REG_HSMCI_FIFO140 (*(__IO uint32_t*)0x40000430U) /**< (HSMCI) FIFO Memory Aperture0 140 */
|
||||
#define REG_HSMCI_FIFO141 (*(__IO uint32_t*)0x40000434U) /**< (HSMCI) FIFO Memory Aperture0 141 */
|
||||
#define REG_HSMCI_FIFO142 (*(__IO uint32_t*)0x40000438U) /**< (HSMCI) FIFO Memory Aperture0 142 */
|
||||
#define REG_HSMCI_FIFO143 (*(__IO uint32_t*)0x4000043CU) /**< (HSMCI) FIFO Memory Aperture0 143 */
|
||||
#define REG_HSMCI_FIFO144 (*(__IO uint32_t*)0x40000440U) /**< (HSMCI) FIFO Memory Aperture0 144 */
|
||||
#define REG_HSMCI_FIFO145 (*(__IO uint32_t*)0x40000444U) /**< (HSMCI) FIFO Memory Aperture0 145 */
|
||||
#define REG_HSMCI_FIFO146 (*(__IO uint32_t*)0x40000448U) /**< (HSMCI) FIFO Memory Aperture0 146 */
|
||||
#define REG_HSMCI_FIFO147 (*(__IO uint32_t*)0x4000044CU) /**< (HSMCI) FIFO Memory Aperture0 147 */
|
||||
#define REG_HSMCI_FIFO148 (*(__IO uint32_t*)0x40000450U) /**< (HSMCI) FIFO Memory Aperture0 148 */
|
||||
#define REG_HSMCI_FIFO149 (*(__IO uint32_t*)0x40000454U) /**< (HSMCI) FIFO Memory Aperture0 149 */
|
||||
#define REG_HSMCI_FIFO150 (*(__IO uint32_t*)0x40000458U) /**< (HSMCI) FIFO Memory Aperture0 150 */
|
||||
#define REG_HSMCI_FIFO151 (*(__IO uint32_t*)0x4000045CU) /**< (HSMCI) FIFO Memory Aperture0 151 */
|
||||
#define REG_HSMCI_FIFO152 (*(__IO uint32_t*)0x40000460U) /**< (HSMCI) FIFO Memory Aperture0 152 */
|
||||
#define REG_HSMCI_FIFO153 (*(__IO uint32_t*)0x40000464U) /**< (HSMCI) FIFO Memory Aperture0 153 */
|
||||
#define REG_HSMCI_FIFO154 (*(__IO uint32_t*)0x40000468U) /**< (HSMCI) FIFO Memory Aperture0 154 */
|
||||
#define REG_HSMCI_FIFO155 (*(__IO uint32_t*)0x4000046CU) /**< (HSMCI) FIFO Memory Aperture0 155 */
|
||||
#define REG_HSMCI_FIFO156 (*(__IO uint32_t*)0x40000470U) /**< (HSMCI) FIFO Memory Aperture0 156 */
|
||||
#define REG_HSMCI_FIFO157 (*(__IO uint32_t*)0x40000474U) /**< (HSMCI) FIFO Memory Aperture0 157 */
|
||||
#define REG_HSMCI_FIFO158 (*(__IO uint32_t*)0x40000478U) /**< (HSMCI) FIFO Memory Aperture0 158 */
|
||||
#define REG_HSMCI_FIFO159 (*(__IO uint32_t*)0x4000047CU) /**< (HSMCI) FIFO Memory Aperture0 159 */
|
||||
#define REG_HSMCI_FIFO160 (*(__IO uint32_t*)0x40000480U) /**< (HSMCI) FIFO Memory Aperture0 160 */
|
||||
#define REG_HSMCI_FIFO161 (*(__IO uint32_t*)0x40000484U) /**< (HSMCI) FIFO Memory Aperture0 161 */
|
||||
#define REG_HSMCI_FIFO162 (*(__IO uint32_t*)0x40000488U) /**< (HSMCI) FIFO Memory Aperture0 162 */
|
||||
#define REG_HSMCI_FIFO163 (*(__IO uint32_t*)0x4000048CU) /**< (HSMCI) FIFO Memory Aperture0 163 */
|
||||
#define REG_HSMCI_FIFO164 (*(__IO uint32_t*)0x40000490U) /**< (HSMCI) FIFO Memory Aperture0 164 */
|
||||
#define REG_HSMCI_FIFO165 (*(__IO uint32_t*)0x40000494U) /**< (HSMCI) FIFO Memory Aperture0 165 */
|
||||
#define REG_HSMCI_FIFO166 (*(__IO uint32_t*)0x40000498U) /**< (HSMCI) FIFO Memory Aperture0 166 */
|
||||
#define REG_HSMCI_FIFO167 (*(__IO uint32_t*)0x4000049CU) /**< (HSMCI) FIFO Memory Aperture0 167 */
|
||||
#define REG_HSMCI_FIFO168 (*(__IO uint32_t*)0x400004A0U) /**< (HSMCI) FIFO Memory Aperture0 168 */
|
||||
#define REG_HSMCI_FIFO169 (*(__IO uint32_t*)0x400004A4U) /**< (HSMCI) FIFO Memory Aperture0 169 */
|
||||
#define REG_HSMCI_FIFO170 (*(__IO uint32_t*)0x400004A8U) /**< (HSMCI) FIFO Memory Aperture0 170 */
|
||||
#define REG_HSMCI_FIFO171 (*(__IO uint32_t*)0x400004ACU) /**< (HSMCI) FIFO Memory Aperture0 171 */
|
||||
#define REG_HSMCI_FIFO172 (*(__IO uint32_t*)0x400004B0U) /**< (HSMCI) FIFO Memory Aperture0 172 */
|
||||
#define REG_HSMCI_FIFO173 (*(__IO uint32_t*)0x400004B4U) /**< (HSMCI) FIFO Memory Aperture0 173 */
|
||||
#define REG_HSMCI_FIFO174 (*(__IO uint32_t*)0x400004B8U) /**< (HSMCI) FIFO Memory Aperture0 174 */
|
||||
#define REG_HSMCI_FIFO175 (*(__IO uint32_t*)0x400004BCU) /**< (HSMCI) FIFO Memory Aperture0 175 */
|
||||
#define REG_HSMCI_FIFO176 (*(__IO uint32_t*)0x400004C0U) /**< (HSMCI) FIFO Memory Aperture0 176 */
|
||||
#define REG_HSMCI_FIFO177 (*(__IO uint32_t*)0x400004C4U) /**< (HSMCI) FIFO Memory Aperture0 177 */
|
||||
#define REG_HSMCI_FIFO178 (*(__IO uint32_t*)0x400004C8U) /**< (HSMCI) FIFO Memory Aperture0 178 */
|
||||
#define REG_HSMCI_FIFO179 (*(__IO uint32_t*)0x400004CCU) /**< (HSMCI) FIFO Memory Aperture0 179 */
|
||||
#define REG_HSMCI_FIFO180 (*(__IO uint32_t*)0x400004D0U) /**< (HSMCI) FIFO Memory Aperture0 180 */
|
||||
#define REG_HSMCI_FIFO181 (*(__IO uint32_t*)0x400004D4U) /**< (HSMCI) FIFO Memory Aperture0 181 */
|
||||
#define REG_HSMCI_FIFO182 (*(__IO uint32_t*)0x400004D8U) /**< (HSMCI) FIFO Memory Aperture0 182 */
|
||||
#define REG_HSMCI_FIFO183 (*(__IO uint32_t*)0x400004DCU) /**< (HSMCI) FIFO Memory Aperture0 183 */
|
||||
#define REG_HSMCI_FIFO184 (*(__IO uint32_t*)0x400004E0U) /**< (HSMCI) FIFO Memory Aperture0 184 */
|
||||
#define REG_HSMCI_FIFO185 (*(__IO uint32_t*)0x400004E4U) /**< (HSMCI) FIFO Memory Aperture0 185 */
|
||||
#define REG_HSMCI_FIFO186 (*(__IO uint32_t*)0x400004E8U) /**< (HSMCI) FIFO Memory Aperture0 186 */
|
||||
#define REG_HSMCI_FIFO187 (*(__IO uint32_t*)0x400004ECU) /**< (HSMCI) FIFO Memory Aperture0 187 */
|
||||
#define REG_HSMCI_FIFO188 (*(__IO uint32_t*)0x400004F0U) /**< (HSMCI) FIFO Memory Aperture0 188 */
|
||||
#define REG_HSMCI_FIFO189 (*(__IO uint32_t*)0x400004F4U) /**< (HSMCI) FIFO Memory Aperture0 189 */
|
||||
#define REG_HSMCI_FIFO190 (*(__IO uint32_t*)0x400004F8U) /**< (HSMCI) FIFO Memory Aperture0 190 */
|
||||
#define REG_HSMCI_FIFO191 (*(__IO uint32_t*)0x400004FCU) /**< (HSMCI) FIFO Memory Aperture0 191 */
|
||||
#define REG_HSMCI_FIFO192 (*(__IO uint32_t*)0x40000500U) /**< (HSMCI) FIFO Memory Aperture0 192 */
|
||||
#define REG_HSMCI_FIFO193 (*(__IO uint32_t*)0x40000504U) /**< (HSMCI) FIFO Memory Aperture0 193 */
|
||||
#define REG_HSMCI_FIFO194 (*(__IO uint32_t*)0x40000508U) /**< (HSMCI) FIFO Memory Aperture0 194 */
|
||||
#define REG_HSMCI_FIFO195 (*(__IO uint32_t*)0x4000050CU) /**< (HSMCI) FIFO Memory Aperture0 195 */
|
||||
#define REG_HSMCI_FIFO196 (*(__IO uint32_t*)0x40000510U) /**< (HSMCI) FIFO Memory Aperture0 196 */
|
||||
#define REG_HSMCI_FIFO197 (*(__IO uint32_t*)0x40000514U) /**< (HSMCI) FIFO Memory Aperture0 197 */
|
||||
#define REG_HSMCI_FIFO198 (*(__IO uint32_t*)0x40000518U) /**< (HSMCI) FIFO Memory Aperture0 198 */
|
||||
#define REG_HSMCI_FIFO199 (*(__IO uint32_t*)0x4000051CU) /**< (HSMCI) FIFO Memory Aperture0 199 */
|
||||
#define REG_HSMCI_FIFO200 (*(__IO uint32_t*)0x40000520U) /**< (HSMCI) FIFO Memory Aperture0 200 */
|
||||
#define REG_HSMCI_FIFO201 (*(__IO uint32_t*)0x40000524U) /**< (HSMCI) FIFO Memory Aperture0 201 */
|
||||
#define REG_HSMCI_FIFO202 (*(__IO uint32_t*)0x40000528U) /**< (HSMCI) FIFO Memory Aperture0 202 */
|
||||
#define REG_HSMCI_FIFO203 (*(__IO uint32_t*)0x4000052CU) /**< (HSMCI) FIFO Memory Aperture0 203 */
|
||||
#define REG_HSMCI_FIFO204 (*(__IO uint32_t*)0x40000530U) /**< (HSMCI) FIFO Memory Aperture0 204 */
|
||||
#define REG_HSMCI_FIFO205 (*(__IO uint32_t*)0x40000534U) /**< (HSMCI) FIFO Memory Aperture0 205 */
|
||||
#define REG_HSMCI_FIFO206 (*(__IO uint32_t*)0x40000538U) /**< (HSMCI) FIFO Memory Aperture0 206 */
|
||||
#define REG_HSMCI_FIFO207 (*(__IO uint32_t*)0x4000053CU) /**< (HSMCI) FIFO Memory Aperture0 207 */
|
||||
#define REG_HSMCI_FIFO208 (*(__IO uint32_t*)0x40000540U) /**< (HSMCI) FIFO Memory Aperture0 208 */
|
||||
#define REG_HSMCI_FIFO209 (*(__IO uint32_t*)0x40000544U) /**< (HSMCI) FIFO Memory Aperture0 209 */
|
||||
#define REG_HSMCI_FIFO210 (*(__IO uint32_t*)0x40000548U) /**< (HSMCI) FIFO Memory Aperture0 210 */
|
||||
#define REG_HSMCI_FIFO211 (*(__IO uint32_t*)0x4000054CU) /**< (HSMCI) FIFO Memory Aperture0 211 */
|
||||
#define REG_HSMCI_FIFO212 (*(__IO uint32_t*)0x40000550U) /**< (HSMCI) FIFO Memory Aperture0 212 */
|
||||
#define REG_HSMCI_FIFO213 (*(__IO uint32_t*)0x40000554U) /**< (HSMCI) FIFO Memory Aperture0 213 */
|
||||
#define REG_HSMCI_FIFO214 (*(__IO uint32_t*)0x40000558U) /**< (HSMCI) FIFO Memory Aperture0 214 */
|
||||
#define REG_HSMCI_FIFO215 (*(__IO uint32_t*)0x4000055CU) /**< (HSMCI) FIFO Memory Aperture0 215 */
|
||||
#define REG_HSMCI_FIFO216 (*(__IO uint32_t*)0x40000560U) /**< (HSMCI) FIFO Memory Aperture0 216 */
|
||||
#define REG_HSMCI_FIFO217 (*(__IO uint32_t*)0x40000564U) /**< (HSMCI) FIFO Memory Aperture0 217 */
|
||||
#define REG_HSMCI_FIFO218 (*(__IO uint32_t*)0x40000568U) /**< (HSMCI) FIFO Memory Aperture0 218 */
|
||||
#define REG_HSMCI_FIFO219 (*(__IO uint32_t*)0x4000056CU) /**< (HSMCI) FIFO Memory Aperture0 219 */
|
||||
#define REG_HSMCI_FIFO220 (*(__IO uint32_t*)0x40000570U) /**< (HSMCI) FIFO Memory Aperture0 220 */
|
||||
#define REG_HSMCI_FIFO221 (*(__IO uint32_t*)0x40000574U) /**< (HSMCI) FIFO Memory Aperture0 221 */
|
||||
#define REG_HSMCI_FIFO222 (*(__IO uint32_t*)0x40000578U) /**< (HSMCI) FIFO Memory Aperture0 222 */
|
||||
#define REG_HSMCI_FIFO223 (*(__IO uint32_t*)0x4000057CU) /**< (HSMCI) FIFO Memory Aperture0 223 */
|
||||
#define REG_HSMCI_FIFO224 (*(__IO uint32_t*)0x40000580U) /**< (HSMCI) FIFO Memory Aperture0 224 */
|
||||
#define REG_HSMCI_FIFO225 (*(__IO uint32_t*)0x40000584U) /**< (HSMCI) FIFO Memory Aperture0 225 */
|
||||
#define REG_HSMCI_FIFO226 (*(__IO uint32_t*)0x40000588U) /**< (HSMCI) FIFO Memory Aperture0 226 */
|
||||
#define REG_HSMCI_FIFO227 (*(__IO uint32_t*)0x4000058CU) /**< (HSMCI) FIFO Memory Aperture0 227 */
|
||||
#define REG_HSMCI_FIFO228 (*(__IO uint32_t*)0x40000590U) /**< (HSMCI) FIFO Memory Aperture0 228 */
|
||||
#define REG_HSMCI_FIFO229 (*(__IO uint32_t*)0x40000594U) /**< (HSMCI) FIFO Memory Aperture0 229 */
|
||||
#define REG_HSMCI_FIFO230 (*(__IO uint32_t*)0x40000598U) /**< (HSMCI) FIFO Memory Aperture0 230 */
|
||||
#define REG_HSMCI_FIFO231 (*(__IO uint32_t*)0x4000059CU) /**< (HSMCI) FIFO Memory Aperture0 231 */
|
||||
#define REG_HSMCI_FIFO232 (*(__IO uint32_t*)0x400005A0U) /**< (HSMCI) FIFO Memory Aperture0 232 */
|
||||
#define REG_HSMCI_FIFO233 (*(__IO uint32_t*)0x400005A4U) /**< (HSMCI) FIFO Memory Aperture0 233 */
|
||||
#define REG_HSMCI_FIFO234 (*(__IO uint32_t*)0x400005A8U) /**< (HSMCI) FIFO Memory Aperture0 234 */
|
||||
#define REG_HSMCI_FIFO235 (*(__IO uint32_t*)0x400005ACU) /**< (HSMCI) FIFO Memory Aperture0 235 */
|
||||
#define REG_HSMCI_FIFO236 (*(__IO uint32_t*)0x400005B0U) /**< (HSMCI) FIFO Memory Aperture0 236 */
|
||||
#define REG_HSMCI_FIFO237 (*(__IO uint32_t*)0x400005B4U) /**< (HSMCI) FIFO Memory Aperture0 237 */
|
||||
#define REG_HSMCI_FIFO238 (*(__IO uint32_t*)0x400005B8U) /**< (HSMCI) FIFO Memory Aperture0 238 */
|
||||
#define REG_HSMCI_FIFO239 (*(__IO uint32_t*)0x400005BCU) /**< (HSMCI) FIFO Memory Aperture0 239 */
|
||||
#define REG_HSMCI_FIFO240 (*(__IO uint32_t*)0x400005C0U) /**< (HSMCI) FIFO Memory Aperture0 240 */
|
||||
#define REG_HSMCI_FIFO241 (*(__IO uint32_t*)0x400005C4U) /**< (HSMCI) FIFO Memory Aperture0 241 */
|
||||
#define REG_HSMCI_FIFO242 (*(__IO uint32_t*)0x400005C8U) /**< (HSMCI) FIFO Memory Aperture0 242 */
|
||||
#define REG_HSMCI_FIFO243 (*(__IO uint32_t*)0x400005CCU) /**< (HSMCI) FIFO Memory Aperture0 243 */
|
||||
#define REG_HSMCI_FIFO244 (*(__IO uint32_t*)0x400005D0U) /**< (HSMCI) FIFO Memory Aperture0 244 */
|
||||
#define REG_HSMCI_FIFO245 (*(__IO uint32_t*)0x400005D4U) /**< (HSMCI) FIFO Memory Aperture0 245 */
|
||||
#define REG_HSMCI_FIFO246 (*(__IO uint32_t*)0x400005D8U) /**< (HSMCI) FIFO Memory Aperture0 246 */
|
||||
#define REG_HSMCI_FIFO247 (*(__IO uint32_t*)0x400005DCU) /**< (HSMCI) FIFO Memory Aperture0 247 */
|
||||
#define REG_HSMCI_FIFO248 (*(__IO uint32_t*)0x400005E0U) /**< (HSMCI) FIFO Memory Aperture0 248 */
|
||||
#define REG_HSMCI_FIFO249 (*(__IO uint32_t*)0x400005E4U) /**< (HSMCI) FIFO Memory Aperture0 249 */
|
||||
#define REG_HSMCI_FIFO250 (*(__IO uint32_t*)0x400005E8U) /**< (HSMCI) FIFO Memory Aperture0 250 */
|
||||
#define REG_HSMCI_FIFO251 (*(__IO uint32_t*)0x400005ECU) /**< (HSMCI) FIFO Memory Aperture0 251 */
|
||||
#define REG_HSMCI_FIFO252 (*(__IO uint32_t*)0x400005F0U) /**< (HSMCI) FIFO Memory Aperture0 252 */
|
||||
#define REG_HSMCI_FIFO253 (*(__IO uint32_t*)0x400005F4U) /**< (HSMCI) FIFO Memory Aperture0 253 */
|
||||
#define REG_HSMCI_FIFO254 (*(__IO uint32_t*)0x400005F8U) /**< (HSMCI) FIFO Memory Aperture0 254 */
|
||||
#define REG_HSMCI_FIFO255 (*(__IO uint32_t*)0x400005FCU) /**< (HSMCI) FIFO Memory Aperture0 255 */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for HSMCI peripheral ========== */
|
||||
#define HSMCI_DMAC_ID_RX 0
|
||||
#define HSMCI_DMAC_ID_TX 0
|
||||
#define HSMCI_INSTANCE_ID 18
|
||||
#define HSMCI_CLOCK_ID 18
|
||||
|
||||
#endif /* _SAME70_HSMCI_INSTANCE_ */
|
||||
71
lib/same70b/include/instance/i2sc0.h
Normal file
71
lib/same70b/include/instance/i2sc0.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for I2SC0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_I2SC0_INSTANCE_H_
|
||||
#define _SAME70_I2SC0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for I2SC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_I2SC0_CR (0x4008C000) /**< (I2SC0) Control Register */
|
||||
#define REG_I2SC0_MR (0x4008C004) /**< (I2SC0) Mode Register */
|
||||
#define REG_I2SC0_SR (0x4008C008) /**< (I2SC0) Status Register */
|
||||
#define REG_I2SC0_SCR (0x4008C00C) /**< (I2SC0) Status Clear Register */
|
||||
#define REG_I2SC0_SSR (0x4008C010) /**< (I2SC0) Status Set Register */
|
||||
#define REG_I2SC0_IER (0x4008C014) /**< (I2SC0) Interrupt Enable Register */
|
||||
#define REG_I2SC0_IDR (0x4008C018) /**< (I2SC0) Interrupt Disable Register */
|
||||
#define REG_I2SC0_IMR (0x4008C01C) /**< (I2SC0) Interrupt Mask Register */
|
||||
#define REG_I2SC0_RHR (0x4008C020) /**< (I2SC0) Receiver Holding Register */
|
||||
#define REG_I2SC0_THR (0x4008C024) /**< (I2SC0) Transmitter Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_I2SC0_CR (*(__O uint32_t*)0x4008C000U) /**< (I2SC0) Control Register */
|
||||
#define REG_I2SC0_MR (*(__IO uint32_t*)0x4008C004U) /**< (I2SC0) Mode Register */
|
||||
#define REG_I2SC0_SR (*(__I uint32_t*)0x4008C008U) /**< (I2SC0) Status Register */
|
||||
#define REG_I2SC0_SCR (*(__O uint32_t*)0x4008C00CU) /**< (I2SC0) Status Clear Register */
|
||||
#define REG_I2SC0_SSR (*(__O uint32_t*)0x4008C010U) /**< (I2SC0) Status Set Register */
|
||||
#define REG_I2SC0_IER (*(__O uint32_t*)0x4008C014U) /**< (I2SC0) Interrupt Enable Register */
|
||||
#define REG_I2SC0_IDR (*(__O uint32_t*)0x4008C018U) /**< (I2SC0) Interrupt Disable Register */
|
||||
#define REG_I2SC0_IMR (*(__I uint32_t*)0x4008C01CU) /**< (I2SC0) Interrupt Mask Register */
|
||||
#define REG_I2SC0_RHR (*(__I uint32_t*)0x4008C020U) /**< (I2SC0) Receiver Holding Register */
|
||||
#define REG_I2SC0_THR (*(__O uint32_t*)0x4008C024U) /**< (I2SC0) Transmitter Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for I2SC0 peripheral ========== */
|
||||
#define I2SC0_INSTANCE_ID 69
|
||||
#define I2SC0_CLOCK_ID 69
|
||||
#define I2SC0_DMAC_ID_TX_LEFT 44
|
||||
#define I2SC0_DMAC_ID_RX_LEFT 45
|
||||
#define I2SC0_DMAC_ID_TX_RIGHT 48
|
||||
#define I2SC0_DMAC_ID_RX_RIGHT 49
|
||||
|
||||
#endif /* _SAME70_I2SC0_INSTANCE_ */
|
||||
71
lib/same70b/include/instance/i2sc1.h
Normal file
71
lib/same70b/include/instance/i2sc1.h
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for I2SC1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_I2SC1_INSTANCE_H_
|
||||
#define _SAME70_I2SC1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for I2SC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_I2SC1_CR (0x40090000) /**< (I2SC1) Control Register */
|
||||
#define REG_I2SC1_MR (0x40090004) /**< (I2SC1) Mode Register */
|
||||
#define REG_I2SC1_SR (0x40090008) /**< (I2SC1) Status Register */
|
||||
#define REG_I2SC1_SCR (0x4009000C) /**< (I2SC1) Status Clear Register */
|
||||
#define REG_I2SC1_SSR (0x40090010) /**< (I2SC1) Status Set Register */
|
||||
#define REG_I2SC1_IER (0x40090014) /**< (I2SC1) Interrupt Enable Register */
|
||||
#define REG_I2SC1_IDR (0x40090018) /**< (I2SC1) Interrupt Disable Register */
|
||||
#define REG_I2SC1_IMR (0x4009001C) /**< (I2SC1) Interrupt Mask Register */
|
||||
#define REG_I2SC1_RHR (0x40090020) /**< (I2SC1) Receiver Holding Register */
|
||||
#define REG_I2SC1_THR (0x40090024) /**< (I2SC1) Transmitter Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_I2SC1_CR (*(__O uint32_t*)0x40090000U) /**< (I2SC1) Control Register */
|
||||
#define REG_I2SC1_MR (*(__IO uint32_t*)0x40090004U) /**< (I2SC1) Mode Register */
|
||||
#define REG_I2SC1_SR (*(__I uint32_t*)0x40090008U) /**< (I2SC1) Status Register */
|
||||
#define REG_I2SC1_SCR (*(__O uint32_t*)0x4009000CU) /**< (I2SC1) Status Clear Register */
|
||||
#define REG_I2SC1_SSR (*(__O uint32_t*)0x40090010U) /**< (I2SC1) Status Set Register */
|
||||
#define REG_I2SC1_IER (*(__O uint32_t*)0x40090014U) /**< (I2SC1) Interrupt Enable Register */
|
||||
#define REG_I2SC1_IDR (*(__O uint32_t*)0x40090018U) /**< (I2SC1) Interrupt Disable Register */
|
||||
#define REG_I2SC1_IMR (*(__I uint32_t*)0x4009001CU) /**< (I2SC1) Interrupt Mask Register */
|
||||
#define REG_I2SC1_RHR (*(__I uint32_t*)0x40090020U) /**< (I2SC1) Receiver Holding Register */
|
||||
#define REG_I2SC1_THR (*(__O uint32_t*)0x40090024U) /**< (I2SC1) Transmitter Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for I2SC1 peripheral ========== */
|
||||
#define I2SC1_INSTANCE_ID 70
|
||||
#define I2SC1_CLOCK_ID 70
|
||||
#define I2SC1_DMAC_ID_TX_LEFT 46
|
||||
#define I2SC1_DMAC_ID_RX_LEFT 47
|
||||
#define I2SC1_DMAC_ID_TX_RIGHT 50
|
||||
#define I2SC1_DMAC_ID_RX_RIGHT 51
|
||||
|
||||
#endif /* _SAME70_I2SC1_INSTANCE_ */
|
||||
85
lib/same70b/include/instance/icm.h
Normal file
85
lib/same70b/include/instance/icm.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for ICM
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_ICM_INSTANCE_H_
|
||||
#define _SAME70_ICM_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for ICM peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_ICM_CFG (0x40048000) /**< (ICM) Configuration Register */
|
||||
#define REG_ICM_CTRL (0x40048004) /**< (ICM) Control Register */
|
||||
#define REG_ICM_SR (0x40048008) /**< (ICM) Status Register */
|
||||
#define REG_ICM_IER (0x40048010) /**< (ICM) Interrupt Enable Register */
|
||||
#define REG_ICM_IDR (0x40048014) /**< (ICM) Interrupt Disable Register */
|
||||
#define REG_ICM_IMR (0x40048018) /**< (ICM) Interrupt Mask Register */
|
||||
#define REG_ICM_ISR (0x4004801C) /**< (ICM) Interrupt Status Register */
|
||||
#define REG_ICM_UASR (0x40048020) /**< (ICM) Undefined Access Status Register */
|
||||
#define REG_ICM_DSCR (0x40048030) /**< (ICM) Region Descriptor Area Start Address Register */
|
||||
#define REG_ICM_HASH (0x40048034) /**< (ICM) Region Hash Area Start Address Register */
|
||||
#define REG_ICM_UIHVAL (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */
|
||||
#define REG_ICM_UIHVAL0 (0x40048038) /**< (ICM) User Initial Hash Value 0 Register 0 */
|
||||
#define REG_ICM_UIHVAL1 (0x4004803C) /**< (ICM) User Initial Hash Value 0 Register 1 */
|
||||
#define REG_ICM_UIHVAL2 (0x40048040) /**< (ICM) User Initial Hash Value 0 Register 2 */
|
||||
#define REG_ICM_UIHVAL3 (0x40048044) /**< (ICM) User Initial Hash Value 0 Register 3 */
|
||||
#define REG_ICM_UIHVAL4 (0x40048048) /**< (ICM) User Initial Hash Value 0 Register 4 */
|
||||
#define REG_ICM_UIHVAL5 (0x4004804C) /**< (ICM) User Initial Hash Value 0 Register 5 */
|
||||
#define REG_ICM_UIHVAL6 (0x40048050) /**< (ICM) User Initial Hash Value 0 Register 6 */
|
||||
#define REG_ICM_UIHVAL7 (0x40048054) /**< (ICM) User Initial Hash Value 0 Register 7 */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_ICM_CFG (*(__IO uint32_t*)0x40048000U) /**< (ICM) Configuration Register */
|
||||
#define REG_ICM_CTRL (*(__O uint32_t*)0x40048004U) /**< (ICM) Control Register */
|
||||
#define REG_ICM_SR (*(__I uint32_t*)0x40048008U) /**< (ICM) Status Register */
|
||||
#define REG_ICM_IER (*(__O uint32_t*)0x40048010U) /**< (ICM) Interrupt Enable Register */
|
||||
#define REG_ICM_IDR (*(__O uint32_t*)0x40048014U) /**< (ICM) Interrupt Disable Register */
|
||||
#define REG_ICM_IMR (*(__I uint32_t*)0x40048018U) /**< (ICM) Interrupt Mask Register */
|
||||
#define REG_ICM_ISR (*(__I uint32_t*)0x4004801CU) /**< (ICM) Interrupt Status Register */
|
||||
#define REG_ICM_UASR (*(__I uint32_t*)0x40048020U) /**< (ICM) Undefined Access Status Register */
|
||||
#define REG_ICM_DSCR (*(__IO uint32_t*)0x40048030U) /**< (ICM) Region Descriptor Area Start Address Register */
|
||||
#define REG_ICM_HASH (*(__IO uint32_t*)0x40048034U) /**< (ICM) Region Hash Area Start Address Register */
|
||||
#define REG_ICM_UIHVAL (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */
|
||||
#define REG_ICM_UIHVAL0 (*(__O uint32_t*)0x40048038U) /**< (ICM) User Initial Hash Value 0 Register 0 */
|
||||
#define REG_ICM_UIHVAL1 (*(__O uint32_t*)0x4004803CU) /**< (ICM) User Initial Hash Value 0 Register 1 */
|
||||
#define REG_ICM_UIHVAL2 (*(__O uint32_t*)0x40048040U) /**< (ICM) User Initial Hash Value 0 Register 2 */
|
||||
#define REG_ICM_UIHVAL3 (*(__O uint32_t*)0x40048044U) /**< (ICM) User Initial Hash Value 0 Register 3 */
|
||||
#define REG_ICM_UIHVAL4 (*(__O uint32_t*)0x40048048U) /**< (ICM) User Initial Hash Value 0 Register 4 */
|
||||
#define REG_ICM_UIHVAL5 (*(__O uint32_t*)0x4004804CU) /**< (ICM) User Initial Hash Value 0 Register 5 */
|
||||
#define REG_ICM_UIHVAL6 (*(__O uint32_t*)0x40048050U) /**< (ICM) User Initial Hash Value 0 Register 6 */
|
||||
#define REG_ICM_UIHVAL7 (*(__O uint32_t*)0x40048054U) /**< (ICM) User Initial Hash Value 0 Register 7 */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for ICM peripheral ========== */
|
||||
#define ICM_INSTANCE_ID 32
|
||||
#define ICM_CLOCK_ID 32
|
||||
|
||||
#endif /* _SAME70_ICM_INSTANCE_ */
|
||||
97
lib/same70b/include/instance/isi.h
Normal file
97
lib/same70b/include/instance/isi.h
Normal file
|
|
@ -0,0 +1,97 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for ISI
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_ISI_INSTANCE_H_
|
||||
#define _SAME70_ISI_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for ISI peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_ISI_CFG1 (0x4004C000) /**< (ISI) ISI Configuration 1 Register */
|
||||
#define REG_ISI_CFG2 (0x4004C004) /**< (ISI) ISI Configuration 2 Register */
|
||||
#define REG_ISI_PSIZE (0x4004C008) /**< (ISI) ISI Preview Size Register */
|
||||
#define REG_ISI_PDECF (0x4004C00C) /**< (ISI) ISI Preview Decimation Factor Register */
|
||||
#define REG_ISI_Y2R_SET0 (0x4004C010) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
|
||||
#define REG_ISI_Y2R_SET1 (0x4004C014) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
|
||||
#define REG_ISI_R2Y_SET0 (0x4004C018) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
|
||||
#define REG_ISI_R2Y_SET1 (0x4004C01C) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
|
||||
#define REG_ISI_R2Y_SET2 (0x4004C020) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
|
||||
#define REG_ISI_CR (0x4004C024) /**< (ISI) ISI Control Register */
|
||||
#define REG_ISI_SR (0x4004C028) /**< (ISI) ISI Status Register */
|
||||
#define REG_ISI_IER (0x4004C02C) /**< (ISI) ISI Interrupt Enable Register */
|
||||
#define REG_ISI_IDR (0x4004C030) /**< (ISI) ISI Interrupt Disable Register */
|
||||
#define REG_ISI_IMR (0x4004C034) /**< (ISI) ISI Interrupt Mask Register */
|
||||
#define REG_ISI_DMA_CHER (0x4004C038) /**< (ISI) DMA Channel Enable Register */
|
||||
#define REG_ISI_DMA_CHDR (0x4004C03C) /**< (ISI) DMA Channel Disable Register */
|
||||
#define REG_ISI_DMA_CHSR (0x4004C040) /**< (ISI) DMA Channel Status Register */
|
||||
#define REG_ISI_DMA_P_ADDR (0x4004C044) /**< (ISI) DMA Preview Base Address Register */
|
||||
#define REG_ISI_DMA_P_CTRL (0x4004C048) /**< (ISI) DMA Preview Control Register */
|
||||
#define REG_ISI_DMA_P_DSCR (0x4004C04C) /**< (ISI) DMA Preview Descriptor Address Register */
|
||||
#define REG_ISI_DMA_C_ADDR (0x4004C050) /**< (ISI) DMA Codec Base Address Register */
|
||||
#define REG_ISI_DMA_C_CTRL (0x4004C054) /**< (ISI) DMA Codec Control Register */
|
||||
#define REG_ISI_DMA_C_DSCR (0x4004C058) /**< (ISI) DMA Codec Descriptor Address Register */
|
||||
#define REG_ISI_WPMR (0x4004C0E4) /**< (ISI) Write Protection Mode Register */
|
||||
#define REG_ISI_WPSR (0x4004C0E8) /**< (ISI) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_ISI_CFG1 (*(__IO uint32_t*)0x4004C000U) /**< (ISI) ISI Configuration 1 Register */
|
||||
#define REG_ISI_CFG2 (*(__IO uint32_t*)0x4004C004U) /**< (ISI) ISI Configuration 2 Register */
|
||||
#define REG_ISI_PSIZE (*(__IO uint32_t*)0x4004C008U) /**< (ISI) ISI Preview Size Register */
|
||||
#define REG_ISI_PDECF (*(__IO uint32_t*)0x4004C00CU) /**< (ISI) ISI Preview Decimation Factor Register */
|
||||
#define REG_ISI_Y2R_SET0 (*(__IO uint32_t*)0x4004C010U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 0 Register */
|
||||
#define REG_ISI_Y2R_SET1 (*(__IO uint32_t*)0x4004C014U) /**< (ISI) ISI Color Space Conversion YCrCb To RGB Set 1 Register */
|
||||
#define REG_ISI_R2Y_SET0 (*(__IO uint32_t*)0x4004C018U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 0 Register */
|
||||
#define REG_ISI_R2Y_SET1 (*(__IO uint32_t*)0x4004C01CU) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 1 Register */
|
||||
#define REG_ISI_R2Y_SET2 (*(__IO uint32_t*)0x4004C020U) /**< (ISI) ISI Color Space Conversion RGB To YCrCb Set 2 Register */
|
||||
#define REG_ISI_CR (*(__O uint32_t*)0x4004C024U) /**< (ISI) ISI Control Register */
|
||||
#define REG_ISI_SR (*(__I uint32_t*)0x4004C028U) /**< (ISI) ISI Status Register */
|
||||
#define REG_ISI_IER (*(__O uint32_t*)0x4004C02CU) /**< (ISI) ISI Interrupt Enable Register */
|
||||
#define REG_ISI_IDR (*(__O uint32_t*)0x4004C030U) /**< (ISI) ISI Interrupt Disable Register */
|
||||
#define REG_ISI_IMR (*(__I uint32_t*)0x4004C034U) /**< (ISI) ISI Interrupt Mask Register */
|
||||
#define REG_ISI_DMA_CHER (*(__O uint32_t*)0x4004C038U) /**< (ISI) DMA Channel Enable Register */
|
||||
#define REG_ISI_DMA_CHDR (*(__O uint32_t*)0x4004C03CU) /**< (ISI) DMA Channel Disable Register */
|
||||
#define REG_ISI_DMA_CHSR (*(__I uint32_t*)0x4004C040U) /**< (ISI) DMA Channel Status Register */
|
||||
#define REG_ISI_DMA_P_ADDR (*(__IO uint32_t*)0x4004C044U) /**< (ISI) DMA Preview Base Address Register */
|
||||
#define REG_ISI_DMA_P_CTRL (*(__IO uint32_t*)0x4004C048U) /**< (ISI) DMA Preview Control Register */
|
||||
#define REG_ISI_DMA_P_DSCR (*(__IO uint32_t*)0x4004C04CU) /**< (ISI) DMA Preview Descriptor Address Register */
|
||||
#define REG_ISI_DMA_C_ADDR (*(__IO uint32_t*)0x4004C050U) /**< (ISI) DMA Codec Base Address Register */
|
||||
#define REG_ISI_DMA_C_CTRL (*(__IO uint32_t*)0x4004C054U) /**< (ISI) DMA Codec Control Register */
|
||||
#define REG_ISI_DMA_C_DSCR (*(__IO uint32_t*)0x4004C058U) /**< (ISI) DMA Codec Descriptor Address Register */
|
||||
#define REG_ISI_WPMR (*(__IO uint32_t*)0x4004C0E4U) /**< (ISI) Write Protection Mode Register */
|
||||
#define REG_ISI_WPSR (*(__I uint32_t*)0x4004C0E8U) /**< (ISI) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for ISI peripheral ========== */
|
||||
#define ISI_INSTANCE_ID 59
|
||||
#define ISI_CLOCK_ID 59
|
||||
|
||||
#endif /* _SAME70_ISI_INSTANCE_ */
|
||||
142
lib/same70b/include/instance/matrix.h
Normal file
142
lib/same70b/include/instance/matrix.h
Normal file
|
|
@ -0,0 +1,142 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for MATRIX
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_MATRIX_INSTANCE_H_
|
||||
#define _SAME70_MATRIX_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for MATRIX peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_MATRIX_PRAS0 (0x40088080) /**< (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRBS0 (0x40088084) /**< (MATRIX) Priority Register B for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 (0x40088088) /**< (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRBS1 (0x4008808C) /**< (MATRIX) Priority Register B for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 (0x40088090) /**< (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRBS2 (0x40088094) /**< (MATRIX) Priority Register B for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 (0x40088098) /**< (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_MATRIX_PRBS3 (0x4008809C) /**< (MATRIX) Priority Register B for Slave 3 */
|
||||
#define REG_MATRIX_PRAS4 (0x400880A0) /**< (MATRIX) Priority Register A for Slave 4 */
|
||||
#define REG_MATRIX_PRBS4 (0x400880A4) /**< (MATRIX) Priority Register B for Slave 4 */
|
||||
#define REG_MATRIX_PRAS5 (0x400880A8) /**< (MATRIX) Priority Register A for Slave 5 */
|
||||
#define REG_MATRIX_PRBS5 (0x400880AC) /**< (MATRIX) Priority Register B for Slave 5 */
|
||||
#define REG_MATRIX_PRAS6 (0x400880B0) /**< (MATRIX) Priority Register A for Slave 6 */
|
||||
#define REG_MATRIX_PRBS6 (0x400880B4) /**< (MATRIX) Priority Register B for Slave 6 */
|
||||
#define REG_MATRIX_PRAS7 (0x400880B8) /**< (MATRIX) Priority Register A for Slave 7 */
|
||||
#define REG_MATRIX_PRBS7 (0x400880BC) /**< (MATRIX) Priority Register B for Slave 7 */
|
||||
#define REG_MATRIX_PRAS8 (0x400880C0) /**< (MATRIX) Priority Register A for Slave 8 */
|
||||
#define REG_MATRIX_PRBS8 (0x400880C4) /**< (MATRIX) Priority Register B for Slave 8 */
|
||||
#define REG_MATRIX_MCFG (0x40088000) /**< (MATRIX) Master Configuration Register 0 */
|
||||
#define REG_MATRIX_MCFG0 (0x40088000) /**< (MATRIX) Master Configuration Register 0 */
|
||||
#define REG_MATRIX_MCFG1 (0x40088004) /**< (MATRIX) Master Configuration Register 1 */
|
||||
#define REG_MATRIX_MCFG2 (0x40088008) /**< (MATRIX) Master Configuration Register 2 */
|
||||
#define REG_MATRIX_MCFG3 (0x4008800C) /**< (MATRIX) Master Configuration Register 3 */
|
||||
#define REG_MATRIX_MCFG4 (0x40088010) /**< (MATRIX) Master Configuration Register 4 */
|
||||
#define REG_MATRIX_MCFG5 (0x40088014) /**< (MATRIX) Master Configuration Register 5 */
|
||||
#define REG_MATRIX_MCFG6 (0x40088018) /**< (MATRIX) Master Configuration Register 6 */
|
||||
#define REG_MATRIX_MCFG7 (0x4008801C) /**< (MATRIX) Master Configuration Register 7 */
|
||||
#define REG_MATRIX_MCFG8 (0x40088020) /**< (MATRIX) Master Configuration Register 8 */
|
||||
#define REG_MATRIX_MCFG9 (0x40088024) /**< (MATRIX) Master Configuration Register 9 */
|
||||
#define REG_MATRIX_MCFG10 (0x40088028) /**< (MATRIX) Master Configuration Register 10 */
|
||||
#define REG_MATRIX_MCFG11 (0x4008802C) /**< (MATRIX) Master Configuration Register 11 */
|
||||
#define REG_MATRIX_MCFG12 (0x40088030) /**< (MATRIX) Master Configuration Register 12 */
|
||||
#define REG_MATRIX_SCFG (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */
|
||||
#define REG_MATRIX_SCFG0 (0x40088040) /**< (MATRIX) Slave Configuration Register 0 */
|
||||
#define REG_MATRIX_SCFG1 (0x40088044) /**< (MATRIX) Slave Configuration Register 1 */
|
||||
#define REG_MATRIX_SCFG2 (0x40088048) /**< (MATRIX) Slave Configuration Register 2 */
|
||||
#define REG_MATRIX_SCFG3 (0x4008804C) /**< (MATRIX) Slave Configuration Register 3 */
|
||||
#define REG_MATRIX_SCFG4 (0x40088050) /**< (MATRIX) Slave Configuration Register 4 */
|
||||
#define REG_MATRIX_SCFG5 (0x40088054) /**< (MATRIX) Slave Configuration Register 5 */
|
||||
#define REG_MATRIX_SCFG6 (0x40088058) /**< (MATRIX) Slave Configuration Register 6 */
|
||||
#define REG_MATRIX_SCFG7 (0x4008805C) /**< (MATRIX) Slave Configuration Register 7 */
|
||||
#define REG_MATRIX_SCFG8 (0x40088060) /**< (MATRIX) Slave Configuration Register 8 */
|
||||
#define REG_MATRIX_MRCR (0x40088100) /**< (MATRIX) Master Remap Control Register */
|
||||
#define REG_CCFG_CAN0 (0x40088110) /**< (MATRIX) CAN0 Configuration Register */
|
||||
#define REG_CCFG_SYSIO (0x40088114) /**< (MATRIX) System I/O and CAN1 Configuration Register */
|
||||
#define REG_CCFG_PCCR (0x40088118) /**< (MATRIX) Peripheral Clock Configuration Register */
|
||||
#define REG_CCFG_DYNCKG (0x4008811C) /**< (MATRIX) Dynamic Clock Gating Register */
|
||||
#define REG_CCFG_SMCNFCS (0x40088124) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */
|
||||
#define REG_MATRIX_WPMR (0x400881E4) /**< (MATRIX) Write Protection Mode Register */
|
||||
#define REG_MATRIX_WPSR (0x400881E8) /**< (MATRIX) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_MATRIX_PRAS0 (*(__IO uint32_t*)0x40088080U) /**< (MATRIX) Priority Register A for Slave 0 */
|
||||
#define REG_MATRIX_PRBS0 (*(__IO uint32_t*)0x40088084U) /**< (MATRIX) Priority Register B for Slave 0 */
|
||||
#define REG_MATRIX_PRAS1 (*(__IO uint32_t*)0x40088088U) /**< (MATRIX) Priority Register A for Slave 1 */
|
||||
#define REG_MATRIX_PRBS1 (*(__IO uint32_t*)0x4008808CU) /**< (MATRIX) Priority Register B for Slave 1 */
|
||||
#define REG_MATRIX_PRAS2 (*(__IO uint32_t*)0x40088090U) /**< (MATRIX) Priority Register A for Slave 2 */
|
||||
#define REG_MATRIX_PRBS2 (*(__IO uint32_t*)0x40088094U) /**< (MATRIX) Priority Register B for Slave 2 */
|
||||
#define REG_MATRIX_PRAS3 (*(__IO uint32_t*)0x40088098U) /**< (MATRIX) Priority Register A for Slave 3 */
|
||||
#define REG_MATRIX_PRBS3 (*(__IO uint32_t*)0x4008809CU) /**< (MATRIX) Priority Register B for Slave 3 */
|
||||
#define REG_MATRIX_PRAS4 (*(__IO uint32_t*)0x400880A0U) /**< (MATRIX) Priority Register A for Slave 4 */
|
||||
#define REG_MATRIX_PRBS4 (*(__IO uint32_t*)0x400880A4U) /**< (MATRIX) Priority Register B for Slave 4 */
|
||||
#define REG_MATRIX_PRAS5 (*(__IO uint32_t*)0x400880A8U) /**< (MATRIX) Priority Register A for Slave 5 */
|
||||
#define REG_MATRIX_PRBS5 (*(__IO uint32_t*)0x400880ACU) /**< (MATRIX) Priority Register B for Slave 5 */
|
||||
#define REG_MATRIX_PRAS6 (*(__IO uint32_t*)0x400880B0U) /**< (MATRIX) Priority Register A for Slave 6 */
|
||||
#define REG_MATRIX_PRBS6 (*(__IO uint32_t*)0x400880B4U) /**< (MATRIX) Priority Register B for Slave 6 */
|
||||
#define REG_MATRIX_PRAS7 (*(__IO uint32_t*)0x400880B8U) /**< (MATRIX) Priority Register A for Slave 7 */
|
||||
#define REG_MATRIX_PRBS7 (*(__IO uint32_t*)0x400880BCU) /**< (MATRIX) Priority Register B for Slave 7 */
|
||||
#define REG_MATRIX_PRAS8 (*(__IO uint32_t*)0x400880C0U) /**< (MATRIX) Priority Register A for Slave 8 */
|
||||
#define REG_MATRIX_PRBS8 (*(__IO uint32_t*)0x400880C4U) /**< (MATRIX) Priority Register B for Slave 8 */
|
||||
#define REG_MATRIX_MCFG (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */
|
||||
#define REG_MATRIX_MCFG0 (*(__IO uint32_t*)0x40088000U) /**< (MATRIX) Master Configuration Register 0 */
|
||||
#define REG_MATRIX_MCFG1 (*(__IO uint32_t*)0x40088004U) /**< (MATRIX) Master Configuration Register 1 */
|
||||
#define REG_MATRIX_MCFG2 (*(__IO uint32_t*)0x40088008U) /**< (MATRIX) Master Configuration Register 2 */
|
||||
#define REG_MATRIX_MCFG3 (*(__IO uint32_t*)0x4008800CU) /**< (MATRIX) Master Configuration Register 3 */
|
||||
#define REG_MATRIX_MCFG4 (*(__IO uint32_t*)0x40088010U) /**< (MATRIX) Master Configuration Register 4 */
|
||||
#define REG_MATRIX_MCFG5 (*(__IO uint32_t*)0x40088014U) /**< (MATRIX) Master Configuration Register 5 */
|
||||
#define REG_MATRIX_MCFG6 (*(__IO uint32_t*)0x40088018U) /**< (MATRIX) Master Configuration Register 6 */
|
||||
#define REG_MATRIX_MCFG7 (*(__IO uint32_t*)0x4008801CU) /**< (MATRIX) Master Configuration Register 7 */
|
||||
#define REG_MATRIX_MCFG8 (*(__IO uint32_t*)0x40088020U) /**< (MATRIX) Master Configuration Register 8 */
|
||||
#define REG_MATRIX_MCFG9 (*(__IO uint32_t*)0x40088024U) /**< (MATRIX) Master Configuration Register 9 */
|
||||
#define REG_MATRIX_MCFG10 (*(__IO uint32_t*)0x40088028U) /**< (MATRIX) Master Configuration Register 10 */
|
||||
#define REG_MATRIX_MCFG11 (*(__IO uint32_t*)0x4008802CU) /**< (MATRIX) Master Configuration Register 11 */
|
||||
#define REG_MATRIX_MCFG12 (*(__IO uint32_t*)0x40088030U) /**< (MATRIX) Master Configuration Register 12 */
|
||||
#define REG_MATRIX_SCFG (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */
|
||||
#define REG_MATRIX_SCFG0 (*(__IO uint32_t*)0x40088040U) /**< (MATRIX) Slave Configuration Register 0 */
|
||||
#define REG_MATRIX_SCFG1 (*(__IO uint32_t*)0x40088044U) /**< (MATRIX) Slave Configuration Register 1 */
|
||||
#define REG_MATRIX_SCFG2 (*(__IO uint32_t*)0x40088048U) /**< (MATRIX) Slave Configuration Register 2 */
|
||||
#define REG_MATRIX_SCFG3 (*(__IO uint32_t*)0x4008804CU) /**< (MATRIX) Slave Configuration Register 3 */
|
||||
#define REG_MATRIX_SCFG4 (*(__IO uint32_t*)0x40088050U) /**< (MATRIX) Slave Configuration Register 4 */
|
||||
#define REG_MATRIX_SCFG5 (*(__IO uint32_t*)0x40088054U) /**< (MATRIX) Slave Configuration Register 5 */
|
||||
#define REG_MATRIX_SCFG6 (*(__IO uint32_t*)0x40088058U) /**< (MATRIX) Slave Configuration Register 6 */
|
||||
#define REG_MATRIX_SCFG7 (*(__IO uint32_t*)0x4008805CU) /**< (MATRIX) Slave Configuration Register 7 */
|
||||
#define REG_MATRIX_SCFG8 (*(__IO uint32_t*)0x40088060U) /**< (MATRIX) Slave Configuration Register 8 */
|
||||
#define REG_MATRIX_MRCR (*(__IO uint32_t*)0x40088100U) /**< (MATRIX) Master Remap Control Register */
|
||||
#define REG_CCFG_CAN0 (*(__IO uint32_t*)0x40088110U) /**< (MATRIX) CAN0 Configuration Register */
|
||||
#define REG_CCFG_SYSIO (*(__IO uint32_t*)0x40088114U) /**< (MATRIX) System I/O and CAN1 Configuration Register */
|
||||
#define REG_CCFG_PCCR (*(__IO uint32_t*)0x40088118U) /**< (MATRIX) Peripheral Clock Configuration Register */
|
||||
#define REG_CCFG_DYNCKG (*(__IO uint32_t*)0x4008811CU) /**< (MATRIX) Dynamic Clock Gating Register */
|
||||
#define REG_CCFG_SMCNFCS (*(__IO uint32_t*)0x40088124U) /**< (MATRIX) SMC NAND Flash Chip Select Configuration Register */
|
||||
#define REG_MATRIX_WPMR (*(__IO uint32_t*)0x400881E4U) /**< (MATRIX) Write Protection Mode Register */
|
||||
#define REG_MATRIX_WPSR (*(__I uint32_t*)0x400881E8U) /**< (MATRIX) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_MATRIX_INSTANCE_ */
|
||||
141
lib/same70b/include/instance/mcan0.h
Normal file
141
lib/same70b/include/instance/mcan0.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for MCAN0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_MCAN0_INSTANCE_H_
|
||||
#define _SAME70_MCAN0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for MCAN0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_MCAN0_CREL (0x40030000) /**< (MCAN0) Core Release Register */
|
||||
#define REG_MCAN0_ENDN (0x40030004) /**< (MCAN0) Endian Register */
|
||||
#define REG_MCAN0_CUST (0x40030008) /**< (MCAN0) Customer Register */
|
||||
#define REG_MCAN0_DBTP (0x4003000C) /**< (MCAN0) Data Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN0_TEST (0x40030010) /**< (MCAN0) Test Register */
|
||||
#define REG_MCAN0_RWD (0x40030014) /**< (MCAN0) RAM Watchdog Register */
|
||||
#define REG_MCAN0_CCCR (0x40030018) /**< (MCAN0) CC Control Register */
|
||||
#define REG_MCAN0_NBTP (0x4003001C) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN0_TSCC (0x40030020) /**< (MCAN0) Timestamp Counter Configuration Register */
|
||||
#define REG_MCAN0_TSCV (0x40030024) /**< (MCAN0) Timestamp Counter Value Register */
|
||||
#define REG_MCAN0_TOCC (0x40030028) /**< (MCAN0) Timeout Counter Configuration Register */
|
||||
#define REG_MCAN0_TOCV (0x4003002C) /**< (MCAN0) Timeout Counter Value Register */
|
||||
#define REG_MCAN0_ECR (0x40030040) /**< (MCAN0) Error Counter Register */
|
||||
#define REG_MCAN0_PSR (0x40030044) /**< (MCAN0) Protocol Status Register */
|
||||
#define REG_MCAN0_TDCR (0x40030048) /**< (MCAN0) Transmit Delay Compensation Register */
|
||||
#define REG_MCAN0_IR (0x40030050) /**< (MCAN0) Interrupt Register */
|
||||
#define REG_MCAN0_IE (0x40030054) /**< (MCAN0) Interrupt Enable Register */
|
||||
#define REG_MCAN0_ILS (0x40030058) /**< (MCAN0) Interrupt Line Select Register */
|
||||
#define REG_MCAN0_ILE (0x4003005C) /**< (MCAN0) Interrupt Line Enable Register */
|
||||
#define REG_MCAN0_GFC (0x40030080) /**< (MCAN0) Global Filter Configuration Register */
|
||||
#define REG_MCAN0_SIDFC (0x40030084) /**< (MCAN0) Standard ID Filter Configuration Register */
|
||||
#define REG_MCAN0_XIDFC (0x40030088) /**< (MCAN0) Extended ID Filter Configuration Register */
|
||||
#define REG_MCAN0_XIDAM (0x40030090) /**< (MCAN0) Extended ID AND Mask Register */
|
||||
#define REG_MCAN0_HPMS (0x40030094) /**< (MCAN0) High Priority Message Status Register */
|
||||
#define REG_MCAN0_NDAT1 (0x40030098) /**< (MCAN0) New Data 1 Register */
|
||||
#define REG_MCAN0_NDAT2 (0x4003009C) /**< (MCAN0) New Data 2 Register */
|
||||
#define REG_MCAN0_RXF0C (0x400300A0) /**< (MCAN0) Receive FIFO 0 Configuration Register */
|
||||
#define REG_MCAN0_RXF0S (0x400300A4) /**< (MCAN0) Receive FIFO 0 Status Register */
|
||||
#define REG_MCAN0_RXF0A (0x400300A8) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */
|
||||
#define REG_MCAN0_RXBC (0x400300AC) /**< (MCAN0) Receive Rx Buffer Configuration Register */
|
||||
#define REG_MCAN0_RXF1C (0x400300B0) /**< (MCAN0) Receive FIFO 1 Configuration Register */
|
||||
#define REG_MCAN0_RXF1S (0x400300B4) /**< (MCAN0) Receive FIFO 1 Status Register */
|
||||
#define REG_MCAN0_RXF1A (0x400300B8) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */
|
||||
#define REG_MCAN0_RXESC (0x400300BC) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
|
||||
#define REG_MCAN0_TXBC (0x400300C0) /**< (MCAN0) Transmit Buffer Configuration Register */
|
||||
#define REG_MCAN0_TXFQS (0x400300C4) /**< (MCAN0) Transmit FIFO/Queue Status Register */
|
||||
#define REG_MCAN0_TXESC (0x400300C8) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */
|
||||
#define REG_MCAN0_TXBRP (0x400300CC) /**< (MCAN0) Transmit Buffer Request Pending Register */
|
||||
#define REG_MCAN0_TXBAR (0x400300D0) /**< (MCAN0) Transmit Buffer Add Request Register */
|
||||
#define REG_MCAN0_TXBCR (0x400300D4) /**< (MCAN0) Transmit Buffer Cancellation Request Register */
|
||||
#define REG_MCAN0_TXBTO (0x400300D8) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */
|
||||
#define REG_MCAN0_TXBCF (0x400300DC) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */
|
||||
#define REG_MCAN0_TXBTIE (0x400300E0) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
|
||||
#define REG_MCAN0_TXBCIE (0x400300E4) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
|
||||
#define REG_MCAN0_TXEFC (0x400300F0) /**< (MCAN0) Transmit Event FIFO Configuration Register */
|
||||
#define REG_MCAN0_TXEFS (0x400300F4) /**< (MCAN0) Transmit Event FIFO Status Register */
|
||||
#define REG_MCAN0_TXEFA (0x400300F8) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_MCAN0_CREL (*(__I uint32_t*)0x40030000U) /**< (MCAN0) Core Release Register */
|
||||
#define REG_MCAN0_ENDN (*(__I uint32_t*)0x40030004U) /**< (MCAN0) Endian Register */
|
||||
#define REG_MCAN0_CUST (*(__IO uint32_t*)0x40030008U) /**< (MCAN0) Customer Register */
|
||||
#define REG_MCAN0_DBTP (*(__IO uint32_t*)0x4003000CU) /**< (MCAN0) Data Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN0_TEST (*(__IO uint32_t*)0x40030010U) /**< (MCAN0) Test Register */
|
||||
#define REG_MCAN0_RWD (*(__IO uint32_t*)0x40030014U) /**< (MCAN0) RAM Watchdog Register */
|
||||
#define REG_MCAN0_CCCR (*(__IO uint32_t*)0x40030018U) /**< (MCAN0) CC Control Register */
|
||||
#define REG_MCAN0_NBTP (*(__IO uint32_t*)0x4003001CU) /**< (MCAN0) Nominal Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN0_TSCC (*(__IO uint32_t*)0x40030020U) /**< (MCAN0) Timestamp Counter Configuration Register */
|
||||
#define REG_MCAN0_TSCV (*(__IO uint32_t*)0x40030024U) /**< (MCAN0) Timestamp Counter Value Register */
|
||||
#define REG_MCAN0_TOCC (*(__IO uint32_t*)0x40030028U) /**< (MCAN0) Timeout Counter Configuration Register */
|
||||
#define REG_MCAN0_TOCV (*(__IO uint32_t*)0x4003002CU) /**< (MCAN0) Timeout Counter Value Register */
|
||||
#define REG_MCAN0_ECR (*(__I uint32_t*)0x40030040U) /**< (MCAN0) Error Counter Register */
|
||||
#define REG_MCAN0_PSR (*(__I uint32_t*)0x40030044U) /**< (MCAN0) Protocol Status Register */
|
||||
#define REG_MCAN0_TDCR (*(__IO uint32_t*)0x40030048U) /**< (MCAN0) Transmit Delay Compensation Register */
|
||||
#define REG_MCAN0_IR (*(__IO uint32_t*)0x40030050U) /**< (MCAN0) Interrupt Register */
|
||||
#define REG_MCAN0_IE (*(__IO uint32_t*)0x40030054U) /**< (MCAN0) Interrupt Enable Register */
|
||||
#define REG_MCAN0_ILS (*(__IO uint32_t*)0x40030058U) /**< (MCAN0) Interrupt Line Select Register */
|
||||
#define REG_MCAN0_ILE (*(__IO uint32_t*)0x4003005CU) /**< (MCAN0) Interrupt Line Enable Register */
|
||||
#define REG_MCAN0_GFC (*(__IO uint32_t*)0x40030080U) /**< (MCAN0) Global Filter Configuration Register */
|
||||
#define REG_MCAN0_SIDFC (*(__IO uint32_t*)0x40030084U) /**< (MCAN0) Standard ID Filter Configuration Register */
|
||||
#define REG_MCAN0_XIDFC (*(__IO uint32_t*)0x40030088U) /**< (MCAN0) Extended ID Filter Configuration Register */
|
||||
#define REG_MCAN0_XIDAM (*(__IO uint32_t*)0x40030090U) /**< (MCAN0) Extended ID AND Mask Register */
|
||||
#define REG_MCAN0_HPMS (*(__I uint32_t*)0x40030094U) /**< (MCAN0) High Priority Message Status Register */
|
||||
#define REG_MCAN0_NDAT1 (*(__IO uint32_t*)0x40030098U) /**< (MCAN0) New Data 1 Register */
|
||||
#define REG_MCAN0_NDAT2 (*(__IO uint32_t*)0x4003009CU) /**< (MCAN0) New Data 2 Register */
|
||||
#define REG_MCAN0_RXF0C (*(__IO uint32_t*)0x400300A0U) /**< (MCAN0) Receive FIFO 0 Configuration Register */
|
||||
#define REG_MCAN0_RXF0S (*(__I uint32_t*)0x400300A4U) /**< (MCAN0) Receive FIFO 0 Status Register */
|
||||
#define REG_MCAN0_RXF0A (*(__IO uint32_t*)0x400300A8U) /**< (MCAN0) Receive FIFO 0 Acknowledge Register */
|
||||
#define REG_MCAN0_RXBC (*(__IO uint32_t*)0x400300ACU) /**< (MCAN0) Receive Rx Buffer Configuration Register */
|
||||
#define REG_MCAN0_RXF1C (*(__IO uint32_t*)0x400300B0U) /**< (MCAN0) Receive FIFO 1 Configuration Register */
|
||||
#define REG_MCAN0_RXF1S (*(__I uint32_t*)0x400300B4U) /**< (MCAN0) Receive FIFO 1 Status Register */
|
||||
#define REG_MCAN0_RXF1A (*(__IO uint32_t*)0x400300B8U) /**< (MCAN0) Receive FIFO 1 Acknowledge Register */
|
||||
#define REG_MCAN0_RXESC (*(__IO uint32_t*)0x400300BCU) /**< (MCAN0) Receive Buffer / FIFO Element Size Configuration Register */
|
||||
#define REG_MCAN0_TXBC (*(__IO uint32_t*)0x400300C0U) /**< (MCAN0) Transmit Buffer Configuration Register */
|
||||
#define REG_MCAN0_TXFQS (*(__I uint32_t*)0x400300C4U) /**< (MCAN0) Transmit FIFO/Queue Status Register */
|
||||
#define REG_MCAN0_TXESC (*(__IO uint32_t*)0x400300C8U) /**< (MCAN0) Transmit Buffer Element Size Configuration Register */
|
||||
#define REG_MCAN0_TXBRP (*(__I uint32_t*)0x400300CCU) /**< (MCAN0) Transmit Buffer Request Pending Register */
|
||||
#define REG_MCAN0_TXBAR (*(__IO uint32_t*)0x400300D0U) /**< (MCAN0) Transmit Buffer Add Request Register */
|
||||
#define REG_MCAN0_TXBCR (*(__IO uint32_t*)0x400300D4U) /**< (MCAN0) Transmit Buffer Cancellation Request Register */
|
||||
#define REG_MCAN0_TXBTO (*(__I uint32_t*)0x400300D8U) /**< (MCAN0) Transmit Buffer Transmission Occurred Register */
|
||||
#define REG_MCAN0_TXBCF (*(__I uint32_t*)0x400300DCU) /**< (MCAN0) Transmit Buffer Cancellation Finished Register */
|
||||
#define REG_MCAN0_TXBTIE (*(__IO uint32_t*)0x400300E0U) /**< (MCAN0) Transmit Buffer Transmission Interrupt Enable Register */
|
||||
#define REG_MCAN0_TXBCIE (*(__IO uint32_t*)0x400300E4U) /**< (MCAN0) Transmit Buffer Cancellation Finished Interrupt Enable Register */
|
||||
#define REG_MCAN0_TXEFC (*(__IO uint32_t*)0x400300F0U) /**< (MCAN0) Transmit Event FIFO Configuration Register */
|
||||
#define REG_MCAN0_TXEFS (*(__I uint32_t*)0x400300F4U) /**< (MCAN0) Transmit Event FIFO Status Register */
|
||||
#define REG_MCAN0_TXEFA (*(__IO uint32_t*)0x400300F8U) /**< (MCAN0) Transmit Event FIFO Acknowledge Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for MCAN0 peripheral ========== */
|
||||
#define MCAN0_INSTANCE_ID 35
|
||||
#define MCAN0_CLOCK_ID 35
|
||||
|
||||
#endif /* _SAME70_MCAN0_INSTANCE_ */
|
||||
141
lib/same70b/include/instance/mcan1.h
Normal file
141
lib/same70b/include/instance/mcan1.h
Normal file
|
|
@ -0,0 +1,141 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for MCAN1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_MCAN1_INSTANCE_H_
|
||||
#define _SAME70_MCAN1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for MCAN1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_MCAN1_CREL (0x40034000) /**< (MCAN1) Core Release Register */
|
||||
#define REG_MCAN1_ENDN (0x40034004) /**< (MCAN1) Endian Register */
|
||||
#define REG_MCAN1_CUST (0x40034008) /**< (MCAN1) Customer Register */
|
||||
#define REG_MCAN1_DBTP (0x4003400C) /**< (MCAN1) Data Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN1_TEST (0x40034010) /**< (MCAN1) Test Register */
|
||||
#define REG_MCAN1_RWD (0x40034014) /**< (MCAN1) RAM Watchdog Register */
|
||||
#define REG_MCAN1_CCCR (0x40034018) /**< (MCAN1) CC Control Register */
|
||||
#define REG_MCAN1_NBTP (0x4003401C) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN1_TSCC (0x40034020) /**< (MCAN1) Timestamp Counter Configuration Register */
|
||||
#define REG_MCAN1_TSCV (0x40034024) /**< (MCAN1) Timestamp Counter Value Register */
|
||||
#define REG_MCAN1_TOCC (0x40034028) /**< (MCAN1) Timeout Counter Configuration Register */
|
||||
#define REG_MCAN1_TOCV (0x4003402C) /**< (MCAN1) Timeout Counter Value Register */
|
||||
#define REG_MCAN1_ECR (0x40034040) /**< (MCAN1) Error Counter Register */
|
||||
#define REG_MCAN1_PSR (0x40034044) /**< (MCAN1) Protocol Status Register */
|
||||
#define REG_MCAN1_TDCR (0x40034048) /**< (MCAN1) Transmit Delay Compensation Register */
|
||||
#define REG_MCAN1_IR (0x40034050) /**< (MCAN1) Interrupt Register */
|
||||
#define REG_MCAN1_IE (0x40034054) /**< (MCAN1) Interrupt Enable Register */
|
||||
#define REG_MCAN1_ILS (0x40034058) /**< (MCAN1) Interrupt Line Select Register */
|
||||
#define REG_MCAN1_ILE (0x4003405C) /**< (MCAN1) Interrupt Line Enable Register */
|
||||
#define REG_MCAN1_GFC (0x40034080) /**< (MCAN1) Global Filter Configuration Register */
|
||||
#define REG_MCAN1_SIDFC (0x40034084) /**< (MCAN1) Standard ID Filter Configuration Register */
|
||||
#define REG_MCAN1_XIDFC (0x40034088) /**< (MCAN1) Extended ID Filter Configuration Register */
|
||||
#define REG_MCAN1_XIDAM (0x40034090) /**< (MCAN1) Extended ID AND Mask Register */
|
||||
#define REG_MCAN1_HPMS (0x40034094) /**< (MCAN1) High Priority Message Status Register */
|
||||
#define REG_MCAN1_NDAT1 (0x40034098) /**< (MCAN1) New Data 1 Register */
|
||||
#define REG_MCAN1_NDAT2 (0x4003409C) /**< (MCAN1) New Data 2 Register */
|
||||
#define REG_MCAN1_RXF0C (0x400340A0) /**< (MCAN1) Receive FIFO 0 Configuration Register */
|
||||
#define REG_MCAN1_RXF0S (0x400340A4) /**< (MCAN1) Receive FIFO 0 Status Register */
|
||||
#define REG_MCAN1_RXF0A (0x400340A8) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */
|
||||
#define REG_MCAN1_RXBC (0x400340AC) /**< (MCAN1) Receive Rx Buffer Configuration Register */
|
||||
#define REG_MCAN1_RXF1C (0x400340B0) /**< (MCAN1) Receive FIFO 1 Configuration Register */
|
||||
#define REG_MCAN1_RXF1S (0x400340B4) /**< (MCAN1) Receive FIFO 1 Status Register */
|
||||
#define REG_MCAN1_RXF1A (0x400340B8) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */
|
||||
#define REG_MCAN1_RXESC (0x400340BC) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */
|
||||
#define REG_MCAN1_TXBC (0x400340C0) /**< (MCAN1) Transmit Buffer Configuration Register */
|
||||
#define REG_MCAN1_TXFQS (0x400340C4) /**< (MCAN1) Transmit FIFO/Queue Status Register */
|
||||
#define REG_MCAN1_TXESC (0x400340C8) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */
|
||||
#define REG_MCAN1_TXBRP (0x400340CC) /**< (MCAN1) Transmit Buffer Request Pending Register */
|
||||
#define REG_MCAN1_TXBAR (0x400340D0) /**< (MCAN1) Transmit Buffer Add Request Register */
|
||||
#define REG_MCAN1_TXBCR (0x400340D4) /**< (MCAN1) Transmit Buffer Cancellation Request Register */
|
||||
#define REG_MCAN1_TXBTO (0x400340D8) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */
|
||||
#define REG_MCAN1_TXBCF (0x400340DC) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */
|
||||
#define REG_MCAN1_TXBTIE (0x400340E0) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */
|
||||
#define REG_MCAN1_TXBCIE (0x400340E4) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */
|
||||
#define REG_MCAN1_TXEFC (0x400340F0) /**< (MCAN1) Transmit Event FIFO Configuration Register */
|
||||
#define REG_MCAN1_TXEFS (0x400340F4) /**< (MCAN1) Transmit Event FIFO Status Register */
|
||||
#define REG_MCAN1_TXEFA (0x400340F8) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_MCAN1_CREL (*(__I uint32_t*)0x40034000U) /**< (MCAN1) Core Release Register */
|
||||
#define REG_MCAN1_ENDN (*(__I uint32_t*)0x40034004U) /**< (MCAN1) Endian Register */
|
||||
#define REG_MCAN1_CUST (*(__IO uint32_t*)0x40034008U) /**< (MCAN1) Customer Register */
|
||||
#define REG_MCAN1_DBTP (*(__IO uint32_t*)0x4003400CU) /**< (MCAN1) Data Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN1_TEST (*(__IO uint32_t*)0x40034010U) /**< (MCAN1) Test Register */
|
||||
#define REG_MCAN1_RWD (*(__IO uint32_t*)0x40034014U) /**< (MCAN1) RAM Watchdog Register */
|
||||
#define REG_MCAN1_CCCR (*(__IO uint32_t*)0x40034018U) /**< (MCAN1) CC Control Register */
|
||||
#define REG_MCAN1_NBTP (*(__IO uint32_t*)0x4003401CU) /**< (MCAN1) Nominal Bit Timing and Prescaler Register */
|
||||
#define REG_MCAN1_TSCC (*(__IO uint32_t*)0x40034020U) /**< (MCAN1) Timestamp Counter Configuration Register */
|
||||
#define REG_MCAN1_TSCV (*(__IO uint32_t*)0x40034024U) /**< (MCAN1) Timestamp Counter Value Register */
|
||||
#define REG_MCAN1_TOCC (*(__IO uint32_t*)0x40034028U) /**< (MCAN1) Timeout Counter Configuration Register */
|
||||
#define REG_MCAN1_TOCV (*(__IO uint32_t*)0x4003402CU) /**< (MCAN1) Timeout Counter Value Register */
|
||||
#define REG_MCAN1_ECR (*(__I uint32_t*)0x40034040U) /**< (MCAN1) Error Counter Register */
|
||||
#define REG_MCAN1_PSR (*(__I uint32_t*)0x40034044U) /**< (MCAN1) Protocol Status Register */
|
||||
#define REG_MCAN1_TDCR (*(__IO uint32_t*)0x40034048U) /**< (MCAN1) Transmit Delay Compensation Register */
|
||||
#define REG_MCAN1_IR (*(__IO uint32_t*)0x40034050U) /**< (MCAN1) Interrupt Register */
|
||||
#define REG_MCAN1_IE (*(__IO uint32_t*)0x40034054U) /**< (MCAN1) Interrupt Enable Register */
|
||||
#define REG_MCAN1_ILS (*(__IO uint32_t*)0x40034058U) /**< (MCAN1) Interrupt Line Select Register */
|
||||
#define REG_MCAN1_ILE (*(__IO uint32_t*)0x4003405CU) /**< (MCAN1) Interrupt Line Enable Register */
|
||||
#define REG_MCAN1_GFC (*(__IO uint32_t*)0x40034080U) /**< (MCAN1) Global Filter Configuration Register */
|
||||
#define REG_MCAN1_SIDFC (*(__IO uint32_t*)0x40034084U) /**< (MCAN1) Standard ID Filter Configuration Register */
|
||||
#define REG_MCAN1_XIDFC (*(__IO uint32_t*)0x40034088U) /**< (MCAN1) Extended ID Filter Configuration Register */
|
||||
#define REG_MCAN1_XIDAM (*(__IO uint32_t*)0x40034090U) /**< (MCAN1) Extended ID AND Mask Register */
|
||||
#define REG_MCAN1_HPMS (*(__I uint32_t*)0x40034094U) /**< (MCAN1) High Priority Message Status Register */
|
||||
#define REG_MCAN1_NDAT1 (*(__IO uint32_t*)0x40034098U) /**< (MCAN1) New Data 1 Register */
|
||||
#define REG_MCAN1_NDAT2 (*(__IO uint32_t*)0x4003409CU) /**< (MCAN1) New Data 2 Register */
|
||||
#define REG_MCAN1_RXF0C (*(__IO uint32_t*)0x400340A0U) /**< (MCAN1) Receive FIFO 0 Configuration Register */
|
||||
#define REG_MCAN1_RXF0S (*(__I uint32_t*)0x400340A4U) /**< (MCAN1) Receive FIFO 0 Status Register */
|
||||
#define REG_MCAN1_RXF0A (*(__IO uint32_t*)0x400340A8U) /**< (MCAN1) Receive FIFO 0 Acknowledge Register */
|
||||
#define REG_MCAN1_RXBC (*(__IO uint32_t*)0x400340ACU) /**< (MCAN1) Receive Rx Buffer Configuration Register */
|
||||
#define REG_MCAN1_RXF1C (*(__IO uint32_t*)0x400340B0U) /**< (MCAN1) Receive FIFO 1 Configuration Register */
|
||||
#define REG_MCAN1_RXF1S (*(__I uint32_t*)0x400340B4U) /**< (MCAN1) Receive FIFO 1 Status Register */
|
||||
#define REG_MCAN1_RXF1A (*(__IO uint32_t*)0x400340B8U) /**< (MCAN1) Receive FIFO 1 Acknowledge Register */
|
||||
#define REG_MCAN1_RXESC (*(__IO uint32_t*)0x400340BCU) /**< (MCAN1) Receive Buffer / FIFO Element Size Configuration Register */
|
||||
#define REG_MCAN1_TXBC (*(__IO uint32_t*)0x400340C0U) /**< (MCAN1) Transmit Buffer Configuration Register */
|
||||
#define REG_MCAN1_TXFQS (*(__I uint32_t*)0x400340C4U) /**< (MCAN1) Transmit FIFO/Queue Status Register */
|
||||
#define REG_MCAN1_TXESC (*(__IO uint32_t*)0x400340C8U) /**< (MCAN1) Transmit Buffer Element Size Configuration Register */
|
||||
#define REG_MCAN1_TXBRP (*(__I uint32_t*)0x400340CCU) /**< (MCAN1) Transmit Buffer Request Pending Register */
|
||||
#define REG_MCAN1_TXBAR (*(__IO uint32_t*)0x400340D0U) /**< (MCAN1) Transmit Buffer Add Request Register */
|
||||
#define REG_MCAN1_TXBCR (*(__IO uint32_t*)0x400340D4U) /**< (MCAN1) Transmit Buffer Cancellation Request Register */
|
||||
#define REG_MCAN1_TXBTO (*(__I uint32_t*)0x400340D8U) /**< (MCAN1) Transmit Buffer Transmission Occurred Register */
|
||||
#define REG_MCAN1_TXBCF (*(__I uint32_t*)0x400340DCU) /**< (MCAN1) Transmit Buffer Cancellation Finished Register */
|
||||
#define REG_MCAN1_TXBTIE (*(__IO uint32_t*)0x400340E0U) /**< (MCAN1) Transmit Buffer Transmission Interrupt Enable Register */
|
||||
#define REG_MCAN1_TXBCIE (*(__IO uint32_t*)0x400340E4U) /**< (MCAN1) Transmit Buffer Cancellation Finished Interrupt Enable Register */
|
||||
#define REG_MCAN1_TXEFC (*(__IO uint32_t*)0x400340F0U) /**< (MCAN1) Transmit Event FIFO Configuration Register */
|
||||
#define REG_MCAN1_TXEFS (*(__I uint32_t*)0x400340F4U) /**< (MCAN1) Transmit Event FIFO Status Register */
|
||||
#define REG_MCAN1_TXEFA (*(__IO uint32_t*)0x400340F8U) /**< (MCAN1) Transmit Event FIFO Acknowledge Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for MCAN1 peripheral ========== */
|
||||
#define MCAN1_INSTANCE_ID 37
|
||||
#define MCAN1_CLOCK_ID 37
|
||||
|
||||
#endif /* _SAME70_MCAN1_INSTANCE_ */
|
||||
160
lib/same70b/include/instance/pioa.h
Normal file
160
lib/same70b/include/instance/pioa.h
Normal file
|
|
@ -0,0 +1,160 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PIOA
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PIOA_INSTANCE_H_
|
||||
#define _SAME70_PIOA_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PIOA peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PIOA_PER (0x400E0E00) /**< (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR (0x400E0E04) /**< (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR (0x400E0E08) /**< (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER (0x400E0E10) /**< (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR (0x400E0E14) /**< (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR (0x400E0E18) /**< (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER (0x400E0E20) /**< (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR (0x400E0E24) /**< (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR (0x400E0E28) /**< (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR (0x400E0E30) /**< (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR (0x400E0E34) /**< (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR (0x400E0E38) /**< (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR (0x400E0E3C) /**< (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER (0x400E0E40) /**< (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR (0x400E0E44) /**< (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR (0x400E0E48) /**< (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR (0x400E0E4C) /**< (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER (0x400E0E50) /**< (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR (0x400E0E54) /**< (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR (0x400E0E58) /**< (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR (0x400E0E60) /**< (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER (0x400E0E64) /**< (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR (0x400E0E68) /**< (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOA_ABCDSR0 (0x400E0E70) /**< (PIOA) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOA_ABCDSR1 (0x400E0E74) /**< (PIOA) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOA_IFSCDR (0x400E0E80) /**< (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER (0x400E0E84) /**< (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR (0x400E0E88) /**< (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR (0x400E0E8C) /**< (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR (0x400E0E90) /**< (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER (0x400E0E94) /**< (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR (0x400E0E98) /**< (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER (0x400E0EA0) /**< (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR (0x400E0EA4) /**< (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR (0x400E0EA8) /**< (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER (0x400E0EB0) /**< (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR (0x400E0EB4) /**< (PIOA) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOA_AIMMR (0x400E0EB8) /**< (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR (0x400E0EC0) /**< (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR (0x400E0EC4) /**< (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR (0x400E0EC8) /**< (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR (0x400E0ED0) /**< (PIOA) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOA_REHLSR (0x400E0ED4) /**< (PIOA) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOA_FRLHSR (0x400E0ED8) /**< (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR (0x400E0EE0) /**< (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR (0x400E0EE4) /**< (PIOA) Write Protection Mode Register */
|
||||
#define REG_PIOA_WPSR (0x400E0EE8) /**< (PIOA) Write Protection Status Register */
|
||||
#define REG_PIOA_SCHMITT (0x400E0F00) /**< (PIOA) Schmitt Trigger Register */
|
||||
#define REG_PIOA_DRIVER (0x400E0F18) /**< (PIOA) I/O Drive Register */
|
||||
#define REG_PIOA_PCMR (0x400E0F50) /**< (PIOA) Parallel Capture Mode Register */
|
||||
#define REG_PIOA_PCIER (0x400E0F54) /**< (PIOA) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOA_PCIDR (0x400E0F58) /**< (PIOA) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOA_PCIMR (0x400E0F5C) /**< (PIOA) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOA_PCISR (0x400E0F60) /**< (PIOA) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOA_PCRHR (0x400E0F64) /**< (PIOA) Parallel Capture Reception Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PIOA_PER (*(__O uint32_t*)0x400E0E00U) /**< (PIOA) PIO Enable Register */
|
||||
#define REG_PIOA_PDR (*(__O uint32_t*)0x400E0E04U) /**< (PIOA) PIO Disable Register */
|
||||
#define REG_PIOA_PSR (*(__I uint32_t*)0x400E0E08U) /**< (PIOA) PIO Status Register */
|
||||
#define REG_PIOA_OER (*(__O uint32_t*)0x400E0E10U) /**< (PIOA) Output Enable Register */
|
||||
#define REG_PIOA_ODR (*(__O uint32_t*)0x400E0E14U) /**< (PIOA) Output Disable Register */
|
||||
#define REG_PIOA_OSR (*(__I uint32_t*)0x400E0E18U) /**< (PIOA) Output Status Register */
|
||||
#define REG_PIOA_IFER (*(__O uint32_t*)0x400E0E20U) /**< (PIOA) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOA_IFDR (*(__O uint32_t*)0x400E0E24U) /**< (PIOA) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOA_IFSR (*(__I uint32_t*)0x400E0E28U) /**< (PIOA) Glitch Input Filter Status Register */
|
||||
#define REG_PIOA_SODR (*(__O uint32_t*)0x400E0E30U) /**< (PIOA) Set Output Data Register */
|
||||
#define REG_PIOA_CODR (*(__O uint32_t*)0x400E0E34U) /**< (PIOA) Clear Output Data Register */
|
||||
#define REG_PIOA_ODSR (*(__IO uint32_t*)0x400E0E38U) /**< (PIOA) Output Data Status Register */
|
||||
#define REG_PIOA_PDSR (*(__I uint32_t*)0x400E0E3CU) /**< (PIOA) Pin Data Status Register */
|
||||
#define REG_PIOA_IER (*(__O uint32_t*)0x400E0E40U) /**< (PIOA) Interrupt Enable Register */
|
||||
#define REG_PIOA_IDR (*(__O uint32_t*)0x400E0E44U) /**< (PIOA) Interrupt Disable Register */
|
||||
#define REG_PIOA_IMR (*(__I uint32_t*)0x400E0E48U) /**< (PIOA) Interrupt Mask Register */
|
||||
#define REG_PIOA_ISR (*(__I uint32_t*)0x400E0E4CU) /**< (PIOA) Interrupt Status Register */
|
||||
#define REG_PIOA_MDER (*(__O uint32_t*)0x400E0E50U) /**< (PIOA) Multi-driver Enable Register */
|
||||
#define REG_PIOA_MDDR (*(__O uint32_t*)0x400E0E54U) /**< (PIOA) Multi-driver Disable Register */
|
||||
#define REG_PIOA_MDSR (*(__I uint32_t*)0x400E0E58U) /**< (PIOA) Multi-driver Status Register */
|
||||
#define REG_PIOA_PUDR (*(__O uint32_t*)0x400E0E60U) /**< (PIOA) Pull-up Disable Register */
|
||||
#define REG_PIOA_PUER (*(__O uint32_t*)0x400E0E64U) /**< (PIOA) Pull-up Enable Register */
|
||||
#define REG_PIOA_PUSR (*(__I uint32_t*)0x400E0E68U) /**< (PIOA) Pad Pull-up Status Register */
|
||||
#define REG_PIOA_ABCDSR (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOA_ABCDSR0 (*(__IO uint32_t*)0x400E0E70U) /**< (PIOA) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOA_ABCDSR1 (*(__IO uint32_t*)0x400E0E74U) /**< (PIOA) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOA_IFSCDR (*(__O uint32_t*)0x400E0E80U) /**< (PIOA) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOA_IFSCER (*(__O uint32_t*)0x400E0E84U) /**< (PIOA) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOA_IFSCSR (*(__I uint32_t*)0x400E0E88U) /**< (PIOA) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOA_SCDR (*(__IO uint32_t*)0x400E0E8CU) /**< (PIOA) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOA_PPDDR (*(__O uint32_t*)0x400E0E90U) /**< (PIOA) Pad Pull-down Disable Register */
|
||||
#define REG_PIOA_PPDER (*(__O uint32_t*)0x400E0E94U) /**< (PIOA) Pad Pull-down Enable Register */
|
||||
#define REG_PIOA_PPDSR (*(__I uint32_t*)0x400E0E98U) /**< (PIOA) Pad Pull-down Status Register */
|
||||
#define REG_PIOA_OWER (*(__O uint32_t*)0x400E0EA0U) /**< (PIOA) Output Write Enable */
|
||||
#define REG_PIOA_OWDR (*(__O uint32_t*)0x400E0EA4U) /**< (PIOA) Output Write Disable */
|
||||
#define REG_PIOA_OWSR (*(__I uint32_t*)0x400E0EA8U) /**< (PIOA) Output Write Status Register */
|
||||
#define REG_PIOA_AIMER (*(__O uint32_t*)0x400E0EB0U) /**< (PIOA) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOA_AIMDR (*(__O uint32_t*)0x400E0EB4U) /**< (PIOA) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOA_AIMMR (*(__I uint32_t*)0x400E0EB8U) /**< (PIOA) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOA_ESR (*(__O uint32_t*)0x400E0EC0U) /**< (PIOA) Edge Select Register */
|
||||
#define REG_PIOA_LSR (*(__O uint32_t*)0x400E0EC4U) /**< (PIOA) Level Select Register */
|
||||
#define REG_PIOA_ELSR (*(__I uint32_t*)0x400E0EC8U) /**< (PIOA) Edge/Level Status Register */
|
||||
#define REG_PIOA_FELLSR (*(__O uint32_t*)0x400E0ED0U) /**< (PIOA) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOA_REHLSR (*(__O uint32_t*)0x400E0ED4U) /**< (PIOA) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOA_FRLHSR (*(__I uint32_t*)0x400E0ED8U) /**< (PIOA) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOA_LOCKSR (*(__I uint32_t*)0x400E0EE0U) /**< (PIOA) Lock Status */
|
||||
#define REG_PIOA_WPMR (*(__IO uint32_t*)0x400E0EE4U) /**< (PIOA) Write Protection Mode Register */
|
||||
#define REG_PIOA_WPSR (*(__I uint32_t*)0x400E0EE8U) /**< (PIOA) Write Protection Status Register */
|
||||
#define REG_PIOA_SCHMITT (*(__IO uint32_t*)0x400E0F00U) /**< (PIOA) Schmitt Trigger Register */
|
||||
#define REG_PIOA_DRIVER (*(__IO uint32_t*)0x400E0F18U) /**< (PIOA) I/O Drive Register */
|
||||
#define REG_PIOA_PCMR (*(__IO uint32_t*)0x400E0F50U) /**< (PIOA) Parallel Capture Mode Register */
|
||||
#define REG_PIOA_PCIER (*(__O uint32_t*)0x400E0F54U) /**< (PIOA) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOA_PCIDR (*(__O uint32_t*)0x400E0F58U) /**< (PIOA) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOA_PCIMR (*(__I uint32_t*)0x400E0F5CU) /**< (PIOA) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOA_PCISR (*(__I uint32_t*)0x400E0F60U) /**< (PIOA) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOA_PCRHR (*(__I uint32_t*)0x400E0F64U) /**< (PIOA) Parallel Capture Reception Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PIOA peripheral ========== */
|
||||
#define PIOA_DMAC_ID_RX 34
|
||||
#define PIOA_INSTANCE_ID 10
|
||||
#define PIOA_CLOCK_ID 10
|
||||
|
||||
#endif /* _SAME70_PIOA_INSTANCE_ */
|
||||
159
lib/same70b/include/instance/piob.h
Normal file
159
lib/same70b/include/instance/piob.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PIOB
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PIOB_INSTANCE_H_
|
||||
#define _SAME70_PIOB_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PIOB peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PIOB_PER (0x400E1000) /**< (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR (0x400E1004) /**< (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR (0x400E1008) /**< (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER (0x400E1010) /**< (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR (0x400E1014) /**< (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR (0x400E1018) /**< (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER (0x400E1020) /**< (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR (0x400E1024) /**< (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR (0x400E1028) /**< (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR (0x400E1030) /**< (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR (0x400E1034) /**< (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR (0x400E1038) /**< (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR (0x400E103C) /**< (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER (0x400E1040) /**< (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR (0x400E1044) /**< (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR (0x400E1048) /**< (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR (0x400E104C) /**< (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER (0x400E1050) /**< (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR (0x400E1054) /**< (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR (0x400E1058) /**< (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR (0x400E1060) /**< (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER (0x400E1064) /**< (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR (0x400E1068) /**< (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOB_ABCDSR0 (0x400E1070) /**< (PIOB) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOB_ABCDSR1 (0x400E1074) /**< (PIOB) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOB_IFSCDR (0x400E1080) /**< (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER (0x400E1084) /**< (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR (0x400E1088) /**< (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR (0x400E108C) /**< (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR (0x400E1090) /**< (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER (0x400E1094) /**< (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR (0x400E1098) /**< (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER (0x400E10A0) /**< (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR (0x400E10A4) /**< (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR (0x400E10A8) /**< (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER (0x400E10B0) /**< (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR (0x400E10B4) /**< (PIOB) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOB_AIMMR (0x400E10B8) /**< (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR (0x400E10C0) /**< (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR (0x400E10C4) /**< (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR (0x400E10C8) /**< (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR (0x400E10D0) /**< (PIOB) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOB_REHLSR (0x400E10D4) /**< (PIOB) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOB_FRLHSR (0x400E10D8) /**< (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR (0x400E10E0) /**< (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR (0x400E10E4) /**< (PIOB) Write Protection Mode Register */
|
||||
#define REG_PIOB_WPSR (0x400E10E8) /**< (PIOB) Write Protection Status Register */
|
||||
#define REG_PIOB_SCHMITT (0x400E1100) /**< (PIOB) Schmitt Trigger Register */
|
||||
#define REG_PIOB_DRIVER (0x400E1118) /**< (PIOB) I/O Drive Register */
|
||||
#define REG_PIOB_PCMR (0x400E1150) /**< (PIOB) Parallel Capture Mode Register */
|
||||
#define REG_PIOB_PCIER (0x400E1154) /**< (PIOB) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOB_PCIDR (0x400E1158) /**< (PIOB) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOB_PCIMR (0x400E115C) /**< (PIOB) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOB_PCISR (0x400E1160) /**< (PIOB) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOB_PCRHR (0x400E1164) /**< (PIOB) Parallel Capture Reception Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PIOB_PER (*(__O uint32_t*)0x400E1000U) /**< (PIOB) PIO Enable Register */
|
||||
#define REG_PIOB_PDR (*(__O uint32_t*)0x400E1004U) /**< (PIOB) PIO Disable Register */
|
||||
#define REG_PIOB_PSR (*(__I uint32_t*)0x400E1008U) /**< (PIOB) PIO Status Register */
|
||||
#define REG_PIOB_OER (*(__O uint32_t*)0x400E1010U) /**< (PIOB) Output Enable Register */
|
||||
#define REG_PIOB_ODR (*(__O uint32_t*)0x400E1014U) /**< (PIOB) Output Disable Register */
|
||||
#define REG_PIOB_OSR (*(__I uint32_t*)0x400E1018U) /**< (PIOB) Output Status Register */
|
||||
#define REG_PIOB_IFER (*(__O uint32_t*)0x400E1020U) /**< (PIOB) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOB_IFDR (*(__O uint32_t*)0x400E1024U) /**< (PIOB) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOB_IFSR (*(__I uint32_t*)0x400E1028U) /**< (PIOB) Glitch Input Filter Status Register */
|
||||
#define REG_PIOB_SODR (*(__O uint32_t*)0x400E1030U) /**< (PIOB) Set Output Data Register */
|
||||
#define REG_PIOB_CODR (*(__O uint32_t*)0x400E1034U) /**< (PIOB) Clear Output Data Register */
|
||||
#define REG_PIOB_ODSR (*(__IO uint32_t*)0x400E1038U) /**< (PIOB) Output Data Status Register */
|
||||
#define REG_PIOB_PDSR (*(__I uint32_t*)0x400E103CU) /**< (PIOB) Pin Data Status Register */
|
||||
#define REG_PIOB_IER (*(__O uint32_t*)0x400E1040U) /**< (PIOB) Interrupt Enable Register */
|
||||
#define REG_PIOB_IDR (*(__O uint32_t*)0x400E1044U) /**< (PIOB) Interrupt Disable Register */
|
||||
#define REG_PIOB_IMR (*(__I uint32_t*)0x400E1048U) /**< (PIOB) Interrupt Mask Register */
|
||||
#define REG_PIOB_ISR (*(__I uint32_t*)0x400E104CU) /**< (PIOB) Interrupt Status Register */
|
||||
#define REG_PIOB_MDER (*(__O uint32_t*)0x400E1050U) /**< (PIOB) Multi-driver Enable Register */
|
||||
#define REG_PIOB_MDDR (*(__O uint32_t*)0x400E1054U) /**< (PIOB) Multi-driver Disable Register */
|
||||
#define REG_PIOB_MDSR (*(__I uint32_t*)0x400E1058U) /**< (PIOB) Multi-driver Status Register */
|
||||
#define REG_PIOB_PUDR (*(__O uint32_t*)0x400E1060U) /**< (PIOB) Pull-up Disable Register */
|
||||
#define REG_PIOB_PUER (*(__O uint32_t*)0x400E1064U) /**< (PIOB) Pull-up Enable Register */
|
||||
#define REG_PIOB_PUSR (*(__I uint32_t*)0x400E1068U) /**< (PIOB) Pad Pull-up Status Register */
|
||||
#define REG_PIOB_ABCDSR (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOB_ABCDSR0 (*(__IO uint32_t*)0x400E1070U) /**< (PIOB) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOB_ABCDSR1 (*(__IO uint32_t*)0x400E1074U) /**< (PIOB) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOB_IFSCDR (*(__O uint32_t*)0x400E1080U) /**< (PIOB) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOB_IFSCER (*(__O uint32_t*)0x400E1084U) /**< (PIOB) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOB_IFSCSR (*(__I uint32_t*)0x400E1088U) /**< (PIOB) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOB_SCDR (*(__IO uint32_t*)0x400E108CU) /**< (PIOB) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOB_PPDDR (*(__O uint32_t*)0x400E1090U) /**< (PIOB) Pad Pull-down Disable Register */
|
||||
#define REG_PIOB_PPDER (*(__O uint32_t*)0x400E1094U) /**< (PIOB) Pad Pull-down Enable Register */
|
||||
#define REG_PIOB_PPDSR (*(__I uint32_t*)0x400E1098U) /**< (PIOB) Pad Pull-down Status Register */
|
||||
#define REG_PIOB_OWER (*(__O uint32_t*)0x400E10A0U) /**< (PIOB) Output Write Enable */
|
||||
#define REG_PIOB_OWDR (*(__O uint32_t*)0x400E10A4U) /**< (PIOB) Output Write Disable */
|
||||
#define REG_PIOB_OWSR (*(__I uint32_t*)0x400E10A8U) /**< (PIOB) Output Write Status Register */
|
||||
#define REG_PIOB_AIMER (*(__O uint32_t*)0x400E10B0U) /**< (PIOB) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOB_AIMDR (*(__O uint32_t*)0x400E10B4U) /**< (PIOB) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOB_AIMMR (*(__I uint32_t*)0x400E10B8U) /**< (PIOB) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOB_ESR (*(__O uint32_t*)0x400E10C0U) /**< (PIOB) Edge Select Register */
|
||||
#define REG_PIOB_LSR (*(__O uint32_t*)0x400E10C4U) /**< (PIOB) Level Select Register */
|
||||
#define REG_PIOB_ELSR (*(__I uint32_t*)0x400E10C8U) /**< (PIOB) Edge/Level Status Register */
|
||||
#define REG_PIOB_FELLSR (*(__O uint32_t*)0x400E10D0U) /**< (PIOB) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOB_REHLSR (*(__O uint32_t*)0x400E10D4U) /**< (PIOB) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOB_FRLHSR (*(__I uint32_t*)0x400E10D8U) /**< (PIOB) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOB_LOCKSR (*(__I uint32_t*)0x400E10E0U) /**< (PIOB) Lock Status */
|
||||
#define REG_PIOB_WPMR (*(__IO uint32_t*)0x400E10E4U) /**< (PIOB) Write Protection Mode Register */
|
||||
#define REG_PIOB_WPSR (*(__I uint32_t*)0x400E10E8U) /**< (PIOB) Write Protection Status Register */
|
||||
#define REG_PIOB_SCHMITT (*(__IO uint32_t*)0x400E1100U) /**< (PIOB) Schmitt Trigger Register */
|
||||
#define REG_PIOB_DRIVER (*(__IO uint32_t*)0x400E1118U) /**< (PIOB) I/O Drive Register */
|
||||
#define REG_PIOB_PCMR (*(__IO uint32_t*)0x400E1150U) /**< (PIOB) Parallel Capture Mode Register */
|
||||
#define REG_PIOB_PCIER (*(__O uint32_t*)0x400E1154U) /**< (PIOB) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOB_PCIDR (*(__O uint32_t*)0x400E1158U) /**< (PIOB) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOB_PCIMR (*(__I uint32_t*)0x400E115CU) /**< (PIOB) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOB_PCISR (*(__I uint32_t*)0x400E1160U) /**< (PIOB) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOB_PCRHR (*(__I uint32_t*)0x400E1164U) /**< (PIOB) Parallel Capture Reception Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PIOB peripheral ========== */
|
||||
#define PIOB_INSTANCE_ID 11
|
||||
#define PIOB_CLOCK_ID 11
|
||||
|
||||
#endif /* _SAME70_PIOB_INSTANCE_ */
|
||||
159
lib/same70b/include/instance/pioc.h
Normal file
159
lib/same70b/include/instance/pioc.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PIOC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PIOC_INSTANCE_H_
|
||||
#define _SAME70_PIOC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PIOC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PIOC_PER (0x400E1200) /**< (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR (0x400E1204) /**< (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR (0x400E1208) /**< (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER (0x400E1210) /**< (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR (0x400E1214) /**< (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR (0x400E1218) /**< (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER (0x400E1220) /**< (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR (0x400E1224) /**< (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR (0x400E1228) /**< (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR (0x400E1230) /**< (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR (0x400E1234) /**< (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR (0x400E1238) /**< (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR (0x400E123C) /**< (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER (0x400E1240) /**< (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR (0x400E1244) /**< (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR (0x400E1248) /**< (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR (0x400E124C) /**< (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER (0x400E1250) /**< (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR (0x400E1254) /**< (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR (0x400E1258) /**< (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR (0x400E1260) /**< (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER (0x400E1264) /**< (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR (0x400E1268) /**< (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOC_ABCDSR0 (0x400E1270) /**< (PIOC) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOC_ABCDSR1 (0x400E1274) /**< (PIOC) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOC_IFSCDR (0x400E1280) /**< (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER (0x400E1284) /**< (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR (0x400E1288) /**< (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR (0x400E128C) /**< (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR (0x400E1290) /**< (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER (0x400E1294) /**< (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR (0x400E1298) /**< (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER (0x400E12A0) /**< (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR (0x400E12A4) /**< (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR (0x400E12A8) /**< (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER (0x400E12B0) /**< (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR (0x400E12B4) /**< (PIOC) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOC_AIMMR (0x400E12B8) /**< (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR (0x400E12C0) /**< (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR (0x400E12C4) /**< (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR (0x400E12C8) /**< (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR (0x400E12D0) /**< (PIOC) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOC_REHLSR (0x400E12D4) /**< (PIOC) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOC_FRLHSR (0x400E12D8) /**< (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR (0x400E12E0) /**< (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR (0x400E12E4) /**< (PIOC) Write Protection Mode Register */
|
||||
#define REG_PIOC_WPSR (0x400E12E8) /**< (PIOC) Write Protection Status Register */
|
||||
#define REG_PIOC_SCHMITT (0x400E1300) /**< (PIOC) Schmitt Trigger Register */
|
||||
#define REG_PIOC_DRIVER (0x400E1318) /**< (PIOC) I/O Drive Register */
|
||||
#define REG_PIOC_PCMR (0x400E1350) /**< (PIOC) Parallel Capture Mode Register */
|
||||
#define REG_PIOC_PCIER (0x400E1354) /**< (PIOC) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOC_PCIDR (0x400E1358) /**< (PIOC) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOC_PCIMR (0x400E135C) /**< (PIOC) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOC_PCISR (0x400E1360) /**< (PIOC) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOC_PCRHR (0x400E1364) /**< (PIOC) Parallel Capture Reception Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PIOC_PER (*(__O uint32_t*)0x400E1200U) /**< (PIOC) PIO Enable Register */
|
||||
#define REG_PIOC_PDR (*(__O uint32_t*)0x400E1204U) /**< (PIOC) PIO Disable Register */
|
||||
#define REG_PIOC_PSR (*(__I uint32_t*)0x400E1208U) /**< (PIOC) PIO Status Register */
|
||||
#define REG_PIOC_OER (*(__O uint32_t*)0x400E1210U) /**< (PIOC) Output Enable Register */
|
||||
#define REG_PIOC_ODR (*(__O uint32_t*)0x400E1214U) /**< (PIOC) Output Disable Register */
|
||||
#define REG_PIOC_OSR (*(__I uint32_t*)0x400E1218U) /**< (PIOC) Output Status Register */
|
||||
#define REG_PIOC_IFER (*(__O uint32_t*)0x400E1220U) /**< (PIOC) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOC_IFDR (*(__O uint32_t*)0x400E1224U) /**< (PIOC) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOC_IFSR (*(__I uint32_t*)0x400E1228U) /**< (PIOC) Glitch Input Filter Status Register */
|
||||
#define REG_PIOC_SODR (*(__O uint32_t*)0x400E1230U) /**< (PIOC) Set Output Data Register */
|
||||
#define REG_PIOC_CODR (*(__O uint32_t*)0x400E1234U) /**< (PIOC) Clear Output Data Register */
|
||||
#define REG_PIOC_ODSR (*(__IO uint32_t*)0x400E1238U) /**< (PIOC) Output Data Status Register */
|
||||
#define REG_PIOC_PDSR (*(__I uint32_t*)0x400E123CU) /**< (PIOC) Pin Data Status Register */
|
||||
#define REG_PIOC_IER (*(__O uint32_t*)0x400E1240U) /**< (PIOC) Interrupt Enable Register */
|
||||
#define REG_PIOC_IDR (*(__O uint32_t*)0x400E1244U) /**< (PIOC) Interrupt Disable Register */
|
||||
#define REG_PIOC_IMR (*(__I uint32_t*)0x400E1248U) /**< (PIOC) Interrupt Mask Register */
|
||||
#define REG_PIOC_ISR (*(__I uint32_t*)0x400E124CU) /**< (PIOC) Interrupt Status Register */
|
||||
#define REG_PIOC_MDER (*(__O uint32_t*)0x400E1250U) /**< (PIOC) Multi-driver Enable Register */
|
||||
#define REG_PIOC_MDDR (*(__O uint32_t*)0x400E1254U) /**< (PIOC) Multi-driver Disable Register */
|
||||
#define REG_PIOC_MDSR (*(__I uint32_t*)0x400E1258U) /**< (PIOC) Multi-driver Status Register */
|
||||
#define REG_PIOC_PUDR (*(__O uint32_t*)0x400E1260U) /**< (PIOC) Pull-up Disable Register */
|
||||
#define REG_PIOC_PUER (*(__O uint32_t*)0x400E1264U) /**< (PIOC) Pull-up Enable Register */
|
||||
#define REG_PIOC_PUSR (*(__I uint32_t*)0x400E1268U) /**< (PIOC) Pad Pull-up Status Register */
|
||||
#define REG_PIOC_ABCDSR (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOC_ABCDSR0 (*(__IO uint32_t*)0x400E1270U) /**< (PIOC) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOC_ABCDSR1 (*(__IO uint32_t*)0x400E1274U) /**< (PIOC) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOC_IFSCDR (*(__O uint32_t*)0x400E1280U) /**< (PIOC) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOC_IFSCER (*(__O uint32_t*)0x400E1284U) /**< (PIOC) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOC_IFSCSR (*(__I uint32_t*)0x400E1288U) /**< (PIOC) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOC_SCDR (*(__IO uint32_t*)0x400E128CU) /**< (PIOC) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOC_PPDDR (*(__O uint32_t*)0x400E1290U) /**< (PIOC) Pad Pull-down Disable Register */
|
||||
#define REG_PIOC_PPDER (*(__O uint32_t*)0x400E1294U) /**< (PIOC) Pad Pull-down Enable Register */
|
||||
#define REG_PIOC_PPDSR (*(__I uint32_t*)0x400E1298U) /**< (PIOC) Pad Pull-down Status Register */
|
||||
#define REG_PIOC_OWER (*(__O uint32_t*)0x400E12A0U) /**< (PIOC) Output Write Enable */
|
||||
#define REG_PIOC_OWDR (*(__O uint32_t*)0x400E12A4U) /**< (PIOC) Output Write Disable */
|
||||
#define REG_PIOC_OWSR (*(__I uint32_t*)0x400E12A8U) /**< (PIOC) Output Write Status Register */
|
||||
#define REG_PIOC_AIMER (*(__O uint32_t*)0x400E12B0U) /**< (PIOC) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOC_AIMDR (*(__O uint32_t*)0x400E12B4U) /**< (PIOC) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOC_AIMMR (*(__I uint32_t*)0x400E12B8U) /**< (PIOC) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOC_ESR (*(__O uint32_t*)0x400E12C0U) /**< (PIOC) Edge Select Register */
|
||||
#define REG_PIOC_LSR (*(__O uint32_t*)0x400E12C4U) /**< (PIOC) Level Select Register */
|
||||
#define REG_PIOC_ELSR (*(__I uint32_t*)0x400E12C8U) /**< (PIOC) Edge/Level Status Register */
|
||||
#define REG_PIOC_FELLSR (*(__O uint32_t*)0x400E12D0U) /**< (PIOC) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOC_REHLSR (*(__O uint32_t*)0x400E12D4U) /**< (PIOC) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOC_FRLHSR (*(__I uint32_t*)0x400E12D8U) /**< (PIOC) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOC_LOCKSR (*(__I uint32_t*)0x400E12E0U) /**< (PIOC) Lock Status */
|
||||
#define REG_PIOC_WPMR (*(__IO uint32_t*)0x400E12E4U) /**< (PIOC) Write Protection Mode Register */
|
||||
#define REG_PIOC_WPSR (*(__I uint32_t*)0x400E12E8U) /**< (PIOC) Write Protection Status Register */
|
||||
#define REG_PIOC_SCHMITT (*(__IO uint32_t*)0x400E1300U) /**< (PIOC) Schmitt Trigger Register */
|
||||
#define REG_PIOC_DRIVER (*(__IO uint32_t*)0x400E1318U) /**< (PIOC) I/O Drive Register */
|
||||
#define REG_PIOC_PCMR (*(__IO uint32_t*)0x400E1350U) /**< (PIOC) Parallel Capture Mode Register */
|
||||
#define REG_PIOC_PCIER (*(__O uint32_t*)0x400E1354U) /**< (PIOC) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOC_PCIDR (*(__O uint32_t*)0x400E1358U) /**< (PIOC) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOC_PCIMR (*(__I uint32_t*)0x400E135CU) /**< (PIOC) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOC_PCISR (*(__I uint32_t*)0x400E1360U) /**< (PIOC) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOC_PCRHR (*(__I uint32_t*)0x400E1364U) /**< (PIOC) Parallel Capture Reception Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PIOC peripheral ========== */
|
||||
#define PIOC_INSTANCE_ID 12
|
||||
#define PIOC_CLOCK_ID 12
|
||||
|
||||
#endif /* _SAME70_PIOC_INSTANCE_ */
|
||||
159
lib/same70b/include/instance/piod.h
Normal file
159
lib/same70b/include/instance/piod.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PIOD
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PIOD_INSTANCE_H_
|
||||
#define _SAME70_PIOD_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PIOD peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PIOD_PER (0x400E1400) /**< (PIOD) PIO Enable Register */
|
||||
#define REG_PIOD_PDR (0x400E1404) /**< (PIOD) PIO Disable Register */
|
||||
#define REG_PIOD_PSR (0x400E1408) /**< (PIOD) PIO Status Register */
|
||||
#define REG_PIOD_OER (0x400E1410) /**< (PIOD) Output Enable Register */
|
||||
#define REG_PIOD_ODR (0x400E1414) /**< (PIOD) Output Disable Register */
|
||||
#define REG_PIOD_OSR (0x400E1418) /**< (PIOD) Output Status Register */
|
||||
#define REG_PIOD_IFER (0x400E1420) /**< (PIOD) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOD_IFDR (0x400E1424) /**< (PIOD) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOD_IFSR (0x400E1428) /**< (PIOD) Glitch Input Filter Status Register */
|
||||
#define REG_PIOD_SODR (0x400E1430) /**< (PIOD) Set Output Data Register */
|
||||
#define REG_PIOD_CODR (0x400E1434) /**< (PIOD) Clear Output Data Register */
|
||||
#define REG_PIOD_ODSR (0x400E1438) /**< (PIOD) Output Data Status Register */
|
||||
#define REG_PIOD_PDSR (0x400E143C) /**< (PIOD) Pin Data Status Register */
|
||||
#define REG_PIOD_IER (0x400E1440) /**< (PIOD) Interrupt Enable Register */
|
||||
#define REG_PIOD_IDR (0x400E1444) /**< (PIOD) Interrupt Disable Register */
|
||||
#define REG_PIOD_IMR (0x400E1448) /**< (PIOD) Interrupt Mask Register */
|
||||
#define REG_PIOD_ISR (0x400E144C) /**< (PIOD) Interrupt Status Register */
|
||||
#define REG_PIOD_MDER (0x400E1450) /**< (PIOD) Multi-driver Enable Register */
|
||||
#define REG_PIOD_MDDR (0x400E1454) /**< (PIOD) Multi-driver Disable Register */
|
||||
#define REG_PIOD_MDSR (0x400E1458) /**< (PIOD) Multi-driver Status Register */
|
||||
#define REG_PIOD_PUDR (0x400E1460) /**< (PIOD) Pull-up Disable Register */
|
||||
#define REG_PIOD_PUER (0x400E1464) /**< (PIOD) Pull-up Enable Register */
|
||||
#define REG_PIOD_PUSR (0x400E1468) /**< (PIOD) Pad Pull-up Status Register */
|
||||
#define REG_PIOD_ABCDSR (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOD_ABCDSR0 (0x400E1470) /**< (PIOD) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOD_ABCDSR1 (0x400E1474) /**< (PIOD) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOD_IFSCDR (0x400E1480) /**< (PIOD) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOD_IFSCER (0x400E1484) /**< (PIOD) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOD_IFSCSR (0x400E1488) /**< (PIOD) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOD_SCDR (0x400E148C) /**< (PIOD) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOD_PPDDR (0x400E1490) /**< (PIOD) Pad Pull-down Disable Register */
|
||||
#define REG_PIOD_PPDER (0x400E1494) /**< (PIOD) Pad Pull-down Enable Register */
|
||||
#define REG_PIOD_PPDSR (0x400E1498) /**< (PIOD) Pad Pull-down Status Register */
|
||||
#define REG_PIOD_OWER (0x400E14A0) /**< (PIOD) Output Write Enable */
|
||||
#define REG_PIOD_OWDR (0x400E14A4) /**< (PIOD) Output Write Disable */
|
||||
#define REG_PIOD_OWSR (0x400E14A8) /**< (PIOD) Output Write Status Register */
|
||||
#define REG_PIOD_AIMER (0x400E14B0) /**< (PIOD) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOD_AIMDR (0x400E14B4) /**< (PIOD) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOD_AIMMR (0x400E14B8) /**< (PIOD) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOD_ESR (0x400E14C0) /**< (PIOD) Edge Select Register */
|
||||
#define REG_PIOD_LSR (0x400E14C4) /**< (PIOD) Level Select Register */
|
||||
#define REG_PIOD_ELSR (0x400E14C8) /**< (PIOD) Edge/Level Status Register */
|
||||
#define REG_PIOD_FELLSR (0x400E14D0) /**< (PIOD) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOD_REHLSR (0x400E14D4) /**< (PIOD) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOD_FRLHSR (0x400E14D8) /**< (PIOD) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOD_LOCKSR (0x400E14E0) /**< (PIOD) Lock Status */
|
||||
#define REG_PIOD_WPMR (0x400E14E4) /**< (PIOD) Write Protection Mode Register */
|
||||
#define REG_PIOD_WPSR (0x400E14E8) /**< (PIOD) Write Protection Status Register */
|
||||
#define REG_PIOD_SCHMITT (0x400E1500) /**< (PIOD) Schmitt Trigger Register */
|
||||
#define REG_PIOD_DRIVER (0x400E1518) /**< (PIOD) I/O Drive Register */
|
||||
#define REG_PIOD_PCMR (0x400E1550) /**< (PIOD) Parallel Capture Mode Register */
|
||||
#define REG_PIOD_PCIER (0x400E1554) /**< (PIOD) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOD_PCIDR (0x400E1558) /**< (PIOD) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOD_PCIMR (0x400E155C) /**< (PIOD) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOD_PCISR (0x400E1560) /**< (PIOD) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOD_PCRHR (0x400E1564) /**< (PIOD) Parallel Capture Reception Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PIOD_PER (*(__O uint32_t*)0x400E1400U) /**< (PIOD) PIO Enable Register */
|
||||
#define REG_PIOD_PDR (*(__O uint32_t*)0x400E1404U) /**< (PIOD) PIO Disable Register */
|
||||
#define REG_PIOD_PSR (*(__I uint32_t*)0x400E1408U) /**< (PIOD) PIO Status Register */
|
||||
#define REG_PIOD_OER (*(__O uint32_t*)0x400E1410U) /**< (PIOD) Output Enable Register */
|
||||
#define REG_PIOD_ODR (*(__O uint32_t*)0x400E1414U) /**< (PIOD) Output Disable Register */
|
||||
#define REG_PIOD_OSR (*(__I uint32_t*)0x400E1418U) /**< (PIOD) Output Status Register */
|
||||
#define REG_PIOD_IFER (*(__O uint32_t*)0x400E1420U) /**< (PIOD) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOD_IFDR (*(__O uint32_t*)0x400E1424U) /**< (PIOD) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOD_IFSR (*(__I uint32_t*)0x400E1428U) /**< (PIOD) Glitch Input Filter Status Register */
|
||||
#define REG_PIOD_SODR (*(__O uint32_t*)0x400E1430U) /**< (PIOD) Set Output Data Register */
|
||||
#define REG_PIOD_CODR (*(__O uint32_t*)0x400E1434U) /**< (PIOD) Clear Output Data Register */
|
||||
#define REG_PIOD_ODSR (*(__IO uint32_t*)0x400E1438U) /**< (PIOD) Output Data Status Register */
|
||||
#define REG_PIOD_PDSR (*(__I uint32_t*)0x400E143CU) /**< (PIOD) Pin Data Status Register */
|
||||
#define REG_PIOD_IER (*(__O uint32_t*)0x400E1440U) /**< (PIOD) Interrupt Enable Register */
|
||||
#define REG_PIOD_IDR (*(__O uint32_t*)0x400E1444U) /**< (PIOD) Interrupt Disable Register */
|
||||
#define REG_PIOD_IMR (*(__I uint32_t*)0x400E1448U) /**< (PIOD) Interrupt Mask Register */
|
||||
#define REG_PIOD_ISR (*(__I uint32_t*)0x400E144CU) /**< (PIOD) Interrupt Status Register */
|
||||
#define REG_PIOD_MDER (*(__O uint32_t*)0x400E1450U) /**< (PIOD) Multi-driver Enable Register */
|
||||
#define REG_PIOD_MDDR (*(__O uint32_t*)0x400E1454U) /**< (PIOD) Multi-driver Disable Register */
|
||||
#define REG_PIOD_MDSR (*(__I uint32_t*)0x400E1458U) /**< (PIOD) Multi-driver Status Register */
|
||||
#define REG_PIOD_PUDR (*(__O uint32_t*)0x400E1460U) /**< (PIOD) Pull-up Disable Register */
|
||||
#define REG_PIOD_PUER (*(__O uint32_t*)0x400E1464U) /**< (PIOD) Pull-up Enable Register */
|
||||
#define REG_PIOD_PUSR (*(__I uint32_t*)0x400E1468U) /**< (PIOD) Pad Pull-up Status Register */
|
||||
#define REG_PIOD_ABCDSR (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOD_ABCDSR0 (*(__IO uint32_t*)0x400E1470U) /**< (PIOD) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOD_ABCDSR1 (*(__IO uint32_t*)0x400E1474U) /**< (PIOD) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOD_IFSCDR (*(__O uint32_t*)0x400E1480U) /**< (PIOD) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOD_IFSCER (*(__O uint32_t*)0x400E1484U) /**< (PIOD) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOD_IFSCSR (*(__I uint32_t*)0x400E1488U) /**< (PIOD) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOD_SCDR (*(__IO uint32_t*)0x400E148CU) /**< (PIOD) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOD_PPDDR (*(__O uint32_t*)0x400E1490U) /**< (PIOD) Pad Pull-down Disable Register */
|
||||
#define REG_PIOD_PPDER (*(__O uint32_t*)0x400E1494U) /**< (PIOD) Pad Pull-down Enable Register */
|
||||
#define REG_PIOD_PPDSR (*(__I uint32_t*)0x400E1498U) /**< (PIOD) Pad Pull-down Status Register */
|
||||
#define REG_PIOD_OWER (*(__O uint32_t*)0x400E14A0U) /**< (PIOD) Output Write Enable */
|
||||
#define REG_PIOD_OWDR (*(__O uint32_t*)0x400E14A4U) /**< (PIOD) Output Write Disable */
|
||||
#define REG_PIOD_OWSR (*(__I uint32_t*)0x400E14A8U) /**< (PIOD) Output Write Status Register */
|
||||
#define REG_PIOD_AIMER (*(__O uint32_t*)0x400E14B0U) /**< (PIOD) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOD_AIMDR (*(__O uint32_t*)0x400E14B4U) /**< (PIOD) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOD_AIMMR (*(__I uint32_t*)0x400E14B8U) /**< (PIOD) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOD_ESR (*(__O uint32_t*)0x400E14C0U) /**< (PIOD) Edge Select Register */
|
||||
#define REG_PIOD_LSR (*(__O uint32_t*)0x400E14C4U) /**< (PIOD) Level Select Register */
|
||||
#define REG_PIOD_ELSR (*(__I uint32_t*)0x400E14C8U) /**< (PIOD) Edge/Level Status Register */
|
||||
#define REG_PIOD_FELLSR (*(__O uint32_t*)0x400E14D0U) /**< (PIOD) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOD_REHLSR (*(__O uint32_t*)0x400E14D4U) /**< (PIOD) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOD_FRLHSR (*(__I uint32_t*)0x400E14D8U) /**< (PIOD) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOD_LOCKSR (*(__I uint32_t*)0x400E14E0U) /**< (PIOD) Lock Status */
|
||||
#define REG_PIOD_WPMR (*(__IO uint32_t*)0x400E14E4U) /**< (PIOD) Write Protection Mode Register */
|
||||
#define REG_PIOD_WPSR (*(__I uint32_t*)0x400E14E8U) /**< (PIOD) Write Protection Status Register */
|
||||
#define REG_PIOD_SCHMITT (*(__IO uint32_t*)0x400E1500U) /**< (PIOD) Schmitt Trigger Register */
|
||||
#define REG_PIOD_DRIVER (*(__IO uint32_t*)0x400E1518U) /**< (PIOD) I/O Drive Register */
|
||||
#define REG_PIOD_PCMR (*(__IO uint32_t*)0x400E1550U) /**< (PIOD) Parallel Capture Mode Register */
|
||||
#define REG_PIOD_PCIER (*(__O uint32_t*)0x400E1554U) /**< (PIOD) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOD_PCIDR (*(__O uint32_t*)0x400E1558U) /**< (PIOD) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOD_PCIMR (*(__I uint32_t*)0x400E155CU) /**< (PIOD) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOD_PCISR (*(__I uint32_t*)0x400E1560U) /**< (PIOD) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOD_PCRHR (*(__I uint32_t*)0x400E1564U) /**< (PIOD) Parallel Capture Reception Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PIOD peripheral ========== */
|
||||
#define PIOD_INSTANCE_ID 16
|
||||
#define PIOD_CLOCK_ID 16
|
||||
|
||||
#endif /* _SAME70_PIOD_INSTANCE_ */
|
||||
159
lib/same70b/include/instance/pioe.h
Normal file
159
lib/same70b/include/instance/pioe.h
Normal file
|
|
@ -0,0 +1,159 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PIOE
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PIOE_INSTANCE_H_
|
||||
#define _SAME70_PIOE_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PIOE peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PIOE_PER (0x400E1600) /**< (PIOE) PIO Enable Register */
|
||||
#define REG_PIOE_PDR (0x400E1604) /**< (PIOE) PIO Disable Register */
|
||||
#define REG_PIOE_PSR (0x400E1608) /**< (PIOE) PIO Status Register */
|
||||
#define REG_PIOE_OER (0x400E1610) /**< (PIOE) Output Enable Register */
|
||||
#define REG_PIOE_ODR (0x400E1614) /**< (PIOE) Output Disable Register */
|
||||
#define REG_PIOE_OSR (0x400E1618) /**< (PIOE) Output Status Register */
|
||||
#define REG_PIOE_IFER (0x400E1620) /**< (PIOE) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOE_IFDR (0x400E1624) /**< (PIOE) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOE_IFSR (0x400E1628) /**< (PIOE) Glitch Input Filter Status Register */
|
||||
#define REG_PIOE_SODR (0x400E1630) /**< (PIOE) Set Output Data Register */
|
||||
#define REG_PIOE_CODR (0x400E1634) /**< (PIOE) Clear Output Data Register */
|
||||
#define REG_PIOE_ODSR (0x400E1638) /**< (PIOE) Output Data Status Register */
|
||||
#define REG_PIOE_PDSR (0x400E163C) /**< (PIOE) Pin Data Status Register */
|
||||
#define REG_PIOE_IER (0x400E1640) /**< (PIOE) Interrupt Enable Register */
|
||||
#define REG_PIOE_IDR (0x400E1644) /**< (PIOE) Interrupt Disable Register */
|
||||
#define REG_PIOE_IMR (0x400E1648) /**< (PIOE) Interrupt Mask Register */
|
||||
#define REG_PIOE_ISR (0x400E164C) /**< (PIOE) Interrupt Status Register */
|
||||
#define REG_PIOE_MDER (0x400E1650) /**< (PIOE) Multi-driver Enable Register */
|
||||
#define REG_PIOE_MDDR (0x400E1654) /**< (PIOE) Multi-driver Disable Register */
|
||||
#define REG_PIOE_MDSR (0x400E1658) /**< (PIOE) Multi-driver Status Register */
|
||||
#define REG_PIOE_PUDR (0x400E1660) /**< (PIOE) Pull-up Disable Register */
|
||||
#define REG_PIOE_PUER (0x400E1664) /**< (PIOE) Pull-up Enable Register */
|
||||
#define REG_PIOE_PUSR (0x400E1668) /**< (PIOE) Pad Pull-up Status Register */
|
||||
#define REG_PIOE_ABCDSR (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOE_ABCDSR0 (0x400E1670) /**< (PIOE) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOE_ABCDSR1 (0x400E1674) /**< (PIOE) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOE_IFSCDR (0x400E1680) /**< (PIOE) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOE_IFSCER (0x400E1684) /**< (PIOE) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOE_IFSCSR (0x400E1688) /**< (PIOE) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOE_SCDR (0x400E168C) /**< (PIOE) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOE_PPDDR (0x400E1690) /**< (PIOE) Pad Pull-down Disable Register */
|
||||
#define REG_PIOE_PPDER (0x400E1694) /**< (PIOE) Pad Pull-down Enable Register */
|
||||
#define REG_PIOE_PPDSR (0x400E1698) /**< (PIOE) Pad Pull-down Status Register */
|
||||
#define REG_PIOE_OWER (0x400E16A0) /**< (PIOE) Output Write Enable */
|
||||
#define REG_PIOE_OWDR (0x400E16A4) /**< (PIOE) Output Write Disable */
|
||||
#define REG_PIOE_OWSR (0x400E16A8) /**< (PIOE) Output Write Status Register */
|
||||
#define REG_PIOE_AIMER (0x400E16B0) /**< (PIOE) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOE_AIMDR (0x400E16B4) /**< (PIOE) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOE_AIMMR (0x400E16B8) /**< (PIOE) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOE_ESR (0x400E16C0) /**< (PIOE) Edge Select Register */
|
||||
#define REG_PIOE_LSR (0x400E16C4) /**< (PIOE) Level Select Register */
|
||||
#define REG_PIOE_ELSR (0x400E16C8) /**< (PIOE) Edge/Level Status Register */
|
||||
#define REG_PIOE_FELLSR (0x400E16D0) /**< (PIOE) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOE_REHLSR (0x400E16D4) /**< (PIOE) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOE_FRLHSR (0x400E16D8) /**< (PIOE) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOE_LOCKSR (0x400E16E0) /**< (PIOE) Lock Status */
|
||||
#define REG_PIOE_WPMR (0x400E16E4) /**< (PIOE) Write Protection Mode Register */
|
||||
#define REG_PIOE_WPSR (0x400E16E8) /**< (PIOE) Write Protection Status Register */
|
||||
#define REG_PIOE_SCHMITT (0x400E1700) /**< (PIOE) Schmitt Trigger Register */
|
||||
#define REG_PIOE_DRIVER (0x400E1718) /**< (PIOE) I/O Drive Register */
|
||||
#define REG_PIOE_PCMR (0x400E1750) /**< (PIOE) Parallel Capture Mode Register */
|
||||
#define REG_PIOE_PCIER (0x400E1754) /**< (PIOE) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOE_PCIDR (0x400E1758) /**< (PIOE) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOE_PCIMR (0x400E175C) /**< (PIOE) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOE_PCISR (0x400E1760) /**< (PIOE) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOE_PCRHR (0x400E1764) /**< (PIOE) Parallel Capture Reception Holding Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PIOE_PER (*(__O uint32_t*)0x400E1600U) /**< (PIOE) PIO Enable Register */
|
||||
#define REG_PIOE_PDR (*(__O uint32_t*)0x400E1604U) /**< (PIOE) PIO Disable Register */
|
||||
#define REG_PIOE_PSR (*(__I uint32_t*)0x400E1608U) /**< (PIOE) PIO Status Register */
|
||||
#define REG_PIOE_OER (*(__O uint32_t*)0x400E1610U) /**< (PIOE) Output Enable Register */
|
||||
#define REG_PIOE_ODR (*(__O uint32_t*)0x400E1614U) /**< (PIOE) Output Disable Register */
|
||||
#define REG_PIOE_OSR (*(__I uint32_t*)0x400E1618U) /**< (PIOE) Output Status Register */
|
||||
#define REG_PIOE_IFER (*(__O uint32_t*)0x400E1620U) /**< (PIOE) Glitch Input Filter Enable Register */
|
||||
#define REG_PIOE_IFDR (*(__O uint32_t*)0x400E1624U) /**< (PIOE) Glitch Input Filter Disable Register */
|
||||
#define REG_PIOE_IFSR (*(__I uint32_t*)0x400E1628U) /**< (PIOE) Glitch Input Filter Status Register */
|
||||
#define REG_PIOE_SODR (*(__O uint32_t*)0x400E1630U) /**< (PIOE) Set Output Data Register */
|
||||
#define REG_PIOE_CODR (*(__O uint32_t*)0x400E1634U) /**< (PIOE) Clear Output Data Register */
|
||||
#define REG_PIOE_ODSR (*(__IO uint32_t*)0x400E1638U) /**< (PIOE) Output Data Status Register */
|
||||
#define REG_PIOE_PDSR (*(__I uint32_t*)0x400E163CU) /**< (PIOE) Pin Data Status Register */
|
||||
#define REG_PIOE_IER (*(__O uint32_t*)0x400E1640U) /**< (PIOE) Interrupt Enable Register */
|
||||
#define REG_PIOE_IDR (*(__O uint32_t*)0x400E1644U) /**< (PIOE) Interrupt Disable Register */
|
||||
#define REG_PIOE_IMR (*(__I uint32_t*)0x400E1648U) /**< (PIOE) Interrupt Mask Register */
|
||||
#define REG_PIOE_ISR (*(__I uint32_t*)0x400E164CU) /**< (PIOE) Interrupt Status Register */
|
||||
#define REG_PIOE_MDER (*(__O uint32_t*)0x400E1650U) /**< (PIOE) Multi-driver Enable Register */
|
||||
#define REG_PIOE_MDDR (*(__O uint32_t*)0x400E1654U) /**< (PIOE) Multi-driver Disable Register */
|
||||
#define REG_PIOE_MDSR (*(__I uint32_t*)0x400E1658U) /**< (PIOE) Multi-driver Status Register */
|
||||
#define REG_PIOE_PUDR (*(__O uint32_t*)0x400E1660U) /**< (PIOE) Pull-up Disable Register */
|
||||
#define REG_PIOE_PUER (*(__O uint32_t*)0x400E1664U) /**< (PIOE) Pull-up Enable Register */
|
||||
#define REG_PIOE_PUSR (*(__I uint32_t*)0x400E1668U) /**< (PIOE) Pad Pull-up Status Register */
|
||||
#define REG_PIOE_ABCDSR (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOE_ABCDSR0 (*(__IO uint32_t*)0x400E1670U) /**< (PIOE) Peripheral ABCD Select Register 0 */
|
||||
#define REG_PIOE_ABCDSR1 (*(__IO uint32_t*)0x400E1674U) /**< (PIOE) Peripheral ABCD Select Register 1 */
|
||||
#define REG_PIOE_IFSCDR (*(__O uint32_t*)0x400E1680U) /**< (PIOE) Input Filter Slow Clock Disable Register */
|
||||
#define REG_PIOE_IFSCER (*(__O uint32_t*)0x400E1684U) /**< (PIOE) Input Filter Slow Clock Enable Register */
|
||||
#define REG_PIOE_IFSCSR (*(__I uint32_t*)0x400E1688U) /**< (PIOE) Input Filter Slow Clock Status Register */
|
||||
#define REG_PIOE_SCDR (*(__IO uint32_t*)0x400E168CU) /**< (PIOE) Slow Clock Divider Debouncing Register */
|
||||
#define REG_PIOE_PPDDR (*(__O uint32_t*)0x400E1690U) /**< (PIOE) Pad Pull-down Disable Register */
|
||||
#define REG_PIOE_PPDER (*(__O uint32_t*)0x400E1694U) /**< (PIOE) Pad Pull-down Enable Register */
|
||||
#define REG_PIOE_PPDSR (*(__I uint32_t*)0x400E1698U) /**< (PIOE) Pad Pull-down Status Register */
|
||||
#define REG_PIOE_OWER (*(__O uint32_t*)0x400E16A0U) /**< (PIOE) Output Write Enable */
|
||||
#define REG_PIOE_OWDR (*(__O uint32_t*)0x400E16A4U) /**< (PIOE) Output Write Disable */
|
||||
#define REG_PIOE_OWSR (*(__I uint32_t*)0x400E16A8U) /**< (PIOE) Output Write Status Register */
|
||||
#define REG_PIOE_AIMER (*(__O uint32_t*)0x400E16B0U) /**< (PIOE) Additional Interrupt Modes Enable Register */
|
||||
#define REG_PIOE_AIMDR (*(__O uint32_t*)0x400E16B4U) /**< (PIOE) Additional Interrupt Modes Disable Register */
|
||||
#define REG_PIOE_AIMMR (*(__I uint32_t*)0x400E16B8U) /**< (PIOE) Additional Interrupt Modes Mask Register */
|
||||
#define REG_PIOE_ESR (*(__O uint32_t*)0x400E16C0U) /**< (PIOE) Edge Select Register */
|
||||
#define REG_PIOE_LSR (*(__O uint32_t*)0x400E16C4U) /**< (PIOE) Level Select Register */
|
||||
#define REG_PIOE_ELSR (*(__I uint32_t*)0x400E16C8U) /**< (PIOE) Edge/Level Status Register */
|
||||
#define REG_PIOE_FELLSR (*(__O uint32_t*)0x400E16D0U) /**< (PIOE) Falling Edge/Low-Level Select Register */
|
||||
#define REG_PIOE_REHLSR (*(__O uint32_t*)0x400E16D4U) /**< (PIOE) Rising Edge/High-Level Select Register */
|
||||
#define REG_PIOE_FRLHSR (*(__I uint32_t*)0x400E16D8U) /**< (PIOE) Fall/Rise - Low/High Status Register */
|
||||
#define REG_PIOE_LOCKSR (*(__I uint32_t*)0x400E16E0U) /**< (PIOE) Lock Status */
|
||||
#define REG_PIOE_WPMR (*(__IO uint32_t*)0x400E16E4U) /**< (PIOE) Write Protection Mode Register */
|
||||
#define REG_PIOE_WPSR (*(__I uint32_t*)0x400E16E8U) /**< (PIOE) Write Protection Status Register */
|
||||
#define REG_PIOE_SCHMITT (*(__IO uint32_t*)0x400E1700U) /**< (PIOE) Schmitt Trigger Register */
|
||||
#define REG_PIOE_DRIVER (*(__IO uint32_t*)0x400E1718U) /**< (PIOE) I/O Drive Register */
|
||||
#define REG_PIOE_PCMR (*(__IO uint32_t*)0x400E1750U) /**< (PIOE) Parallel Capture Mode Register */
|
||||
#define REG_PIOE_PCIER (*(__O uint32_t*)0x400E1754U) /**< (PIOE) Parallel Capture Interrupt Enable Register */
|
||||
#define REG_PIOE_PCIDR (*(__O uint32_t*)0x400E1758U) /**< (PIOE) Parallel Capture Interrupt Disable Register */
|
||||
#define REG_PIOE_PCIMR (*(__I uint32_t*)0x400E175CU) /**< (PIOE) Parallel Capture Interrupt Mask Register */
|
||||
#define REG_PIOE_PCISR (*(__I uint32_t*)0x400E1760U) /**< (PIOE) Parallel Capture Interrupt Status Register */
|
||||
#define REG_PIOE_PCRHR (*(__I uint32_t*)0x400E1764U) /**< (PIOE) Parallel Capture Reception Holding Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PIOE peripheral ========== */
|
||||
#define PIOE_INSTANCE_ID 17
|
||||
#define PIOE_CLOCK_ID 17
|
||||
|
||||
#endif /* _SAME70_PIOE_INSTANCE_ */
|
||||
136
lib/same70b/include/instance/pmc.h
Normal file
136
lib/same70b/include/instance/pmc.h
Normal file
|
|
@ -0,0 +1,136 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PMC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PMC_INSTANCE_H_
|
||||
#define _SAME70_PMC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PMC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PMC_SCER (0x400E0600) /**< (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR (0x400E0604) /**< (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR (0x400E0608) /**< (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER0 (0x400E0610) /**< (PMC) Peripheral Clock Enable Register 0 */
|
||||
#define REG_PMC_PCDR0 (0x400E0614) /**< (PMC) Peripheral Clock Disable Register 0 */
|
||||
#define REG_PMC_PCSR0 (0x400E0618) /**< (PMC) Peripheral Clock Status Register 0 */
|
||||
#define REG_CKGR_UCKR (0x400E061C) /**< (PMC) UTMI Clock Register */
|
||||
#define REG_CKGR_MOR (0x400E0620) /**< (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR (0x400E0624) /**< (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLAR (0x400E0628) /**< (PMC) PLLA Register */
|
||||
#define REG_PMC_MCKR (0x400E0630) /**< (PMC) Master Clock Register */
|
||||
#define REG_PMC_USB (0x400E0638) /**< (PMC) USB Clock Register */
|
||||
#define REG_PMC_PCK (0x400E0640) /**< (PMC) Programmable Clock Register */
|
||||
#define REG_PMC_PCK0 (0x400E0640) /**< (PMC) Programmable Clock Register 0 */
|
||||
#define REG_PMC_PCK1 (0x400E0644) /**< (PMC) Programmable Clock Register 1 */
|
||||
#define REG_PMC_PCK2 (0x400E0648) /**< (PMC) Programmable Clock Register 2 */
|
||||
#define REG_PMC_PCK3 (0x400E064C) /**< (PMC) Programmable Clock Register 3 */
|
||||
#define REG_PMC_PCK4 (0x400E0650) /**< (PMC) Programmable Clock Register 4 */
|
||||
#define REG_PMC_PCK5 (0x400E0654) /**< (PMC) Programmable Clock Register 5 */
|
||||
#define REG_PMC_PCK6 (0x400E0658) /**< (PMC) Programmable Clock Register 6 */
|
||||
#define REG_PMC_PCK7 (0x400E065C) /**< (PMC) Programmable Clock Register 7 */
|
||||
#define REG_PMC_IER (0x400E0660) /**< (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR (0x400E0664) /**< (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR (0x400E0668) /**< (PMC) Status Register */
|
||||
#define REG_PMC_IMR (0x400E066C) /**< (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR (0x400E0670) /**< (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR (0x400E0674) /**< (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR (0x400E0678) /**< (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR (0x400E06E4) /**< (PMC) Write Protection Mode Register */
|
||||
#define REG_PMC_WPSR (0x400E06E8) /**< (PMC) Write Protection Status Register */
|
||||
#define REG_PMC_PCER1 (0x400E0700) /**< (PMC) Peripheral Clock Enable Register 1 */
|
||||
#define REG_PMC_PCDR1 (0x400E0704) /**< (PMC) Peripheral Clock Disable Register 1 */
|
||||
#define REG_PMC_PCSR1 (0x400E0708) /**< (PMC) Peripheral Clock Status Register 1 */
|
||||
#define REG_PMC_PCR (0x400E070C) /**< (PMC) Peripheral Control Register */
|
||||
#define REG_PMC_OCR (0x400E0710) /**< (PMC) Oscillator Calibration Register */
|
||||
#define REG_PMC_SLPWK_ER0 (0x400E0714) /**< (PMC) SleepWalking Enable Register 0 */
|
||||
#define REG_PMC_SLPWK_DR0 (0x400E0718) /**< (PMC) SleepWalking Disable Register 0 */
|
||||
#define REG_PMC_SLPWK_SR0 (0x400E071C) /**< (PMC) SleepWalking Status Register 0 */
|
||||
#define REG_PMC_SLPWK_ASR0 (0x400E0720) /**< (PMC) SleepWalking Activity Status Register 0 */
|
||||
#define REG_PMC_PMMR (0x400E0730) /**< (PMC) PLL Maximum Multiplier Value Register */
|
||||
#define REG_PMC_SLPWK_ER1 (0x400E0734) /**< (PMC) SleepWalking Enable Register 1 */
|
||||
#define REG_PMC_SLPWK_DR1 (0x400E0738) /**< (PMC) SleepWalking Disable Register 1 */
|
||||
#define REG_PMC_SLPWK_SR1 (0x400E073C) /**< (PMC) SleepWalking Status Register 1 */
|
||||
#define REG_PMC_SLPWK_ASR1 (0x400E0740) /**< (PMC) SleepWalking Activity Status Register 1 */
|
||||
#define REG_PMC_SLPWK_AIPR (0x400E0744) /**< (PMC) SleepWalking Activity In Progress Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PMC_SCER (*(__O uint32_t*)0x400E0600U) /**< (PMC) System Clock Enable Register */
|
||||
#define REG_PMC_SCDR (*(__O uint32_t*)0x400E0604U) /**< (PMC) System Clock Disable Register */
|
||||
#define REG_PMC_SCSR (*(__I uint32_t*)0x400E0608U) /**< (PMC) System Clock Status Register */
|
||||
#define REG_PMC_PCER0 (*(__O uint32_t*)0x400E0610U) /**< (PMC) Peripheral Clock Enable Register 0 */
|
||||
#define REG_PMC_PCDR0 (*(__O uint32_t*)0x400E0614U) /**< (PMC) Peripheral Clock Disable Register 0 */
|
||||
#define REG_PMC_PCSR0 (*(__I uint32_t*)0x400E0618U) /**< (PMC) Peripheral Clock Status Register 0 */
|
||||
#define REG_CKGR_UCKR (*(__IO uint32_t*)0x400E061CU) /**< (PMC) UTMI Clock Register */
|
||||
#define REG_CKGR_MOR (*(__IO uint32_t*)0x400E0620U) /**< (PMC) Main Oscillator Register */
|
||||
#define REG_CKGR_MCFR (*(__IO uint32_t*)0x400E0624U) /**< (PMC) Main Clock Frequency Register */
|
||||
#define REG_CKGR_PLLAR (*(__IO uint32_t*)0x400E0628U) /**< (PMC) PLLA Register */
|
||||
#define REG_PMC_MCKR (*(__IO uint32_t*)0x400E0630U) /**< (PMC) Master Clock Register */
|
||||
#define REG_PMC_USB (*(__IO uint32_t*)0x400E0638U) /**< (PMC) USB Clock Register */
|
||||
#define REG_PMC_PCK (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register */
|
||||
#define REG_PMC_PCK0 (*(__IO uint32_t*)0x400E0640U) /**< (PMC) Programmable Clock Register 0 */
|
||||
#define REG_PMC_PCK1 (*(__IO uint32_t*)0x400E0644U) /**< (PMC) Programmable Clock Register 1 */
|
||||
#define REG_PMC_PCK2 (*(__IO uint32_t*)0x400E0648U) /**< (PMC) Programmable Clock Register 2 */
|
||||
#define REG_PMC_PCK3 (*(__IO uint32_t*)0x400E064CU) /**< (PMC) Programmable Clock Register 3 */
|
||||
#define REG_PMC_PCK4 (*(__IO uint32_t*)0x400E0650U) /**< (PMC) Programmable Clock Register 4 */
|
||||
#define REG_PMC_PCK5 (*(__IO uint32_t*)0x400E0654U) /**< (PMC) Programmable Clock Register 5 */
|
||||
#define REG_PMC_PCK6 (*(__IO uint32_t*)0x400E0658U) /**< (PMC) Programmable Clock Register 6 */
|
||||
#define REG_PMC_PCK7 (*(__IO uint32_t*)0x400E065CU) /**< (PMC) Programmable Clock Register 7 */
|
||||
#define REG_PMC_IER (*(__O uint32_t*)0x400E0660U) /**< (PMC) Interrupt Enable Register */
|
||||
#define REG_PMC_IDR (*(__O uint32_t*)0x400E0664U) /**< (PMC) Interrupt Disable Register */
|
||||
#define REG_PMC_SR (*(__I uint32_t*)0x400E0668U) /**< (PMC) Status Register */
|
||||
#define REG_PMC_IMR (*(__I uint32_t*)0x400E066CU) /**< (PMC) Interrupt Mask Register */
|
||||
#define REG_PMC_FSMR (*(__IO uint32_t*)0x400E0670U) /**< (PMC) Fast Startup Mode Register */
|
||||
#define REG_PMC_FSPR (*(__IO uint32_t*)0x400E0674U) /**< (PMC) Fast Startup Polarity Register */
|
||||
#define REG_PMC_FOCR (*(__O uint32_t*)0x400E0678U) /**< (PMC) Fault Output Clear Register */
|
||||
#define REG_PMC_WPMR (*(__IO uint32_t*)0x400E06E4U) /**< (PMC) Write Protection Mode Register */
|
||||
#define REG_PMC_WPSR (*(__I uint32_t*)0x400E06E8U) /**< (PMC) Write Protection Status Register */
|
||||
#define REG_PMC_PCER1 (*(__O uint32_t*)0x400E0700U) /**< (PMC) Peripheral Clock Enable Register 1 */
|
||||
#define REG_PMC_PCDR1 (*(__O uint32_t*)0x400E0704U) /**< (PMC) Peripheral Clock Disable Register 1 */
|
||||
#define REG_PMC_PCSR1 (*(__I uint32_t*)0x400E0708U) /**< (PMC) Peripheral Clock Status Register 1 */
|
||||
#define REG_PMC_PCR (*(__IO uint32_t*)0x400E070CU) /**< (PMC) Peripheral Control Register */
|
||||
#define REG_PMC_OCR (*(__IO uint32_t*)0x400E0710U) /**< (PMC) Oscillator Calibration Register */
|
||||
#define REG_PMC_SLPWK_ER0 (*(__O uint32_t*)0x400E0714U) /**< (PMC) SleepWalking Enable Register 0 */
|
||||
#define REG_PMC_SLPWK_DR0 (*(__O uint32_t*)0x400E0718U) /**< (PMC) SleepWalking Disable Register 0 */
|
||||
#define REG_PMC_SLPWK_SR0 (*(__I uint32_t*)0x400E071CU) /**< (PMC) SleepWalking Status Register 0 */
|
||||
#define REG_PMC_SLPWK_ASR0 (*(__I uint32_t*)0x400E0720U) /**< (PMC) SleepWalking Activity Status Register 0 */
|
||||
#define REG_PMC_PMMR (*(__IO uint32_t*)0x400E0730U) /**< (PMC) PLL Maximum Multiplier Value Register */
|
||||
#define REG_PMC_SLPWK_ER1 (*(__O uint32_t*)0x400E0734U) /**< (PMC) SleepWalking Enable Register 1 */
|
||||
#define REG_PMC_SLPWK_DR1 (*(__O uint32_t*)0x400E0738U) /**< (PMC) SleepWalking Disable Register 1 */
|
||||
#define REG_PMC_SLPWK_SR1 (*(__I uint32_t*)0x400E073CU) /**< (PMC) SleepWalking Status Register 1 */
|
||||
#define REG_PMC_SLPWK_ASR1 (*(__I uint32_t*)0x400E0740U) /**< (PMC) SleepWalking Activity Status Register 1 */
|
||||
#define REG_PMC_SLPWK_AIPR (*(__I uint32_t*)0x400E0744U) /**< (PMC) SleepWalking Activity In Progress Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PMC peripheral ========== */
|
||||
#define PMC_INSTANCE_ID 5
|
||||
|
||||
#endif /* _SAME70_PMC_INSTANCE_ */
|
||||
274
lib/same70b/include/instance/pwm0.h
Normal file
274
lib/same70b/include/instance/pwm0.h
Normal file
|
|
@ -0,0 +1,274 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PWM0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PWM0_INSTANCE_H_
|
||||
#define _SAME70_PWM0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PWM0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PWM0_CMPV0 (0x40020130) /**< (PWM0) PWM Comparison 0 Value Register 0 */
|
||||
#define REG_PWM0_CMPVUPD0 (0x40020134) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */
|
||||
#define REG_PWM0_CMPM0 (0x40020138) /**< (PWM0) PWM Comparison 0 Mode Register 0 */
|
||||
#define REG_PWM0_CMPMUPD0 (0x4002013C) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */
|
||||
#define REG_PWM0_CMPV1 (0x40020140) /**< (PWM0) PWM Comparison 0 Value Register 1 */
|
||||
#define REG_PWM0_CMPVUPD1 (0x40020144) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */
|
||||
#define REG_PWM0_CMPM1 (0x40020148) /**< (PWM0) PWM Comparison 0 Mode Register 1 */
|
||||
#define REG_PWM0_CMPMUPD1 (0x4002014C) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */
|
||||
#define REG_PWM0_CMPV2 (0x40020150) /**< (PWM0) PWM Comparison 0 Value Register 2 */
|
||||
#define REG_PWM0_CMPVUPD2 (0x40020154) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */
|
||||
#define REG_PWM0_CMPM2 (0x40020158) /**< (PWM0) PWM Comparison 0 Mode Register 2 */
|
||||
#define REG_PWM0_CMPMUPD2 (0x4002015C) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */
|
||||
#define REG_PWM0_CMPV3 (0x40020160) /**< (PWM0) PWM Comparison 0 Value Register 3 */
|
||||
#define REG_PWM0_CMPVUPD3 (0x40020164) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */
|
||||
#define REG_PWM0_CMPM3 (0x40020168) /**< (PWM0) PWM Comparison 0 Mode Register 3 */
|
||||
#define REG_PWM0_CMPMUPD3 (0x4002016C) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */
|
||||
#define REG_PWM0_CMPV4 (0x40020170) /**< (PWM0) PWM Comparison 0 Value Register 4 */
|
||||
#define REG_PWM0_CMPVUPD4 (0x40020174) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */
|
||||
#define REG_PWM0_CMPM4 (0x40020178) /**< (PWM0) PWM Comparison 0 Mode Register 4 */
|
||||
#define REG_PWM0_CMPMUPD4 (0x4002017C) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */
|
||||
#define REG_PWM0_CMPV5 (0x40020180) /**< (PWM0) PWM Comparison 0 Value Register 5 */
|
||||
#define REG_PWM0_CMPVUPD5 (0x40020184) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */
|
||||
#define REG_PWM0_CMPM5 (0x40020188) /**< (PWM0) PWM Comparison 0 Mode Register 5 */
|
||||
#define REG_PWM0_CMPMUPD5 (0x4002018C) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */
|
||||
#define REG_PWM0_CMPV6 (0x40020190) /**< (PWM0) PWM Comparison 0 Value Register 6 */
|
||||
#define REG_PWM0_CMPVUPD6 (0x40020194) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */
|
||||
#define REG_PWM0_CMPM6 (0x40020198) /**< (PWM0) PWM Comparison 0 Mode Register 6 */
|
||||
#define REG_PWM0_CMPMUPD6 (0x4002019C) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */
|
||||
#define REG_PWM0_CMPV7 (0x400201A0) /**< (PWM0) PWM Comparison 0 Value Register 7 */
|
||||
#define REG_PWM0_CMPVUPD7 (0x400201A4) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */
|
||||
#define REG_PWM0_CMPM7 (0x400201A8) /**< (PWM0) PWM Comparison 0 Mode Register 7 */
|
||||
#define REG_PWM0_CMPMUPD7 (0x400201AC) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */
|
||||
#define REG_PWM0_CMR0 (0x40020200) /**< (PWM0) PWM Channel Mode Register 0 */
|
||||
#define REG_PWM0_CDTY0 (0x40020204) /**< (PWM0) PWM Channel Duty Cycle Register 0 */
|
||||
#define REG_PWM0_CDTYUPD0 (0x40020208) /**< (PWM0) PWM Channel Duty Cycle Update Register 0 */
|
||||
#define REG_PWM0_CPRD0 (0x4002020C) /**< (PWM0) PWM Channel Period Register 0 */
|
||||
#define REG_PWM0_CPRDUPD0 (0x40020210) /**< (PWM0) PWM Channel Period Update Register 0 */
|
||||
#define REG_PWM0_CCNT0 (0x40020214) /**< (PWM0) PWM Channel Counter Register 0 */
|
||||
#define REG_PWM0_DT0 (0x40020218) /**< (PWM0) PWM Channel Dead Time Register 0 */
|
||||
#define REG_PWM0_DTUPD0 (0x4002021C) /**< (PWM0) PWM Channel Dead Time Update Register 0 */
|
||||
#define REG_PWM0_CMR1 (0x40020220) /**< (PWM0) PWM Channel Mode Register 1 */
|
||||
#define REG_PWM0_CDTY1 (0x40020224) /**< (PWM0) PWM Channel Duty Cycle Register 1 */
|
||||
#define REG_PWM0_CDTYUPD1 (0x40020228) /**< (PWM0) PWM Channel Duty Cycle Update Register 1 */
|
||||
#define REG_PWM0_CPRD1 (0x4002022C) /**< (PWM0) PWM Channel Period Register 1 */
|
||||
#define REG_PWM0_CPRDUPD1 (0x40020230) /**< (PWM0) PWM Channel Period Update Register 1 */
|
||||
#define REG_PWM0_CCNT1 (0x40020234) /**< (PWM0) PWM Channel Counter Register 1 */
|
||||
#define REG_PWM0_DT1 (0x40020238) /**< (PWM0) PWM Channel Dead Time Register 1 */
|
||||
#define REG_PWM0_DTUPD1 (0x4002023C) /**< (PWM0) PWM Channel Dead Time Update Register 1 */
|
||||
#define REG_PWM0_CMR2 (0x40020240) /**< (PWM0) PWM Channel Mode Register 2 */
|
||||
#define REG_PWM0_CDTY2 (0x40020244) /**< (PWM0) PWM Channel Duty Cycle Register 2 */
|
||||
#define REG_PWM0_CDTYUPD2 (0x40020248) /**< (PWM0) PWM Channel Duty Cycle Update Register 2 */
|
||||
#define REG_PWM0_CPRD2 (0x4002024C) /**< (PWM0) PWM Channel Period Register 2 */
|
||||
#define REG_PWM0_CPRDUPD2 (0x40020250) /**< (PWM0) PWM Channel Period Update Register 2 */
|
||||
#define REG_PWM0_CCNT2 (0x40020254) /**< (PWM0) PWM Channel Counter Register 2 */
|
||||
#define REG_PWM0_DT2 (0x40020258) /**< (PWM0) PWM Channel Dead Time Register 2 */
|
||||
#define REG_PWM0_DTUPD2 (0x4002025C) /**< (PWM0) PWM Channel Dead Time Update Register 2 */
|
||||
#define REG_PWM0_CMR3 (0x40020260) /**< (PWM0) PWM Channel Mode Register 3 */
|
||||
#define REG_PWM0_CDTY3 (0x40020264) /**< (PWM0) PWM Channel Duty Cycle Register 3 */
|
||||
#define REG_PWM0_CDTYUPD3 (0x40020268) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */
|
||||
#define REG_PWM0_CPRD3 (0x4002026C) /**< (PWM0) PWM Channel Period Register 3 */
|
||||
#define REG_PWM0_CPRDUPD3 (0x40020270) /**< (PWM0) PWM Channel Period Update Register 3 */
|
||||
#define REG_PWM0_CCNT3 (0x40020274) /**< (PWM0) PWM Channel Counter Register 3 */
|
||||
#define REG_PWM0_DT3 (0x40020278) /**< (PWM0) PWM Channel Dead Time Register 3 */
|
||||
#define REG_PWM0_DTUPD3 (0x4002027C) /**< (PWM0) PWM Channel Dead Time Update Register 3 */
|
||||
#define REG_PWM0_CLK (0x40020000) /**< (PWM0) PWM Clock Register */
|
||||
#define REG_PWM0_ENA (0x40020004) /**< (PWM0) PWM Enable Register */
|
||||
#define REG_PWM0_DIS (0x40020008) /**< (PWM0) PWM Disable Register */
|
||||
#define REG_PWM0_SR (0x4002000C) /**< (PWM0) PWM Status Register */
|
||||
#define REG_PWM0_IER1 (0x40020010) /**< (PWM0) PWM Interrupt Enable Register 1 */
|
||||
#define REG_PWM0_IDR1 (0x40020014) /**< (PWM0) PWM Interrupt Disable Register 1 */
|
||||
#define REG_PWM0_IMR1 (0x40020018) /**< (PWM0) PWM Interrupt Mask Register 1 */
|
||||
#define REG_PWM0_ISR1 (0x4002001C) /**< (PWM0) PWM Interrupt Status Register 1 */
|
||||
#define REG_PWM0_SCM (0x40020020) /**< (PWM0) PWM Sync Channels Mode Register */
|
||||
#define REG_PWM0_DMAR (0x40020024) /**< (PWM0) PWM DMA Register */
|
||||
#define REG_PWM0_SCUC (0x40020028) /**< (PWM0) PWM Sync Channels Update Control Register */
|
||||
#define REG_PWM0_SCUP (0x4002002C) /**< (PWM0) PWM Sync Channels Update Period Register */
|
||||
#define REG_PWM0_SCUPUPD (0x40020030) /**< (PWM0) PWM Sync Channels Update Period Update Register */
|
||||
#define REG_PWM0_IER2 (0x40020034) /**< (PWM0) PWM Interrupt Enable Register 2 */
|
||||
#define REG_PWM0_IDR2 (0x40020038) /**< (PWM0) PWM Interrupt Disable Register 2 */
|
||||
#define REG_PWM0_IMR2 (0x4002003C) /**< (PWM0) PWM Interrupt Mask Register 2 */
|
||||
#define REG_PWM0_ISR2 (0x40020040) /**< (PWM0) PWM Interrupt Status Register 2 */
|
||||
#define REG_PWM0_OOV (0x40020044) /**< (PWM0) PWM Output Override Value Register */
|
||||
#define REG_PWM0_OS (0x40020048) /**< (PWM0) PWM Output Selection Register */
|
||||
#define REG_PWM0_OSS (0x4002004C) /**< (PWM0) PWM Output Selection Set Register */
|
||||
#define REG_PWM0_OSC (0x40020050) /**< (PWM0) PWM Output Selection Clear Register */
|
||||
#define REG_PWM0_OSSUPD (0x40020054) /**< (PWM0) PWM Output Selection Set Update Register */
|
||||
#define REG_PWM0_OSCUPD (0x40020058) /**< (PWM0) PWM Output Selection Clear Update Register */
|
||||
#define REG_PWM0_FMR (0x4002005C) /**< (PWM0) PWM Fault Mode Register */
|
||||
#define REG_PWM0_FSR (0x40020060) /**< (PWM0) PWM Fault Status Register */
|
||||
#define REG_PWM0_FCR (0x40020064) /**< (PWM0) PWM Fault Clear Register */
|
||||
#define REG_PWM0_FPV1 (0x40020068) /**< (PWM0) PWM Fault Protection Value Register 1 */
|
||||
#define REG_PWM0_FPE (0x4002006C) /**< (PWM0) PWM Fault Protection Enable Register */
|
||||
#define REG_PWM0_ELMR (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM0_ELMR0 (0x4002007C) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM0_ELMR1 (0x40020080) /**< (PWM0) PWM Event Line 0 Mode Register 1 */
|
||||
#define REG_PWM0_SSPR (0x400200A0) /**< (PWM0) PWM Spread Spectrum Register */
|
||||
#define REG_PWM0_SSPUP (0x400200A4) /**< (PWM0) PWM Spread Spectrum Update Register */
|
||||
#define REG_PWM0_SMMR (0x400200B0) /**< (PWM0) PWM Stepper Motor Mode Register */
|
||||
#define REG_PWM0_FPV2 (0x400200C0) /**< (PWM0) PWM Fault Protection Value 2 Register */
|
||||
#define REG_PWM0_WPCR (0x400200E4) /**< (PWM0) PWM Write Protection Control Register */
|
||||
#define REG_PWM0_WPSR (0x400200E8) /**< (PWM0) PWM Write Protection Status Register */
|
||||
#define REG_PWM0_CMUPD0 (0x40020400) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
|
||||
#define REG_PWM0_CMUPD1 (0x40020420) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
|
||||
#define REG_PWM0_ETRG1 (0x4002042C) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */
|
||||
#define REG_PWM0_LEBR1 (0x40020430) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
|
||||
#define REG_PWM0_CMUPD2 (0x40020440) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
|
||||
#define REG_PWM0_ETRG2 (0x4002044C) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */
|
||||
#define REG_PWM0_LEBR2 (0x40020450) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
|
||||
#define REG_PWM0_CMUPD3 (0x40020460) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PWM0_CMPV0 (*(__IO uint32_t*)0x40020130U) /**< (PWM0) PWM Comparison 0 Value Register 0 */
|
||||
#define REG_PWM0_CMPVUPD0 (*(__O uint32_t*)0x40020134U) /**< (PWM0) PWM Comparison 0 Value Update Register 0 */
|
||||
#define REG_PWM0_CMPM0 (*(__IO uint32_t*)0x40020138U) /**< (PWM0) PWM Comparison 0 Mode Register 0 */
|
||||
#define REG_PWM0_CMPMUPD0 (*(__O uint32_t*)0x4002013CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 0 */
|
||||
#define REG_PWM0_CMPV1 (*(__IO uint32_t*)0x40020140U) /**< (PWM0) PWM Comparison 0 Value Register 1 */
|
||||
#define REG_PWM0_CMPVUPD1 (*(__O uint32_t*)0x40020144U) /**< (PWM0) PWM Comparison 0 Value Update Register 1 */
|
||||
#define REG_PWM0_CMPM1 (*(__IO uint32_t*)0x40020148U) /**< (PWM0) PWM Comparison 0 Mode Register 1 */
|
||||
#define REG_PWM0_CMPMUPD1 (*(__O uint32_t*)0x4002014CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 1 */
|
||||
#define REG_PWM0_CMPV2 (*(__IO uint32_t*)0x40020150U) /**< (PWM0) PWM Comparison 0 Value Register 2 */
|
||||
#define REG_PWM0_CMPVUPD2 (*(__O uint32_t*)0x40020154U) /**< (PWM0) PWM Comparison 0 Value Update Register 2 */
|
||||
#define REG_PWM0_CMPM2 (*(__IO uint32_t*)0x40020158U) /**< (PWM0) PWM Comparison 0 Mode Register 2 */
|
||||
#define REG_PWM0_CMPMUPD2 (*(__O uint32_t*)0x4002015CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 2 */
|
||||
#define REG_PWM0_CMPV3 (*(__IO uint32_t*)0x40020160U) /**< (PWM0) PWM Comparison 0 Value Register 3 */
|
||||
#define REG_PWM0_CMPVUPD3 (*(__O uint32_t*)0x40020164U) /**< (PWM0) PWM Comparison 0 Value Update Register 3 */
|
||||
#define REG_PWM0_CMPM3 (*(__IO uint32_t*)0x40020168U) /**< (PWM0) PWM Comparison 0 Mode Register 3 */
|
||||
#define REG_PWM0_CMPMUPD3 (*(__O uint32_t*)0x4002016CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 3 */
|
||||
#define REG_PWM0_CMPV4 (*(__IO uint32_t*)0x40020170U) /**< (PWM0) PWM Comparison 0 Value Register 4 */
|
||||
#define REG_PWM0_CMPVUPD4 (*(__O uint32_t*)0x40020174U) /**< (PWM0) PWM Comparison 0 Value Update Register 4 */
|
||||
#define REG_PWM0_CMPM4 (*(__IO uint32_t*)0x40020178U) /**< (PWM0) PWM Comparison 0 Mode Register 4 */
|
||||
#define REG_PWM0_CMPMUPD4 (*(__O uint32_t*)0x4002017CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 4 */
|
||||
#define REG_PWM0_CMPV5 (*(__IO uint32_t*)0x40020180U) /**< (PWM0) PWM Comparison 0 Value Register 5 */
|
||||
#define REG_PWM0_CMPVUPD5 (*(__O uint32_t*)0x40020184U) /**< (PWM0) PWM Comparison 0 Value Update Register 5 */
|
||||
#define REG_PWM0_CMPM5 (*(__IO uint32_t*)0x40020188U) /**< (PWM0) PWM Comparison 0 Mode Register 5 */
|
||||
#define REG_PWM0_CMPMUPD5 (*(__O uint32_t*)0x4002018CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 5 */
|
||||
#define REG_PWM0_CMPV6 (*(__IO uint32_t*)0x40020190U) /**< (PWM0) PWM Comparison 0 Value Register 6 */
|
||||
#define REG_PWM0_CMPVUPD6 (*(__O uint32_t*)0x40020194U) /**< (PWM0) PWM Comparison 0 Value Update Register 6 */
|
||||
#define REG_PWM0_CMPM6 (*(__IO uint32_t*)0x40020198U) /**< (PWM0) PWM Comparison 0 Mode Register 6 */
|
||||
#define REG_PWM0_CMPMUPD6 (*(__O uint32_t*)0x4002019CU) /**< (PWM0) PWM Comparison 0 Mode Update Register 6 */
|
||||
#define REG_PWM0_CMPV7 (*(__IO uint32_t*)0x400201A0U) /**< (PWM0) PWM Comparison 0 Value Register 7 */
|
||||
#define REG_PWM0_CMPVUPD7 (*(__O uint32_t*)0x400201A4U) /**< (PWM0) PWM Comparison 0 Value Update Register 7 */
|
||||
#define REG_PWM0_CMPM7 (*(__IO uint32_t*)0x400201A8U) /**< (PWM0) PWM Comparison 0 Mode Register 7 */
|
||||
#define REG_PWM0_CMPMUPD7 (*(__O uint32_t*)0x400201ACU) /**< (PWM0) PWM Comparison 0 Mode Update Register 7 */
|
||||
#define REG_PWM0_CMR0 (*(__IO uint32_t*)0x40020200U) /**< (PWM0) PWM Channel Mode Register 0 */
|
||||
#define REG_PWM0_CDTY0 (*(__IO uint32_t*)0x40020204U) /**< (PWM0) PWM Channel Duty Cycle Register 0 */
|
||||
#define REG_PWM0_CDTYUPD0 (*(__O uint32_t*)0x40020208U) /**< (PWM0) PWM Channel Duty Cycle Update Register 0 */
|
||||
#define REG_PWM0_CPRD0 (*(__IO uint32_t*)0x4002020CU) /**< (PWM0) PWM Channel Period Register 0 */
|
||||
#define REG_PWM0_CPRDUPD0 (*(__O uint32_t*)0x40020210U) /**< (PWM0) PWM Channel Period Update Register 0 */
|
||||
#define REG_PWM0_CCNT0 (*(__I uint32_t*)0x40020214U) /**< (PWM0) PWM Channel Counter Register 0 */
|
||||
#define REG_PWM0_DT0 (*(__IO uint32_t*)0x40020218U) /**< (PWM0) PWM Channel Dead Time Register 0 */
|
||||
#define REG_PWM0_DTUPD0 (*(__O uint32_t*)0x4002021CU) /**< (PWM0) PWM Channel Dead Time Update Register 0 */
|
||||
#define REG_PWM0_CMR1 (*(__IO uint32_t*)0x40020220U) /**< (PWM0) PWM Channel Mode Register 1 */
|
||||
#define REG_PWM0_CDTY1 (*(__IO uint32_t*)0x40020224U) /**< (PWM0) PWM Channel Duty Cycle Register 1 */
|
||||
#define REG_PWM0_CDTYUPD1 (*(__O uint32_t*)0x40020228U) /**< (PWM0) PWM Channel Duty Cycle Update Register 1 */
|
||||
#define REG_PWM0_CPRD1 (*(__IO uint32_t*)0x4002022CU) /**< (PWM0) PWM Channel Period Register 1 */
|
||||
#define REG_PWM0_CPRDUPD1 (*(__O uint32_t*)0x40020230U) /**< (PWM0) PWM Channel Period Update Register 1 */
|
||||
#define REG_PWM0_CCNT1 (*(__I uint32_t*)0x40020234U) /**< (PWM0) PWM Channel Counter Register 1 */
|
||||
#define REG_PWM0_DT1 (*(__IO uint32_t*)0x40020238U) /**< (PWM0) PWM Channel Dead Time Register 1 */
|
||||
#define REG_PWM0_DTUPD1 (*(__O uint32_t*)0x4002023CU) /**< (PWM0) PWM Channel Dead Time Update Register 1 */
|
||||
#define REG_PWM0_CMR2 (*(__IO uint32_t*)0x40020240U) /**< (PWM0) PWM Channel Mode Register 2 */
|
||||
#define REG_PWM0_CDTY2 (*(__IO uint32_t*)0x40020244U) /**< (PWM0) PWM Channel Duty Cycle Register 2 */
|
||||
#define REG_PWM0_CDTYUPD2 (*(__O uint32_t*)0x40020248U) /**< (PWM0) PWM Channel Duty Cycle Update Register 2 */
|
||||
#define REG_PWM0_CPRD2 (*(__IO uint32_t*)0x4002024CU) /**< (PWM0) PWM Channel Period Register 2 */
|
||||
#define REG_PWM0_CPRDUPD2 (*(__O uint32_t*)0x40020250U) /**< (PWM0) PWM Channel Period Update Register 2 */
|
||||
#define REG_PWM0_CCNT2 (*(__I uint32_t*)0x40020254U) /**< (PWM0) PWM Channel Counter Register 2 */
|
||||
#define REG_PWM0_DT2 (*(__IO uint32_t*)0x40020258U) /**< (PWM0) PWM Channel Dead Time Register 2 */
|
||||
#define REG_PWM0_DTUPD2 (*(__O uint32_t*)0x4002025CU) /**< (PWM0) PWM Channel Dead Time Update Register 2 */
|
||||
#define REG_PWM0_CMR3 (*(__IO uint32_t*)0x40020260U) /**< (PWM0) PWM Channel Mode Register 3 */
|
||||
#define REG_PWM0_CDTY3 (*(__IO uint32_t*)0x40020264U) /**< (PWM0) PWM Channel Duty Cycle Register 3 */
|
||||
#define REG_PWM0_CDTYUPD3 (*(__O uint32_t*)0x40020268U) /**< (PWM0) PWM Channel Duty Cycle Update Register 3 */
|
||||
#define REG_PWM0_CPRD3 (*(__IO uint32_t*)0x4002026CU) /**< (PWM0) PWM Channel Period Register 3 */
|
||||
#define REG_PWM0_CPRDUPD3 (*(__O uint32_t*)0x40020270U) /**< (PWM0) PWM Channel Period Update Register 3 */
|
||||
#define REG_PWM0_CCNT3 (*(__I uint32_t*)0x40020274U) /**< (PWM0) PWM Channel Counter Register 3 */
|
||||
#define REG_PWM0_DT3 (*(__IO uint32_t*)0x40020278U) /**< (PWM0) PWM Channel Dead Time Register 3 */
|
||||
#define REG_PWM0_DTUPD3 (*(__O uint32_t*)0x4002027CU) /**< (PWM0) PWM Channel Dead Time Update Register 3 */
|
||||
#define REG_PWM0_CLK (*(__IO uint32_t*)0x40020000U) /**< (PWM0) PWM Clock Register */
|
||||
#define REG_PWM0_ENA (*(__O uint32_t*)0x40020004U) /**< (PWM0) PWM Enable Register */
|
||||
#define REG_PWM0_DIS (*(__O uint32_t*)0x40020008U) /**< (PWM0) PWM Disable Register */
|
||||
#define REG_PWM0_SR (*(__I uint32_t*)0x4002000CU) /**< (PWM0) PWM Status Register */
|
||||
#define REG_PWM0_IER1 (*(__O uint32_t*)0x40020010U) /**< (PWM0) PWM Interrupt Enable Register 1 */
|
||||
#define REG_PWM0_IDR1 (*(__O uint32_t*)0x40020014U) /**< (PWM0) PWM Interrupt Disable Register 1 */
|
||||
#define REG_PWM0_IMR1 (*(__I uint32_t*)0x40020018U) /**< (PWM0) PWM Interrupt Mask Register 1 */
|
||||
#define REG_PWM0_ISR1 (*(__I uint32_t*)0x4002001CU) /**< (PWM0) PWM Interrupt Status Register 1 */
|
||||
#define REG_PWM0_SCM (*(__IO uint32_t*)0x40020020U) /**< (PWM0) PWM Sync Channels Mode Register */
|
||||
#define REG_PWM0_DMAR (*(__O uint32_t*)0x40020024U) /**< (PWM0) PWM DMA Register */
|
||||
#define REG_PWM0_SCUC (*(__IO uint32_t*)0x40020028U) /**< (PWM0) PWM Sync Channels Update Control Register */
|
||||
#define REG_PWM0_SCUP (*(__IO uint32_t*)0x4002002CU) /**< (PWM0) PWM Sync Channels Update Period Register */
|
||||
#define REG_PWM0_SCUPUPD (*(__O uint32_t*)0x40020030U) /**< (PWM0) PWM Sync Channels Update Period Update Register */
|
||||
#define REG_PWM0_IER2 (*(__O uint32_t*)0x40020034U) /**< (PWM0) PWM Interrupt Enable Register 2 */
|
||||
#define REG_PWM0_IDR2 (*(__O uint32_t*)0x40020038U) /**< (PWM0) PWM Interrupt Disable Register 2 */
|
||||
#define REG_PWM0_IMR2 (*(__I uint32_t*)0x4002003CU) /**< (PWM0) PWM Interrupt Mask Register 2 */
|
||||
#define REG_PWM0_ISR2 (*(__I uint32_t*)0x40020040U) /**< (PWM0) PWM Interrupt Status Register 2 */
|
||||
#define REG_PWM0_OOV (*(__IO uint32_t*)0x40020044U) /**< (PWM0) PWM Output Override Value Register */
|
||||
#define REG_PWM0_OS (*(__IO uint32_t*)0x40020048U) /**< (PWM0) PWM Output Selection Register */
|
||||
#define REG_PWM0_OSS (*(__O uint32_t*)0x4002004CU) /**< (PWM0) PWM Output Selection Set Register */
|
||||
#define REG_PWM0_OSC (*(__O uint32_t*)0x40020050U) /**< (PWM0) PWM Output Selection Clear Register */
|
||||
#define REG_PWM0_OSSUPD (*(__O uint32_t*)0x40020054U) /**< (PWM0) PWM Output Selection Set Update Register */
|
||||
#define REG_PWM0_OSCUPD (*(__O uint32_t*)0x40020058U) /**< (PWM0) PWM Output Selection Clear Update Register */
|
||||
#define REG_PWM0_FMR (*(__IO uint32_t*)0x4002005CU) /**< (PWM0) PWM Fault Mode Register */
|
||||
#define REG_PWM0_FSR (*(__I uint32_t*)0x40020060U) /**< (PWM0) PWM Fault Status Register */
|
||||
#define REG_PWM0_FCR (*(__O uint32_t*)0x40020064U) /**< (PWM0) PWM Fault Clear Register */
|
||||
#define REG_PWM0_FPV1 (*(__IO uint32_t*)0x40020068U) /**< (PWM0) PWM Fault Protection Value Register 1 */
|
||||
#define REG_PWM0_FPE (*(__IO uint32_t*)0x4002006CU) /**< (PWM0) PWM Fault Protection Enable Register */
|
||||
#define REG_PWM0_ELMR (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM0_ELMR0 (*(__IO uint32_t*)0x4002007CU) /**< (PWM0) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM0_ELMR1 (*(__IO uint32_t*)0x40020080U) /**< (PWM0) PWM Event Line 0 Mode Register 1 */
|
||||
#define REG_PWM0_SSPR (*(__IO uint32_t*)0x400200A0U) /**< (PWM0) PWM Spread Spectrum Register */
|
||||
#define REG_PWM0_SSPUP (*(__O uint32_t*)0x400200A4U) /**< (PWM0) PWM Spread Spectrum Update Register */
|
||||
#define REG_PWM0_SMMR (*(__IO uint32_t*)0x400200B0U) /**< (PWM0) PWM Stepper Motor Mode Register */
|
||||
#define REG_PWM0_FPV2 (*(__IO uint32_t*)0x400200C0U) /**< (PWM0) PWM Fault Protection Value 2 Register */
|
||||
#define REG_PWM0_WPCR (*(__O uint32_t*)0x400200E4U) /**< (PWM0) PWM Write Protection Control Register */
|
||||
#define REG_PWM0_WPSR (*(__I uint32_t*)0x400200E8U) /**< (PWM0) PWM Write Protection Status Register */
|
||||
#define REG_PWM0_CMUPD0 (*(__O uint32_t*)0x40020400U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 0) */
|
||||
#define REG_PWM0_CMUPD1 (*(__O uint32_t*)0x40020420U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 1) */
|
||||
#define REG_PWM0_ETRG1 (*(__IO uint32_t*)0x4002042CU) /**< (PWM0) PWM External Trigger Register (trg_num = 1) */
|
||||
#define REG_PWM0_LEBR1 (*(__IO uint32_t*)0x40020430U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 1) */
|
||||
#define REG_PWM0_CMUPD2 (*(__O uint32_t*)0x40020440U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 2) */
|
||||
#define REG_PWM0_ETRG2 (*(__IO uint32_t*)0x4002044CU) /**< (PWM0) PWM External Trigger Register (trg_num = 2) */
|
||||
#define REG_PWM0_LEBR2 (*(__IO uint32_t*)0x40020450U) /**< (PWM0) PWM Leading-Edge Blanking Register (trg_num = 2) */
|
||||
#define REG_PWM0_CMUPD3 (*(__O uint32_t*)0x40020460U) /**< (PWM0) PWM Channel Mode Update Register (ch_num = 3) */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PWM0 peripheral ========== */
|
||||
#define PWM0_DMAC_ID_TX 13
|
||||
#define PWM0_INSTANCE_ID 31
|
||||
#define PWM0_CLOCK_ID 31
|
||||
#define PWM0_FAULT_PWM_ID0 0x0 /* Fault 0 - PWM0_PWMFI0 Input pin */
|
||||
#define PWM0_FAULT_PWM_ID1 0x1 /* Fault 1 - PWM0_PWMFI1 Input pin */
|
||||
#define PWM0_FAULT_PWM_ID2 0x2 /* Fault 2 - PWM0_PWMFI2 Input pin */
|
||||
#define PWM0_FAULT_PWM_ID3 0x3 /* Fault 3 - MAIN_OSC_PMC */
|
||||
#define PWM0_FAULT_PWM_ID4 0x4 /* Fault 4 - AFEC0 */
|
||||
#define PWM0_FAULT_PWM_ID5 0x5 /* Fault 5 - AFEC1 */
|
||||
#define PWM0_FAULT_PWM_ID6 0x6 /* Fault 6 - ACC */
|
||||
#define PWM0_FAULT_PWM_ID7 0x7 /* Fault 7 - TC0 */
|
||||
|
||||
#endif /* _SAME70_PWM0_INSTANCE_ */
|
||||
274
lib/same70b/include/instance/pwm1.h
Normal file
274
lib/same70b/include/instance/pwm1.h
Normal file
|
|
@ -0,0 +1,274 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for PWM1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_PWM1_INSTANCE_H_
|
||||
#define _SAME70_PWM1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for PWM1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_PWM1_CMPV0 (0x4005C130) /**< (PWM1) PWM Comparison 0 Value Register 0 */
|
||||
#define REG_PWM1_CMPVUPD0 (0x4005C134) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */
|
||||
#define REG_PWM1_CMPM0 (0x4005C138) /**< (PWM1) PWM Comparison 0 Mode Register 0 */
|
||||
#define REG_PWM1_CMPMUPD0 (0x4005C13C) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */
|
||||
#define REG_PWM1_CMPV1 (0x4005C140) /**< (PWM1) PWM Comparison 0 Value Register 1 */
|
||||
#define REG_PWM1_CMPVUPD1 (0x4005C144) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */
|
||||
#define REG_PWM1_CMPM1 (0x4005C148) /**< (PWM1) PWM Comparison 0 Mode Register 1 */
|
||||
#define REG_PWM1_CMPMUPD1 (0x4005C14C) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */
|
||||
#define REG_PWM1_CMPV2 (0x4005C150) /**< (PWM1) PWM Comparison 0 Value Register 2 */
|
||||
#define REG_PWM1_CMPVUPD2 (0x4005C154) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */
|
||||
#define REG_PWM1_CMPM2 (0x4005C158) /**< (PWM1) PWM Comparison 0 Mode Register 2 */
|
||||
#define REG_PWM1_CMPMUPD2 (0x4005C15C) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */
|
||||
#define REG_PWM1_CMPV3 (0x4005C160) /**< (PWM1) PWM Comparison 0 Value Register 3 */
|
||||
#define REG_PWM1_CMPVUPD3 (0x4005C164) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */
|
||||
#define REG_PWM1_CMPM3 (0x4005C168) /**< (PWM1) PWM Comparison 0 Mode Register 3 */
|
||||
#define REG_PWM1_CMPMUPD3 (0x4005C16C) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */
|
||||
#define REG_PWM1_CMPV4 (0x4005C170) /**< (PWM1) PWM Comparison 0 Value Register 4 */
|
||||
#define REG_PWM1_CMPVUPD4 (0x4005C174) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */
|
||||
#define REG_PWM1_CMPM4 (0x4005C178) /**< (PWM1) PWM Comparison 0 Mode Register 4 */
|
||||
#define REG_PWM1_CMPMUPD4 (0x4005C17C) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */
|
||||
#define REG_PWM1_CMPV5 (0x4005C180) /**< (PWM1) PWM Comparison 0 Value Register 5 */
|
||||
#define REG_PWM1_CMPVUPD5 (0x4005C184) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */
|
||||
#define REG_PWM1_CMPM5 (0x4005C188) /**< (PWM1) PWM Comparison 0 Mode Register 5 */
|
||||
#define REG_PWM1_CMPMUPD5 (0x4005C18C) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */
|
||||
#define REG_PWM1_CMPV6 (0x4005C190) /**< (PWM1) PWM Comparison 0 Value Register 6 */
|
||||
#define REG_PWM1_CMPVUPD6 (0x4005C194) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */
|
||||
#define REG_PWM1_CMPM6 (0x4005C198) /**< (PWM1) PWM Comparison 0 Mode Register 6 */
|
||||
#define REG_PWM1_CMPMUPD6 (0x4005C19C) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */
|
||||
#define REG_PWM1_CMPV7 (0x4005C1A0) /**< (PWM1) PWM Comparison 0 Value Register 7 */
|
||||
#define REG_PWM1_CMPVUPD7 (0x4005C1A4) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */
|
||||
#define REG_PWM1_CMPM7 (0x4005C1A8) /**< (PWM1) PWM Comparison 0 Mode Register 7 */
|
||||
#define REG_PWM1_CMPMUPD7 (0x4005C1AC) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */
|
||||
#define REG_PWM1_CMR0 (0x4005C200) /**< (PWM1) PWM Channel Mode Register 0 */
|
||||
#define REG_PWM1_CDTY0 (0x4005C204) /**< (PWM1) PWM Channel Duty Cycle Register 0 */
|
||||
#define REG_PWM1_CDTYUPD0 (0x4005C208) /**< (PWM1) PWM Channel Duty Cycle Update Register 0 */
|
||||
#define REG_PWM1_CPRD0 (0x4005C20C) /**< (PWM1) PWM Channel Period Register 0 */
|
||||
#define REG_PWM1_CPRDUPD0 (0x4005C210) /**< (PWM1) PWM Channel Period Update Register 0 */
|
||||
#define REG_PWM1_CCNT0 (0x4005C214) /**< (PWM1) PWM Channel Counter Register 0 */
|
||||
#define REG_PWM1_DT0 (0x4005C218) /**< (PWM1) PWM Channel Dead Time Register 0 */
|
||||
#define REG_PWM1_DTUPD0 (0x4005C21C) /**< (PWM1) PWM Channel Dead Time Update Register 0 */
|
||||
#define REG_PWM1_CMR1 (0x4005C220) /**< (PWM1) PWM Channel Mode Register 1 */
|
||||
#define REG_PWM1_CDTY1 (0x4005C224) /**< (PWM1) PWM Channel Duty Cycle Register 1 */
|
||||
#define REG_PWM1_CDTYUPD1 (0x4005C228) /**< (PWM1) PWM Channel Duty Cycle Update Register 1 */
|
||||
#define REG_PWM1_CPRD1 (0x4005C22C) /**< (PWM1) PWM Channel Period Register 1 */
|
||||
#define REG_PWM1_CPRDUPD1 (0x4005C230) /**< (PWM1) PWM Channel Period Update Register 1 */
|
||||
#define REG_PWM1_CCNT1 (0x4005C234) /**< (PWM1) PWM Channel Counter Register 1 */
|
||||
#define REG_PWM1_DT1 (0x4005C238) /**< (PWM1) PWM Channel Dead Time Register 1 */
|
||||
#define REG_PWM1_DTUPD1 (0x4005C23C) /**< (PWM1) PWM Channel Dead Time Update Register 1 */
|
||||
#define REG_PWM1_CMR2 (0x4005C240) /**< (PWM1) PWM Channel Mode Register 2 */
|
||||
#define REG_PWM1_CDTY2 (0x4005C244) /**< (PWM1) PWM Channel Duty Cycle Register 2 */
|
||||
#define REG_PWM1_CDTYUPD2 (0x4005C248) /**< (PWM1) PWM Channel Duty Cycle Update Register 2 */
|
||||
#define REG_PWM1_CPRD2 (0x4005C24C) /**< (PWM1) PWM Channel Period Register 2 */
|
||||
#define REG_PWM1_CPRDUPD2 (0x4005C250) /**< (PWM1) PWM Channel Period Update Register 2 */
|
||||
#define REG_PWM1_CCNT2 (0x4005C254) /**< (PWM1) PWM Channel Counter Register 2 */
|
||||
#define REG_PWM1_DT2 (0x4005C258) /**< (PWM1) PWM Channel Dead Time Register 2 */
|
||||
#define REG_PWM1_DTUPD2 (0x4005C25C) /**< (PWM1) PWM Channel Dead Time Update Register 2 */
|
||||
#define REG_PWM1_CMR3 (0x4005C260) /**< (PWM1) PWM Channel Mode Register 3 */
|
||||
#define REG_PWM1_CDTY3 (0x4005C264) /**< (PWM1) PWM Channel Duty Cycle Register 3 */
|
||||
#define REG_PWM1_CDTYUPD3 (0x4005C268) /**< (PWM1) PWM Channel Duty Cycle Update Register 3 */
|
||||
#define REG_PWM1_CPRD3 (0x4005C26C) /**< (PWM1) PWM Channel Period Register 3 */
|
||||
#define REG_PWM1_CPRDUPD3 (0x4005C270) /**< (PWM1) PWM Channel Period Update Register 3 */
|
||||
#define REG_PWM1_CCNT3 (0x4005C274) /**< (PWM1) PWM Channel Counter Register 3 */
|
||||
#define REG_PWM1_DT3 (0x4005C278) /**< (PWM1) PWM Channel Dead Time Register 3 */
|
||||
#define REG_PWM1_DTUPD3 (0x4005C27C) /**< (PWM1) PWM Channel Dead Time Update Register 3 */
|
||||
#define REG_PWM1_CLK (0x4005C000) /**< (PWM1) PWM Clock Register */
|
||||
#define REG_PWM1_ENA (0x4005C004) /**< (PWM1) PWM Enable Register */
|
||||
#define REG_PWM1_DIS (0x4005C008) /**< (PWM1) PWM Disable Register */
|
||||
#define REG_PWM1_SR (0x4005C00C) /**< (PWM1) PWM Status Register */
|
||||
#define REG_PWM1_IER1 (0x4005C010) /**< (PWM1) PWM Interrupt Enable Register 1 */
|
||||
#define REG_PWM1_IDR1 (0x4005C014) /**< (PWM1) PWM Interrupt Disable Register 1 */
|
||||
#define REG_PWM1_IMR1 (0x4005C018) /**< (PWM1) PWM Interrupt Mask Register 1 */
|
||||
#define REG_PWM1_ISR1 (0x4005C01C) /**< (PWM1) PWM Interrupt Status Register 1 */
|
||||
#define REG_PWM1_SCM (0x4005C020) /**< (PWM1) PWM Sync Channels Mode Register */
|
||||
#define REG_PWM1_DMAR (0x4005C024) /**< (PWM1) PWM DMA Register */
|
||||
#define REG_PWM1_SCUC (0x4005C028) /**< (PWM1) PWM Sync Channels Update Control Register */
|
||||
#define REG_PWM1_SCUP (0x4005C02C) /**< (PWM1) PWM Sync Channels Update Period Register */
|
||||
#define REG_PWM1_SCUPUPD (0x4005C030) /**< (PWM1) PWM Sync Channels Update Period Update Register */
|
||||
#define REG_PWM1_IER2 (0x4005C034) /**< (PWM1) PWM Interrupt Enable Register 2 */
|
||||
#define REG_PWM1_IDR2 (0x4005C038) /**< (PWM1) PWM Interrupt Disable Register 2 */
|
||||
#define REG_PWM1_IMR2 (0x4005C03C) /**< (PWM1) PWM Interrupt Mask Register 2 */
|
||||
#define REG_PWM1_ISR2 (0x4005C040) /**< (PWM1) PWM Interrupt Status Register 2 */
|
||||
#define REG_PWM1_OOV (0x4005C044) /**< (PWM1) PWM Output Override Value Register */
|
||||
#define REG_PWM1_OS (0x4005C048) /**< (PWM1) PWM Output Selection Register */
|
||||
#define REG_PWM1_OSS (0x4005C04C) /**< (PWM1) PWM Output Selection Set Register */
|
||||
#define REG_PWM1_OSC (0x4005C050) /**< (PWM1) PWM Output Selection Clear Register */
|
||||
#define REG_PWM1_OSSUPD (0x4005C054) /**< (PWM1) PWM Output Selection Set Update Register */
|
||||
#define REG_PWM1_OSCUPD (0x4005C058) /**< (PWM1) PWM Output Selection Clear Update Register */
|
||||
#define REG_PWM1_FMR (0x4005C05C) /**< (PWM1) PWM Fault Mode Register */
|
||||
#define REG_PWM1_FSR (0x4005C060) /**< (PWM1) PWM Fault Status Register */
|
||||
#define REG_PWM1_FCR (0x4005C064) /**< (PWM1) PWM Fault Clear Register */
|
||||
#define REG_PWM1_FPV1 (0x4005C068) /**< (PWM1) PWM Fault Protection Value Register 1 */
|
||||
#define REG_PWM1_FPE (0x4005C06C) /**< (PWM1) PWM Fault Protection Enable Register */
|
||||
#define REG_PWM1_ELMR (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM1_ELMR0 (0x4005C07C) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM1_ELMR1 (0x4005C080) /**< (PWM1) PWM Event Line 0 Mode Register 1 */
|
||||
#define REG_PWM1_SSPR (0x4005C0A0) /**< (PWM1) PWM Spread Spectrum Register */
|
||||
#define REG_PWM1_SSPUP (0x4005C0A4) /**< (PWM1) PWM Spread Spectrum Update Register */
|
||||
#define REG_PWM1_SMMR (0x4005C0B0) /**< (PWM1) PWM Stepper Motor Mode Register */
|
||||
#define REG_PWM1_FPV2 (0x4005C0C0) /**< (PWM1) PWM Fault Protection Value 2 Register */
|
||||
#define REG_PWM1_WPCR (0x4005C0E4) /**< (PWM1) PWM Write Protection Control Register */
|
||||
#define REG_PWM1_WPSR (0x4005C0E8) /**< (PWM1) PWM Write Protection Status Register */
|
||||
#define REG_PWM1_CMUPD0 (0x4005C400) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
|
||||
#define REG_PWM1_CMUPD1 (0x4005C420) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
|
||||
#define REG_PWM1_ETRG1 (0x4005C42C) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */
|
||||
#define REG_PWM1_LEBR1 (0x4005C430) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
|
||||
#define REG_PWM1_CMUPD2 (0x4005C440) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
|
||||
#define REG_PWM1_ETRG2 (0x4005C44C) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */
|
||||
#define REG_PWM1_LEBR2 (0x4005C450) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
|
||||
#define REG_PWM1_CMUPD3 (0x4005C460) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_PWM1_CMPV0 (*(__IO uint32_t*)0x4005C130U) /**< (PWM1) PWM Comparison 0 Value Register 0 */
|
||||
#define REG_PWM1_CMPVUPD0 (*(__O uint32_t*)0x4005C134U) /**< (PWM1) PWM Comparison 0 Value Update Register 0 */
|
||||
#define REG_PWM1_CMPM0 (*(__IO uint32_t*)0x4005C138U) /**< (PWM1) PWM Comparison 0 Mode Register 0 */
|
||||
#define REG_PWM1_CMPMUPD0 (*(__O uint32_t*)0x4005C13CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 0 */
|
||||
#define REG_PWM1_CMPV1 (*(__IO uint32_t*)0x4005C140U) /**< (PWM1) PWM Comparison 0 Value Register 1 */
|
||||
#define REG_PWM1_CMPVUPD1 (*(__O uint32_t*)0x4005C144U) /**< (PWM1) PWM Comparison 0 Value Update Register 1 */
|
||||
#define REG_PWM1_CMPM1 (*(__IO uint32_t*)0x4005C148U) /**< (PWM1) PWM Comparison 0 Mode Register 1 */
|
||||
#define REG_PWM1_CMPMUPD1 (*(__O uint32_t*)0x4005C14CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 1 */
|
||||
#define REG_PWM1_CMPV2 (*(__IO uint32_t*)0x4005C150U) /**< (PWM1) PWM Comparison 0 Value Register 2 */
|
||||
#define REG_PWM1_CMPVUPD2 (*(__O uint32_t*)0x4005C154U) /**< (PWM1) PWM Comparison 0 Value Update Register 2 */
|
||||
#define REG_PWM1_CMPM2 (*(__IO uint32_t*)0x4005C158U) /**< (PWM1) PWM Comparison 0 Mode Register 2 */
|
||||
#define REG_PWM1_CMPMUPD2 (*(__O uint32_t*)0x4005C15CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 2 */
|
||||
#define REG_PWM1_CMPV3 (*(__IO uint32_t*)0x4005C160U) /**< (PWM1) PWM Comparison 0 Value Register 3 */
|
||||
#define REG_PWM1_CMPVUPD3 (*(__O uint32_t*)0x4005C164U) /**< (PWM1) PWM Comparison 0 Value Update Register 3 */
|
||||
#define REG_PWM1_CMPM3 (*(__IO uint32_t*)0x4005C168U) /**< (PWM1) PWM Comparison 0 Mode Register 3 */
|
||||
#define REG_PWM1_CMPMUPD3 (*(__O uint32_t*)0x4005C16CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 3 */
|
||||
#define REG_PWM1_CMPV4 (*(__IO uint32_t*)0x4005C170U) /**< (PWM1) PWM Comparison 0 Value Register 4 */
|
||||
#define REG_PWM1_CMPVUPD4 (*(__O uint32_t*)0x4005C174U) /**< (PWM1) PWM Comparison 0 Value Update Register 4 */
|
||||
#define REG_PWM1_CMPM4 (*(__IO uint32_t*)0x4005C178U) /**< (PWM1) PWM Comparison 0 Mode Register 4 */
|
||||
#define REG_PWM1_CMPMUPD4 (*(__O uint32_t*)0x4005C17CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 4 */
|
||||
#define REG_PWM1_CMPV5 (*(__IO uint32_t*)0x4005C180U) /**< (PWM1) PWM Comparison 0 Value Register 5 */
|
||||
#define REG_PWM1_CMPVUPD5 (*(__O uint32_t*)0x4005C184U) /**< (PWM1) PWM Comparison 0 Value Update Register 5 */
|
||||
#define REG_PWM1_CMPM5 (*(__IO uint32_t*)0x4005C188U) /**< (PWM1) PWM Comparison 0 Mode Register 5 */
|
||||
#define REG_PWM1_CMPMUPD5 (*(__O uint32_t*)0x4005C18CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 5 */
|
||||
#define REG_PWM1_CMPV6 (*(__IO uint32_t*)0x4005C190U) /**< (PWM1) PWM Comparison 0 Value Register 6 */
|
||||
#define REG_PWM1_CMPVUPD6 (*(__O uint32_t*)0x4005C194U) /**< (PWM1) PWM Comparison 0 Value Update Register 6 */
|
||||
#define REG_PWM1_CMPM6 (*(__IO uint32_t*)0x4005C198U) /**< (PWM1) PWM Comparison 0 Mode Register 6 */
|
||||
#define REG_PWM1_CMPMUPD6 (*(__O uint32_t*)0x4005C19CU) /**< (PWM1) PWM Comparison 0 Mode Update Register 6 */
|
||||
#define REG_PWM1_CMPV7 (*(__IO uint32_t*)0x4005C1A0U) /**< (PWM1) PWM Comparison 0 Value Register 7 */
|
||||
#define REG_PWM1_CMPVUPD7 (*(__O uint32_t*)0x4005C1A4U) /**< (PWM1) PWM Comparison 0 Value Update Register 7 */
|
||||
#define REG_PWM1_CMPM7 (*(__IO uint32_t*)0x4005C1A8U) /**< (PWM1) PWM Comparison 0 Mode Register 7 */
|
||||
#define REG_PWM1_CMPMUPD7 (*(__O uint32_t*)0x4005C1ACU) /**< (PWM1) PWM Comparison 0 Mode Update Register 7 */
|
||||
#define REG_PWM1_CMR0 (*(__IO uint32_t*)0x4005C200U) /**< (PWM1) PWM Channel Mode Register 0 */
|
||||
#define REG_PWM1_CDTY0 (*(__IO uint32_t*)0x4005C204U) /**< (PWM1) PWM Channel Duty Cycle Register 0 */
|
||||
#define REG_PWM1_CDTYUPD0 (*(__O uint32_t*)0x4005C208U) /**< (PWM1) PWM Channel Duty Cycle Update Register 0 */
|
||||
#define REG_PWM1_CPRD0 (*(__IO uint32_t*)0x4005C20CU) /**< (PWM1) PWM Channel Period Register 0 */
|
||||
#define REG_PWM1_CPRDUPD0 (*(__O uint32_t*)0x4005C210U) /**< (PWM1) PWM Channel Period Update Register 0 */
|
||||
#define REG_PWM1_CCNT0 (*(__I uint32_t*)0x4005C214U) /**< (PWM1) PWM Channel Counter Register 0 */
|
||||
#define REG_PWM1_DT0 (*(__IO uint32_t*)0x4005C218U) /**< (PWM1) PWM Channel Dead Time Register 0 */
|
||||
#define REG_PWM1_DTUPD0 (*(__O uint32_t*)0x4005C21CU) /**< (PWM1) PWM Channel Dead Time Update Register 0 */
|
||||
#define REG_PWM1_CMR1 (*(__IO uint32_t*)0x4005C220U) /**< (PWM1) PWM Channel Mode Register 1 */
|
||||
#define REG_PWM1_CDTY1 (*(__IO uint32_t*)0x4005C224U) /**< (PWM1) PWM Channel Duty Cycle Register 1 */
|
||||
#define REG_PWM1_CDTYUPD1 (*(__O uint32_t*)0x4005C228U) /**< (PWM1) PWM Channel Duty Cycle Update Register 1 */
|
||||
#define REG_PWM1_CPRD1 (*(__IO uint32_t*)0x4005C22CU) /**< (PWM1) PWM Channel Period Register 1 */
|
||||
#define REG_PWM1_CPRDUPD1 (*(__O uint32_t*)0x4005C230U) /**< (PWM1) PWM Channel Period Update Register 1 */
|
||||
#define REG_PWM1_CCNT1 (*(__I uint32_t*)0x4005C234U) /**< (PWM1) PWM Channel Counter Register 1 */
|
||||
#define REG_PWM1_DT1 (*(__IO uint32_t*)0x4005C238U) /**< (PWM1) PWM Channel Dead Time Register 1 */
|
||||
#define REG_PWM1_DTUPD1 (*(__O uint32_t*)0x4005C23CU) /**< (PWM1) PWM Channel Dead Time Update Register 1 */
|
||||
#define REG_PWM1_CMR2 (*(__IO uint32_t*)0x4005C240U) /**< (PWM1) PWM Channel Mode Register 2 */
|
||||
#define REG_PWM1_CDTY2 (*(__IO uint32_t*)0x4005C244U) /**< (PWM1) PWM Channel Duty Cycle Register 2 */
|
||||
#define REG_PWM1_CDTYUPD2 (*(__O uint32_t*)0x4005C248U) /**< (PWM1) PWM Channel Duty Cycle Update Register 2 */
|
||||
#define REG_PWM1_CPRD2 (*(__IO uint32_t*)0x4005C24CU) /**< (PWM1) PWM Channel Period Register 2 */
|
||||
#define REG_PWM1_CPRDUPD2 (*(__O uint32_t*)0x4005C250U) /**< (PWM1) PWM Channel Period Update Register 2 */
|
||||
#define REG_PWM1_CCNT2 (*(__I uint32_t*)0x4005C254U) /**< (PWM1) PWM Channel Counter Register 2 */
|
||||
#define REG_PWM1_DT2 (*(__IO uint32_t*)0x4005C258U) /**< (PWM1) PWM Channel Dead Time Register 2 */
|
||||
#define REG_PWM1_DTUPD2 (*(__O uint32_t*)0x4005C25CU) /**< (PWM1) PWM Channel Dead Time Update Register 2 */
|
||||
#define REG_PWM1_CMR3 (*(__IO uint32_t*)0x4005C260U) /**< (PWM1) PWM Channel Mode Register 3 */
|
||||
#define REG_PWM1_CDTY3 (*(__IO uint32_t*)0x4005C264U) /**< (PWM1) PWM Channel Duty Cycle Register 3 */
|
||||
#define REG_PWM1_CDTYUPD3 (*(__O uint32_t*)0x4005C268U) /**< (PWM1) PWM Channel Duty Cycle Update Register 3 */
|
||||
#define REG_PWM1_CPRD3 (*(__IO uint32_t*)0x4005C26CU) /**< (PWM1) PWM Channel Period Register 3 */
|
||||
#define REG_PWM1_CPRDUPD3 (*(__O uint32_t*)0x4005C270U) /**< (PWM1) PWM Channel Period Update Register 3 */
|
||||
#define REG_PWM1_CCNT3 (*(__I uint32_t*)0x4005C274U) /**< (PWM1) PWM Channel Counter Register 3 */
|
||||
#define REG_PWM1_DT3 (*(__IO uint32_t*)0x4005C278U) /**< (PWM1) PWM Channel Dead Time Register 3 */
|
||||
#define REG_PWM1_DTUPD3 (*(__O uint32_t*)0x4005C27CU) /**< (PWM1) PWM Channel Dead Time Update Register 3 */
|
||||
#define REG_PWM1_CLK (*(__IO uint32_t*)0x4005C000U) /**< (PWM1) PWM Clock Register */
|
||||
#define REG_PWM1_ENA (*(__O uint32_t*)0x4005C004U) /**< (PWM1) PWM Enable Register */
|
||||
#define REG_PWM1_DIS (*(__O uint32_t*)0x4005C008U) /**< (PWM1) PWM Disable Register */
|
||||
#define REG_PWM1_SR (*(__I uint32_t*)0x4005C00CU) /**< (PWM1) PWM Status Register */
|
||||
#define REG_PWM1_IER1 (*(__O uint32_t*)0x4005C010U) /**< (PWM1) PWM Interrupt Enable Register 1 */
|
||||
#define REG_PWM1_IDR1 (*(__O uint32_t*)0x4005C014U) /**< (PWM1) PWM Interrupt Disable Register 1 */
|
||||
#define REG_PWM1_IMR1 (*(__I uint32_t*)0x4005C018U) /**< (PWM1) PWM Interrupt Mask Register 1 */
|
||||
#define REG_PWM1_ISR1 (*(__I uint32_t*)0x4005C01CU) /**< (PWM1) PWM Interrupt Status Register 1 */
|
||||
#define REG_PWM1_SCM (*(__IO uint32_t*)0x4005C020U) /**< (PWM1) PWM Sync Channels Mode Register */
|
||||
#define REG_PWM1_DMAR (*(__O uint32_t*)0x4005C024U) /**< (PWM1) PWM DMA Register */
|
||||
#define REG_PWM1_SCUC (*(__IO uint32_t*)0x4005C028U) /**< (PWM1) PWM Sync Channels Update Control Register */
|
||||
#define REG_PWM1_SCUP (*(__IO uint32_t*)0x4005C02CU) /**< (PWM1) PWM Sync Channels Update Period Register */
|
||||
#define REG_PWM1_SCUPUPD (*(__O uint32_t*)0x4005C030U) /**< (PWM1) PWM Sync Channels Update Period Update Register */
|
||||
#define REG_PWM1_IER2 (*(__O uint32_t*)0x4005C034U) /**< (PWM1) PWM Interrupt Enable Register 2 */
|
||||
#define REG_PWM1_IDR2 (*(__O uint32_t*)0x4005C038U) /**< (PWM1) PWM Interrupt Disable Register 2 */
|
||||
#define REG_PWM1_IMR2 (*(__I uint32_t*)0x4005C03CU) /**< (PWM1) PWM Interrupt Mask Register 2 */
|
||||
#define REG_PWM1_ISR2 (*(__I uint32_t*)0x4005C040U) /**< (PWM1) PWM Interrupt Status Register 2 */
|
||||
#define REG_PWM1_OOV (*(__IO uint32_t*)0x4005C044U) /**< (PWM1) PWM Output Override Value Register */
|
||||
#define REG_PWM1_OS (*(__IO uint32_t*)0x4005C048U) /**< (PWM1) PWM Output Selection Register */
|
||||
#define REG_PWM1_OSS (*(__O uint32_t*)0x4005C04CU) /**< (PWM1) PWM Output Selection Set Register */
|
||||
#define REG_PWM1_OSC (*(__O uint32_t*)0x4005C050U) /**< (PWM1) PWM Output Selection Clear Register */
|
||||
#define REG_PWM1_OSSUPD (*(__O uint32_t*)0x4005C054U) /**< (PWM1) PWM Output Selection Set Update Register */
|
||||
#define REG_PWM1_OSCUPD (*(__O uint32_t*)0x4005C058U) /**< (PWM1) PWM Output Selection Clear Update Register */
|
||||
#define REG_PWM1_FMR (*(__IO uint32_t*)0x4005C05CU) /**< (PWM1) PWM Fault Mode Register */
|
||||
#define REG_PWM1_FSR (*(__I uint32_t*)0x4005C060U) /**< (PWM1) PWM Fault Status Register */
|
||||
#define REG_PWM1_FCR (*(__O uint32_t*)0x4005C064U) /**< (PWM1) PWM Fault Clear Register */
|
||||
#define REG_PWM1_FPV1 (*(__IO uint32_t*)0x4005C068U) /**< (PWM1) PWM Fault Protection Value Register 1 */
|
||||
#define REG_PWM1_FPE (*(__IO uint32_t*)0x4005C06CU) /**< (PWM1) PWM Fault Protection Enable Register */
|
||||
#define REG_PWM1_ELMR (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM1_ELMR0 (*(__IO uint32_t*)0x4005C07CU) /**< (PWM1) PWM Event Line 0 Mode Register 0 */
|
||||
#define REG_PWM1_ELMR1 (*(__IO uint32_t*)0x4005C080U) /**< (PWM1) PWM Event Line 0 Mode Register 1 */
|
||||
#define REG_PWM1_SSPR (*(__IO uint32_t*)0x4005C0A0U) /**< (PWM1) PWM Spread Spectrum Register */
|
||||
#define REG_PWM1_SSPUP (*(__O uint32_t*)0x4005C0A4U) /**< (PWM1) PWM Spread Spectrum Update Register */
|
||||
#define REG_PWM1_SMMR (*(__IO uint32_t*)0x4005C0B0U) /**< (PWM1) PWM Stepper Motor Mode Register */
|
||||
#define REG_PWM1_FPV2 (*(__IO uint32_t*)0x4005C0C0U) /**< (PWM1) PWM Fault Protection Value 2 Register */
|
||||
#define REG_PWM1_WPCR (*(__O uint32_t*)0x4005C0E4U) /**< (PWM1) PWM Write Protection Control Register */
|
||||
#define REG_PWM1_WPSR (*(__I uint32_t*)0x4005C0E8U) /**< (PWM1) PWM Write Protection Status Register */
|
||||
#define REG_PWM1_CMUPD0 (*(__O uint32_t*)0x4005C400U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 0) */
|
||||
#define REG_PWM1_CMUPD1 (*(__O uint32_t*)0x4005C420U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 1) */
|
||||
#define REG_PWM1_ETRG1 (*(__IO uint32_t*)0x4005C42CU) /**< (PWM1) PWM External Trigger Register (trg_num = 1) */
|
||||
#define REG_PWM1_LEBR1 (*(__IO uint32_t*)0x4005C430U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 1) */
|
||||
#define REG_PWM1_CMUPD2 (*(__O uint32_t*)0x4005C440U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 2) */
|
||||
#define REG_PWM1_ETRG2 (*(__IO uint32_t*)0x4005C44CU) /**< (PWM1) PWM External Trigger Register (trg_num = 2) */
|
||||
#define REG_PWM1_LEBR2 (*(__IO uint32_t*)0x4005C450U) /**< (PWM1) PWM Leading-Edge Blanking Register (trg_num = 2) */
|
||||
#define REG_PWM1_CMUPD3 (*(__O uint32_t*)0x4005C460U) /**< (PWM1) PWM Channel Mode Update Register (ch_num = 3) */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for PWM1 peripheral ========== */
|
||||
#define PWM1_DMAC_ID_TX 39
|
||||
#define PWM1_INSTANCE_ID 60
|
||||
#define PWM1_CLOCK_ID 60
|
||||
#define PWM1_FAULT_PWM_ID0 0x0 /* Fault 0 - PWM0_PWMFI0 Input pin */
|
||||
#define PWM1_FAULT_PWM_ID1 0x1 /* Fault 1 - PWM0_PWMFI1 Input pin */
|
||||
#define PWM1_FAULT_PWM_ID2 0x2 /* Fault 2 - PWM0_PWMFI2 Input pin */
|
||||
#define PWM1_FAULT_PWM_ID3 0x3 /* Fault 3 - MAIN_OSC_PMC */
|
||||
#define PWM1_FAULT_PWM_ID4 0x4 /* Fault 4 - AFEC0 */
|
||||
#define PWM1_FAULT_PWM_ID5 0x5 /* Fault 5 - AFEC1 */
|
||||
#define PWM1_FAULT_PWM_ID6 0x6 /* Fault 6 - ACC */
|
||||
#define PWM1_FAULT_PWM_ID7 0x7 /* Fault 7 - TC1 */
|
||||
|
||||
#endif /* _SAME70_PWM1_INSTANCE_ */
|
||||
81
lib/same70b/include/instance/qspi.h
Normal file
81
lib/same70b/include/instance/qspi.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for QSPI
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_QSPI_INSTANCE_H_
|
||||
#define _SAME70_QSPI_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for QSPI peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_QSPI_CR (0x4007C000) /**< (QSPI) Control Register */
|
||||
#define REG_QSPI_MR (0x4007C004) /**< (QSPI) Mode Register */
|
||||
#define REG_QSPI_RDR (0x4007C008) /**< (QSPI) Receive Data Register */
|
||||
#define REG_QSPI_TDR (0x4007C00C) /**< (QSPI) Transmit Data Register */
|
||||
#define REG_QSPI_SR (0x4007C010) /**< (QSPI) Status Register */
|
||||
#define REG_QSPI_IER (0x4007C014) /**< (QSPI) Interrupt Enable Register */
|
||||
#define REG_QSPI_IDR (0x4007C018) /**< (QSPI) Interrupt Disable Register */
|
||||
#define REG_QSPI_IMR (0x4007C01C) /**< (QSPI) Interrupt Mask Register */
|
||||
#define REG_QSPI_SCR (0x4007C020) /**< (QSPI) Serial Clock Register */
|
||||
#define REG_QSPI_IAR (0x4007C030) /**< (QSPI) Instruction Address Register */
|
||||
#define REG_QSPI_ICR (0x4007C034) /**< (QSPI) Instruction Code Register */
|
||||
#define REG_QSPI_IFR (0x4007C038) /**< (QSPI) Instruction Frame Register */
|
||||
#define REG_QSPI_SMR (0x4007C040) /**< (QSPI) Scrambling Mode Register */
|
||||
#define REG_QSPI_SKR (0x4007C044) /**< (QSPI) Scrambling Key Register */
|
||||
#define REG_QSPI_WPMR (0x4007C0E4) /**< (QSPI) Write Protection Mode Register */
|
||||
#define REG_QSPI_WPSR (0x4007C0E8) /**< (QSPI) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_QSPI_CR (*(__O uint32_t*)0x4007C000U) /**< (QSPI) Control Register */
|
||||
#define REG_QSPI_MR (*(__IO uint32_t*)0x4007C004U) /**< (QSPI) Mode Register */
|
||||
#define REG_QSPI_RDR (*(__I uint32_t*)0x4007C008U) /**< (QSPI) Receive Data Register */
|
||||
#define REG_QSPI_TDR (*(__O uint32_t*)0x4007C00CU) /**< (QSPI) Transmit Data Register */
|
||||
#define REG_QSPI_SR (*(__I uint32_t*)0x4007C010U) /**< (QSPI) Status Register */
|
||||
#define REG_QSPI_IER (*(__O uint32_t*)0x4007C014U) /**< (QSPI) Interrupt Enable Register */
|
||||
#define REG_QSPI_IDR (*(__O uint32_t*)0x4007C018U) /**< (QSPI) Interrupt Disable Register */
|
||||
#define REG_QSPI_IMR (*(__I uint32_t*)0x4007C01CU) /**< (QSPI) Interrupt Mask Register */
|
||||
#define REG_QSPI_SCR (*(__IO uint32_t*)0x4007C020U) /**< (QSPI) Serial Clock Register */
|
||||
#define REG_QSPI_IAR (*(__IO uint32_t*)0x4007C030U) /**< (QSPI) Instruction Address Register */
|
||||
#define REG_QSPI_ICR (*(__IO uint32_t*)0x4007C034U) /**< (QSPI) Instruction Code Register */
|
||||
#define REG_QSPI_IFR (*(__IO uint32_t*)0x4007C038U) /**< (QSPI) Instruction Frame Register */
|
||||
#define REG_QSPI_SMR (*(__IO uint32_t*)0x4007C040U) /**< (QSPI) Scrambling Mode Register */
|
||||
#define REG_QSPI_SKR (*(__O uint32_t*)0x4007C044U) /**< (QSPI) Scrambling Key Register */
|
||||
#define REG_QSPI_WPMR (*(__IO uint32_t*)0x4007C0E4U) /**< (QSPI) Write Protection Mode Register */
|
||||
#define REG_QSPI_WPSR (*(__I uint32_t*)0x4007C0E8U) /**< (QSPI) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for QSPI peripheral ========== */
|
||||
#define QSPI_DMAC_ID_RX 6
|
||||
#define QSPI_DMAC_ID_TX 5
|
||||
#define QSPI_INSTANCE_ID 43
|
||||
#define QSPI_CLOCK_ID 43
|
||||
|
||||
#endif /* _SAME70_QSPI_INSTANCE_ */
|
||||
52
lib/same70b/include/instance/rstc.h
Normal file
52
lib/same70b/include/instance/rstc.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RSTC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_RSTC_INSTANCE_H_
|
||||
#define _SAME70_RSTC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for RSTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_RSTC_CR (0x400E1800) /**< (RSTC) Control Register */
|
||||
#define REG_RSTC_SR (0x400E1804) /**< (RSTC) Status Register */
|
||||
#define REG_RSTC_MR (0x400E1808) /**< (RSTC) Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_RSTC_CR (*(__O uint32_t*)0x400E1800U) /**< (RSTC) Control Register */
|
||||
#define REG_RSTC_SR (*(__I uint32_t*)0x400E1804U) /**< (RSTC) Status Register */
|
||||
#define REG_RSTC_MR (*(__IO uint32_t*)0x400E1808U) /**< (RSTC) Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for RSTC peripheral ========== */
|
||||
#define RSTC_INSTANCE_ID 1
|
||||
|
||||
#endif /* _SAME70_RSTC_INSTANCE_ */
|
||||
52
lib/same70b/include/instance/rswdt.h
Normal file
52
lib/same70b/include/instance/rswdt.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RSWDT
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_RSWDT_INSTANCE_H_
|
||||
#define _SAME70_RSWDT_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for RSWDT peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_RSWDT_CR (0x400E1900) /**< (RSWDT) Control Register */
|
||||
#define REG_RSWDT_MR (0x400E1904) /**< (RSWDT) Mode Register */
|
||||
#define REG_RSWDT_SR (0x400E1908) /**< (RSWDT) Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_RSWDT_CR (*(__O uint32_t*)0x400E1900U) /**< (RSWDT) Control Register */
|
||||
#define REG_RSWDT_MR (*(__IO uint32_t*)0x400E1904U) /**< (RSWDT) Mode Register */
|
||||
#define REG_RSWDT_SR (*(__I uint32_t*)0x400E1908U) /**< (RSWDT) Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for RSWDT peripheral ========== */
|
||||
#define RSWDT_INSTANCE_ID 63
|
||||
|
||||
#endif /* _SAME70_RSWDT_INSTANCE_ */
|
||||
70
lib/same70b/include/instance/rtc.h
Normal file
70
lib/same70b/include/instance/rtc.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RTC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_RTC_INSTANCE_H_
|
||||
#define _SAME70_RTC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for RTC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_RTC_CR (0x400E1860) /**< (RTC) Control Register */
|
||||
#define REG_RTC_MR (0x400E1864) /**< (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR (0x400E1868) /**< (RTC) Time Register */
|
||||
#define REG_RTC_CALR (0x400E186C) /**< (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR (0x400E1870) /**< (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR (0x400E1874) /**< (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR (0x400E1878) /**< (RTC) Status Register */
|
||||
#define REG_RTC_SCCR (0x400E187C) /**< (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER (0x400E1880) /**< (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR (0x400E1884) /**< (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR (0x400E1888) /**< (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER (0x400E188C) /**< (RTC) Valid Entry Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_RTC_CR (*(__IO uint32_t*)0x400E1860U) /**< (RTC) Control Register */
|
||||
#define REG_RTC_MR (*(__IO uint32_t*)0x400E1864U) /**< (RTC) Mode Register */
|
||||
#define REG_RTC_TIMR (*(__IO uint32_t*)0x400E1868U) /**< (RTC) Time Register */
|
||||
#define REG_RTC_CALR (*(__IO uint32_t*)0x400E186CU) /**< (RTC) Calendar Register */
|
||||
#define REG_RTC_TIMALR (*(__IO uint32_t*)0x400E1870U) /**< (RTC) Time Alarm Register */
|
||||
#define REG_RTC_CALALR (*(__IO uint32_t*)0x400E1874U) /**< (RTC) Calendar Alarm Register */
|
||||
#define REG_RTC_SR (*(__I uint32_t*)0x400E1878U) /**< (RTC) Status Register */
|
||||
#define REG_RTC_SCCR (*(__O uint32_t*)0x400E187CU) /**< (RTC) Status Clear Command Register */
|
||||
#define REG_RTC_IER (*(__O uint32_t*)0x400E1880U) /**< (RTC) Interrupt Enable Register */
|
||||
#define REG_RTC_IDR (*(__O uint32_t*)0x400E1884U) /**< (RTC) Interrupt Disable Register */
|
||||
#define REG_RTC_IMR (*(__I uint32_t*)0x400E1888U) /**< (RTC) Interrupt Mask Register */
|
||||
#define REG_RTC_VER (*(__I uint32_t*)0x400E188CU) /**< (RTC) Valid Entry Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for RTC peripheral ========== */
|
||||
#define RTC_INSTANCE_ID 2
|
||||
|
||||
#endif /* _SAME70_RTC_INSTANCE_ */
|
||||
54
lib/same70b/include/instance/rtt.h
Normal file
54
lib/same70b/include/instance/rtt.h
Normal file
|
|
@ -0,0 +1,54 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for RTT
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_RTT_INSTANCE_H_
|
||||
#define _SAME70_RTT_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for RTT peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_RTT_MR (0x400E1830) /**< (RTT) Mode Register */
|
||||
#define REG_RTT_AR (0x400E1834) /**< (RTT) Alarm Register */
|
||||
#define REG_RTT_VR (0x400E1838) /**< (RTT) Value Register */
|
||||
#define REG_RTT_SR (0x400E183C) /**< (RTT) Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_RTT_MR (*(__IO uint32_t*)0x400E1830U) /**< (RTT) Mode Register */
|
||||
#define REG_RTT_AR (*(__IO uint32_t*)0x400E1834U) /**< (RTT) Alarm Register */
|
||||
#define REG_RTT_VR (*(__I uint32_t*)0x400E1838U) /**< (RTT) Value Register */
|
||||
#define REG_RTT_SR (*(__I uint32_t*)0x400E183CU) /**< (RTT) Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for RTT peripheral ========== */
|
||||
#define RTT_INSTANCE_ID 3
|
||||
|
||||
#endif /* _SAME70_RTT_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/sdramc.h
Normal file
73
lib/same70b/include/instance/sdramc.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SDRAMC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SDRAMC_INSTANCE_H_
|
||||
#define _SAME70_SDRAMC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SDRAMC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SDRAMC_MR (0x40084000) /**< (SDRAMC) SDRAMC Mode Register */
|
||||
#define REG_SDRAMC_TR (0x40084004) /**< (SDRAMC) SDRAMC Refresh Timer Register */
|
||||
#define REG_SDRAMC_CR (0x40084008) /**< (SDRAMC) SDRAMC Configuration Register */
|
||||
#define REG_SDRAMC_LPR (0x40084010) /**< (SDRAMC) SDRAMC Low Power Register */
|
||||
#define REG_SDRAMC_IER (0x40084014) /**< (SDRAMC) SDRAMC Interrupt Enable Register */
|
||||
#define REG_SDRAMC_IDR (0x40084018) /**< (SDRAMC) SDRAMC Interrupt Disable Register */
|
||||
#define REG_SDRAMC_IMR (0x4008401C) /**< (SDRAMC) SDRAMC Interrupt Mask Register */
|
||||
#define REG_SDRAMC_ISR (0x40084020) /**< (SDRAMC) SDRAMC Interrupt Status Register */
|
||||
#define REG_SDRAMC_MDR (0x40084024) /**< (SDRAMC) SDRAMC Memory Device Register */
|
||||
#define REG_SDRAMC_CFR1 (0x40084028) /**< (SDRAMC) SDRAMC Configuration Register 1 */
|
||||
#define REG_SDRAMC_OCMS (0x4008402C) /**< (SDRAMC) SDRAMC OCMS Register */
|
||||
#define REG_SDRAMC_OCMS_KEY1 (0x40084030) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */
|
||||
#define REG_SDRAMC_OCMS_KEY2 (0x40084034) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SDRAMC_MR (*(__IO uint32_t*)0x40084000U) /**< (SDRAMC) SDRAMC Mode Register */
|
||||
#define REG_SDRAMC_TR (*(__IO uint32_t*)0x40084004U) /**< (SDRAMC) SDRAMC Refresh Timer Register */
|
||||
#define REG_SDRAMC_CR (*(__IO uint32_t*)0x40084008U) /**< (SDRAMC) SDRAMC Configuration Register */
|
||||
#define REG_SDRAMC_LPR (*(__IO uint32_t*)0x40084010U) /**< (SDRAMC) SDRAMC Low Power Register */
|
||||
#define REG_SDRAMC_IER (*(__O uint32_t*)0x40084014U) /**< (SDRAMC) SDRAMC Interrupt Enable Register */
|
||||
#define REG_SDRAMC_IDR (*(__O uint32_t*)0x40084018U) /**< (SDRAMC) SDRAMC Interrupt Disable Register */
|
||||
#define REG_SDRAMC_IMR (*(__I uint32_t*)0x4008401CU) /**< (SDRAMC) SDRAMC Interrupt Mask Register */
|
||||
#define REG_SDRAMC_ISR (*(__I uint32_t*)0x40084020U) /**< (SDRAMC) SDRAMC Interrupt Status Register */
|
||||
#define REG_SDRAMC_MDR (*(__IO uint32_t*)0x40084024U) /**< (SDRAMC) SDRAMC Memory Device Register */
|
||||
#define REG_SDRAMC_CFR1 (*(__IO uint32_t*)0x40084028U) /**< (SDRAMC) SDRAMC Configuration Register 1 */
|
||||
#define REG_SDRAMC_OCMS (*(__IO uint32_t*)0x4008402CU) /**< (SDRAMC) SDRAMC OCMS Register */
|
||||
#define REG_SDRAMC_OCMS_KEY1 (*(__O uint32_t*)0x40084030U) /**< (SDRAMC) SDRAMC OCMS KEY1 Register */
|
||||
#define REG_SDRAMC_OCMS_KEY2 (*(__O uint32_t*)0x40084034U) /**< (SDRAMC) SDRAMC OCMS KEY2 Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SDRAMC peripheral ========== */
|
||||
#define SDRAMC_INSTANCE_ID 62
|
||||
#define SDRAMC_CLOCK_ID 62
|
||||
|
||||
#endif /* _SAME70_SDRAMC_INSTANCE_ */
|
||||
89
lib/same70b/include/instance/smc.h
Normal file
89
lib/same70b/include/instance/smc.h
Normal file
|
|
@ -0,0 +1,89 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SMC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SMC_INSTANCE_H_
|
||||
#define _SAME70_SMC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SMC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SMC_SETUP0 (0x40080000) /**< (SMC) SMC Setup Register 0 */
|
||||
#define REG_SMC_PULSE0 (0x40080004) /**< (SMC) SMC Pulse Register 0 */
|
||||
#define REG_SMC_CYCLE0 (0x40080008) /**< (SMC) SMC Cycle Register 0 */
|
||||
#define REG_SMC_MODE0 (0x4008000C) /**< (SMC) SMC Mode Register 0 */
|
||||
#define REG_SMC_SETUP1 (0x40080010) /**< (SMC) SMC Setup Register 1 */
|
||||
#define REG_SMC_PULSE1 (0x40080014) /**< (SMC) SMC Pulse Register 1 */
|
||||
#define REG_SMC_CYCLE1 (0x40080018) /**< (SMC) SMC Cycle Register 1 */
|
||||
#define REG_SMC_MODE1 (0x4008001C) /**< (SMC) SMC Mode Register 1 */
|
||||
#define REG_SMC_SETUP2 (0x40080020) /**< (SMC) SMC Setup Register 2 */
|
||||
#define REG_SMC_PULSE2 (0x40080024) /**< (SMC) SMC Pulse Register 2 */
|
||||
#define REG_SMC_CYCLE2 (0x40080028) /**< (SMC) SMC Cycle Register 2 */
|
||||
#define REG_SMC_MODE2 (0x4008002C) /**< (SMC) SMC Mode Register 2 */
|
||||
#define REG_SMC_SETUP3 (0x40080030) /**< (SMC) SMC Setup Register 3 */
|
||||
#define REG_SMC_PULSE3 (0x40080034) /**< (SMC) SMC Pulse Register 3 */
|
||||
#define REG_SMC_CYCLE3 (0x40080038) /**< (SMC) SMC Cycle Register 3 */
|
||||
#define REG_SMC_MODE3 (0x4008003C) /**< (SMC) SMC Mode Register 3 */
|
||||
#define REG_SMC_OCMS (0x40080080) /**< (SMC) SMC Off-Chip Memory Scrambling Register */
|
||||
#define REG_SMC_KEY1 (0x40080084) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */
|
||||
#define REG_SMC_KEY2 (0x40080088) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */
|
||||
#define REG_SMC_WPMR (0x400800E4) /**< (SMC) SMC Write Protection Mode Register */
|
||||
#define REG_SMC_WPSR (0x400800E8) /**< (SMC) SMC Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SMC_SETUP0 (*(__IO uint32_t*)0x40080000U) /**< (SMC) SMC Setup Register 0 */
|
||||
#define REG_SMC_PULSE0 (*(__IO uint32_t*)0x40080004U) /**< (SMC) SMC Pulse Register 0 */
|
||||
#define REG_SMC_CYCLE0 (*(__IO uint32_t*)0x40080008U) /**< (SMC) SMC Cycle Register 0 */
|
||||
#define REG_SMC_MODE0 (*(__IO uint32_t*)0x4008000CU) /**< (SMC) SMC Mode Register 0 */
|
||||
#define REG_SMC_SETUP1 (*(__IO uint32_t*)0x40080010U) /**< (SMC) SMC Setup Register 1 */
|
||||
#define REG_SMC_PULSE1 (*(__IO uint32_t*)0x40080014U) /**< (SMC) SMC Pulse Register 1 */
|
||||
#define REG_SMC_CYCLE1 (*(__IO uint32_t*)0x40080018U) /**< (SMC) SMC Cycle Register 1 */
|
||||
#define REG_SMC_MODE1 (*(__IO uint32_t*)0x4008001CU) /**< (SMC) SMC Mode Register 1 */
|
||||
#define REG_SMC_SETUP2 (*(__IO uint32_t*)0x40080020U) /**< (SMC) SMC Setup Register 2 */
|
||||
#define REG_SMC_PULSE2 (*(__IO uint32_t*)0x40080024U) /**< (SMC) SMC Pulse Register 2 */
|
||||
#define REG_SMC_CYCLE2 (*(__IO uint32_t*)0x40080028U) /**< (SMC) SMC Cycle Register 2 */
|
||||
#define REG_SMC_MODE2 (*(__IO uint32_t*)0x4008002CU) /**< (SMC) SMC Mode Register 2 */
|
||||
#define REG_SMC_SETUP3 (*(__IO uint32_t*)0x40080030U) /**< (SMC) SMC Setup Register 3 */
|
||||
#define REG_SMC_PULSE3 (*(__IO uint32_t*)0x40080034U) /**< (SMC) SMC Pulse Register 3 */
|
||||
#define REG_SMC_CYCLE3 (*(__IO uint32_t*)0x40080038U) /**< (SMC) SMC Cycle Register 3 */
|
||||
#define REG_SMC_MODE3 (*(__IO uint32_t*)0x4008003CU) /**< (SMC) SMC Mode Register 3 */
|
||||
#define REG_SMC_OCMS (*(__IO uint32_t*)0x40080080U) /**< (SMC) SMC Off-Chip Memory Scrambling Register */
|
||||
#define REG_SMC_KEY1 (*(__O uint32_t*)0x40080084U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY1 Register */
|
||||
#define REG_SMC_KEY2 (*(__O uint32_t*)0x40080088U) /**< (SMC) SMC Off-Chip Memory Scrambling KEY2 Register */
|
||||
#define REG_SMC_WPMR (*(__IO uint32_t*)0x400800E4U) /**< (SMC) SMC Write Protection Mode Register */
|
||||
#define REG_SMC_WPSR (*(__I uint32_t*)0x400800E8U) /**< (SMC) SMC Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SMC peripheral ========== */
|
||||
#define SMC_INSTANCE_ID 9
|
||||
#define SMC_CLOCK_ID 9
|
||||
|
||||
#endif /* _SAME70_SMC_INSTANCE_ */
|
||||
79
lib/same70b/include/instance/spi0.h
Normal file
79
lib/same70b/include/instance/spi0.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SPI0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SPI0_INSTANCE_H_
|
||||
#define _SAME70_SPI0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SPI0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SPI0_CR (0x40008000) /**< (SPI0) Control Register */
|
||||
#define REG_SPI0_MR (0x40008004) /**< (SPI0) Mode Register */
|
||||
#define REG_SPI0_RDR (0x40008008) /**< (SPI0) Receive Data Register */
|
||||
#define REG_SPI0_TDR (0x4000800C) /**< (SPI0) Transmit Data Register */
|
||||
#define REG_SPI0_SR (0x40008010) /**< (SPI0) Status Register */
|
||||
#define REG_SPI0_IER (0x40008014) /**< (SPI0) Interrupt Enable Register */
|
||||
#define REG_SPI0_IDR (0x40008018) /**< (SPI0) Interrupt Disable Register */
|
||||
#define REG_SPI0_IMR (0x4000801C) /**< (SPI0) Interrupt Mask Register */
|
||||
#define REG_SPI0_CSR (0x40008030) /**< (SPI0) Chip Select Register */
|
||||
#define REG_SPI0_CSR0 (0x40008030) /**< (SPI0) Chip Select Register 0 */
|
||||
#define REG_SPI0_CSR1 (0x40008034) /**< (SPI0) Chip Select Register 1 */
|
||||
#define REG_SPI0_CSR2 (0x40008038) /**< (SPI0) Chip Select Register 2 */
|
||||
#define REG_SPI0_CSR3 (0x4000803C) /**< (SPI0) Chip Select Register 3 */
|
||||
#define REG_SPI0_WPMR (0x400080E4) /**< (SPI0) Write Protection Mode Register */
|
||||
#define REG_SPI0_WPSR (0x400080E8) /**< (SPI0) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SPI0_CR (*(__O uint32_t*)0x40008000U) /**< (SPI0) Control Register */
|
||||
#define REG_SPI0_MR (*(__IO uint32_t*)0x40008004U) /**< (SPI0) Mode Register */
|
||||
#define REG_SPI0_RDR (*(__I uint32_t*)0x40008008U) /**< (SPI0) Receive Data Register */
|
||||
#define REG_SPI0_TDR (*(__O uint32_t*)0x4000800CU) /**< (SPI0) Transmit Data Register */
|
||||
#define REG_SPI0_SR (*(__I uint32_t*)0x40008010U) /**< (SPI0) Status Register */
|
||||
#define REG_SPI0_IER (*(__O uint32_t*)0x40008014U) /**< (SPI0) Interrupt Enable Register */
|
||||
#define REG_SPI0_IDR (*(__O uint32_t*)0x40008018U) /**< (SPI0) Interrupt Disable Register */
|
||||
#define REG_SPI0_IMR (*(__I uint32_t*)0x4000801CU) /**< (SPI0) Interrupt Mask Register */
|
||||
#define REG_SPI0_CSR (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register */
|
||||
#define REG_SPI0_CSR0 (*(__IO uint32_t*)0x40008030U) /**< (SPI0) Chip Select Register 0 */
|
||||
#define REG_SPI0_CSR1 (*(__IO uint32_t*)0x40008034U) /**< (SPI0) Chip Select Register 1 */
|
||||
#define REG_SPI0_CSR2 (*(__IO uint32_t*)0x40008038U) /**< (SPI0) Chip Select Register 2 */
|
||||
#define REG_SPI0_CSR3 (*(__IO uint32_t*)0x4000803CU) /**< (SPI0) Chip Select Register 3 */
|
||||
#define REG_SPI0_WPMR (*(__IO uint32_t*)0x400080E4U) /**< (SPI0) Write Protection Mode Register */
|
||||
#define REG_SPI0_WPSR (*(__I uint32_t*)0x400080E8U) /**< (SPI0) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SPI0 peripheral ========== */
|
||||
#define SPI0_DMAC_ID_RX 2
|
||||
#define SPI0_DMAC_ID_TX 1
|
||||
#define SPI0_INSTANCE_ID 21
|
||||
#define SPI0_CLOCK_ID 21
|
||||
|
||||
#endif /* _SAME70_SPI0_INSTANCE_ */
|
||||
79
lib/same70b/include/instance/spi1.h
Normal file
79
lib/same70b/include/instance/spi1.h
Normal file
|
|
@ -0,0 +1,79 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SPI1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SPI1_INSTANCE_H_
|
||||
#define _SAME70_SPI1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SPI1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SPI1_CR (0x40058000) /**< (SPI1) Control Register */
|
||||
#define REG_SPI1_MR (0x40058004) /**< (SPI1) Mode Register */
|
||||
#define REG_SPI1_RDR (0x40058008) /**< (SPI1) Receive Data Register */
|
||||
#define REG_SPI1_TDR (0x4005800C) /**< (SPI1) Transmit Data Register */
|
||||
#define REG_SPI1_SR (0x40058010) /**< (SPI1) Status Register */
|
||||
#define REG_SPI1_IER (0x40058014) /**< (SPI1) Interrupt Enable Register */
|
||||
#define REG_SPI1_IDR (0x40058018) /**< (SPI1) Interrupt Disable Register */
|
||||
#define REG_SPI1_IMR (0x4005801C) /**< (SPI1) Interrupt Mask Register */
|
||||
#define REG_SPI1_CSR (0x40058030) /**< (SPI1) Chip Select Register */
|
||||
#define REG_SPI1_CSR0 (0x40058030) /**< (SPI1) Chip Select Register 0 */
|
||||
#define REG_SPI1_CSR1 (0x40058034) /**< (SPI1) Chip Select Register 1 */
|
||||
#define REG_SPI1_CSR2 (0x40058038) /**< (SPI1) Chip Select Register 2 */
|
||||
#define REG_SPI1_CSR3 (0x4005803C) /**< (SPI1) Chip Select Register 3 */
|
||||
#define REG_SPI1_WPMR (0x400580E4) /**< (SPI1) Write Protection Mode Register */
|
||||
#define REG_SPI1_WPSR (0x400580E8) /**< (SPI1) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SPI1_CR (*(__O uint32_t*)0x40058000U) /**< (SPI1) Control Register */
|
||||
#define REG_SPI1_MR (*(__IO uint32_t*)0x40058004U) /**< (SPI1) Mode Register */
|
||||
#define REG_SPI1_RDR (*(__I uint32_t*)0x40058008U) /**< (SPI1) Receive Data Register */
|
||||
#define REG_SPI1_TDR (*(__O uint32_t*)0x4005800CU) /**< (SPI1) Transmit Data Register */
|
||||
#define REG_SPI1_SR (*(__I uint32_t*)0x40058010U) /**< (SPI1) Status Register */
|
||||
#define REG_SPI1_IER (*(__O uint32_t*)0x40058014U) /**< (SPI1) Interrupt Enable Register */
|
||||
#define REG_SPI1_IDR (*(__O uint32_t*)0x40058018U) /**< (SPI1) Interrupt Disable Register */
|
||||
#define REG_SPI1_IMR (*(__I uint32_t*)0x4005801CU) /**< (SPI1) Interrupt Mask Register */
|
||||
#define REG_SPI1_CSR (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register */
|
||||
#define REG_SPI1_CSR0 (*(__IO uint32_t*)0x40058030U) /**< (SPI1) Chip Select Register 0 */
|
||||
#define REG_SPI1_CSR1 (*(__IO uint32_t*)0x40058034U) /**< (SPI1) Chip Select Register 1 */
|
||||
#define REG_SPI1_CSR2 (*(__IO uint32_t*)0x40058038U) /**< (SPI1) Chip Select Register 2 */
|
||||
#define REG_SPI1_CSR3 (*(__IO uint32_t*)0x4005803CU) /**< (SPI1) Chip Select Register 3 */
|
||||
#define REG_SPI1_WPMR (*(__IO uint32_t*)0x400580E4U) /**< (SPI1) Write Protection Mode Register */
|
||||
#define REG_SPI1_WPSR (*(__I uint32_t*)0x400580E8U) /**< (SPI1) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SPI1 peripheral ========== */
|
||||
#define SPI1_DMAC_ID_RX 4
|
||||
#define SPI1_DMAC_ID_TX 3
|
||||
#define SPI1_INSTANCE_ID 42
|
||||
#define SPI1_CLOCK_ID 42
|
||||
|
||||
#endif /* _SAME70_SPI1_INSTANCE_ */
|
||||
85
lib/same70b/include/instance/ssc.h
Normal file
85
lib/same70b/include/instance/ssc.h
Normal file
|
|
@ -0,0 +1,85 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SSC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SSC_INSTANCE_H_
|
||||
#define _SAME70_SSC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SSC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SSC_CR (0x40004000) /**< (SSC) Control Register */
|
||||
#define REG_SSC_CMR (0x40004004) /**< (SSC) Clock Mode Register */
|
||||
#define REG_SSC_RCMR (0x40004010) /**< (SSC) Receive Clock Mode Register */
|
||||
#define REG_SSC_RFMR (0x40004014) /**< (SSC) Receive Frame Mode Register */
|
||||
#define REG_SSC_TCMR (0x40004018) /**< (SSC) Transmit Clock Mode Register */
|
||||
#define REG_SSC_TFMR (0x4000401C) /**< (SSC) Transmit Frame Mode Register */
|
||||
#define REG_SSC_RHR (0x40004020) /**< (SSC) Receive Holding Register */
|
||||
#define REG_SSC_THR (0x40004024) /**< (SSC) Transmit Holding Register */
|
||||
#define REG_SSC_RSHR (0x40004030) /**< (SSC) Receive Sync. Holding Register */
|
||||
#define REG_SSC_TSHR (0x40004034) /**< (SSC) Transmit Sync. Holding Register */
|
||||
#define REG_SSC_RC0R (0x40004038) /**< (SSC) Receive Compare 0 Register */
|
||||
#define REG_SSC_RC1R (0x4000403C) /**< (SSC) Receive Compare 1 Register */
|
||||
#define REG_SSC_SR (0x40004040) /**< (SSC) Status Register */
|
||||
#define REG_SSC_IER (0x40004044) /**< (SSC) Interrupt Enable Register */
|
||||
#define REG_SSC_IDR (0x40004048) /**< (SSC) Interrupt Disable Register */
|
||||
#define REG_SSC_IMR (0x4000404C) /**< (SSC) Interrupt Mask Register */
|
||||
#define REG_SSC_WPMR (0x400040E4) /**< (SSC) Write Protection Mode Register */
|
||||
#define REG_SSC_WPSR (0x400040E8) /**< (SSC) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SSC_CR (*(__O uint32_t*)0x40004000U) /**< (SSC) Control Register */
|
||||
#define REG_SSC_CMR (*(__IO uint32_t*)0x40004004U) /**< (SSC) Clock Mode Register */
|
||||
#define REG_SSC_RCMR (*(__IO uint32_t*)0x40004010U) /**< (SSC) Receive Clock Mode Register */
|
||||
#define REG_SSC_RFMR (*(__IO uint32_t*)0x40004014U) /**< (SSC) Receive Frame Mode Register */
|
||||
#define REG_SSC_TCMR (*(__IO uint32_t*)0x40004018U) /**< (SSC) Transmit Clock Mode Register */
|
||||
#define REG_SSC_TFMR (*(__IO uint32_t*)0x4000401CU) /**< (SSC) Transmit Frame Mode Register */
|
||||
#define REG_SSC_RHR (*(__I uint32_t*)0x40004020U) /**< (SSC) Receive Holding Register */
|
||||
#define REG_SSC_THR (*(__O uint32_t*)0x40004024U) /**< (SSC) Transmit Holding Register */
|
||||
#define REG_SSC_RSHR (*(__I uint32_t*)0x40004030U) /**< (SSC) Receive Sync. Holding Register */
|
||||
#define REG_SSC_TSHR (*(__IO uint32_t*)0x40004034U) /**< (SSC) Transmit Sync. Holding Register */
|
||||
#define REG_SSC_RC0R (*(__IO uint32_t*)0x40004038U) /**< (SSC) Receive Compare 0 Register */
|
||||
#define REG_SSC_RC1R (*(__IO uint32_t*)0x4000403CU) /**< (SSC) Receive Compare 1 Register */
|
||||
#define REG_SSC_SR (*(__I uint32_t*)0x40004040U) /**< (SSC) Status Register */
|
||||
#define REG_SSC_IER (*(__O uint32_t*)0x40004044U) /**< (SSC) Interrupt Enable Register */
|
||||
#define REG_SSC_IDR (*(__O uint32_t*)0x40004048U) /**< (SSC) Interrupt Disable Register */
|
||||
#define REG_SSC_IMR (*(__I uint32_t*)0x4000404CU) /**< (SSC) Interrupt Mask Register */
|
||||
#define REG_SSC_WPMR (*(__IO uint32_t*)0x400040E4U) /**< (SSC) Write Protection Mode Register */
|
||||
#define REG_SSC_WPSR (*(__I uint32_t*)0x400040E8U) /**< (SSC) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SSC peripheral ========== */
|
||||
#define SSC_DMAC_ID_RX 33
|
||||
#define SSC_DMAC_ID_TX 32
|
||||
#define SSC_INSTANCE_ID 22
|
||||
#define SSC_CLOCK_ID 22
|
||||
|
||||
#endif /* _SAME70_SSC_INSTANCE_ */
|
||||
58
lib/same70b/include/instance/supc.h
Normal file
58
lib/same70b/include/instance/supc.h
Normal file
|
|
@ -0,0 +1,58 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for SUPC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_SUPC_INSTANCE_H_
|
||||
#define _SAME70_SUPC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for SUPC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_SUPC_CR (0x400E1810) /**< (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR (0x400E1814) /**< (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR (0x400E1818) /**< (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR (0x400E181C) /**< (SUPC) Supply Controller Wake-up Mode Register */
|
||||
#define REG_SUPC_WUIR (0x400E1820) /**< (SUPC) Supply Controller Wake-up Inputs Register */
|
||||
#define REG_SUPC_SR (0x400E1824) /**< (SUPC) Supply Controller Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_SUPC_CR (*(__O uint32_t*)0x400E1810U) /**< (SUPC) Supply Controller Control Register */
|
||||
#define REG_SUPC_SMMR (*(__IO uint32_t*)0x400E1814U) /**< (SUPC) Supply Controller Supply Monitor Mode Register */
|
||||
#define REG_SUPC_MR (*(__IO uint32_t*)0x400E1818U) /**< (SUPC) Supply Controller Mode Register */
|
||||
#define REG_SUPC_WUMR (*(__IO uint32_t*)0x400E181CU) /**< (SUPC) Supply Controller Wake-up Mode Register */
|
||||
#define REG_SUPC_WUIR (*(__IO uint32_t*)0x400E1820U) /**< (SUPC) Supply Controller Wake-up Inputs Register */
|
||||
#define REG_SUPC_SR (*(__I uint32_t*)0x400E1824U) /**< (SUPC) Supply Controller Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for SUPC peripheral ========== */
|
||||
#define SUPC_INSTANCE_ID 0
|
||||
|
||||
#endif /* _SAME70_SUPC_INSTANCE_ */
|
||||
157
lib/same70b/include/instance/tc0.h
Normal file
157
lib/same70b/include/instance/tc0.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TC0_INSTANCE_H_
|
||||
#define _SAME70_TC0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TC0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TC0_CCR0 (0x4000C000) /**< (TC0) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC0_CMR0 (0x4000C004) /**< (TC0) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_SMMR0 (0x4000C008) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_RAB0 (0x4000C00C) /**< (TC0) Register AB (channel = 0) 0 */
|
||||
#define REG_TC0_CV0 (0x4000C010) /**< (TC0) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC0_RA0 (0x4000C014) /**< (TC0) Register A (channel = 0) 0 */
|
||||
#define REG_TC0_RB0 (0x4000C018) /**< (TC0) Register B (channel = 0) 0 */
|
||||
#define REG_TC0_RC0 (0x4000C01C) /**< (TC0) Register C (channel = 0) 0 */
|
||||
#define REG_TC0_SR0 (0x4000C020) /**< (TC0) Status Register (channel = 0) 0 */
|
||||
#define REG_TC0_IER0 (0x4000C024) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC0_IDR0 (0x4000C028) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC0_IMR0 (0x4000C02C) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC0_EMR0 (0x4000C030) /**< (TC0) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_CCR1 (0x4000C040) /**< (TC0) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC0_CMR1 (0x4000C044) /**< (TC0) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_SMMR1 (0x4000C048) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_RAB1 (0x4000C04C) /**< (TC0) Register AB (channel = 0) 1 */
|
||||
#define REG_TC0_CV1 (0x4000C050) /**< (TC0) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC0_RA1 (0x4000C054) /**< (TC0) Register A (channel = 0) 1 */
|
||||
#define REG_TC0_RB1 (0x4000C058) /**< (TC0) Register B (channel = 0) 1 */
|
||||
#define REG_TC0_RC1 (0x4000C05C) /**< (TC0) Register C (channel = 0) 1 */
|
||||
#define REG_TC0_SR1 (0x4000C060) /**< (TC0) Status Register (channel = 0) 1 */
|
||||
#define REG_TC0_IER1 (0x4000C064) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC0_IDR1 (0x4000C068) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC0_IMR1 (0x4000C06C) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC0_EMR1 (0x4000C070) /**< (TC0) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_CCR2 (0x4000C080) /**< (TC0) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC0_CMR2 (0x4000C084) /**< (TC0) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_SMMR2 (0x4000C088) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_RAB2 (0x4000C08C) /**< (TC0) Register AB (channel = 0) 2 */
|
||||
#define REG_TC0_CV2 (0x4000C090) /**< (TC0) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC0_RA2 (0x4000C094) /**< (TC0) Register A (channel = 0) 2 */
|
||||
#define REG_TC0_RB2 (0x4000C098) /**< (TC0) Register B (channel = 0) 2 */
|
||||
#define REG_TC0_RC2 (0x4000C09C) /**< (TC0) Register C (channel = 0) 2 */
|
||||
#define REG_TC0_SR2 (0x4000C0A0) /**< (TC0) Status Register (channel = 0) 2 */
|
||||
#define REG_TC0_IER2 (0x4000C0A4) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC0_IDR2 (0x4000C0A8) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC0_IMR2 (0x4000C0AC) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC0_EMR2 (0x4000C0B0) /**< (TC0) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_BCR (0x4000C0C0) /**< (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR (0x4000C0C4) /**< (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER (0x4000C0C8) /**< (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR (0x4000C0CC) /**< (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR (0x4000C0D0) /**< (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR (0x4000C0D4) /**< (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_FMR (0x4000C0D8) /**< (TC0) Fault Mode Register */
|
||||
#define REG_TC0_WPMR (0x4000C0E4) /**< (TC0) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TC0_CCR0 (*(__O uint32_t*)0x4000C000U) /**< (TC0) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC0_CMR0 (*(__IO uint32_t*)0x4000C004U) /**< (TC0) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_SMMR0 (*(__IO uint32_t*)0x4000C008U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_RAB0 (*(__I uint32_t*)0x4000C00CU) /**< (TC0) Register AB (channel = 0) 0 */
|
||||
#define REG_TC0_CV0 (*(__I uint32_t*)0x4000C010U) /**< (TC0) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC0_RA0 (*(__IO uint32_t*)0x4000C014U) /**< (TC0) Register A (channel = 0) 0 */
|
||||
#define REG_TC0_RB0 (*(__IO uint32_t*)0x4000C018U) /**< (TC0) Register B (channel = 0) 0 */
|
||||
#define REG_TC0_RC0 (*(__IO uint32_t*)0x4000C01CU) /**< (TC0) Register C (channel = 0) 0 */
|
||||
#define REG_TC0_SR0 (*(__I uint32_t*)0x4000C020U) /**< (TC0) Status Register (channel = 0) 0 */
|
||||
#define REG_TC0_IER0 (*(__O uint32_t*)0x4000C024U) /**< (TC0) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC0_IDR0 (*(__O uint32_t*)0x4000C028U) /**< (TC0) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC0_IMR0 (*(__I uint32_t*)0x4000C02CU) /**< (TC0) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC0_EMR0 (*(__IO uint32_t*)0x4000C030U) /**< (TC0) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC0_CCR1 (*(__O uint32_t*)0x4000C040U) /**< (TC0) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC0_CMR1 (*(__IO uint32_t*)0x4000C044U) /**< (TC0) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_SMMR1 (*(__IO uint32_t*)0x4000C048U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_RAB1 (*(__I uint32_t*)0x4000C04CU) /**< (TC0) Register AB (channel = 0) 1 */
|
||||
#define REG_TC0_CV1 (*(__I uint32_t*)0x4000C050U) /**< (TC0) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC0_RA1 (*(__IO uint32_t*)0x4000C054U) /**< (TC0) Register A (channel = 0) 1 */
|
||||
#define REG_TC0_RB1 (*(__IO uint32_t*)0x4000C058U) /**< (TC0) Register B (channel = 0) 1 */
|
||||
#define REG_TC0_RC1 (*(__IO uint32_t*)0x4000C05CU) /**< (TC0) Register C (channel = 0) 1 */
|
||||
#define REG_TC0_SR1 (*(__I uint32_t*)0x4000C060U) /**< (TC0) Status Register (channel = 0) 1 */
|
||||
#define REG_TC0_IER1 (*(__O uint32_t*)0x4000C064U) /**< (TC0) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC0_IDR1 (*(__O uint32_t*)0x4000C068U) /**< (TC0) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC0_IMR1 (*(__I uint32_t*)0x4000C06CU) /**< (TC0) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC0_EMR1 (*(__IO uint32_t*)0x4000C070U) /**< (TC0) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC0_CCR2 (*(__O uint32_t*)0x4000C080U) /**< (TC0) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC0_CMR2 (*(__IO uint32_t*)0x4000C084U) /**< (TC0) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_SMMR2 (*(__IO uint32_t*)0x4000C088U) /**< (TC0) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_RAB2 (*(__I uint32_t*)0x4000C08CU) /**< (TC0) Register AB (channel = 0) 2 */
|
||||
#define REG_TC0_CV2 (*(__I uint32_t*)0x4000C090U) /**< (TC0) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC0_RA2 (*(__IO uint32_t*)0x4000C094U) /**< (TC0) Register A (channel = 0) 2 */
|
||||
#define REG_TC0_RB2 (*(__IO uint32_t*)0x4000C098U) /**< (TC0) Register B (channel = 0) 2 */
|
||||
#define REG_TC0_RC2 (*(__IO uint32_t*)0x4000C09CU) /**< (TC0) Register C (channel = 0) 2 */
|
||||
#define REG_TC0_SR2 (*(__I uint32_t*)0x4000C0A0U) /**< (TC0) Status Register (channel = 0) 2 */
|
||||
#define REG_TC0_IER2 (*(__O uint32_t*)0x4000C0A4U) /**< (TC0) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC0_IDR2 (*(__O uint32_t*)0x4000C0A8U) /**< (TC0) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC0_IMR2 (*(__I uint32_t*)0x4000C0ACU) /**< (TC0) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC0_EMR2 (*(__IO uint32_t*)0x4000C0B0U) /**< (TC0) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC0_BCR (*(__O uint32_t*)0x4000C0C0U) /**< (TC0) Block Control Register */
|
||||
#define REG_TC0_BMR (*(__IO uint32_t*)0x4000C0C4U) /**< (TC0) Block Mode Register */
|
||||
#define REG_TC0_QIER (*(__O uint32_t*)0x4000C0C8U) /**< (TC0) QDEC Interrupt Enable Register */
|
||||
#define REG_TC0_QIDR (*(__O uint32_t*)0x4000C0CCU) /**< (TC0) QDEC Interrupt Disable Register */
|
||||
#define REG_TC0_QIMR (*(__I uint32_t*)0x4000C0D0U) /**< (TC0) QDEC Interrupt Mask Register */
|
||||
#define REG_TC0_QISR (*(__I uint32_t*)0x4000C0D4U) /**< (TC0) QDEC Interrupt Status Register */
|
||||
#define REG_TC0_FMR (*(__IO uint32_t*)0x4000C0D8U) /**< (TC0) Fault Mode Register */
|
||||
#define REG_TC0_WPMR (*(__IO uint32_t*)0x4000C0E4U) /**< (TC0) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TC0 peripheral ========== */
|
||||
#define TC0_DMAC_ID_RX 40
|
||||
#define TC0_INSTANCE_ID_CHANNEL0 23
|
||||
#define TC0_INSTANCE_ID_CHANNEL1 24
|
||||
#define TC0_INSTANCE_ID_CHANNEL2 25
|
||||
#define TC0_CLOCK_ID_CHANNEL0 23
|
||||
#define TC0_CLOCK_ID_CHANNEL1 24
|
||||
#define TC0_CLOCK_ID_CHANNEL2 25
|
||||
#define TC0_TCCLKS_ 0 /* MCK */
|
||||
#define TC0_TCCLKS_TIMER_CLOCK1 1 /* PCK */
|
||||
#define TC0_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */
|
||||
#define TC0_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */
|
||||
#define TC0_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */
|
||||
#define TC0_TCCLKS_TIMER_CLOCK5 5 /* SLCK */
|
||||
#define TC0_TCCLKS_XC0 6 /* XC0 */
|
||||
#define TC0_TCCLKS_XC1 7 /* XC1 */
|
||||
#define TC0_TCCLKS_XC2 8 /* XC2 */
|
||||
#define TC0_NUM_INTERRUPT_LINES 3
|
||||
#define TC0_TIMER_WIDTH 16
|
||||
|
||||
#endif /* _SAME70_TC0_INSTANCE_ */
|
||||
157
lib/same70b/include/instance/tc1.h
Normal file
157
lib/same70b/include/instance/tc1.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TC1_INSTANCE_H_
|
||||
#define _SAME70_TC1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TC1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TC1_CCR0 (0x40010000) /**< (TC1) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC1_CMR0 (0x40010004) /**< (TC1) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_SMMR0 (0x40010008) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_RAB0 (0x4001000C) /**< (TC1) Register AB (channel = 0) 0 */
|
||||
#define REG_TC1_CV0 (0x40010010) /**< (TC1) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC1_RA0 (0x40010014) /**< (TC1) Register A (channel = 0) 0 */
|
||||
#define REG_TC1_RB0 (0x40010018) /**< (TC1) Register B (channel = 0) 0 */
|
||||
#define REG_TC1_RC0 (0x4001001C) /**< (TC1) Register C (channel = 0) 0 */
|
||||
#define REG_TC1_SR0 (0x40010020) /**< (TC1) Status Register (channel = 0) 0 */
|
||||
#define REG_TC1_IER0 (0x40010024) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC1_IDR0 (0x40010028) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC1_IMR0 (0x4001002C) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC1_EMR0 (0x40010030) /**< (TC1) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_CCR1 (0x40010040) /**< (TC1) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC1_CMR1 (0x40010044) /**< (TC1) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_SMMR1 (0x40010048) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_RAB1 (0x4001004C) /**< (TC1) Register AB (channel = 0) 1 */
|
||||
#define REG_TC1_CV1 (0x40010050) /**< (TC1) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC1_RA1 (0x40010054) /**< (TC1) Register A (channel = 0) 1 */
|
||||
#define REG_TC1_RB1 (0x40010058) /**< (TC1) Register B (channel = 0) 1 */
|
||||
#define REG_TC1_RC1 (0x4001005C) /**< (TC1) Register C (channel = 0) 1 */
|
||||
#define REG_TC1_SR1 (0x40010060) /**< (TC1) Status Register (channel = 0) 1 */
|
||||
#define REG_TC1_IER1 (0x40010064) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC1_IDR1 (0x40010068) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC1_IMR1 (0x4001006C) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC1_EMR1 (0x40010070) /**< (TC1) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_CCR2 (0x40010080) /**< (TC1) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC1_CMR2 (0x40010084) /**< (TC1) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_SMMR2 (0x40010088) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_RAB2 (0x4001008C) /**< (TC1) Register AB (channel = 0) 2 */
|
||||
#define REG_TC1_CV2 (0x40010090) /**< (TC1) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC1_RA2 (0x40010094) /**< (TC1) Register A (channel = 0) 2 */
|
||||
#define REG_TC1_RB2 (0x40010098) /**< (TC1) Register B (channel = 0) 2 */
|
||||
#define REG_TC1_RC2 (0x4001009C) /**< (TC1) Register C (channel = 0) 2 */
|
||||
#define REG_TC1_SR2 (0x400100A0) /**< (TC1) Status Register (channel = 0) 2 */
|
||||
#define REG_TC1_IER2 (0x400100A4) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC1_IDR2 (0x400100A8) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC1_IMR2 (0x400100AC) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC1_EMR2 (0x400100B0) /**< (TC1) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_BCR (0x400100C0) /**< (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR (0x400100C4) /**< (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER (0x400100C8) /**< (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR (0x400100CC) /**< (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR (0x400100D0) /**< (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR (0x400100D4) /**< (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_FMR (0x400100D8) /**< (TC1) Fault Mode Register */
|
||||
#define REG_TC1_WPMR (0x400100E4) /**< (TC1) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TC1_CCR0 (*(__O uint32_t*)0x40010000U) /**< (TC1) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC1_CMR0 (*(__IO uint32_t*)0x40010004U) /**< (TC1) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_SMMR0 (*(__IO uint32_t*)0x40010008U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_RAB0 (*(__I uint32_t*)0x4001000CU) /**< (TC1) Register AB (channel = 0) 0 */
|
||||
#define REG_TC1_CV0 (*(__I uint32_t*)0x40010010U) /**< (TC1) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC1_RA0 (*(__IO uint32_t*)0x40010014U) /**< (TC1) Register A (channel = 0) 0 */
|
||||
#define REG_TC1_RB0 (*(__IO uint32_t*)0x40010018U) /**< (TC1) Register B (channel = 0) 0 */
|
||||
#define REG_TC1_RC0 (*(__IO uint32_t*)0x4001001CU) /**< (TC1) Register C (channel = 0) 0 */
|
||||
#define REG_TC1_SR0 (*(__I uint32_t*)0x40010020U) /**< (TC1) Status Register (channel = 0) 0 */
|
||||
#define REG_TC1_IER0 (*(__O uint32_t*)0x40010024U) /**< (TC1) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC1_IDR0 (*(__O uint32_t*)0x40010028U) /**< (TC1) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC1_IMR0 (*(__I uint32_t*)0x4001002CU) /**< (TC1) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC1_EMR0 (*(__IO uint32_t*)0x40010030U) /**< (TC1) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC1_CCR1 (*(__O uint32_t*)0x40010040U) /**< (TC1) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC1_CMR1 (*(__IO uint32_t*)0x40010044U) /**< (TC1) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_SMMR1 (*(__IO uint32_t*)0x40010048U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_RAB1 (*(__I uint32_t*)0x4001004CU) /**< (TC1) Register AB (channel = 0) 1 */
|
||||
#define REG_TC1_CV1 (*(__I uint32_t*)0x40010050U) /**< (TC1) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC1_RA1 (*(__IO uint32_t*)0x40010054U) /**< (TC1) Register A (channel = 0) 1 */
|
||||
#define REG_TC1_RB1 (*(__IO uint32_t*)0x40010058U) /**< (TC1) Register B (channel = 0) 1 */
|
||||
#define REG_TC1_RC1 (*(__IO uint32_t*)0x4001005CU) /**< (TC1) Register C (channel = 0) 1 */
|
||||
#define REG_TC1_SR1 (*(__I uint32_t*)0x40010060U) /**< (TC1) Status Register (channel = 0) 1 */
|
||||
#define REG_TC1_IER1 (*(__O uint32_t*)0x40010064U) /**< (TC1) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC1_IDR1 (*(__O uint32_t*)0x40010068U) /**< (TC1) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC1_IMR1 (*(__I uint32_t*)0x4001006CU) /**< (TC1) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC1_EMR1 (*(__IO uint32_t*)0x40010070U) /**< (TC1) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC1_CCR2 (*(__O uint32_t*)0x40010080U) /**< (TC1) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC1_CMR2 (*(__IO uint32_t*)0x40010084U) /**< (TC1) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_SMMR2 (*(__IO uint32_t*)0x40010088U) /**< (TC1) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_RAB2 (*(__I uint32_t*)0x4001008CU) /**< (TC1) Register AB (channel = 0) 2 */
|
||||
#define REG_TC1_CV2 (*(__I uint32_t*)0x40010090U) /**< (TC1) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC1_RA2 (*(__IO uint32_t*)0x40010094U) /**< (TC1) Register A (channel = 0) 2 */
|
||||
#define REG_TC1_RB2 (*(__IO uint32_t*)0x40010098U) /**< (TC1) Register B (channel = 0) 2 */
|
||||
#define REG_TC1_RC2 (*(__IO uint32_t*)0x4001009CU) /**< (TC1) Register C (channel = 0) 2 */
|
||||
#define REG_TC1_SR2 (*(__I uint32_t*)0x400100A0U) /**< (TC1) Status Register (channel = 0) 2 */
|
||||
#define REG_TC1_IER2 (*(__O uint32_t*)0x400100A4U) /**< (TC1) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC1_IDR2 (*(__O uint32_t*)0x400100A8U) /**< (TC1) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC1_IMR2 (*(__I uint32_t*)0x400100ACU) /**< (TC1) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC1_EMR2 (*(__IO uint32_t*)0x400100B0U) /**< (TC1) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC1_BCR (*(__O uint32_t*)0x400100C0U) /**< (TC1) Block Control Register */
|
||||
#define REG_TC1_BMR (*(__IO uint32_t*)0x400100C4U) /**< (TC1) Block Mode Register */
|
||||
#define REG_TC1_QIER (*(__O uint32_t*)0x400100C8U) /**< (TC1) QDEC Interrupt Enable Register */
|
||||
#define REG_TC1_QIDR (*(__O uint32_t*)0x400100CCU) /**< (TC1) QDEC Interrupt Disable Register */
|
||||
#define REG_TC1_QIMR (*(__I uint32_t*)0x400100D0U) /**< (TC1) QDEC Interrupt Mask Register */
|
||||
#define REG_TC1_QISR (*(__I uint32_t*)0x400100D4U) /**< (TC1) QDEC Interrupt Status Register */
|
||||
#define REG_TC1_FMR (*(__IO uint32_t*)0x400100D8U) /**< (TC1) Fault Mode Register */
|
||||
#define REG_TC1_WPMR (*(__IO uint32_t*)0x400100E4U) /**< (TC1) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TC1 peripheral ========== */
|
||||
#define TC1_DMAC_ID_RX 41
|
||||
#define TC1_INSTANCE_ID_CHANNEL0 26
|
||||
#define TC1_INSTANCE_ID_CHANNEL1 27
|
||||
#define TC1_INSTANCE_ID_CHANNEL2 28
|
||||
#define TC1_CLOCK_ID_CHANNEL0 26
|
||||
#define TC1_CLOCK_ID_CHANNEL1 27
|
||||
#define TC1_CLOCK_ID_CHANNEL2 28
|
||||
#define TC1_TCCLKS_ 0 /* MCK */
|
||||
#define TC1_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */
|
||||
#define TC1_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */
|
||||
#define TC1_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */
|
||||
#define TC1_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */
|
||||
#define TC1_TCCLKS_TIMER_CLOCK5 5 /* SLCK */
|
||||
#define TC1_TCCLKS_XC0 6 /* XC0 */
|
||||
#define TC1_TCCLKS_XC1 7 /* XC1 */
|
||||
#define TC1_TCCLKS_XC2 8 /* XC2 */
|
||||
#define TC1_NUM_INTERRUPT_LINES 3
|
||||
#define TC1_TIMER_WIDTH 16
|
||||
|
||||
#endif /* _SAME70_TC1_INSTANCE_ */
|
||||
157
lib/same70b/include/instance/tc2.h
Normal file
157
lib/same70b/include/instance/tc2.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC2
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TC2_INSTANCE_H_
|
||||
#define _SAME70_TC2_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TC2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TC2_CCR0 (0x40014000) /**< (TC2) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC2_CMR0 (0x40014004) /**< (TC2) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_SMMR0 (0x40014008) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_RAB0 (0x4001400C) /**< (TC2) Register AB (channel = 0) 0 */
|
||||
#define REG_TC2_CV0 (0x40014010) /**< (TC2) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC2_RA0 (0x40014014) /**< (TC2) Register A (channel = 0) 0 */
|
||||
#define REG_TC2_RB0 (0x40014018) /**< (TC2) Register B (channel = 0) 0 */
|
||||
#define REG_TC2_RC0 (0x4001401C) /**< (TC2) Register C (channel = 0) 0 */
|
||||
#define REG_TC2_SR0 (0x40014020) /**< (TC2) Status Register (channel = 0) 0 */
|
||||
#define REG_TC2_IER0 (0x40014024) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC2_IDR0 (0x40014028) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC2_IMR0 (0x4001402C) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC2_EMR0 (0x40014030) /**< (TC2) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_CCR1 (0x40014040) /**< (TC2) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC2_CMR1 (0x40014044) /**< (TC2) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_SMMR1 (0x40014048) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_RAB1 (0x4001404C) /**< (TC2) Register AB (channel = 0) 1 */
|
||||
#define REG_TC2_CV1 (0x40014050) /**< (TC2) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC2_RA1 (0x40014054) /**< (TC2) Register A (channel = 0) 1 */
|
||||
#define REG_TC2_RB1 (0x40014058) /**< (TC2) Register B (channel = 0) 1 */
|
||||
#define REG_TC2_RC1 (0x4001405C) /**< (TC2) Register C (channel = 0) 1 */
|
||||
#define REG_TC2_SR1 (0x40014060) /**< (TC2) Status Register (channel = 0) 1 */
|
||||
#define REG_TC2_IER1 (0x40014064) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC2_IDR1 (0x40014068) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC2_IMR1 (0x4001406C) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC2_EMR1 (0x40014070) /**< (TC2) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_CCR2 (0x40014080) /**< (TC2) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC2_CMR2 (0x40014084) /**< (TC2) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_SMMR2 (0x40014088) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_RAB2 (0x4001408C) /**< (TC2) Register AB (channel = 0) 2 */
|
||||
#define REG_TC2_CV2 (0x40014090) /**< (TC2) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC2_RA2 (0x40014094) /**< (TC2) Register A (channel = 0) 2 */
|
||||
#define REG_TC2_RB2 (0x40014098) /**< (TC2) Register B (channel = 0) 2 */
|
||||
#define REG_TC2_RC2 (0x4001409C) /**< (TC2) Register C (channel = 0) 2 */
|
||||
#define REG_TC2_SR2 (0x400140A0) /**< (TC2) Status Register (channel = 0) 2 */
|
||||
#define REG_TC2_IER2 (0x400140A4) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC2_IDR2 (0x400140A8) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC2_IMR2 (0x400140AC) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC2_EMR2 (0x400140B0) /**< (TC2) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_BCR (0x400140C0) /**< (TC2) Block Control Register */
|
||||
#define REG_TC2_BMR (0x400140C4) /**< (TC2) Block Mode Register */
|
||||
#define REG_TC2_QIER (0x400140C8) /**< (TC2) QDEC Interrupt Enable Register */
|
||||
#define REG_TC2_QIDR (0x400140CC) /**< (TC2) QDEC Interrupt Disable Register */
|
||||
#define REG_TC2_QIMR (0x400140D0) /**< (TC2) QDEC Interrupt Mask Register */
|
||||
#define REG_TC2_QISR (0x400140D4) /**< (TC2) QDEC Interrupt Status Register */
|
||||
#define REG_TC2_FMR (0x400140D8) /**< (TC2) Fault Mode Register */
|
||||
#define REG_TC2_WPMR (0x400140E4) /**< (TC2) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TC2_CCR0 (*(__O uint32_t*)0x40014000U) /**< (TC2) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC2_CMR0 (*(__IO uint32_t*)0x40014004U) /**< (TC2) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_SMMR0 (*(__IO uint32_t*)0x40014008U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_RAB0 (*(__I uint32_t*)0x4001400CU) /**< (TC2) Register AB (channel = 0) 0 */
|
||||
#define REG_TC2_CV0 (*(__I uint32_t*)0x40014010U) /**< (TC2) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC2_RA0 (*(__IO uint32_t*)0x40014014U) /**< (TC2) Register A (channel = 0) 0 */
|
||||
#define REG_TC2_RB0 (*(__IO uint32_t*)0x40014018U) /**< (TC2) Register B (channel = 0) 0 */
|
||||
#define REG_TC2_RC0 (*(__IO uint32_t*)0x4001401CU) /**< (TC2) Register C (channel = 0) 0 */
|
||||
#define REG_TC2_SR0 (*(__I uint32_t*)0x40014020U) /**< (TC2) Status Register (channel = 0) 0 */
|
||||
#define REG_TC2_IER0 (*(__O uint32_t*)0x40014024U) /**< (TC2) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC2_IDR0 (*(__O uint32_t*)0x40014028U) /**< (TC2) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC2_IMR0 (*(__I uint32_t*)0x4001402CU) /**< (TC2) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC2_EMR0 (*(__IO uint32_t*)0x40014030U) /**< (TC2) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC2_CCR1 (*(__O uint32_t*)0x40014040U) /**< (TC2) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC2_CMR1 (*(__IO uint32_t*)0x40014044U) /**< (TC2) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_SMMR1 (*(__IO uint32_t*)0x40014048U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_RAB1 (*(__I uint32_t*)0x4001404CU) /**< (TC2) Register AB (channel = 0) 1 */
|
||||
#define REG_TC2_CV1 (*(__I uint32_t*)0x40014050U) /**< (TC2) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC2_RA1 (*(__IO uint32_t*)0x40014054U) /**< (TC2) Register A (channel = 0) 1 */
|
||||
#define REG_TC2_RB1 (*(__IO uint32_t*)0x40014058U) /**< (TC2) Register B (channel = 0) 1 */
|
||||
#define REG_TC2_RC1 (*(__IO uint32_t*)0x4001405CU) /**< (TC2) Register C (channel = 0) 1 */
|
||||
#define REG_TC2_SR1 (*(__I uint32_t*)0x40014060U) /**< (TC2) Status Register (channel = 0) 1 */
|
||||
#define REG_TC2_IER1 (*(__O uint32_t*)0x40014064U) /**< (TC2) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC2_IDR1 (*(__O uint32_t*)0x40014068U) /**< (TC2) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC2_IMR1 (*(__I uint32_t*)0x4001406CU) /**< (TC2) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC2_EMR1 (*(__IO uint32_t*)0x40014070U) /**< (TC2) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC2_CCR2 (*(__O uint32_t*)0x40014080U) /**< (TC2) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC2_CMR2 (*(__IO uint32_t*)0x40014084U) /**< (TC2) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_SMMR2 (*(__IO uint32_t*)0x40014088U) /**< (TC2) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_RAB2 (*(__I uint32_t*)0x4001408CU) /**< (TC2) Register AB (channel = 0) 2 */
|
||||
#define REG_TC2_CV2 (*(__I uint32_t*)0x40014090U) /**< (TC2) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC2_RA2 (*(__IO uint32_t*)0x40014094U) /**< (TC2) Register A (channel = 0) 2 */
|
||||
#define REG_TC2_RB2 (*(__IO uint32_t*)0x40014098U) /**< (TC2) Register B (channel = 0) 2 */
|
||||
#define REG_TC2_RC2 (*(__IO uint32_t*)0x4001409CU) /**< (TC2) Register C (channel = 0) 2 */
|
||||
#define REG_TC2_SR2 (*(__I uint32_t*)0x400140A0U) /**< (TC2) Status Register (channel = 0) 2 */
|
||||
#define REG_TC2_IER2 (*(__O uint32_t*)0x400140A4U) /**< (TC2) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC2_IDR2 (*(__O uint32_t*)0x400140A8U) /**< (TC2) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC2_IMR2 (*(__I uint32_t*)0x400140ACU) /**< (TC2) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC2_EMR2 (*(__IO uint32_t*)0x400140B0U) /**< (TC2) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC2_BCR (*(__O uint32_t*)0x400140C0U) /**< (TC2) Block Control Register */
|
||||
#define REG_TC2_BMR (*(__IO uint32_t*)0x400140C4U) /**< (TC2) Block Mode Register */
|
||||
#define REG_TC2_QIER (*(__O uint32_t*)0x400140C8U) /**< (TC2) QDEC Interrupt Enable Register */
|
||||
#define REG_TC2_QIDR (*(__O uint32_t*)0x400140CCU) /**< (TC2) QDEC Interrupt Disable Register */
|
||||
#define REG_TC2_QIMR (*(__I uint32_t*)0x400140D0U) /**< (TC2) QDEC Interrupt Mask Register */
|
||||
#define REG_TC2_QISR (*(__I uint32_t*)0x400140D4U) /**< (TC2) QDEC Interrupt Status Register */
|
||||
#define REG_TC2_FMR (*(__IO uint32_t*)0x400140D8U) /**< (TC2) Fault Mode Register */
|
||||
#define REG_TC2_WPMR (*(__IO uint32_t*)0x400140E4U) /**< (TC2) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TC2 peripheral ========== */
|
||||
#define TC2_DMAC_ID_RX 42
|
||||
#define TC2_INSTANCE_ID_CHANNEL0 47
|
||||
#define TC2_INSTANCE_ID_CHANNEL1 48
|
||||
#define TC2_INSTANCE_ID_CHANNEL2 49
|
||||
#define TC2_CLOCK_ID_CHANNEL0 47
|
||||
#define TC2_CLOCK_ID_CHANNEL1 48
|
||||
#define TC2_CLOCK_ID_CHANNEL2 49
|
||||
#define TC2_TCCLKS_ 0 /* MCK */
|
||||
#define TC2_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */
|
||||
#define TC2_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */
|
||||
#define TC2_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */
|
||||
#define TC2_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */
|
||||
#define TC2_TCCLKS_TIMER_CLOCK5 5 /* SLCK */
|
||||
#define TC2_TCCLKS_XC0 6 /* XC0 */
|
||||
#define TC2_TCCLKS_XC1 7 /* XC1 */
|
||||
#define TC2_TCCLKS_XC2 8 /* XC2 */
|
||||
#define TC2_NUM_INTERRUPT_LINES 3
|
||||
#define TC2_TIMER_WIDTH 16
|
||||
|
||||
#endif /* _SAME70_TC2_INSTANCE_ */
|
||||
157
lib/same70b/include/instance/tc3.h
Normal file
157
lib/same70b/include/instance/tc3.h
Normal file
|
|
@ -0,0 +1,157 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TC3
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TC3_INSTANCE_H_
|
||||
#define _SAME70_TC3_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TC3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TC3_CCR0 (0x40054000) /**< (TC3) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC3_CMR0 (0x40054004) /**< (TC3) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_SMMR0 (0x40054008) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_RAB0 (0x4005400C) /**< (TC3) Register AB (channel = 0) 0 */
|
||||
#define REG_TC3_CV0 (0x40054010) /**< (TC3) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC3_RA0 (0x40054014) /**< (TC3) Register A (channel = 0) 0 */
|
||||
#define REG_TC3_RB0 (0x40054018) /**< (TC3) Register B (channel = 0) 0 */
|
||||
#define REG_TC3_RC0 (0x4005401C) /**< (TC3) Register C (channel = 0) 0 */
|
||||
#define REG_TC3_SR0 (0x40054020) /**< (TC3) Status Register (channel = 0) 0 */
|
||||
#define REG_TC3_IER0 (0x40054024) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC3_IDR0 (0x40054028) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC3_IMR0 (0x4005402C) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC3_EMR0 (0x40054030) /**< (TC3) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_CCR1 (0x40054040) /**< (TC3) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC3_CMR1 (0x40054044) /**< (TC3) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_SMMR1 (0x40054048) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_RAB1 (0x4005404C) /**< (TC3) Register AB (channel = 0) 1 */
|
||||
#define REG_TC3_CV1 (0x40054050) /**< (TC3) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC3_RA1 (0x40054054) /**< (TC3) Register A (channel = 0) 1 */
|
||||
#define REG_TC3_RB1 (0x40054058) /**< (TC3) Register B (channel = 0) 1 */
|
||||
#define REG_TC3_RC1 (0x4005405C) /**< (TC3) Register C (channel = 0) 1 */
|
||||
#define REG_TC3_SR1 (0x40054060) /**< (TC3) Status Register (channel = 0) 1 */
|
||||
#define REG_TC3_IER1 (0x40054064) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC3_IDR1 (0x40054068) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC3_IMR1 (0x4005406C) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC3_EMR1 (0x40054070) /**< (TC3) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_CCR2 (0x40054080) /**< (TC3) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC3_CMR2 (0x40054084) /**< (TC3) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_SMMR2 (0x40054088) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_RAB2 (0x4005408C) /**< (TC3) Register AB (channel = 0) 2 */
|
||||
#define REG_TC3_CV2 (0x40054090) /**< (TC3) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC3_RA2 (0x40054094) /**< (TC3) Register A (channel = 0) 2 */
|
||||
#define REG_TC3_RB2 (0x40054098) /**< (TC3) Register B (channel = 0) 2 */
|
||||
#define REG_TC3_RC2 (0x4005409C) /**< (TC3) Register C (channel = 0) 2 */
|
||||
#define REG_TC3_SR2 (0x400540A0) /**< (TC3) Status Register (channel = 0) 2 */
|
||||
#define REG_TC3_IER2 (0x400540A4) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC3_IDR2 (0x400540A8) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC3_IMR2 (0x400540AC) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC3_EMR2 (0x400540B0) /**< (TC3) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_BCR (0x400540C0) /**< (TC3) Block Control Register */
|
||||
#define REG_TC3_BMR (0x400540C4) /**< (TC3) Block Mode Register */
|
||||
#define REG_TC3_QIER (0x400540C8) /**< (TC3) QDEC Interrupt Enable Register */
|
||||
#define REG_TC3_QIDR (0x400540CC) /**< (TC3) QDEC Interrupt Disable Register */
|
||||
#define REG_TC3_QIMR (0x400540D0) /**< (TC3) QDEC Interrupt Mask Register */
|
||||
#define REG_TC3_QISR (0x400540D4) /**< (TC3) QDEC Interrupt Status Register */
|
||||
#define REG_TC3_FMR (0x400540D8) /**< (TC3) Fault Mode Register */
|
||||
#define REG_TC3_WPMR (0x400540E4) /**< (TC3) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TC3_CCR0 (*(__O uint32_t*)0x40054000U) /**< (TC3) Channel Control Register (channel = 0) 0 */
|
||||
#define REG_TC3_CMR0 (*(__IO uint32_t*)0x40054004U) /**< (TC3) Channel Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_SMMR0 (*(__IO uint32_t*)0x40054008U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_RAB0 (*(__I uint32_t*)0x4005400CU) /**< (TC3) Register AB (channel = 0) 0 */
|
||||
#define REG_TC3_CV0 (*(__I uint32_t*)0x40054010U) /**< (TC3) Counter Value (channel = 0) 0 */
|
||||
#define REG_TC3_RA0 (*(__IO uint32_t*)0x40054014U) /**< (TC3) Register A (channel = 0) 0 */
|
||||
#define REG_TC3_RB0 (*(__IO uint32_t*)0x40054018U) /**< (TC3) Register B (channel = 0) 0 */
|
||||
#define REG_TC3_RC0 (*(__IO uint32_t*)0x4005401CU) /**< (TC3) Register C (channel = 0) 0 */
|
||||
#define REG_TC3_SR0 (*(__I uint32_t*)0x40054020U) /**< (TC3) Status Register (channel = 0) 0 */
|
||||
#define REG_TC3_IER0 (*(__O uint32_t*)0x40054024U) /**< (TC3) Interrupt Enable Register (channel = 0) 0 */
|
||||
#define REG_TC3_IDR0 (*(__O uint32_t*)0x40054028U) /**< (TC3) Interrupt Disable Register (channel = 0) 0 */
|
||||
#define REG_TC3_IMR0 (*(__I uint32_t*)0x4005402CU) /**< (TC3) Interrupt Mask Register (channel = 0) 0 */
|
||||
#define REG_TC3_EMR0 (*(__IO uint32_t*)0x40054030U) /**< (TC3) Extended Mode Register (channel = 0) 0 */
|
||||
#define REG_TC3_CCR1 (*(__O uint32_t*)0x40054040U) /**< (TC3) Channel Control Register (channel = 0) 1 */
|
||||
#define REG_TC3_CMR1 (*(__IO uint32_t*)0x40054044U) /**< (TC3) Channel Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_SMMR1 (*(__IO uint32_t*)0x40054048U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_RAB1 (*(__I uint32_t*)0x4005404CU) /**< (TC3) Register AB (channel = 0) 1 */
|
||||
#define REG_TC3_CV1 (*(__I uint32_t*)0x40054050U) /**< (TC3) Counter Value (channel = 0) 1 */
|
||||
#define REG_TC3_RA1 (*(__IO uint32_t*)0x40054054U) /**< (TC3) Register A (channel = 0) 1 */
|
||||
#define REG_TC3_RB1 (*(__IO uint32_t*)0x40054058U) /**< (TC3) Register B (channel = 0) 1 */
|
||||
#define REG_TC3_RC1 (*(__IO uint32_t*)0x4005405CU) /**< (TC3) Register C (channel = 0) 1 */
|
||||
#define REG_TC3_SR1 (*(__I uint32_t*)0x40054060U) /**< (TC3) Status Register (channel = 0) 1 */
|
||||
#define REG_TC3_IER1 (*(__O uint32_t*)0x40054064U) /**< (TC3) Interrupt Enable Register (channel = 0) 1 */
|
||||
#define REG_TC3_IDR1 (*(__O uint32_t*)0x40054068U) /**< (TC3) Interrupt Disable Register (channel = 0) 1 */
|
||||
#define REG_TC3_IMR1 (*(__I uint32_t*)0x4005406CU) /**< (TC3) Interrupt Mask Register (channel = 0) 1 */
|
||||
#define REG_TC3_EMR1 (*(__IO uint32_t*)0x40054070U) /**< (TC3) Extended Mode Register (channel = 0) 1 */
|
||||
#define REG_TC3_CCR2 (*(__O uint32_t*)0x40054080U) /**< (TC3) Channel Control Register (channel = 0) 2 */
|
||||
#define REG_TC3_CMR2 (*(__IO uint32_t*)0x40054084U) /**< (TC3) Channel Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_SMMR2 (*(__IO uint32_t*)0x40054088U) /**< (TC3) Stepper Motor Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_RAB2 (*(__I uint32_t*)0x4005408CU) /**< (TC3) Register AB (channel = 0) 2 */
|
||||
#define REG_TC3_CV2 (*(__I uint32_t*)0x40054090U) /**< (TC3) Counter Value (channel = 0) 2 */
|
||||
#define REG_TC3_RA2 (*(__IO uint32_t*)0x40054094U) /**< (TC3) Register A (channel = 0) 2 */
|
||||
#define REG_TC3_RB2 (*(__IO uint32_t*)0x40054098U) /**< (TC3) Register B (channel = 0) 2 */
|
||||
#define REG_TC3_RC2 (*(__IO uint32_t*)0x4005409CU) /**< (TC3) Register C (channel = 0) 2 */
|
||||
#define REG_TC3_SR2 (*(__I uint32_t*)0x400540A0U) /**< (TC3) Status Register (channel = 0) 2 */
|
||||
#define REG_TC3_IER2 (*(__O uint32_t*)0x400540A4U) /**< (TC3) Interrupt Enable Register (channel = 0) 2 */
|
||||
#define REG_TC3_IDR2 (*(__O uint32_t*)0x400540A8U) /**< (TC3) Interrupt Disable Register (channel = 0) 2 */
|
||||
#define REG_TC3_IMR2 (*(__I uint32_t*)0x400540ACU) /**< (TC3) Interrupt Mask Register (channel = 0) 2 */
|
||||
#define REG_TC3_EMR2 (*(__IO uint32_t*)0x400540B0U) /**< (TC3) Extended Mode Register (channel = 0) 2 */
|
||||
#define REG_TC3_BCR (*(__O uint32_t*)0x400540C0U) /**< (TC3) Block Control Register */
|
||||
#define REG_TC3_BMR (*(__IO uint32_t*)0x400540C4U) /**< (TC3) Block Mode Register */
|
||||
#define REG_TC3_QIER (*(__O uint32_t*)0x400540C8U) /**< (TC3) QDEC Interrupt Enable Register */
|
||||
#define REG_TC3_QIDR (*(__O uint32_t*)0x400540CCU) /**< (TC3) QDEC Interrupt Disable Register */
|
||||
#define REG_TC3_QIMR (*(__I uint32_t*)0x400540D0U) /**< (TC3) QDEC Interrupt Mask Register */
|
||||
#define REG_TC3_QISR (*(__I uint32_t*)0x400540D4U) /**< (TC3) QDEC Interrupt Status Register */
|
||||
#define REG_TC3_FMR (*(__IO uint32_t*)0x400540D8U) /**< (TC3) Fault Mode Register */
|
||||
#define REG_TC3_WPMR (*(__IO uint32_t*)0x400540E4U) /**< (TC3) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TC3 peripheral ========== */
|
||||
#define TC3_DMAC_ID_RX 43
|
||||
#define TC3_INSTANCE_ID_CHANNEL0 50
|
||||
#define TC3_INSTANCE_ID_CHANNEL1 51
|
||||
#define TC3_INSTANCE_ID_CHANNEL2 52
|
||||
#define TC3_CLOCK_ID_CHANNEL0 50
|
||||
#define TC3_CLOCK_ID_CHANNEL1 51
|
||||
#define TC3_CLOCK_ID_CHANNEL2 52
|
||||
#define TC3_TCCLKS_ 0 /* MCK */
|
||||
#define TC3_TCCLKS_TIMER_CLOCK1 1 /* PCK6 */
|
||||
#define TC3_TCCLKS_TIMER_CLOCK2 2 /* MCK/8 */
|
||||
#define TC3_TCCLKS_TIMER_CLOCK3 3 /* MCK/32 */
|
||||
#define TC3_TCCLKS_TIMER_CLOCK4 4 /* MCK/128 */
|
||||
#define TC3_TCCLKS_TIMER_CLOCK5 5 /* SLCK */
|
||||
#define TC3_TCCLKS_XC0 6 /* XC0 */
|
||||
#define TC3_TCCLKS_XC1 7 /* XC1 */
|
||||
#define TC3_TCCLKS_XC2 8 /* XC2 */
|
||||
#define TC3_NUM_INTERRUPT_LINES 3
|
||||
#define TC3_TIMER_WIDTH 16
|
||||
|
||||
#endif /* _SAME70_TC3_INSTANCE_ */
|
||||
59
lib/same70b/include/instance/trng.h
Normal file
59
lib/same70b/include/instance/trng.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TRNG
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TRNG_INSTANCE_H_
|
||||
#define _SAME70_TRNG_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TRNG peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TRNG_CR (0x40070000) /**< (TRNG) Control Register */
|
||||
#define REG_TRNG_IER (0x40070010) /**< (TRNG) Interrupt Enable Register */
|
||||
#define REG_TRNG_IDR (0x40070014) /**< (TRNG) Interrupt Disable Register */
|
||||
#define REG_TRNG_IMR (0x40070018) /**< (TRNG) Interrupt Mask Register */
|
||||
#define REG_TRNG_ISR (0x4007001C) /**< (TRNG) Interrupt Status Register */
|
||||
#define REG_TRNG_ODATA (0x40070050) /**< (TRNG) Output Data Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TRNG_CR (*(__O uint32_t*)0x40070000U) /**< (TRNG) Control Register */
|
||||
#define REG_TRNG_IER (*(__O uint32_t*)0x40070010U) /**< (TRNG) Interrupt Enable Register */
|
||||
#define REG_TRNG_IDR (*(__O uint32_t*)0x40070014U) /**< (TRNG) Interrupt Disable Register */
|
||||
#define REG_TRNG_IMR (*(__I uint32_t*)0x40070018U) /**< (TRNG) Interrupt Mask Register */
|
||||
#define REG_TRNG_ISR (*(__I uint32_t*)0x4007001CU) /**< (TRNG) Interrupt Status Register */
|
||||
#define REG_TRNG_ODATA (*(__I uint32_t*)0x40070050U) /**< (TRNG) Output Data Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TRNG peripheral ========== */
|
||||
#define TRNG_INSTANCE_ID 57
|
||||
#define TRNG_CLOCK_ID 57
|
||||
|
||||
#endif /* _SAME70_TRNG_INSTANCE_ */
|
||||
81
lib/same70b/include/instance/twihs0.h
Normal file
81
lib/same70b/include/instance/twihs0.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TWIHS0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TWIHS0_INSTANCE_H_
|
||||
#define _SAME70_TWIHS0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TWIHS0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TWIHS0_CR (0x40018000) /**< (TWIHS0) Control Register */
|
||||
#define REG_TWIHS0_MMR (0x40018004) /**< (TWIHS0) Master Mode Register */
|
||||
#define REG_TWIHS0_SMR (0x40018008) /**< (TWIHS0) Slave Mode Register */
|
||||
#define REG_TWIHS0_IADR (0x4001800C) /**< (TWIHS0) Internal Address Register */
|
||||
#define REG_TWIHS0_CWGR (0x40018010) /**< (TWIHS0) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS0_SR (0x40018020) /**< (TWIHS0) Status Register */
|
||||
#define REG_TWIHS0_IER (0x40018024) /**< (TWIHS0) Interrupt Enable Register */
|
||||
#define REG_TWIHS0_IDR (0x40018028) /**< (TWIHS0) Interrupt Disable Register */
|
||||
#define REG_TWIHS0_IMR (0x4001802C) /**< (TWIHS0) Interrupt Mask Register */
|
||||
#define REG_TWIHS0_RHR (0x40018030) /**< (TWIHS0) Receive Holding Register */
|
||||
#define REG_TWIHS0_THR (0x40018034) /**< (TWIHS0) Transmit Holding Register */
|
||||
#define REG_TWIHS0_SMBTR (0x40018038) /**< (TWIHS0) SMBus Timing Register */
|
||||
#define REG_TWIHS0_FILTR (0x40018044) /**< (TWIHS0) Filter Register */
|
||||
#define REG_TWIHS0_SWMR (0x4001804C) /**< (TWIHS0) SleepWalking Matching Register */
|
||||
#define REG_TWIHS0_WPMR (0x400180E4) /**< (TWIHS0) Write Protection Mode Register */
|
||||
#define REG_TWIHS0_WPSR (0x400180E8) /**< (TWIHS0) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TWIHS0_CR (*(__O uint32_t*)0x40018000U) /**< (TWIHS0) Control Register */
|
||||
#define REG_TWIHS0_MMR (*(__IO uint32_t*)0x40018004U) /**< (TWIHS0) Master Mode Register */
|
||||
#define REG_TWIHS0_SMR (*(__IO uint32_t*)0x40018008U) /**< (TWIHS0) Slave Mode Register */
|
||||
#define REG_TWIHS0_IADR (*(__IO uint32_t*)0x4001800CU) /**< (TWIHS0) Internal Address Register */
|
||||
#define REG_TWIHS0_CWGR (*(__IO uint32_t*)0x40018010U) /**< (TWIHS0) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS0_SR (*(__I uint32_t*)0x40018020U) /**< (TWIHS0) Status Register */
|
||||
#define REG_TWIHS0_IER (*(__O uint32_t*)0x40018024U) /**< (TWIHS0) Interrupt Enable Register */
|
||||
#define REG_TWIHS0_IDR (*(__O uint32_t*)0x40018028U) /**< (TWIHS0) Interrupt Disable Register */
|
||||
#define REG_TWIHS0_IMR (*(__I uint32_t*)0x4001802CU) /**< (TWIHS0) Interrupt Mask Register */
|
||||
#define REG_TWIHS0_RHR (*(__I uint32_t*)0x40018030U) /**< (TWIHS0) Receive Holding Register */
|
||||
#define REG_TWIHS0_THR (*(__O uint32_t*)0x40018034U) /**< (TWIHS0) Transmit Holding Register */
|
||||
#define REG_TWIHS0_SMBTR (*(__IO uint32_t*)0x40018038U) /**< (TWIHS0) SMBus Timing Register */
|
||||
#define REG_TWIHS0_FILTR (*(__IO uint32_t*)0x40018044U) /**< (TWIHS0) Filter Register */
|
||||
#define REG_TWIHS0_SWMR (*(__IO uint32_t*)0x4001804CU) /**< (TWIHS0) SleepWalking Matching Register */
|
||||
#define REG_TWIHS0_WPMR (*(__IO uint32_t*)0x400180E4U) /**< (TWIHS0) Write Protection Mode Register */
|
||||
#define REG_TWIHS0_WPSR (*(__I uint32_t*)0x400180E8U) /**< (TWIHS0) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TWIHS0 peripheral ========== */
|
||||
#define TWIHS0_DMAC_ID_RX 15
|
||||
#define TWIHS0_DMAC_ID_TX 14
|
||||
#define TWIHS0_INSTANCE_ID 19
|
||||
#define TWIHS0_CLOCK_ID 19
|
||||
|
||||
#endif /* _SAME70_TWIHS0_INSTANCE_ */
|
||||
81
lib/same70b/include/instance/twihs1.h
Normal file
81
lib/same70b/include/instance/twihs1.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TWIHS1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TWIHS1_INSTANCE_H_
|
||||
#define _SAME70_TWIHS1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TWIHS1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TWIHS1_CR (0x4001C000) /**< (TWIHS1) Control Register */
|
||||
#define REG_TWIHS1_MMR (0x4001C004) /**< (TWIHS1) Master Mode Register */
|
||||
#define REG_TWIHS1_SMR (0x4001C008) /**< (TWIHS1) Slave Mode Register */
|
||||
#define REG_TWIHS1_IADR (0x4001C00C) /**< (TWIHS1) Internal Address Register */
|
||||
#define REG_TWIHS1_CWGR (0x4001C010) /**< (TWIHS1) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS1_SR (0x4001C020) /**< (TWIHS1) Status Register */
|
||||
#define REG_TWIHS1_IER (0x4001C024) /**< (TWIHS1) Interrupt Enable Register */
|
||||
#define REG_TWIHS1_IDR (0x4001C028) /**< (TWIHS1) Interrupt Disable Register */
|
||||
#define REG_TWIHS1_IMR (0x4001C02C) /**< (TWIHS1) Interrupt Mask Register */
|
||||
#define REG_TWIHS1_RHR (0x4001C030) /**< (TWIHS1) Receive Holding Register */
|
||||
#define REG_TWIHS1_THR (0x4001C034) /**< (TWIHS1) Transmit Holding Register */
|
||||
#define REG_TWIHS1_SMBTR (0x4001C038) /**< (TWIHS1) SMBus Timing Register */
|
||||
#define REG_TWIHS1_FILTR (0x4001C044) /**< (TWIHS1) Filter Register */
|
||||
#define REG_TWIHS1_SWMR (0x4001C04C) /**< (TWIHS1) SleepWalking Matching Register */
|
||||
#define REG_TWIHS1_WPMR (0x4001C0E4) /**< (TWIHS1) Write Protection Mode Register */
|
||||
#define REG_TWIHS1_WPSR (0x4001C0E8) /**< (TWIHS1) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TWIHS1_CR (*(__O uint32_t*)0x4001C000U) /**< (TWIHS1) Control Register */
|
||||
#define REG_TWIHS1_MMR (*(__IO uint32_t*)0x4001C004U) /**< (TWIHS1) Master Mode Register */
|
||||
#define REG_TWIHS1_SMR (*(__IO uint32_t*)0x4001C008U) /**< (TWIHS1) Slave Mode Register */
|
||||
#define REG_TWIHS1_IADR (*(__IO uint32_t*)0x4001C00CU) /**< (TWIHS1) Internal Address Register */
|
||||
#define REG_TWIHS1_CWGR (*(__IO uint32_t*)0x4001C010U) /**< (TWIHS1) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS1_SR (*(__I uint32_t*)0x4001C020U) /**< (TWIHS1) Status Register */
|
||||
#define REG_TWIHS1_IER (*(__O uint32_t*)0x4001C024U) /**< (TWIHS1) Interrupt Enable Register */
|
||||
#define REG_TWIHS1_IDR (*(__O uint32_t*)0x4001C028U) /**< (TWIHS1) Interrupt Disable Register */
|
||||
#define REG_TWIHS1_IMR (*(__I uint32_t*)0x4001C02CU) /**< (TWIHS1) Interrupt Mask Register */
|
||||
#define REG_TWIHS1_RHR (*(__I uint32_t*)0x4001C030U) /**< (TWIHS1) Receive Holding Register */
|
||||
#define REG_TWIHS1_THR (*(__O uint32_t*)0x4001C034U) /**< (TWIHS1) Transmit Holding Register */
|
||||
#define REG_TWIHS1_SMBTR (*(__IO uint32_t*)0x4001C038U) /**< (TWIHS1) SMBus Timing Register */
|
||||
#define REG_TWIHS1_FILTR (*(__IO uint32_t*)0x4001C044U) /**< (TWIHS1) Filter Register */
|
||||
#define REG_TWIHS1_SWMR (*(__IO uint32_t*)0x4001C04CU) /**< (TWIHS1) SleepWalking Matching Register */
|
||||
#define REG_TWIHS1_WPMR (*(__IO uint32_t*)0x4001C0E4U) /**< (TWIHS1) Write Protection Mode Register */
|
||||
#define REG_TWIHS1_WPSR (*(__I uint32_t*)0x4001C0E8U) /**< (TWIHS1) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TWIHS1 peripheral ========== */
|
||||
#define TWIHS1_DMAC_ID_RX 17
|
||||
#define TWIHS1_DMAC_ID_TX 16
|
||||
#define TWIHS1_INSTANCE_ID 20
|
||||
#define TWIHS1_CLOCK_ID 20
|
||||
|
||||
#endif /* _SAME70_TWIHS1_INSTANCE_ */
|
||||
81
lib/same70b/include/instance/twihs2.h
Normal file
81
lib/same70b/include/instance/twihs2.h
Normal file
|
|
@ -0,0 +1,81 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for TWIHS2
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_TWIHS2_INSTANCE_H_
|
||||
#define _SAME70_TWIHS2_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for TWIHS2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_TWIHS2_CR (0x40060000) /**< (TWIHS2) Control Register */
|
||||
#define REG_TWIHS2_MMR (0x40060004) /**< (TWIHS2) Master Mode Register */
|
||||
#define REG_TWIHS2_SMR (0x40060008) /**< (TWIHS2) Slave Mode Register */
|
||||
#define REG_TWIHS2_IADR (0x4006000C) /**< (TWIHS2) Internal Address Register */
|
||||
#define REG_TWIHS2_CWGR (0x40060010) /**< (TWIHS2) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS2_SR (0x40060020) /**< (TWIHS2) Status Register */
|
||||
#define REG_TWIHS2_IER (0x40060024) /**< (TWIHS2) Interrupt Enable Register */
|
||||
#define REG_TWIHS2_IDR (0x40060028) /**< (TWIHS2) Interrupt Disable Register */
|
||||
#define REG_TWIHS2_IMR (0x4006002C) /**< (TWIHS2) Interrupt Mask Register */
|
||||
#define REG_TWIHS2_RHR (0x40060030) /**< (TWIHS2) Receive Holding Register */
|
||||
#define REG_TWIHS2_THR (0x40060034) /**< (TWIHS2) Transmit Holding Register */
|
||||
#define REG_TWIHS2_SMBTR (0x40060038) /**< (TWIHS2) SMBus Timing Register */
|
||||
#define REG_TWIHS2_FILTR (0x40060044) /**< (TWIHS2) Filter Register */
|
||||
#define REG_TWIHS2_SWMR (0x4006004C) /**< (TWIHS2) SleepWalking Matching Register */
|
||||
#define REG_TWIHS2_WPMR (0x400600E4) /**< (TWIHS2) Write Protection Mode Register */
|
||||
#define REG_TWIHS2_WPSR (0x400600E8) /**< (TWIHS2) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_TWIHS2_CR (*(__O uint32_t*)0x40060000U) /**< (TWIHS2) Control Register */
|
||||
#define REG_TWIHS2_MMR (*(__IO uint32_t*)0x40060004U) /**< (TWIHS2) Master Mode Register */
|
||||
#define REG_TWIHS2_SMR (*(__IO uint32_t*)0x40060008U) /**< (TWIHS2) Slave Mode Register */
|
||||
#define REG_TWIHS2_IADR (*(__IO uint32_t*)0x4006000CU) /**< (TWIHS2) Internal Address Register */
|
||||
#define REG_TWIHS2_CWGR (*(__IO uint32_t*)0x40060010U) /**< (TWIHS2) Clock Waveform Generator Register */
|
||||
#define REG_TWIHS2_SR (*(__I uint32_t*)0x40060020U) /**< (TWIHS2) Status Register */
|
||||
#define REG_TWIHS2_IER (*(__O uint32_t*)0x40060024U) /**< (TWIHS2) Interrupt Enable Register */
|
||||
#define REG_TWIHS2_IDR (*(__O uint32_t*)0x40060028U) /**< (TWIHS2) Interrupt Disable Register */
|
||||
#define REG_TWIHS2_IMR (*(__I uint32_t*)0x4006002CU) /**< (TWIHS2) Interrupt Mask Register */
|
||||
#define REG_TWIHS2_RHR (*(__I uint32_t*)0x40060030U) /**< (TWIHS2) Receive Holding Register */
|
||||
#define REG_TWIHS2_THR (*(__O uint32_t*)0x40060034U) /**< (TWIHS2) Transmit Holding Register */
|
||||
#define REG_TWIHS2_SMBTR (*(__IO uint32_t*)0x40060038U) /**< (TWIHS2) SMBus Timing Register */
|
||||
#define REG_TWIHS2_FILTR (*(__IO uint32_t*)0x40060044U) /**< (TWIHS2) Filter Register */
|
||||
#define REG_TWIHS2_SWMR (*(__IO uint32_t*)0x4006004CU) /**< (TWIHS2) SleepWalking Matching Register */
|
||||
#define REG_TWIHS2_WPMR (*(__IO uint32_t*)0x400600E4U) /**< (TWIHS2) Write Protection Mode Register */
|
||||
#define REG_TWIHS2_WPSR (*(__I uint32_t*)0x400600E8U) /**< (TWIHS2) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for TWIHS2 peripheral ========== */
|
||||
#define TWIHS2_DMAC_ID_RX 19
|
||||
#define TWIHS2_DMAC_ID_TX 18
|
||||
#define TWIHS2_INSTANCE_ID 41
|
||||
#define TWIHS2_CLOCK_ID 41
|
||||
|
||||
#endif /* _SAME70_TWIHS2_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/uart0.h
Normal file
73
lib/same70b/include/instance/uart0.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UART0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UART0_INSTANCE_H_
|
||||
#define _SAME70_UART0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UART0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UART0_CR (0x400E0800) /**< (UART0) Control Register */
|
||||
#define REG_UART0_MR (0x400E0804) /**< (UART0) Mode Register */
|
||||
#define REG_UART0_IER (0x400E0808) /**< (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR (0x400E080C) /**< (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR (0x400E0810) /**< (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR (0x400E0814) /**< (UART0) Status Register */
|
||||
#define REG_UART0_RHR (0x400E0818) /**< (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR (0x400E081C) /**< (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR (0x400E0820) /**< (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_CMPR (0x400E0824) /**< (UART0) Comparison Register */
|
||||
#define REG_UART0_WPMR (0x400E08E4) /**< (UART0) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UART0_CR (*(__O uint32_t*)0x400E0800U) /**< (UART0) Control Register */
|
||||
#define REG_UART0_MR (*(__IO uint32_t*)0x400E0804U) /**< (UART0) Mode Register */
|
||||
#define REG_UART0_IER (*(__O uint32_t*)0x400E0808U) /**< (UART0) Interrupt Enable Register */
|
||||
#define REG_UART0_IDR (*(__O uint32_t*)0x400E080CU) /**< (UART0) Interrupt Disable Register */
|
||||
#define REG_UART0_IMR (*(__I uint32_t*)0x400E0810U) /**< (UART0) Interrupt Mask Register */
|
||||
#define REG_UART0_SR (*(__I uint32_t*)0x400E0814U) /**< (UART0) Status Register */
|
||||
#define REG_UART0_RHR (*(__I uint32_t*)0x400E0818U) /**< (UART0) Receive Holding Register */
|
||||
#define REG_UART0_THR (*(__O uint32_t*)0x400E081CU) /**< (UART0) Transmit Holding Register */
|
||||
#define REG_UART0_BRGR (*(__IO uint32_t*)0x400E0820U) /**< (UART0) Baud Rate Generator Register */
|
||||
#define REG_UART0_CMPR (*(__IO uint32_t*)0x400E0824U) /**< (UART0) Comparison Register */
|
||||
#define REG_UART0_WPMR (*(__IO uint32_t*)0x400E08E4U) /**< (UART0) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for UART0 peripheral ========== */
|
||||
#define UART0_DMAC_ID_RX 21
|
||||
#define UART0_DMAC_ID_TX 20
|
||||
#define UART0_INSTANCE_ID 7
|
||||
#define UART0_CLOCK_ID 7
|
||||
#define UART0_BRSRCCK_PERIPH_CLK 0 /* MCK */
|
||||
#define UART0_BRSRCCK_PMC_PCK 0 /* PCK4 */
|
||||
|
||||
#endif /* _SAME70_UART0_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/uart1.h
Normal file
73
lib/same70b/include/instance/uart1.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UART1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UART1_INSTANCE_H_
|
||||
#define _SAME70_UART1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UART1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UART1_CR (0x400E0A00) /**< (UART1) Control Register */
|
||||
#define REG_UART1_MR (0x400E0A04) /**< (UART1) Mode Register */
|
||||
#define REG_UART1_IER (0x400E0A08) /**< (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR (0x400E0A0C) /**< (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR (0x400E0A10) /**< (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR (0x400E0A14) /**< (UART1) Status Register */
|
||||
#define REG_UART1_RHR (0x400E0A18) /**< (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR (0x400E0A1C) /**< (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR (0x400E0A20) /**< (UART1) Baud Rate Generator Register */
|
||||
#define REG_UART1_CMPR (0x400E0A24) /**< (UART1) Comparison Register */
|
||||
#define REG_UART1_WPMR (0x400E0AE4) /**< (UART1) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UART1_CR (*(__O uint32_t*)0x400E0A00U) /**< (UART1) Control Register */
|
||||
#define REG_UART1_MR (*(__IO uint32_t*)0x400E0A04U) /**< (UART1) Mode Register */
|
||||
#define REG_UART1_IER (*(__O uint32_t*)0x400E0A08U) /**< (UART1) Interrupt Enable Register */
|
||||
#define REG_UART1_IDR (*(__O uint32_t*)0x400E0A0CU) /**< (UART1) Interrupt Disable Register */
|
||||
#define REG_UART1_IMR (*(__I uint32_t*)0x400E0A10U) /**< (UART1) Interrupt Mask Register */
|
||||
#define REG_UART1_SR (*(__I uint32_t*)0x400E0A14U) /**< (UART1) Status Register */
|
||||
#define REG_UART1_RHR (*(__I uint32_t*)0x400E0A18U) /**< (UART1) Receive Holding Register */
|
||||
#define REG_UART1_THR (*(__O uint32_t*)0x400E0A1CU) /**< (UART1) Transmit Holding Register */
|
||||
#define REG_UART1_BRGR (*(__IO uint32_t*)0x400E0A20U) /**< (UART1) Baud Rate Generator Register */
|
||||
#define REG_UART1_CMPR (*(__IO uint32_t*)0x400E0A24U) /**< (UART1) Comparison Register */
|
||||
#define REG_UART1_WPMR (*(__IO uint32_t*)0x400E0AE4U) /**< (UART1) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for UART1 peripheral ========== */
|
||||
#define UART1_DMAC_ID_RX 23
|
||||
#define UART1_DMAC_ID_TX 22
|
||||
#define UART1_INSTANCE_ID 8
|
||||
#define UART1_CLOCK_ID 8
|
||||
#define UART1_BRSRCCK_PERIPH_CLK 0 /* MCK */
|
||||
#define UART1_BRSRCCK_PMC_PCK 0 /* PCK4 */
|
||||
|
||||
#endif /* _SAME70_UART1_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/uart2.h
Normal file
73
lib/same70b/include/instance/uart2.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UART2
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UART2_INSTANCE_H_
|
||||
#define _SAME70_UART2_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UART2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UART2_CR (0x400E1A00) /**< (UART2) Control Register */
|
||||
#define REG_UART2_MR (0x400E1A04) /**< (UART2) Mode Register */
|
||||
#define REG_UART2_IER (0x400E1A08) /**< (UART2) Interrupt Enable Register */
|
||||
#define REG_UART2_IDR (0x400E1A0C) /**< (UART2) Interrupt Disable Register */
|
||||
#define REG_UART2_IMR (0x400E1A10) /**< (UART2) Interrupt Mask Register */
|
||||
#define REG_UART2_SR (0x400E1A14) /**< (UART2) Status Register */
|
||||
#define REG_UART2_RHR (0x400E1A18) /**< (UART2) Receive Holding Register */
|
||||
#define REG_UART2_THR (0x400E1A1C) /**< (UART2) Transmit Holding Register */
|
||||
#define REG_UART2_BRGR (0x400E1A20) /**< (UART2) Baud Rate Generator Register */
|
||||
#define REG_UART2_CMPR (0x400E1A24) /**< (UART2) Comparison Register */
|
||||
#define REG_UART2_WPMR (0x400E1AE4) /**< (UART2) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UART2_CR (*(__O uint32_t*)0x400E1A00U) /**< (UART2) Control Register */
|
||||
#define REG_UART2_MR (*(__IO uint32_t*)0x400E1A04U) /**< (UART2) Mode Register */
|
||||
#define REG_UART2_IER (*(__O uint32_t*)0x400E1A08U) /**< (UART2) Interrupt Enable Register */
|
||||
#define REG_UART2_IDR (*(__O uint32_t*)0x400E1A0CU) /**< (UART2) Interrupt Disable Register */
|
||||
#define REG_UART2_IMR (*(__I uint32_t*)0x400E1A10U) /**< (UART2) Interrupt Mask Register */
|
||||
#define REG_UART2_SR (*(__I uint32_t*)0x400E1A14U) /**< (UART2) Status Register */
|
||||
#define REG_UART2_RHR (*(__I uint32_t*)0x400E1A18U) /**< (UART2) Receive Holding Register */
|
||||
#define REG_UART2_THR (*(__O uint32_t*)0x400E1A1CU) /**< (UART2) Transmit Holding Register */
|
||||
#define REG_UART2_BRGR (*(__IO uint32_t*)0x400E1A20U) /**< (UART2) Baud Rate Generator Register */
|
||||
#define REG_UART2_CMPR (*(__IO uint32_t*)0x400E1A24U) /**< (UART2) Comparison Register */
|
||||
#define REG_UART2_WPMR (*(__IO uint32_t*)0x400E1AE4U) /**< (UART2) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for UART2 peripheral ========== */
|
||||
#define UART2_DMAC_ID_RX 25
|
||||
#define UART2_DMAC_ID_TX 24
|
||||
#define UART2_INSTANCE_ID 44
|
||||
#define UART2_CLOCK_ID 44
|
||||
#define UART2_BRSRCCK_PERIPH_CLK 0 /* MCK */
|
||||
#define UART2_BRSRCCK_PMC_PCK 0 /* PCK4 */
|
||||
|
||||
#endif /* _SAME70_UART2_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/uart3.h
Normal file
73
lib/same70b/include/instance/uart3.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UART3
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UART3_INSTANCE_H_
|
||||
#define _SAME70_UART3_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UART3 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UART3_CR (0x400E1C00) /**< (UART3) Control Register */
|
||||
#define REG_UART3_MR (0x400E1C04) /**< (UART3) Mode Register */
|
||||
#define REG_UART3_IER (0x400E1C08) /**< (UART3) Interrupt Enable Register */
|
||||
#define REG_UART3_IDR (0x400E1C0C) /**< (UART3) Interrupt Disable Register */
|
||||
#define REG_UART3_IMR (0x400E1C10) /**< (UART3) Interrupt Mask Register */
|
||||
#define REG_UART3_SR (0x400E1C14) /**< (UART3) Status Register */
|
||||
#define REG_UART3_RHR (0x400E1C18) /**< (UART3) Receive Holding Register */
|
||||
#define REG_UART3_THR (0x400E1C1C) /**< (UART3) Transmit Holding Register */
|
||||
#define REG_UART3_BRGR (0x400E1C20) /**< (UART3) Baud Rate Generator Register */
|
||||
#define REG_UART3_CMPR (0x400E1C24) /**< (UART3) Comparison Register */
|
||||
#define REG_UART3_WPMR (0x400E1CE4) /**< (UART3) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UART3_CR (*(__O uint32_t*)0x400E1C00U) /**< (UART3) Control Register */
|
||||
#define REG_UART3_MR (*(__IO uint32_t*)0x400E1C04U) /**< (UART3) Mode Register */
|
||||
#define REG_UART3_IER (*(__O uint32_t*)0x400E1C08U) /**< (UART3) Interrupt Enable Register */
|
||||
#define REG_UART3_IDR (*(__O uint32_t*)0x400E1C0CU) /**< (UART3) Interrupt Disable Register */
|
||||
#define REG_UART3_IMR (*(__I uint32_t*)0x400E1C10U) /**< (UART3) Interrupt Mask Register */
|
||||
#define REG_UART3_SR (*(__I uint32_t*)0x400E1C14U) /**< (UART3) Status Register */
|
||||
#define REG_UART3_RHR (*(__I uint32_t*)0x400E1C18U) /**< (UART3) Receive Holding Register */
|
||||
#define REG_UART3_THR (*(__O uint32_t*)0x400E1C1CU) /**< (UART3) Transmit Holding Register */
|
||||
#define REG_UART3_BRGR (*(__IO uint32_t*)0x400E1C20U) /**< (UART3) Baud Rate Generator Register */
|
||||
#define REG_UART3_CMPR (*(__IO uint32_t*)0x400E1C24U) /**< (UART3) Comparison Register */
|
||||
#define REG_UART3_WPMR (*(__IO uint32_t*)0x400E1CE4U) /**< (UART3) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for UART3 peripheral ========== */
|
||||
#define UART3_DMAC_ID_RX 27
|
||||
#define UART3_DMAC_ID_TX 26
|
||||
#define UART3_INSTANCE_ID 45
|
||||
#define UART3_CLOCK_ID 45
|
||||
#define UART3_BRSRCCK_PERIPH_CLK 0 /* MCK */
|
||||
#define UART3_BRSRCCK_PMC_PCK 0 /* PCK4 */
|
||||
|
||||
#endif /* _SAME70_UART3_INSTANCE_ */
|
||||
73
lib/same70b/include/instance/uart4.h
Normal file
73
lib/same70b/include/instance/uart4.h
Normal file
|
|
@ -0,0 +1,73 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UART4
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UART4_INSTANCE_H_
|
||||
#define _SAME70_UART4_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UART4 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UART4_CR (0x400E1E00) /**< (UART4) Control Register */
|
||||
#define REG_UART4_MR (0x400E1E04) /**< (UART4) Mode Register */
|
||||
#define REG_UART4_IER (0x400E1E08) /**< (UART4) Interrupt Enable Register */
|
||||
#define REG_UART4_IDR (0x400E1E0C) /**< (UART4) Interrupt Disable Register */
|
||||
#define REG_UART4_IMR (0x400E1E10) /**< (UART4) Interrupt Mask Register */
|
||||
#define REG_UART4_SR (0x400E1E14) /**< (UART4) Status Register */
|
||||
#define REG_UART4_RHR (0x400E1E18) /**< (UART4) Receive Holding Register */
|
||||
#define REG_UART4_THR (0x400E1E1C) /**< (UART4) Transmit Holding Register */
|
||||
#define REG_UART4_BRGR (0x400E1E20) /**< (UART4) Baud Rate Generator Register */
|
||||
#define REG_UART4_CMPR (0x400E1E24) /**< (UART4) Comparison Register */
|
||||
#define REG_UART4_WPMR (0x400E1EE4) /**< (UART4) Write Protection Mode Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UART4_CR (*(__O uint32_t*)0x400E1E00U) /**< (UART4) Control Register */
|
||||
#define REG_UART4_MR (*(__IO uint32_t*)0x400E1E04U) /**< (UART4) Mode Register */
|
||||
#define REG_UART4_IER (*(__O uint32_t*)0x400E1E08U) /**< (UART4) Interrupt Enable Register */
|
||||
#define REG_UART4_IDR (*(__O uint32_t*)0x400E1E0CU) /**< (UART4) Interrupt Disable Register */
|
||||
#define REG_UART4_IMR (*(__I uint32_t*)0x400E1E10U) /**< (UART4) Interrupt Mask Register */
|
||||
#define REG_UART4_SR (*(__I uint32_t*)0x400E1E14U) /**< (UART4) Status Register */
|
||||
#define REG_UART4_RHR (*(__I uint32_t*)0x400E1E18U) /**< (UART4) Receive Holding Register */
|
||||
#define REG_UART4_THR (*(__O uint32_t*)0x400E1E1CU) /**< (UART4) Transmit Holding Register */
|
||||
#define REG_UART4_BRGR (*(__IO uint32_t*)0x400E1E20U) /**< (UART4) Baud Rate Generator Register */
|
||||
#define REG_UART4_CMPR (*(__IO uint32_t*)0x400E1E24U) /**< (UART4) Comparison Register */
|
||||
#define REG_UART4_WPMR (*(__IO uint32_t*)0x400E1EE4U) /**< (UART4) Write Protection Mode Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for UART4 peripheral ========== */
|
||||
#define UART4_DMAC_ID_RX 29
|
||||
#define UART4_DMAC_ID_TX 28
|
||||
#define UART4_INSTANCE_ID 46
|
||||
#define UART4_CLOCK_ID 46
|
||||
#define UART4_BRSRCCK_PERIPH_CLK 0 /* MCK */
|
||||
#define UART4_BRSRCCK_PMC_PCK 0 /* PCK4 */
|
||||
|
||||
#endif /* _SAME70_UART4_INSTANCE_ */
|
||||
115
lib/same70b/include/instance/usart0.h
Normal file
115
lib/same70b/include/instance/usart0.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USART0
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_USART0_INSTANCE_H_
|
||||
#define _SAME70_USART0_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for USART0 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_USART0_US_CR (0x40024000) /**< (USART0) Control Register */
|
||||
#define REG_USART0_US_MR (0x40024004) /**< (USART0) Mode Register */
|
||||
#define REG_USART0_US_IER (0x40024008) /**< (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_US_IDR (0x4002400C) /**< (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_US_IMR (0x40024010) /**< (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_US_CSR (0x40024014) /**< (USART0) Channel Status Register */
|
||||
#define REG_USART0_US_RHR (0x40024018) /**< (USART0) Receive Holding Register */
|
||||
#define REG_USART0_US_THR (0x4002401C) /**< (USART0) Transmit Holding Register */
|
||||
#define REG_USART0_US_BRGR (0x40024020) /**< (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_US_RTOR (0x40024024) /**< (USART0) Receiver Timeout Register */
|
||||
#define REG_USART0_US_TTGR (0x40024028) /**< (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_US_FIDI (0x40024040) /**< (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_US_NER (0x40024044) /**< (USART0) Number of Errors Register */
|
||||
#define REG_USART0_US_IF (0x4002404C) /**< (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_US_MAN (0x40024050) /**< (USART0) Manchester Configuration Register */
|
||||
#define REG_USART0_US_LINMR (0x40024054) /**< (USART0) LIN Mode Register */
|
||||
#define REG_USART0_US_LINIR (0x40024058) /**< (USART0) LIN Identifier Register */
|
||||
#define REG_USART0_US_LINBRR (0x4002405C) /**< (USART0) LIN Baud Rate Register */
|
||||
#define REG_USART0_US_LONMR (0x40024060) /**< (USART0) LON Mode Register */
|
||||
#define REG_USART0_US_LONPR (0x40024064) /**< (USART0) LON Preamble Register */
|
||||
#define REG_USART0_US_LONDL (0x40024068) /**< (USART0) LON Data Length Register */
|
||||
#define REG_USART0_US_LONL2HDR (0x4002406C) /**< (USART0) LON L2HDR Register */
|
||||
#define REG_USART0_US_LONBL (0x40024070) /**< (USART0) LON Backlog Register */
|
||||
#define REG_USART0_US_LONB1TX (0x40024074) /**< (USART0) LON Beta1 Tx Register */
|
||||
#define REG_USART0_US_LONB1RX (0x40024078) /**< (USART0) LON Beta1 Rx Register */
|
||||
#define REG_USART0_US_LONPRIO (0x4002407C) /**< (USART0) LON Priority Register */
|
||||
#define REG_USART0_US_IDTTX (0x40024080) /**< (USART0) LON IDT Tx Register */
|
||||
#define REG_USART0_US_IDTRX (0x40024084) /**< (USART0) LON IDT Rx Register */
|
||||
#define REG_USART0_US_ICDIFF (0x40024088) /**< (USART0) IC DIFF Register */
|
||||
#define REG_USART0_US_WPMR (0x400240E4) /**< (USART0) Write Protection Mode Register */
|
||||
#define REG_USART0_US_WPSR (0x400240E8) /**< (USART0) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_USART0_US_CR (*(__O uint32_t*)0x40024000U) /**< (USART0) Control Register */
|
||||
#define REG_USART0_US_MR (*(__IO uint32_t*)0x40024004U) /**< (USART0) Mode Register */
|
||||
#define REG_USART0_US_IER (*(__O uint32_t*)0x40024008U) /**< (USART0) Interrupt Enable Register */
|
||||
#define REG_USART0_US_IDR (*(__O uint32_t*)0x4002400CU) /**< (USART0) Interrupt Disable Register */
|
||||
#define REG_USART0_US_IMR (*(__I uint32_t*)0x40024010U) /**< (USART0) Interrupt Mask Register */
|
||||
#define REG_USART0_US_CSR (*(__I uint32_t*)0x40024014U) /**< (USART0) Channel Status Register */
|
||||
#define REG_USART0_US_RHR (*(__I uint32_t*)0x40024018U) /**< (USART0) Receive Holding Register */
|
||||
#define REG_USART0_US_THR (*(__O uint32_t*)0x4002401CU) /**< (USART0) Transmit Holding Register */
|
||||
#define REG_USART0_US_BRGR (*(__IO uint32_t*)0x40024020U) /**< (USART0) Baud Rate Generator Register */
|
||||
#define REG_USART0_US_RTOR (*(__IO uint32_t*)0x40024024U) /**< (USART0) Receiver Timeout Register */
|
||||
#define REG_USART0_US_TTGR (*(__IO uint32_t*)0x40024028U) /**< (USART0) Transmitter Timeguard Register */
|
||||
#define REG_USART0_US_FIDI (*(__IO uint32_t*)0x40024040U) /**< (USART0) FI DI Ratio Register */
|
||||
#define REG_USART0_US_NER (*(__I uint32_t*)0x40024044U) /**< (USART0) Number of Errors Register */
|
||||
#define REG_USART0_US_IF (*(__IO uint32_t*)0x4002404CU) /**< (USART0) IrDA Filter Register */
|
||||
#define REG_USART0_US_MAN (*(__IO uint32_t*)0x40024050U) /**< (USART0) Manchester Configuration Register */
|
||||
#define REG_USART0_US_LINMR (*(__IO uint32_t*)0x40024054U) /**< (USART0) LIN Mode Register */
|
||||
#define REG_USART0_US_LINIR (*(__IO uint32_t*)0x40024058U) /**< (USART0) LIN Identifier Register */
|
||||
#define REG_USART0_US_LINBRR (*(__I uint32_t*)0x4002405CU) /**< (USART0) LIN Baud Rate Register */
|
||||
#define REG_USART0_US_LONMR (*(__IO uint32_t*)0x40024060U) /**< (USART0) LON Mode Register */
|
||||
#define REG_USART0_US_LONPR (*(__IO uint32_t*)0x40024064U) /**< (USART0) LON Preamble Register */
|
||||
#define REG_USART0_US_LONDL (*(__IO uint32_t*)0x40024068U) /**< (USART0) LON Data Length Register */
|
||||
#define REG_USART0_US_LONL2HDR (*(__IO uint32_t*)0x4002406CU) /**< (USART0) LON L2HDR Register */
|
||||
#define REG_USART0_US_LONBL (*(__I uint32_t*)0x40024070U) /**< (USART0) LON Backlog Register */
|
||||
#define REG_USART0_US_LONB1TX (*(__IO uint32_t*)0x40024074U) /**< (USART0) LON Beta1 Tx Register */
|
||||
#define REG_USART0_US_LONB1RX (*(__IO uint32_t*)0x40024078U) /**< (USART0) LON Beta1 Rx Register */
|
||||
#define REG_USART0_US_LONPRIO (*(__IO uint32_t*)0x4002407CU) /**< (USART0) LON Priority Register */
|
||||
#define REG_USART0_US_IDTTX (*(__IO uint32_t*)0x40024080U) /**< (USART0) LON IDT Tx Register */
|
||||
#define REG_USART0_US_IDTRX (*(__IO uint32_t*)0x40024084U) /**< (USART0) LON IDT Rx Register */
|
||||
#define REG_USART0_US_ICDIFF (*(__IO uint32_t*)0x40024088U) /**< (USART0) IC DIFF Register */
|
||||
#define REG_USART0_US_WPMR (*(__IO uint32_t*)0x400240E4U) /**< (USART0) Write Protection Mode Register */
|
||||
#define REG_USART0_US_WPSR (*(__I uint32_t*)0x400240E8U) /**< (USART0) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for USART0 peripheral ========== */
|
||||
#define USART0_DMAC_ID_RX 8
|
||||
#define USART0_DMAC_ID_TX 7
|
||||
#define USART0_INSTANCE_ID 13
|
||||
#define USART0_CLOCK_ID 13
|
||||
#define USART0_USCLKS_MCK 0 /* MCK */
|
||||
#define USART0_USCLKS_DIV 1 /* MCK/8 */
|
||||
#define USART0_USCLKS_PCK 2 /* PCK4 */
|
||||
#define USART0_USCLKS_SCK 3 /* SCK */
|
||||
|
||||
#endif /* _SAME70_USART0_INSTANCE_ */
|
||||
115
lib/same70b/include/instance/usart1.h
Normal file
115
lib/same70b/include/instance/usart1.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USART1
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_USART1_INSTANCE_H_
|
||||
#define _SAME70_USART1_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for USART1 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_USART1_US_CR (0x40028000) /**< (USART1) Control Register */
|
||||
#define REG_USART1_US_MR (0x40028004) /**< (USART1) Mode Register */
|
||||
#define REG_USART1_US_IER (0x40028008) /**< (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_US_IDR (0x4002800C) /**< (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_US_IMR (0x40028010) /**< (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_US_CSR (0x40028014) /**< (USART1) Channel Status Register */
|
||||
#define REG_USART1_US_RHR (0x40028018) /**< (USART1) Receive Holding Register */
|
||||
#define REG_USART1_US_THR (0x4002801C) /**< (USART1) Transmit Holding Register */
|
||||
#define REG_USART1_US_BRGR (0x40028020) /**< (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_US_RTOR (0x40028024) /**< (USART1) Receiver Timeout Register */
|
||||
#define REG_USART1_US_TTGR (0x40028028) /**< (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_US_FIDI (0x40028040) /**< (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_US_NER (0x40028044) /**< (USART1) Number of Errors Register */
|
||||
#define REG_USART1_US_IF (0x4002804C) /**< (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_US_MAN (0x40028050) /**< (USART1) Manchester Configuration Register */
|
||||
#define REG_USART1_US_LINMR (0x40028054) /**< (USART1) LIN Mode Register */
|
||||
#define REG_USART1_US_LINIR (0x40028058) /**< (USART1) LIN Identifier Register */
|
||||
#define REG_USART1_US_LINBRR (0x4002805C) /**< (USART1) LIN Baud Rate Register */
|
||||
#define REG_USART1_US_LONMR (0x40028060) /**< (USART1) LON Mode Register */
|
||||
#define REG_USART1_US_LONPR (0x40028064) /**< (USART1) LON Preamble Register */
|
||||
#define REG_USART1_US_LONDL (0x40028068) /**< (USART1) LON Data Length Register */
|
||||
#define REG_USART1_US_LONL2HDR (0x4002806C) /**< (USART1) LON L2HDR Register */
|
||||
#define REG_USART1_US_LONBL (0x40028070) /**< (USART1) LON Backlog Register */
|
||||
#define REG_USART1_US_LONB1TX (0x40028074) /**< (USART1) LON Beta1 Tx Register */
|
||||
#define REG_USART1_US_LONB1RX (0x40028078) /**< (USART1) LON Beta1 Rx Register */
|
||||
#define REG_USART1_US_LONPRIO (0x4002807C) /**< (USART1) LON Priority Register */
|
||||
#define REG_USART1_US_IDTTX (0x40028080) /**< (USART1) LON IDT Tx Register */
|
||||
#define REG_USART1_US_IDTRX (0x40028084) /**< (USART1) LON IDT Rx Register */
|
||||
#define REG_USART1_US_ICDIFF (0x40028088) /**< (USART1) IC DIFF Register */
|
||||
#define REG_USART1_US_WPMR (0x400280E4) /**< (USART1) Write Protection Mode Register */
|
||||
#define REG_USART1_US_WPSR (0x400280E8) /**< (USART1) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_USART1_US_CR (*(__O uint32_t*)0x40028000U) /**< (USART1) Control Register */
|
||||
#define REG_USART1_US_MR (*(__IO uint32_t*)0x40028004U) /**< (USART1) Mode Register */
|
||||
#define REG_USART1_US_IER (*(__O uint32_t*)0x40028008U) /**< (USART1) Interrupt Enable Register */
|
||||
#define REG_USART1_US_IDR (*(__O uint32_t*)0x4002800CU) /**< (USART1) Interrupt Disable Register */
|
||||
#define REG_USART1_US_IMR (*(__I uint32_t*)0x40028010U) /**< (USART1) Interrupt Mask Register */
|
||||
#define REG_USART1_US_CSR (*(__I uint32_t*)0x40028014U) /**< (USART1) Channel Status Register */
|
||||
#define REG_USART1_US_RHR (*(__I uint32_t*)0x40028018U) /**< (USART1) Receive Holding Register */
|
||||
#define REG_USART1_US_THR (*(__O uint32_t*)0x4002801CU) /**< (USART1) Transmit Holding Register */
|
||||
#define REG_USART1_US_BRGR (*(__IO uint32_t*)0x40028020U) /**< (USART1) Baud Rate Generator Register */
|
||||
#define REG_USART1_US_RTOR (*(__IO uint32_t*)0x40028024U) /**< (USART1) Receiver Timeout Register */
|
||||
#define REG_USART1_US_TTGR (*(__IO uint32_t*)0x40028028U) /**< (USART1) Transmitter Timeguard Register */
|
||||
#define REG_USART1_US_FIDI (*(__IO uint32_t*)0x40028040U) /**< (USART1) FI DI Ratio Register */
|
||||
#define REG_USART1_US_NER (*(__I uint32_t*)0x40028044U) /**< (USART1) Number of Errors Register */
|
||||
#define REG_USART1_US_IF (*(__IO uint32_t*)0x4002804CU) /**< (USART1) IrDA Filter Register */
|
||||
#define REG_USART1_US_MAN (*(__IO uint32_t*)0x40028050U) /**< (USART1) Manchester Configuration Register */
|
||||
#define REG_USART1_US_LINMR (*(__IO uint32_t*)0x40028054U) /**< (USART1) LIN Mode Register */
|
||||
#define REG_USART1_US_LINIR (*(__IO uint32_t*)0x40028058U) /**< (USART1) LIN Identifier Register */
|
||||
#define REG_USART1_US_LINBRR (*(__I uint32_t*)0x4002805CU) /**< (USART1) LIN Baud Rate Register */
|
||||
#define REG_USART1_US_LONMR (*(__IO uint32_t*)0x40028060U) /**< (USART1) LON Mode Register */
|
||||
#define REG_USART1_US_LONPR (*(__IO uint32_t*)0x40028064U) /**< (USART1) LON Preamble Register */
|
||||
#define REG_USART1_US_LONDL (*(__IO uint32_t*)0x40028068U) /**< (USART1) LON Data Length Register */
|
||||
#define REG_USART1_US_LONL2HDR (*(__IO uint32_t*)0x4002806CU) /**< (USART1) LON L2HDR Register */
|
||||
#define REG_USART1_US_LONBL (*(__I uint32_t*)0x40028070U) /**< (USART1) LON Backlog Register */
|
||||
#define REG_USART1_US_LONB1TX (*(__IO uint32_t*)0x40028074U) /**< (USART1) LON Beta1 Tx Register */
|
||||
#define REG_USART1_US_LONB1RX (*(__IO uint32_t*)0x40028078U) /**< (USART1) LON Beta1 Rx Register */
|
||||
#define REG_USART1_US_LONPRIO (*(__IO uint32_t*)0x4002807CU) /**< (USART1) LON Priority Register */
|
||||
#define REG_USART1_US_IDTTX (*(__IO uint32_t*)0x40028080U) /**< (USART1) LON IDT Tx Register */
|
||||
#define REG_USART1_US_IDTRX (*(__IO uint32_t*)0x40028084U) /**< (USART1) LON IDT Rx Register */
|
||||
#define REG_USART1_US_ICDIFF (*(__IO uint32_t*)0x40028088U) /**< (USART1) IC DIFF Register */
|
||||
#define REG_USART1_US_WPMR (*(__IO uint32_t*)0x400280E4U) /**< (USART1) Write Protection Mode Register */
|
||||
#define REG_USART1_US_WPSR (*(__I uint32_t*)0x400280E8U) /**< (USART1) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for USART1 peripheral ========== */
|
||||
#define USART1_DMAC_ID_RX 10
|
||||
#define USART1_DMAC_ID_TX 9
|
||||
#define USART1_INSTANCE_ID 14
|
||||
#define USART1_CLOCK_ID 14
|
||||
#define USART1_USCLKS_MCK 0 /* MCK */
|
||||
#define USART1_USCLKS_DIV 1 /* MCK/8 */
|
||||
#define USART1_USCLKS_PCK 2 /* PCK4 */
|
||||
#define USART1_USCLKS_SCK 3 /* SCK */
|
||||
|
||||
#endif /* _SAME70_USART1_INSTANCE_ */
|
||||
115
lib/same70b/include/instance/usart2.h
Normal file
115
lib/same70b/include/instance/usart2.h
Normal file
|
|
@ -0,0 +1,115 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USART2
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_USART2_INSTANCE_H_
|
||||
#define _SAME70_USART2_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for USART2 peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_USART2_US_CR (0x4002C000) /**< (USART2) Control Register */
|
||||
#define REG_USART2_US_MR (0x4002C004) /**< (USART2) Mode Register */
|
||||
#define REG_USART2_US_IER (0x4002C008) /**< (USART2) Interrupt Enable Register */
|
||||
#define REG_USART2_US_IDR (0x4002C00C) /**< (USART2) Interrupt Disable Register */
|
||||
#define REG_USART2_US_IMR (0x4002C010) /**< (USART2) Interrupt Mask Register */
|
||||
#define REG_USART2_US_CSR (0x4002C014) /**< (USART2) Channel Status Register */
|
||||
#define REG_USART2_US_RHR (0x4002C018) /**< (USART2) Receive Holding Register */
|
||||
#define REG_USART2_US_THR (0x4002C01C) /**< (USART2) Transmit Holding Register */
|
||||
#define REG_USART2_US_BRGR (0x4002C020) /**< (USART2) Baud Rate Generator Register */
|
||||
#define REG_USART2_US_RTOR (0x4002C024) /**< (USART2) Receiver Timeout Register */
|
||||
#define REG_USART2_US_TTGR (0x4002C028) /**< (USART2) Transmitter Timeguard Register */
|
||||
#define REG_USART2_US_FIDI (0x4002C040) /**< (USART2) FI DI Ratio Register */
|
||||
#define REG_USART2_US_NER (0x4002C044) /**< (USART2) Number of Errors Register */
|
||||
#define REG_USART2_US_IF (0x4002C04C) /**< (USART2) IrDA Filter Register */
|
||||
#define REG_USART2_US_MAN (0x4002C050) /**< (USART2) Manchester Configuration Register */
|
||||
#define REG_USART2_US_LINMR (0x4002C054) /**< (USART2) LIN Mode Register */
|
||||
#define REG_USART2_US_LINIR (0x4002C058) /**< (USART2) LIN Identifier Register */
|
||||
#define REG_USART2_US_LINBRR (0x4002C05C) /**< (USART2) LIN Baud Rate Register */
|
||||
#define REG_USART2_US_LONMR (0x4002C060) /**< (USART2) LON Mode Register */
|
||||
#define REG_USART2_US_LONPR (0x4002C064) /**< (USART2) LON Preamble Register */
|
||||
#define REG_USART2_US_LONDL (0x4002C068) /**< (USART2) LON Data Length Register */
|
||||
#define REG_USART2_US_LONL2HDR (0x4002C06C) /**< (USART2) LON L2HDR Register */
|
||||
#define REG_USART2_US_LONBL (0x4002C070) /**< (USART2) LON Backlog Register */
|
||||
#define REG_USART2_US_LONB1TX (0x4002C074) /**< (USART2) LON Beta1 Tx Register */
|
||||
#define REG_USART2_US_LONB1RX (0x4002C078) /**< (USART2) LON Beta1 Rx Register */
|
||||
#define REG_USART2_US_LONPRIO (0x4002C07C) /**< (USART2) LON Priority Register */
|
||||
#define REG_USART2_US_IDTTX (0x4002C080) /**< (USART2) LON IDT Tx Register */
|
||||
#define REG_USART2_US_IDTRX (0x4002C084) /**< (USART2) LON IDT Rx Register */
|
||||
#define REG_USART2_US_ICDIFF (0x4002C088) /**< (USART2) IC DIFF Register */
|
||||
#define REG_USART2_US_WPMR (0x4002C0E4) /**< (USART2) Write Protection Mode Register */
|
||||
#define REG_USART2_US_WPSR (0x4002C0E8) /**< (USART2) Write Protection Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_USART2_US_CR (*(__O uint32_t*)0x4002C000U) /**< (USART2) Control Register */
|
||||
#define REG_USART2_US_MR (*(__IO uint32_t*)0x4002C004U) /**< (USART2) Mode Register */
|
||||
#define REG_USART2_US_IER (*(__O uint32_t*)0x4002C008U) /**< (USART2) Interrupt Enable Register */
|
||||
#define REG_USART2_US_IDR (*(__O uint32_t*)0x4002C00CU) /**< (USART2) Interrupt Disable Register */
|
||||
#define REG_USART2_US_IMR (*(__I uint32_t*)0x4002C010U) /**< (USART2) Interrupt Mask Register */
|
||||
#define REG_USART2_US_CSR (*(__I uint32_t*)0x4002C014U) /**< (USART2) Channel Status Register */
|
||||
#define REG_USART2_US_RHR (*(__I uint32_t*)0x4002C018U) /**< (USART2) Receive Holding Register */
|
||||
#define REG_USART2_US_THR (*(__O uint32_t*)0x4002C01CU) /**< (USART2) Transmit Holding Register */
|
||||
#define REG_USART2_US_BRGR (*(__IO uint32_t*)0x4002C020U) /**< (USART2) Baud Rate Generator Register */
|
||||
#define REG_USART2_US_RTOR (*(__IO uint32_t*)0x4002C024U) /**< (USART2) Receiver Timeout Register */
|
||||
#define REG_USART2_US_TTGR (*(__IO uint32_t*)0x4002C028U) /**< (USART2) Transmitter Timeguard Register */
|
||||
#define REG_USART2_US_FIDI (*(__IO uint32_t*)0x4002C040U) /**< (USART2) FI DI Ratio Register */
|
||||
#define REG_USART2_US_NER (*(__I uint32_t*)0x4002C044U) /**< (USART2) Number of Errors Register */
|
||||
#define REG_USART2_US_IF (*(__IO uint32_t*)0x4002C04CU) /**< (USART2) IrDA Filter Register */
|
||||
#define REG_USART2_US_MAN (*(__IO uint32_t*)0x4002C050U) /**< (USART2) Manchester Configuration Register */
|
||||
#define REG_USART2_US_LINMR (*(__IO uint32_t*)0x4002C054U) /**< (USART2) LIN Mode Register */
|
||||
#define REG_USART2_US_LINIR (*(__IO uint32_t*)0x4002C058U) /**< (USART2) LIN Identifier Register */
|
||||
#define REG_USART2_US_LINBRR (*(__I uint32_t*)0x4002C05CU) /**< (USART2) LIN Baud Rate Register */
|
||||
#define REG_USART2_US_LONMR (*(__IO uint32_t*)0x4002C060U) /**< (USART2) LON Mode Register */
|
||||
#define REG_USART2_US_LONPR (*(__IO uint32_t*)0x4002C064U) /**< (USART2) LON Preamble Register */
|
||||
#define REG_USART2_US_LONDL (*(__IO uint32_t*)0x4002C068U) /**< (USART2) LON Data Length Register */
|
||||
#define REG_USART2_US_LONL2HDR (*(__IO uint32_t*)0x4002C06CU) /**< (USART2) LON L2HDR Register */
|
||||
#define REG_USART2_US_LONBL (*(__I uint32_t*)0x4002C070U) /**< (USART2) LON Backlog Register */
|
||||
#define REG_USART2_US_LONB1TX (*(__IO uint32_t*)0x4002C074U) /**< (USART2) LON Beta1 Tx Register */
|
||||
#define REG_USART2_US_LONB1RX (*(__IO uint32_t*)0x4002C078U) /**< (USART2) LON Beta1 Rx Register */
|
||||
#define REG_USART2_US_LONPRIO (*(__IO uint32_t*)0x4002C07CU) /**< (USART2) LON Priority Register */
|
||||
#define REG_USART2_US_IDTTX (*(__IO uint32_t*)0x4002C080U) /**< (USART2) LON IDT Tx Register */
|
||||
#define REG_USART2_US_IDTRX (*(__IO uint32_t*)0x4002C084U) /**< (USART2) LON IDT Rx Register */
|
||||
#define REG_USART2_US_ICDIFF (*(__IO uint32_t*)0x4002C088U) /**< (USART2) IC DIFF Register */
|
||||
#define REG_USART2_US_WPMR (*(__IO uint32_t*)0x4002C0E4U) /**< (USART2) Write Protection Mode Register */
|
||||
#define REG_USART2_US_WPSR (*(__I uint32_t*)0x4002C0E8U) /**< (USART2) Write Protection Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for USART2 peripheral ========== */
|
||||
#define USART2_DMAC_ID_RX 12
|
||||
#define USART2_DMAC_ID_TX 11
|
||||
#define USART2_INSTANCE_ID 15
|
||||
#define USART2_CLOCK_ID 15
|
||||
#define USART2_USCLKS_MCK 0 /* MCK */
|
||||
#define USART2_USCLKS_DIV 1 /* MCK/8 */
|
||||
#define USART2_USCLKS_PCK 2 /* PCK4 */
|
||||
#define USART2_USCLKS_SCK 3 /* SCK */
|
||||
|
||||
#endif /* _SAME70_USART2_INSTANCE_ */
|
||||
561
lib/same70b/include/instance/usbhs.h
Normal file
561
lib/same70b/include/instance/usbhs.h
Normal file
|
|
@ -0,0 +1,561 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for USBHS
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_USBHS_INSTANCE_H_
|
||||
#define _SAME70_USBHS_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for USBHS peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_USBHS_DEVDMANXTDSC0 (0x40038310) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 0 */
|
||||
#define REG_USBHS_DEVDMAADDRESS0 (0x40038314) /**< (USBHS) Device DMA Channel Address Register 0 */
|
||||
#define REG_USBHS_DEVDMACONTROL0 (0x40038318) /**< (USBHS) Device DMA Channel Control Register 0 */
|
||||
#define REG_USBHS_DEVDMASTATUS0 (0x4003831C) /**< (USBHS) Device DMA Channel Status Register 0 */
|
||||
#define REG_USBHS_DEVDMANXTDSC1 (0x40038320) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 1 */
|
||||
#define REG_USBHS_DEVDMAADDRESS1 (0x40038324) /**< (USBHS) Device DMA Channel Address Register 1 */
|
||||
#define REG_USBHS_DEVDMACONTROL1 (0x40038328) /**< (USBHS) Device DMA Channel Control Register 1 */
|
||||
#define REG_USBHS_DEVDMASTATUS1 (0x4003832C) /**< (USBHS) Device DMA Channel Status Register 1 */
|
||||
#define REG_USBHS_DEVDMANXTDSC2 (0x40038330) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 2 */
|
||||
#define REG_USBHS_DEVDMAADDRESS2 (0x40038334) /**< (USBHS) Device DMA Channel Address Register 2 */
|
||||
#define REG_USBHS_DEVDMACONTROL2 (0x40038338) /**< (USBHS) Device DMA Channel Control Register 2 */
|
||||
#define REG_USBHS_DEVDMASTATUS2 (0x4003833C) /**< (USBHS) Device DMA Channel Status Register 2 */
|
||||
#define REG_USBHS_DEVDMANXTDSC3 (0x40038340) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 3 */
|
||||
#define REG_USBHS_DEVDMAADDRESS3 (0x40038344) /**< (USBHS) Device DMA Channel Address Register 3 */
|
||||
#define REG_USBHS_DEVDMACONTROL3 (0x40038348) /**< (USBHS) Device DMA Channel Control Register 3 */
|
||||
#define REG_USBHS_DEVDMASTATUS3 (0x4003834C) /**< (USBHS) Device DMA Channel Status Register 3 */
|
||||
#define REG_USBHS_DEVDMANXTDSC4 (0x40038350) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 4 */
|
||||
#define REG_USBHS_DEVDMAADDRESS4 (0x40038354) /**< (USBHS) Device DMA Channel Address Register 4 */
|
||||
#define REG_USBHS_DEVDMACONTROL4 (0x40038358) /**< (USBHS) Device DMA Channel Control Register 4 */
|
||||
#define REG_USBHS_DEVDMASTATUS4 (0x4003835C) /**< (USBHS) Device DMA Channel Status Register 4 */
|
||||
#define REG_USBHS_DEVDMANXTDSC5 (0x40038360) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 5 */
|
||||
#define REG_USBHS_DEVDMAADDRESS5 (0x40038364) /**< (USBHS) Device DMA Channel Address Register 5 */
|
||||
#define REG_USBHS_DEVDMACONTROL5 (0x40038368) /**< (USBHS) Device DMA Channel Control Register 5 */
|
||||
#define REG_USBHS_DEVDMASTATUS5 (0x4003836C) /**< (USBHS) Device DMA Channel Status Register 5 */
|
||||
#define REG_USBHS_DEVDMANXTDSC6 (0x40038370) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 6 */
|
||||
#define REG_USBHS_DEVDMAADDRESS6 (0x40038374) /**< (USBHS) Device DMA Channel Address Register 6 */
|
||||
#define REG_USBHS_DEVDMACONTROL6 (0x40038378) /**< (USBHS) Device DMA Channel Control Register 6 */
|
||||
#define REG_USBHS_DEVDMASTATUS6 (0x4003837C) /**< (USBHS) Device DMA Channel Status Register 6 */
|
||||
#define REG_USBHS_HSTDMANXTDSC0 (0x40038710) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 0 */
|
||||
#define REG_USBHS_HSTDMAADDRESS0 (0x40038714) /**< (USBHS) Host DMA Channel Address Register 0 */
|
||||
#define REG_USBHS_HSTDMACONTROL0 (0x40038718) /**< (USBHS) Host DMA Channel Control Register 0 */
|
||||
#define REG_USBHS_HSTDMASTATUS0 (0x4003871C) /**< (USBHS) Host DMA Channel Status Register 0 */
|
||||
#define REG_USBHS_HSTDMANXTDSC1 (0x40038720) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 1 */
|
||||
#define REG_USBHS_HSTDMAADDRESS1 (0x40038724) /**< (USBHS) Host DMA Channel Address Register 1 */
|
||||
#define REG_USBHS_HSTDMACONTROL1 (0x40038728) /**< (USBHS) Host DMA Channel Control Register 1 */
|
||||
#define REG_USBHS_HSTDMASTATUS1 (0x4003872C) /**< (USBHS) Host DMA Channel Status Register 1 */
|
||||
#define REG_USBHS_HSTDMANXTDSC2 (0x40038730) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 2 */
|
||||
#define REG_USBHS_HSTDMAADDRESS2 (0x40038734) /**< (USBHS) Host DMA Channel Address Register 2 */
|
||||
#define REG_USBHS_HSTDMACONTROL2 (0x40038738) /**< (USBHS) Host DMA Channel Control Register 2 */
|
||||
#define REG_USBHS_HSTDMASTATUS2 (0x4003873C) /**< (USBHS) Host DMA Channel Status Register 2 */
|
||||
#define REG_USBHS_HSTDMANXTDSC3 (0x40038740) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 3 */
|
||||
#define REG_USBHS_HSTDMAADDRESS3 (0x40038744) /**< (USBHS) Host DMA Channel Address Register 3 */
|
||||
#define REG_USBHS_HSTDMACONTROL3 (0x40038748) /**< (USBHS) Host DMA Channel Control Register 3 */
|
||||
#define REG_USBHS_HSTDMASTATUS3 (0x4003874C) /**< (USBHS) Host DMA Channel Status Register 3 */
|
||||
#define REG_USBHS_HSTDMANXTDSC4 (0x40038750) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 4 */
|
||||
#define REG_USBHS_HSTDMAADDRESS4 (0x40038754) /**< (USBHS) Host DMA Channel Address Register 4 */
|
||||
#define REG_USBHS_HSTDMACONTROL4 (0x40038758) /**< (USBHS) Host DMA Channel Control Register 4 */
|
||||
#define REG_USBHS_HSTDMASTATUS4 (0x4003875C) /**< (USBHS) Host DMA Channel Status Register 4 */
|
||||
#define REG_USBHS_HSTDMANXTDSC5 (0x40038760) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 5 */
|
||||
#define REG_USBHS_HSTDMAADDRESS5 (0x40038764) /**< (USBHS) Host DMA Channel Address Register 5 */
|
||||
#define REG_USBHS_HSTDMACONTROL5 (0x40038768) /**< (USBHS) Host DMA Channel Control Register 5 */
|
||||
#define REG_USBHS_HSTDMASTATUS5 (0x4003876C) /**< (USBHS) Host DMA Channel Status Register 5 */
|
||||
#define REG_USBHS_HSTDMANXTDSC6 (0x40038770) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 6 */
|
||||
#define REG_USBHS_HSTDMAADDRESS6 (0x40038774) /**< (USBHS) Host DMA Channel Address Register 6 */
|
||||
#define REG_USBHS_HSTDMACONTROL6 (0x40038778) /**< (USBHS) Host DMA Channel Control Register 6 */
|
||||
#define REG_USBHS_HSTDMASTATUS6 (0x4003877C) /**< (USBHS) Host DMA Channel Status Register 6 */
|
||||
#define REG_USBHS_DEVCTRL (0x40038000) /**< (USBHS) Device General Control Register */
|
||||
#define REG_USBHS_DEVISR (0x40038004) /**< (USBHS) Device Global Interrupt Status Register */
|
||||
#define REG_USBHS_DEVICR (0x40038008) /**< (USBHS) Device Global Interrupt Clear Register */
|
||||
#define REG_USBHS_DEVIFR (0x4003800C) /**< (USBHS) Device Global Interrupt Set Register */
|
||||
#define REG_USBHS_DEVIMR (0x40038010) /**< (USBHS) Device Global Interrupt Mask Register */
|
||||
#define REG_USBHS_DEVIDR (0x40038014) /**< (USBHS) Device Global Interrupt Disable Register */
|
||||
#define REG_USBHS_DEVIER (0x40038018) /**< (USBHS) Device Global Interrupt Enable Register */
|
||||
#define REG_USBHS_DEVEPT (0x4003801C) /**< (USBHS) Device Endpoint Register */
|
||||
#define REG_USBHS_DEVFNUM (0x40038020) /**< (USBHS) Device Frame Number Register */
|
||||
#define REG_USBHS_DEVEPTCFG (0x40038100) /**< (USBHS) Device Endpoint Configuration Register */
|
||||
#define REG_USBHS_DEVEPTCFG0 (0x40038100) /**< (USBHS) Device Endpoint Configuration Register 0 */
|
||||
#define REG_USBHS_DEVEPTCFG1 (0x40038104) /**< (USBHS) Device Endpoint Configuration Register 1 */
|
||||
#define REG_USBHS_DEVEPTCFG2 (0x40038108) /**< (USBHS) Device Endpoint Configuration Register 2 */
|
||||
#define REG_USBHS_DEVEPTCFG3 (0x4003810C) /**< (USBHS) Device Endpoint Configuration Register 3 */
|
||||
#define REG_USBHS_DEVEPTCFG4 (0x40038110) /**< (USBHS) Device Endpoint Configuration Register 4 */
|
||||
#define REG_USBHS_DEVEPTCFG5 (0x40038114) /**< (USBHS) Device Endpoint Configuration Register 5 */
|
||||
#define REG_USBHS_DEVEPTCFG6 (0x40038118) /**< (USBHS) Device Endpoint Configuration Register 6 */
|
||||
#define REG_USBHS_DEVEPTCFG7 (0x4003811C) /**< (USBHS) Device Endpoint Configuration Register 7 */
|
||||
#define REG_USBHS_DEVEPTCFG8 (0x40038120) /**< (USBHS) Device Endpoint Configuration Register 8 */
|
||||
#define REG_USBHS_DEVEPTCFG9 (0x40038124) /**< (USBHS) Device Endpoint Configuration Register 9 */
|
||||
#define REG_USBHS_DEVEPTISR (0x40038130) /**< (USBHS) Device Endpoint Interrupt Status Register */
|
||||
#define REG_USBHS_DEVEPTISR0 (0x40038130) /**< (USBHS) Device Endpoint Interrupt Status Register 0 */
|
||||
#define REG_USBHS_DEVEPTISR1 (0x40038134) /**< (USBHS) Device Endpoint Interrupt Status Register 1 */
|
||||
#define REG_USBHS_DEVEPTISR2 (0x40038138) /**< (USBHS) Device Endpoint Interrupt Status Register 2 */
|
||||
#define REG_USBHS_DEVEPTISR3 (0x4003813C) /**< (USBHS) Device Endpoint Interrupt Status Register 3 */
|
||||
#define REG_USBHS_DEVEPTISR4 (0x40038140) /**< (USBHS) Device Endpoint Interrupt Status Register 4 */
|
||||
#define REG_USBHS_DEVEPTISR5 (0x40038144) /**< (USBHS) Device Endpoint Interrupt Status Register 5 */
|
||||
#define REG_USBHS_DEVEPTISR6 (0x40038148) /**< (USBHS) Device Endpoint Interrupt Status Register 6 */
|
||||
#define REG_USBHS_DEVEPTISR7 (0x4003814C) /**< (USBHS) Device Endpoint Interrupt Status Register 7 */
|
||||
#define REG_USBHS_DEVEPTISR8 (0x40038150) /**< (USBHS) Device Endpoint Interrupt Status Register 8 */
|
||||
#define REG_USBHS_DEVEPTISR9 (0x40038154) /**< (USBHS) Device Endpoint Interrupt Status Register 9 */
|
||||
#define REG_USBHS_DEVEPTICR (0x40038160) /**< (USBHS) Device Endpoint Interrupt Clear Register */
|
||||
#define REG_USBHS_DEVEPTICR0 (0x40038160) /**< (USBHS) Device Endpoint Interrupt Clear Register 0 */
|
||||
#define REG_USBHS_DEVEPTICR1 (0x40038164) /**< (USBHS) Device Endpoint Interrupt Clear Register 1 */
|
||||
#define REG_USBHS_DEVEPTICR2 (0x40038168) /**< (USBHS) Device Endpoint Interrupt Clear Register 2 */
|
||||
#define REG_USBHS_DEVEPTICR3 (0x4003816C) /**< (USBHS) Device Endpoint Interrupt Clear Register 3 */
|
||||
#define REG_USBHS_DEVEPTICR4 (0x40038170) /**< (USBHS) Device Endpoint Interrupt Clear Register 4 */
|
||||
#define REG_USBHS_DEVEPTICR5 (0x40038174) /**< (USBHS) Device Endpoint Interrupt Clear Register 5 */
|
||||
#define REG_USBHS_DEVEPTICR6 (0x40038178) /**< (USBHS) Device Endpoint Interrupt Clear Register 6 */
|
||||
#define REG_USBHS_DEVEPTICR7 (0x4003817C) /**< (USBHS) Device Endpoint Interrupt Clear Register 7 */
|
||||
#define REG_USBHS_DEVEPTICR8 (0x40038180) /**< (USBHS) Device Endpoint Interrupt Clear Register 8 */
|
||||
#define REG_USBHS_DEVEPTICR9 (0x40038184) /**< (USBHS) Device Endpoint Interrupt Clear Register 9 */
|
||||
#define REG_USBHS_DEVEPTIFR (0x40038190) /**< (USBHS) Device Endpoint Interrupt Set Register */
|
||||
#define REG_USBHS_DEVEPTIFR0 (0x40038190) /**< (USBHS) Device Endpoint Interrupt Set Register 0 */
|
||||
#define REG_USBHS_DEVEPTIFR1 (0x40038194) /**< (USBHS) Device Endpoint Interrupt Set Register 1 */
|
||||
#define REG_USBHS_DEVEPTIFR2 (0x40038198) /**< (USBHS) Device Endpoint Interrupt Set Register 2 */
|
||||
#define REG_USBHS_DEVEPTIFR3 (0x4003819C) /**< (USBHS) Device Endpoint Interrupt Set Register 3 */
|
||||
#define REG_USBHS_DEVEPTIFR4 (0x400381A0) /**< (USBHS) Device Endpoint Interrupt Set Register 4 */
|
||||
#define REG_USBHS_DEVEPTIFR5 (0x400381A4) /**< (USBHS) Device Endpoint Interrupt Set Register 5 */
|
||||
#define REG_USBHS_DEVEPTIFR6 (0x400381A8) /**< (USBHS) Device Endpoint Interrupt Set Register 6 */
|
||||
#define REG_USBHS_DEVEPTIFR7 (0x400381AC) /**< (USBHS) Device Endpoint Interrupt Set Register 7 */
|
||||
#define REG_USBHS_DEVEPTIFR8 (0x400381B0) /**< (USBHS) Device Endpoint Interrupt Set Register 8 */
|
||||
#define REG_USBHS_DEVEPTIFR9 (0x400381B4) /**< (USBHS) Device Endpoint Interrupt Set Register 9 */
|
||||
#define REG_USBHS_DEVEPTIMR (0x400381C0) /**< (USBHS) Device Endpoint Interrupt Mask Register */
|
||||
#define REG_USBHS_DEVEPTIMR0 (0x400381C0) /**< (USBHS) Device Endpoint Interrupt Mask Register 0 */
|
||||
#define REG_USBHS_DEVEPTIMR1 (0x400381C4) /**< (USBHS) Device Endpoint Interrupt Mask Register 1 */
|
||||
#define REG_USBHS_DEVEPTIMR2 (0x400381C8) /**< (USBHS) Device Endpoint Interrupt Mask Register 2 */
|
||||
#define REG_USBHS_DEVEPTIMR3 (0x400381CC) /**< (USBHS) Device Endpoint Interrupt Mask Register 3 */
|
||||
#define REG_USBHS_DEVEPTIMR4 (0x400381D0) /**< (USBHS) Device Endpoint Interrupt Mask Register 4 */
|
||||
#define REG_USBHS_DEVEPTIMR5 (0x400381D4) /**< (USBHS) Device Endpoint Interrupt Mask Register 5 */
|
||||
#define REG_USBHS_DEVEPTIMR6 (0x400381D8) /**< (USBHS) Device Endpoint Interrupt Mask Register 6 */
|
||||
#define REG_USBHS_DEVEPTIMR7 (0x400381DC) /**< (USBHS) Device Endpoint Interrupt Mask Register 7 */
|
||||
#define REG_USBHS_DEVEPTIMR8 (0x400381E0) /**< (USBHS) Device Endpoint Interrupt Mask Register 8 */
|
||||
#define REG_USBHS_DEVEPTIMR9 (0x400381E4) /**< (USBHS) Device Endpoint Interrupt Mask Register 9 */
|
||||
#define REG_USBHS_DEVEPTIER (0x400381F0) /**< (USBHS) Device Endpoint Interrupt Enable Register */
|
||||
#define REG_USBHS_DEVEPTIER0 (0x400381F0) /**< (USBHS) Device Endpoint Interrupt Enable Register 0 */
|
||||
#define REG_USBHS_DEVEPTIER1 (0x400381F4) /**< (USBHS) Device Endpoint Interrupt Enable Register 1 */
|
||||
#define REG_USBHS_DEVEPTIER2 (0x400381F8) /**< (USBHS) Device Endpoint Interrupt Enable Register 2 */
|
||||
#define REG_USBHS_DEVEPTIER3 (0x400381FC) /**< (USBHS) Device Endpoint Interrupt Enable Register 3 */
|
||||
#define REG_USBHS_DEVEPTIER4 (0x40038200) /**< (USBHS) Device Endpoint Interrupt Enable Register 4 */
|
||||
#define REG_USBHS_DEVEPTIER5 (0x40038204) /**< (USBHS) Device Endpoint Interrupt Enable Register 5 */
|
||||
#define REG_USBHS_DEVEPTIER6 (0x40038208) /**< (USBHS) Device Endpoint Interrupt Enable Register 6 */
|
||||
#define REG_USBHS_DEVEPTIER7 (0x4003820C) /**< (USBHS) Device Endpoint Interrupt Enable Register 7 */
|
||||
#define REG_USBHS_DEVEPTIER8 (0x40038210) /**< (USBHS) Device Endpoint Interrupt Enable Register 8 */
|
||||
#define REG_USBHS_DEVEPTIER9 (0x40038214) /**< (USBHS) Device Endpoint Interrupt Enable Register 9 */
|
||||
#define REG_USBHS_DEVEPTIDR (0x40038220) /**< (USBHS) Device Endpoint Interrupt Disable Register */
|
||||
#define REG_USBHS_DEVEPTIDR0 (0x40038220) /**< (USBHS) Device Endpoint Interrupt Disable Register 0 */
|
||||
#define REG_USBHS_DEVEPTIDR1 (0x40038224) /**< (USBHS) Device Endpoint Interrupt Disable Register 1 */
|
||||
#define REG_USBHS_DEVEPTIDR2 (0x40038228) /**< (USBHS) Device Endpoint Interrupt Disable Register 2 */
|
||||
#define REG_USBHS_DEVEPTIDR3 (0x4003822C) /**< (USBHS) Device Endpoint Interrupt Disable Register 3 */
|
||||
#define REG_USBHS_DEVEPTIDR4 (0x40038230) /**< (USBHS) Device Endpoint Interrupt Disable Register 4 */
|
||||
#define REG_USBHS_DEVEPTIDR5 (0x40038234) /**< (USBHS) Device Endpoint Interrupt Disable Register 5 */
|
||||
#define REG_USBHS_DEVEPTIDR6 (0x40038238) /**< (USBHS) Device Endpoint Interrupt Disable Register 6 */
|
||||
#define REG_USBHS_DEVEPTIDR7 (0x4003823C) /**< (USBHS) Device Endpoint Interrupt Disable Register 7 */
|
||||
#define REG_USBHS_DEVEPTIDR8 (0x40038240) /**< (USBHS) Device Endpoint Interrupt Disable Register 8 */
|
||||
#define REG_USBHS_DEVEPTIDR9 (0x40038244) /**< (USBHS) Device Endpoint Interrupt Disable Register 9 */
|
||||
#define REG_USBHS_HSTCTRL (0x40038400) /**< (USBHS) Host General Control Register */
|
||||
#define REG_USBHS_HSTISR (0x40038404) /**< (USBHS) Host Global Interrupt Status Register */
|
||||
#define REG_USBHS_HSTICR (0x40038408) /**< (USBHS) Host Global Interrupt Clear Register */
|
||||
#define REG_USBHS_HSTIFR (0x4003840C) /**< (USBHS) Host Global Interrupt Set Register */
|
||||
#define REG_USBHS_HSTIMR (0x40038410) /**< (USBHS) Host Global Interrupt Mask Register */
|
||||
#define REG_USBHS_HSTIDR (0x40038414) /**< (USBHS) Host Global Interrupt Disable Register */
|
||||
#define REG_USBHS_HSTIER (0x40038418) /**< (USBHS) Host Global Interrupt Enable Register */
|
||||
#define REG_USBHS_HSTPIP (0x4003841C) /**< (USBHS) Host Pipe Register */
|
||||
#define REG_USBHS_HSTFNUM (0x40038420) /**< (USBHS) Host Frame Number Register */
|
||||
#define REG_USBHS_HSTADDR1 (0x40038424) /**< (USBHS) Host Address 1 Register */
|
||||
#define REG_USBHS_HSTADDR2 (0x40038428) /**< (USBHS) Host Address 2 Register */
|
||||
#define REG_USBHS_HSTADDR3 (0x4003842C) /**< (USBHS) Host Address 3 Register */
|
||||
#define REG_USBHS_HSTPIPCFG (0x40038500) /**< (USBHS) Host Pipe Configuration Register */
|
||||
#define REG_USBHS_HSTPIPCFG0 (0x40038500) /**< (USBHS) Host Pipe Configuration Register 0 */
|
||||
#define REG_USBHS_HSTPIPCFG1 (0x40038504) /**< (USBHS) Host Pipe Configuration Register 1 */
|
||||
#define REG_USBHS_HSTPIPCFG2 (0x40038508) /**< (USBHS) Host Pipe Configuration Register 2 */
|
||||
#define REG_USBHS_HSTPIPCFG3 (0x4003850C) /**< (USBHS) Host Pipe Configuration Register 3 */
|
||||
#define REG_USBHS_HSTPIPCFG4 (0x40038510) /**< (USBHS) Host Pipe Configuration Register 4 */
|
||||
#define REG_USBHS_HSTPIPCFG5 (0x40038514) /**< (USBHS) Host Pipe Configuration Register 5 */
|
||||
#define REG_USBHS_HSTPIPCFG6 (0x40038518) /**< (USBHS) Host Pipe Configuration Register 6 */
|
||||
#define REG_USBHS_HSTPIPCFG7 (0x4003851C) /**< (USBHS) Host Pipe Configuration Register 7 */
|
||||
#define REG_USBHS_HSTPIPCFG8 (0x40038520) /**< (USBHS) Host Pipe Configuration Register 8 */
|
||||
#define REG_USBHS_HSTPIPCFG9 (0x40038524) /**< (USBHS) Host Pipe Configuration Register 9 */
|
||||
#define REG_USBHS_HSTPIPISR (0x40038530) /**< (USBHS) Host Pipe Status Register */
|
||||
#define REG_USBHS_HSTPIPISR0 (0x40038530) /**< (USBHS) Host Pipe Status Register 0 */
|
||||
#define REG_USBHS_HSTPIPISR1 (0x40038534) /**< (USBHS) Host Pipe Status Register 1 */
|
||||
#define REG_USBHS_HSTPIPISR2 (0x40038538) /**< (USBHS) Host Pipe Status Register 2 */
|
||||
#define REG_USBHS_HSTPIPISR3 (0x4003853C) /**< (USBHS) Host Pipe Status Register 3 */
|
||||
#define REG_USBHS_HSTPIPISR4 (0x40038540) /**< (USBHS) Host Pipe Status Register 4 */
|
||||
#define REG_USBHS_HSTPIPISR5 (0x40038544) /**< (USBHS) Host Pipe Status Register 5 */
|
||||
#define REG_USBHS_HSTPIPISR6 (0x40038548) /**< (USBHS) Host Pipe Status Register 6 */
|
||||
#define REG_USBHS_HSTPIPISR7 (0x4003854C) /**< (USBHS) Host Pipe Status Register 7 */
|
||||
#define REG_USBHS_HSTPIPISR8 (0x40038550) /**< (USBHS) Host Pipe Status Register 8 */
|
||||
#define REG_USBHS_HSTPIPISR9 (0x40038554) /**< (USBHS) Host Pipe Status Register 9 */
|
||||
#define REG_USBHS_HSTPIPICR (0x40038560) /**< (USBHS) Host Pipe Clear Register */
|
||||
#define REG_USBHS_HSTPIPICR0 (0x40038560) /**< (USBHS) Host Pipe Clear Register 0 */
|
||||
#define REG_USBHS_HSTPIPICR1 (0x40038564) /**< (USBHS) Host Pipe Clear Register 1 */
|
||||
#define REG_USBHS_HSTPIPICR2 (0x40038568) /**< (USBHS) Host Pipe Clear Register 2 */
|
||||
#define REG_USBHS_HSTPIPICR3 (0x4003856C) /**< (USBHS) Host Pipe Clear Register 3 */
|
||||
#define REG_USBHS_HSTPIPICR4 (0x40038570) /**< (USBHS) Host Pipe Clear Register 4 */
|
||||
#define REG_USBHS_HSTPIPICR5 (0x40038574) /**< (USBHS) Host Pipe Clear Register 5 */
|
||||
#define REG_USBHS_HSTPIPICR6 (0x40038578) /**< (USBHS) Host Pipe Clear Register 6 */
|
||||
#define REG_USBHS_HSTPIPICR7 (0x4003857C) /**< (USBHS) Host Pipe Clear Register 7 */
|
||||
#define REG_USBHS_HSTPIPICR8 (0x40038580) /**< (USBHS) Host Pipe Clear Register 8 */
|
||||
#define REG_USBHS_HSTPIPICR9 (0x40038584) /**< (USBHS) Host Pipe Clear Register 9 */
|
||||
#define REG_USBHS_HSTPIPIFR (0x40038590) /**< (USBHS) Host Pipe Set Register */
|
||||
#define REG_USBHS_HSTPIPIFR0 (0x40038590) /**< (USBHS) Host Pipe Set Register 0 */
|
||||
#define REG_USBHS_HSTPIPIFR1 (0x40038594) /**< (USBHS) Host Pipe Set Register 1 */
|
||||
#define REG_USBHS_HSTPIPIFR2 (0x40038598) /**< (USBHS) Host Pipe Set Register 2 */
|
||||
#define REG_USBHS_HSTPIPIFR3 (0x4003859C) /**< (USBHS) Host Pipe Set Register 3 */
|
||||
#define REG_USBHS_HSTPIPIFR4 (0x400385A0) /**< (USBHS) Host Pipe Set Register 4 */
|
||||
#define REG_USBHS_HSTPIPIFR5 (0x400385A4) /**< (USBHS) Host Pipe Set Register 5 */
|
||||
#define REG_USBHS_HSTPIPIFR6 (0x400385A8) /**< (USBHS) Host Pipe Set Register 6 */
|
||||
#define REG_USBHS_HSTPIPIFR7 (0x400385AC) /**< (USBHS) Host Pipe Set Register 7 */
|
||||
#define REG_USBHS_HSTPIPIFR8 (0x400385B0) /**< (USBHS) Host Pipe Set Register 8 */
|
||||
#define REG_USBHS_HSTPIPIFR9 (0x400385B4) /**< (USBHS) Host Pipe Set Register 9 */
|
||||
#define REG_USBHS_HSTPIPIMR (0x400385C0) /**< (USBHS) Host Pipe Mask Register */
|
||||
#define REG_USBHS_HSTPIPIMR0 (0x400385C0) /**< (USBHS) Host Pipe Mask Register 0 */
|
||||
#define REG_USBHS_HSTPIPIMR1 (0x400385C4) /**< (USBHS) Host Pipe Mask Register 1 */
|
||||
#define REG_USBHS_HSTPIPIMR2 (0x400385C8) /**< (USBHS) Host Pipe Mask Register 2 */
|
||||
#define REG_USBHS_HSTPIPIMR3 (0x400385CC) /**< (USBHS) Host Pipe Mask Register 3 */
|
||||
#define REG_USBHS_HSTPIPIMR4 (0x400385D0) /**< (USBHS) Host Pipe Mask Register 4 */
|
||||
#define REG_USBHS_HSTPIPIMR5 (0x400385D4) /**< (USBHS) Host Pipe Mask Register 5 */
|
||||
#define REG_USBHS_HSTPIPIMR6 (0x400385D8) /**< (USBHS) Host Pipe Mask Register 6 */
|
||||
#define REG_USBHS_HSTPIPIMR7 (0x400385DC) /**< (USBHS) Host Pipe Mask Register 7 */
|
||||
#define REG_USBHS_HSTPIPIMR8 (0x400385E0) /**< (USBHS) Host Pipe Mask Register 8 */
|
||||
#define REG_USBHS_HSTPIPIMR9 (0x400385E4) /**< (USBHS) Host Pipe Mask Register 9 */
|
||||
#define REG_USBHS_HSTPIPIER (0x400385F0) /**< (USBHS) Host Pipe Enable Register */
|
||||
#define REG_USBHS_HSTPIPIER0 (0x400385F0) /**< (USBHS) Host Pipe Enable Register 0 */
|
||||
#define REG_USBHS_HSTPIPIER1 (0x400385F4) /**< (USBHS) Host Pipe Enable Register 1 */
|
||||
#define REG_USBHS_HSTPIPIER2 (0x400385F8) /**< (USBHS) Host Pipe Enable Register 2 */
|
||||
#define REG_USBHS_HSTPIPIER3 (0x400385FC) /**< (USBHS) Host Pipe Enable Register 3 */
|
||||
#define REG_USBHS_HSTPIPIER4 (0x40038600) /**< (USBHS) Host Pipe Enable Register 4 */
|
||||
#define REG_USBHS_HSTPIPIER5 (0x40038604) /**< (USBHS) Host Pipe Enable Register 5 */
|
||||
#define REG_USBHS_HSTPIPIER6 (0x40038608) /**< (USBHS) Host Pipe Enable Register 6 */
|
||||
#define REG_USBHS_HSTPIPIER7 (0x4003860C) /**< (USBHS) Host Pipe Enable Register 7 */
|
||||
#define REG_USBHS_HSTPIPIER8 (0x40038610) /**< (USBHS) Host Pipe Enable Register 8 */
|
||||
#define REG_USBHS_HSTPIPIER9 (0x40038614) /**< (USBHS) Host Pipe Enable Register 9 */
|
||||
#define REG_USBHS_HSTPIPIDR (0x40038620) /**< (USBHS) Host Pipe Disable Register */
|
||||
#define REG_USBHS_HSTPIPIDR0 (0x40038620) /**< (USBHS) Host Pipe Disable Register 0 */
|
||||
#define REG_USBHS_HSTPIPIDR1 (0x40038624) /**< (USBHS) Host Pipe Disable Register 1 */
|
||||
#define REG_USBHS_HSTPIPIDR2 (0x40038628) /**< (USBHS) Host Pipe Disable Register 2 */
|
||||
#define REG_USBHS_HSTPIPIDR3 (0x4003862C) /**< (USBHS) Host Pipe Disable Register 3 */
|
||||
#define REG_USBHS_HSTPIPIDR4 (0x40038630) /**< (USBHS) Host Pipe Disable Register 4 */
|
||||
#define REG_USBHS_HSTPIPIDR5 (0x40038634) /**< (USBHS) Host Pipe Disable Register 5 */
|
||||
#define REG_USBHS_HSTPIPIDR6 (0x40038638) /**< (USBHS) Host Pipe Disable Register 6 */
|
||||
#define REG_USBHS_HSTPIPIDR7 (0x4003863C) /**< (USBHS) Host Pipe Disable Register 7 */
|
||||
#define REG_USBHS_HSTPIPIDR8 (0x40038640) /**< (USBHS) Host Pipe Disable Register 8 */
|
||||
#define REG_USBHS_HSTPIPIDR9 (0x40038644) /**< (USBHS) Host Pipe Disable Register 9 */
|
||||
#define REG_USBHS_HSTPIPINRQ (0x40038650) /**< (USBHS) Host Pipe IN Request Register */
|
||||
#define REG_USBHS_HSTPIPINRQ0 (0x40038650) /**< (USBHS) Host Pipe IN Request Register 0 */
|
||||
#define REG_USBHS_HSTPIPINRQ1 (0x40038654) /**< (USBHS) Host Pipe IN Request Register 1 */
|
||||
#define REG_USBHS_HSTPIPINRQ2 (0x40038658) /**< (USBHS) Host Pipe IN Request Register 2 */
|
||||
#define REG_USBHS_HSTPIPINRQ3 (0x4003865C) /**< (USBHS) Host Pipe IN Request Register 3 */
|
||||
#define REG_USBHS_HSTPIPINRQ4 (0x40038660) /**< (USBHS) Host Pipe IN Request Register 4 */
|
||||
#define REG_USBHS_HSTPIPINRQ5 (0x40038664) /**< (USBHS) Host Pipe IN Request Register 5 */
|
||||
#define REG_USBHS_HSTPIPINRQ6 (0x40038668) /**< (USBHS) Host Pipe IN Request Register 6 */
|
||||
#define REG_USBHS_HSTPIPINRQ7 (0x4003866C) /**< (USBHS) Host Pipe IN Request Register 7 */
|
||||
#define REG_USBHS_HSTPIPINRQ8 (0x40038670) /**< (USBHS) Host Pipe IN Request Register 8 */
|
||||
#define REG_USBHS_HSTPIPINRQ9 (0x40038674) /**< (USBHS) Host Pipe IN Request Register 9 */
|
||||
#define REG_USBHS_HSTPIPERR (0x40038680) /**< (USBHS) Host Pipe Error Register */
|
||||
#define REG_USBHS_HSTPIPERR0 (0x40038680) /**< (USBHS) Host Pipe Error Register 0 */
|
||||
#define REG_USBHS_HSTPIPERR1 (0x40038684) /**< (USBHS) Host Pipe Error Register 1 */
|
||||
#define REG_USBHS_HSTPIPERR2 (0x40038688) /**< (USBHS) Host Pipe Error Register 2 */
|
||||
#define REG_USBHS_HSTPIPERR3 (0x4003868C) /**< (USBHS) Host Pipe Error Register 3 */
|
||||
#define REG_USBHS_HSTPIPERR4 (0x40038690) /**< (USBHS) Host Pipe Error Register 4 */
|
||||
#define REG_USBHS_HSTPIPERR5 (0x40038694) /**< (USBHS) Host Pipe Error Register 5 */
|
||||
#define REG_USBHS_HSTPIPERR6 (0x40038698) /**< (USBHS) Host Pipe Error Register 6 */
|
||||
#define REG_USBHS_HSTPIPERR7 (0x4003869C) /**< (USBHS) Host Pipe Error Register 7 */
|
||||
#define REG_USBHS_HSTPIPERR8 (0x400386A0) /**< (USBHS) Host Pipe Error Register 8 */
|
||||
#define REG_USBHS_HSTPIPERR9 (0x400386A4) /**< (USBHS) Host Pipe Error Register 9 */
|
||||
#define REG_USBHS_CTRL (0x40038800) /**< (USBHS) General Control Register */
|
||||
#define REG_USBHS_SR (0x40038804) /**< (USBHS) General Status Register */
|
||||
#define REG_USBHS_SCR (0x40038808) /**< (USBHS) General Status Clear Register */
|
||||
#define REG_USBHS_SFR (0x4003880C) /**< (USBHS) General Status Set Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_USBHS_DEVDMANXTDSC0 (*(__IO uint32_t*)0x40038310U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 0 */
|
||||
#define REG_USBHS_DEVDMAADDRESS0 (*(__IO uint32_t*)0x40038314U) /**< (USBHS) Device DMA Channel Address Register 0 */
|
||||
#define REG_USBHS_DEVDMACONTROL0 (*(__IO uint32_t*)0x40038318U) /**< (USBHS) Device DMA Channel Control Register 0 */
|
||||
#define REG_USBHS_DEVDMASTATUS0 (*(__IO uint32_t*)0x4003831CU) /**< (USBHS) Device DMA Channel Status Register 0 */
|
||||
#define REG_USBHS_DEVDMANXTDSC1 (*(__IO uint32_t*)0x40038320U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 1 */
|
||||
#define REG_USBHS_DEVDMAADDRESS1 (*(__IO uint32_t*)0x40038324U) /**< (USBHS) Device DMA Channel Address Register 1 */
|
||||
#define REG_USBHS_DEVDMACONTROL1 (*(__IO uint32_t*)0x40038328U) /**< (USBHS) Device DMA Channel Control Register 1 */
|
||||
#define REG_USBHS_DEVDMASTATUS1 (*(__IO uint32_t*)0x4003832CU) /**< (USBHS) Device DMA Channel Status Register 1 */
|
||||
#define REG_USBHS_DEVDMANXTDSC2 (*(__IO uint32_t*)0x40038330U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 2 */
|
||||
#define REG_USBHS_DEVDMAADDRESS2 (*(__IO uint32_t*)0x40038334U) /**< (USBHS) Device DMA Channel Address Register 2 */
|
||||
#define REG_USBHS_DEVDMACONTROL2 (*(__IO uint32_t*)0x40038338U) /**< (USBHS) Device DMA Channel Control Register 2 */
|
||||
#define REG_USBHS_DEVDMASTATUS2 (*(__IO uint32_t*)0x4003833CU) /**< (USBHS) Device DMA Channel Status Register 2 */
|
||||
#define REG_USBHS_DEVDMANXTDSC3 (*(__IO uint32_t*)0x40038340U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 3 */
|
||||
#define REG_USBHS_DEVDMAADDRESS3 (*(__IO uint32_t*)0x40038344U) /**< (USBHS) Device DMA Channel Address Register 3 */
|
||||
#define REG_USBHS_DEVDMACONTROL3 (*(__IO uint32_t*)0x40038348U) /**< (USBHS) Device DMA Channel Control Register 3 */
|
||||
#define REG_USBHS_DEVDMASTATUS3 (*(__IO uint32_t*)0x4003834CU) /**< (USBHS) Device DMA Channel Status Register 3 */
|
||||
#define REG_USBHS_DEVDMANXTDSC4 (*(__IO uint32_t*)0x40038350U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 4 */
|
||||
#define REG_USBHS_DEVDMAADDRESS4 (*(__IO uint32_t*)0x40038354U) /**< (USBHS) Device DMA Channel Address Register 4 */
|
||||
#define REG_USBHS_DEVDMACONTROL4 (*(__IO uint32_t*)0x40038358U) /**< (USBHS) Device DMA Channel Control Register 4 */
|
||||
#define REG_USBHS_DEVDMASTATUS4 (*(__IO uint32_t*)0x4003835CU) /**< (USBHS) Device DMA Channel Status Register 4 */
|
||||
#define REG_USBHS_DEVDMANXTDSC5 (*(__IO uint32_t*)0x40038360U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 5 */
|
||||
#define REG_USBHS_DEVDMAADDRESS5 (*(__IO uint32_t*)0x40038364U) /**< (USBHS) Device DMA Channel Address Register 5 */
|
||||
#define REG_USBHS_DEVDMACONTROL5 (*(__IO uint32_t*)0x40038368U) /**< (USBHS) Device DMA Channel Control Register 5 */
|
||||
#define REG_USBHS_DEVDMASTATUS5 (*(__IO uint32_t*)0x4003836CU) /**< (USBHS) Device DMA Channel Status Register 5 */
|
||||
#define REG_USBHS_DEVDMANXTDSC6 (*(__IO uint32_t*)0x40038370U) /**< (USBHS) Device DMA Channel Next Descriptor Address Register 6 */
|
||||
#define REG_USBHS_DEVDMAADDRESS6 (*(__IO uint32_t*)0x40038374U) /**< (USBHS) Device DMA Channel Address Register 6 */
|
||||
#define REG_USBHS_DEVDMACONTROL6 (*(__IO uint32_t*)0x40038378U) /**< (USBHS) Device DMA Channel Control Register 6 */
|
||||
#define REG_USBHS_DEVDMASTATUS6 (*(__IO uint32_t*)0x4003837CU) /**< (USBHS) Device DMA Channel Status Register 6 */
|
||||
#define REG_USBHS_HSTDMANXTDSC0 (*(__IO uint32_t*)0x40038710U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 0 */
|
||||
#define REG_USBHS_HSTDMAADDRESS0 (*(__IO uint32_t*)0x40038714U) /**< (USBHS) Host DMA Channel Address Register 0 */
|
||||
#define REG_USBHS_HSTDMACONTROL0 (*(__IO uint32_t*)0x40038718U) /**< (USBHS) Host DMA Channel Control Register 0 */
|
||||
#define REG_USBHS_HSTDMASTATUS0 (*(__IO uint32_t*)0x4003871CU) /**< (USBHS) Host DMA Channel Status Register 0 */
|
||||
#define REG_USBHS_HSTDMANXTDSC1 (*(__IO uint32_t*)0x40038720U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 1 */
|
||||
#define REG_USBHS_HSTDMAADDRESS1 (*(__IO uint32_t*)0x40038724U) /**< (USBHS) Host DMA Channel Address Register 1 */
|
||||
#define REG_USBHS_HSTDMACONTROL1 (*(__IO uint32_t*)0x40038728U) /**< (USBHS) Host DMA Channel Control Register 1 */
|
||||
#define REG_USBHS_HSTDMASTATUS1 (*(__IO uint32_t*)0x4003872CU) /**< (USBHS) Host DMA Channel Status Register 1 */
|
||||
#define REG_USBHS_HSTDMANXTDSC2 (*(__IO uint32_t*)0x40038730U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 2 */
|
||||
#define REG_USBHS_HSTDMAADDRESS2 (*(__IO uint32_t*)0x40038734U) /**< (USBHS) Host DMA Channel Address Register 2 */
|
||||
#define REG_USBHS_HSTDMACONTROL2 (*(__IO uint32_t*)0x40038738U) /**< (USBHS) Host DMA Channel Control Register 2 */
|
||||
#define REG_USBHS_HSTDMASTATUS2 (*(__IO uint32_t*)0x4003873CU) /**< (USBHS) Host DMA Channel Status Register 2 */
|
||||
#define REG_USBHS_HSTDMANXTDSC3 (*(__IO uint32_t*)0x40038740U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 3 */
|
||||
#define REG_USBHS_HSTDMAADDRESS3 (*(__IO uint32_t*)0x40038744U) /**< (USBHS) Host DMA Channel Address Register 3 */
|
||||
#define REG_USBHS_HSTDMACONTROL3 (*(__IO uint32_t*)0x40038748U) /**< (USBHS) Host DMA Channel Control Register 3 */
|
||||
#define REG_USBHS_HSTDMASTATUS3 (*(__IO uint32_t*)0x4003874CU) /**< (USBHS) Host DMA Channel Status Register 3 */
|
||||
#define REG_USBHS_HSTDMANXTDSC4 (*(__IO uint32_t*)0x40038750U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 4 */
|
||||
#define REG_USBHS_HSTDMAADDRESS4 (*(__IO uint32_t*)0x40038754U) /**< (USBHS) Host DMA Channel Address Register 4 */
|
||||
#define REG_USBHS_HSTDMACONTROL4 (*(__IO uint32_t*)0x40038758U) /**< (USBHS) Host DMA Channel Control Register 4 */
|
||||
#define REG_USBHS_HSTDMASTATUS4 (*(__IO uint32_t*)0x4003875CU) /**< (USBHS) Host DMA Channel Status Register 4 */
|
||||
#define REG_USBHS_HSTDMANXTDSC5 (*(__IO uint32_t*)0x40038760U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 5 */
|
||||
#define REG_USBHS_HSTDMAADDRESS5 (*(__IO uint32_t*)0x40038764U) /**< (USBHS) Host DMA Channel Address Register 5 */
|
||||
#define REG_USBHS_HSTDMACONTROL5 (*(__IO uint32_t*)0x40038768U) /**< (USBHS) Host DMA Channel Control Register 5 */
|
||||
#define REG_USBHS_HSTDMASTATUS5 (*(__IO uint32_t*)0x4003876CU) /**< (USBHS) Host DMA Channel Status Register 5 */
|
||||
#define REG_USBHS_HSTDMANXTDSC6 (*(__IO uint32_t*)0x40038770U) /**< (USBHS) Host DMA Channel Next Descriptor Address Register 6 */
|
||||
#define REG_USBHS_HSTDMAADDRESS6 (*(__IO uint32_t*)0x40038774U) /**< (USBHS) Host DMA Channel Address Register 6 */
|
||||
#define REG_USBHS_HSTDMACONTROL6 (*(__IO uint32_t*)0x40038778U) /**< (USBHS) Host DMA Channel Control Register 6 */
|
||||
#define REG_USBHS_HSTDMASTATUS6 (*(__IO uint32_t*)0x4003877CU) /**< (USBHS) Host DMA Channel Status Register 6 */
|
||||
#define REG_USBHS_DEVCTRL (*(__IO uint32_t*)0x40038000U) /**< (USBHS) Device General Control Register */
|
||||
#define REG_USBHS_DEVISR (*(__I uint32_t*)0x40038004U) /**< (USBHS) Device Global Interrupt Status Register */
|
||||
#define REG_USBHS_DEVICR (*(__O uint32_t*)0x40038008U) /**< (USBHS) Device Global Interrupt Clear Register */
|
||||
#define REG_USBHS_DEVIFR (*(__O uint32_t*)0x4003800CU) /**< (USBHS) Device Global Interrupt Set Register */
|
||||
#define REG_USBHS_DEVIMR (*(__I uint32_t*)0x40038010U) /**< (USBHS) Device Global Interrupt Mask Register */
|
||||
#define REG_USBHS_DEVIDR (*(__O uint32_t*)0x40038014U) /**< (USBHS) Device Global Interrupt Disable Register */
|
||||
#define REG_USBHS_DEVIER (*(__O uint32_t*)0x40038018U) /**< (USBHS) Device Global Interrupt Enable Register */
|
||||
#define REG_USBHS_DEVEPT (*(__IO uint32_t*)0x4003801CU) /**< (USBHS) Device Endpoint Register */
|
||||
#define REG_USBHS_DEVFNUM (*(__I uint32_t*)0x40038020U) /**< (USBHS) Device Frame Number Register */
|
||||
#define REG_USBHS_DEVEPTCFG (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register */
|
||||
#define REG_USBHS_DEVEPTCFG0 (*(__IO uint32_t*)0x40038100U) /**< (USBHS) Device Endpoint Configuration Register 0 */
|
||||
#define REG_USBHS_DEVEPTCFG1 (*(__IO uint32_t*)0x40038104U) /**< (USBHS) Device Endpoint Configuration Register 1 */
|
||||
#define REG_USBHS_DEVEPTCFG2 (*(__IO uint32_t*)0x40038108U) /**< (USBHS) Device Endpoint Configuration Register 2 */
|
||||
#define REG_USBHS_DEVEPTCFG3 (*(__IO uint32_t*)0x4003810CU) /**< (USBHS) Device Endpoint Configuration Register 3 */
|
||||
#define REG_USBHS_DEVEPTCFG4 (*(__IO uint32_t*)0x40038110U) /**< (USBHS) Device Endpoint Configuration Register 4 */
|
||||
#define REG_USBHS_DEVEPTCFG5 (*(__IO uint32_t*)0x40038114U) /**< (USBHS) Device Endpoint Configuration Register 5 */
|
||||
#define REG_USBHS_DEVEPTCFG6 (*(__IO uint32_t*)0x40038118U) /**< (USBHS) Device Endpoint Configuration Register 6 */
|
||||
#define REG_USBHS_DEVEPTCFG7 (*(__IO uint32_t*)0x4003811CU) /**< (USBHS) Device Endpoint Configuration Register 7 */
|
||||
#define REG_USBHS_DEVEPTCFG8 (*(__IO uint32_t*)0x40038120U) /**< (USBHS) Device Endpoint Configuration Register 8 */
|
||||
#define REG_USBHS_DEVEPTCFG9 (*(__IO uint32_t*)0x40038124U) /**< (USBHS) Device Endpoint Configuration Register 9 */
|
||||
#define REG_USBHS_DEVEPTISR (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Interrupt Status Register */
|
||||
#define REG_USBHS_DEVEPTISR0 (*(__I uint32_t*)0x40038130U) /**< (USBHS) Device Endpoint Interrupt Status Register 0 */
|
||||
#define REG_USBHS_DEVEPTISR1 (*(__I uint32_t*)0x40038134U) /**< (USBHS) Device Endpoint Interrupt Status Register 1 */
|
||||
#define REG_USBHS_DEVEPTISR2 (*(__I uint32_t*)0x40038138U) /**< (USBHS) Device Endpoint Interrupt Status Register 2 */
|
||||
#define REG_USBHS_DEVEPTISR3 (*(__I uint32_t*)0x4003813CU) /**< (USBHS) Device Endpoint Interrupt Status Register 3 */
|
||||
#define REG_USBHS_DEVEPTISR4 (*(__I uint32_t*)0x40038140U) /**< (USBHS) Device Endpoint Interrupt Status Register 4 */
|
||||
#define REG_USBHS_DEVEPTISR5 (*(__I uint32_t*)0x40038144U) /**< (USBHS) Device Endpoint Interrupt Status Register 5 */
|
||||
#define REG_USBHS_DEVEPTISR6 (*(__I uint32_t*)0x40038148U) /**< (USBHS) Device Endpoint Interrupt Status Register 6 */
|
||||
#define REG_USBHS_DEVEPTISR7 (*(__I uint32_t*)0x4003814CU) /**< (USBHS) Device Endpoint Interrupt Status Register 7 */
|
||||
#define REG_USBHS_DEVEPTISR8 (*(__I uint32_t*)0x40038150U) /**< (USBHS) Device Endpoint Interrupt Status Register 8 */
|
||||
#define REG_USBHS_DEVEPTISR9 (*(__I uint32_t*)0x40038154U) /**< (USBHS) Device Endpoint Interrupt Status Register 9 */
|
||||
#define REG_USBHS_DEVEPTICR (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Interrupt Clear Register */
|
||||
#define REG_USBHS_DEVEPTICR0 (*(__O uint32_t*)0x40038160U) /**< (USBHS) Device Endpoint Interrupt Clear Register 0 */
|
||||
#define REG_USBHS_DEVEPTICR1 (*(__O uint32_t*)0x40038164U) /**< (USBHS) Device Endpoint Interrupt Clear Register 1 */
|
||||
#define REG_USBHS_DEVEPTICR2 (*(__O uint32_t*)0x40038168U) /**< (USBHS) Device Endpoint Interrupt Clear Register 2 */
|
||||
#define REG_USBHS_DEVEPTICR3 (*(__O uint32_t*)0x4003816CU) /**< (USBHS) Device Endpoint Interrupt Clear Register 3 */
|
||||
#define REG_USBHS_DEVEPTICR4 (*(__O uint32_t*)0x40038170U) /**< (USBHS) Device Endpoint Interrupt Clear Register 4 */
|
||||
#define REG_USBHS_DEVEPTICR5 (*(__O uint32_t*)0x40038174U) /**< (USBHS) Device Endpoint Interrupt Clear Register 5 */
|
||||
#define REG_USBHS_DEVEPTICR6 (*(__O uint32_t*)0x40038178U) /**< (USBHS) Device Endpoint Interrupt Clear Register 6 */
|
||||
#define REG_USBHS_DEVEPTICR7 (*(__O uint32_t*)0x4003817CU) /**< (USBHS) Device Endpoint Interrupt Clear Register 7 */
|
||||
#define REG_USBHS_DEVEPTICR8 (*(__O uint32_t*)0x40038180U) /**< (USBHS) Device Endpoint Interrupt Clear Register 8 */
|
||||
#define REG_USBHS_DEVEPTICR9 (*(__O uint32_t*)0x40038184U) /**< (USBHS) Device Endpoint Interrupt Clear Register 9 */
|
||||
#define REG_USBHS_DEVEPTIFR (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Interrupt Set Register */
|
||||
#define REG_USBHS_DEVEPTIFR0 (*(__O uint32_t*)0x40038190U) /**< (USBHS) Device Endpoint Interrupt Set Register 0 */
|
||||
#define REG_USBHS_DEVEPTIFR1 (*(__O uint32_t*)0x40038194U) /**< (USBHS) Device Endpoint Interrupt Set Register 1 */
|
||||
#define REG_USBHS_DEVEPTIFR2 (*(__O uint32_t*)0x40038198U) /**< (USBHS) Device Endpoint Interrupt Set Register 2 */
|
||||
#define REG_USBHS_DEVEPTIFR3 (*(__O uint32_t*)0x4003819CU) /**< (USBHS) Device Endpoint Interrupt Set Register 3 */
|
||||
#define REG_USBHS_DEVEPTIFR4 (*(__O uint32_t*)0x400381A0U) /**< (USBHS) Device Endpoint Interrupt Set Register 4 */
|
||||
#define REG_USBHS_DEVEPTIFR5 (*(__O uint32_t*)0x400381A4U) /**< (USBHS) Device Endpoint Interrupt Set Register 5 */
|
||||
#define REG_USBHS_DEVEPTIFR6 (*(__O uint32_t*)0x400381A8U) /**< (USBHS) Device Endpoint Interrupt Set Register 6 */
|
||||
#define REG_USBHS_DEVEPTIFR7 (*(__O uint32_t*)0x400381ACU) /**< (USBHS) Device Endpoint Interrupt Set Register 7 */
|
||||
#define REG_USBHS_DEVEPTIFR8 (*(__O uint32_t*)0x400381B0U) /**< (USBHS) Device Endpoint Interrupt Set Register 8 */
|
||||
#define REG_USBHS_DEVEPTIFR9 (*(__O uint32_t*)0x400381B4U) /**< (USBHS) Device Endpoint Interrupt Set Register 9 */
|
||||
#define REG_USBHS_DEVEPTIMR (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Interrupt Mask Register */
|
||||
#define REG_USBHS_DEVEPTIMR0 (*(__I uint32_t*)0x400381C0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 0 */
|
||||
#define REG_USBHS_DEVEPTIMR1 (*(__I uint32_t*)0x400381C4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 1 */
|
||||
#define REG_USBHS_DEVEPTIMR2 (*(__I uint32_t*)0x400381C8U) /**< (USBHS) Device Endpoint Interrupt Mask Register 2 */
|
||||
#define REG_USBHS_DEVEPTIMR3 (*(__I uint32_t*)0x400381CCU) /**< (USBHS) Device Endpoint Interrupt Mask Register 3 */
|
||||
#define REG_USBHS_DEVEPTIMR4 (*(__I uint32_t*)0x400381D0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 4 */
|
||||
#define REG_USBHS_DEVEPTIMR5 (*(__I uint32_t*)0x400381D4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 5 */
|
||||
#define REG_USBHS_DEVEPTIMR6 (*(__I uint32_t*)0x400381D8U) /**< (USBHS) Device Endpoint Interrupt Mask Register 6 */
|
||||
#define REG_USBHS_DEVEPTIMR7 (*(__I uint32_t*)0x400381DCU) /**< (USBHS) Device Endpoint Interrupt Mask Register 7 */
|
||||
#define REG_USBHS_DEVEPTIMR8 (*(__I uint32_t*)0x400381E0U) /**< (USBHS) Device Endpoint Interrupt Mask Register 8 */
|
||||
#define REG_USBHS_DEVEPTIMR9 (*(__I uint32_t*)0x400381E4U) /**< (USBHS) Device Endpoint Interrupt Mask Register 9 */
|
||||
#define REG_USBHS_DEVEPTIER (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Interrupt Enable Register */
|
||||
#define REG_USBHS_DEVEPTIER0 (*(__O uint32_t*)0x400381F0U) /**< (USBHS) Device Endpoint Interrupt Enable Register 0 */
|
||||
#define REG_USBHS_DEVEPTIER1 (*(__O uint32_t*)0x400381F4U) /**< (USBHS) Device Endpoint Interrupt Enable Register 1 */
|
||||
#define REG_USBHS_DEVEPTIER2 (*(__O uint32_t*)0x400381F8U) /**< (USBHS) Device Endpoint Interrupt Enable Register 2 */
|
||||
#define REG_USBHS_DEVEPTIER3 (*(__O uint32_t*)0x400381FCU) /**< (USBHS) Device Endpoint Interrupt Enable Register 3 */
|
||||
#define REG_USBHS_DEVEPTIER4 (*(__O uint32_t*)0x40038200U) /**< (USBHS) Device Endpoint Interrupt Enable Register 4 */
|
||||
#define REG_USBHS_DEVEPTIER5 (*(__O uint32_t*)0x40038204U) /**< (USBHS) Device Endpoint Interrupt Enable Register 5 */
|
||||
#define REG_USBHS_DEVEPTIER6 (*(__O uint32_t*)0x40038208U) /**< (USBHS) Device Endpoint Interrupt Enable Register 6 */
|
||||
#define REG_USBHS_DEVEPTIER7 (*(__O uint32_t*)0x4003820CU) /**< (USBHS) Device Endpoint Interrupt Enable Register 7 */
|
||||
#define REG_USBHS_DEVEPTIER8 (*(__O uint32_t*)0x40038210U) /**< (USBHS) Device Endpoint Interrupt Enable Register 8 */
|
||||
#define REG_USBHS_DEVEPTIER9 (*(__O uint32_t*)0x40038214U) /**< (USBHS) Device Endpoint Interrupt Enable Register 9 */
|
||||
#define REG_USBHS_DEVEPTIDR (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Interrupt Disable Register */
|
||||
#define REG_USBHS_DEVEPTIDR0 (*(__O uint32_t*)0x40038220U) /**< (USBHS) Device Endpoint Interrupt Disable Register 0 */
|
||||
#define REG_USBHS_DEVEPTIDR1 (*(__O uint32_t*)0x40038224U) /**< (USBHS) Device Endpoint Interrupt Disable Register 1 */
|
||||
#define REG_USBHS_DEVEPTIDR2 (*(__O uint32_t*)0x40038228U) /**< (USBHS) Device Endpoint Interrupt Disable Register 2 */
|
||||
#define REG_USBHS_DEVEPTIDR3 (*(__O uint32_t*)0x4003822CU) /**< (USBHS) Device Endpoint Interrupt Disable Register 3 */
|
||||
#define REG_USBHS_DEVEPTIDR4 (*(__O uint32_t*)0x40038230U) /**< (USBHS) Device Endpoint Interrupt Disable Register 4 */
|
||||
#define REG_USBHS_DEVEPTIDR5 (*(__O uint32_t*)0x40038234U) /**< (USBHS) Device Endpoint Interrupt Disable Register 5 */
|
||||
#define REG_USBHS_DEVEPTIDR6 (*(__O uint32_t*)0x40038238U) /**< (USBHS) Device Endpoint Interrupt Disable Register 6 */
|
||||
#define REG_USBHS_DEVEPTIDR7 (*(__O uint32_t*)0x4003823CU) /**< (USBHS) Device Endpoint Interrupt Disable Register 7 */
|
||||
#define REG_USBHS_DEVEPTIDR8 (*(__O uint32_t*)0x40038240U) /**< (USBHS) Device Endpoint Interrupt Disable Register 8 */
|
||||
#define REG_USBHS_DEVEPTIDR9 (*(__O uint32_t*)0x40038244U) /**< (USBHS) Device Endpoint Interrupt Disable Register 9 */
|
||||
#define REG_USBHS_HSTCTRL (*(__IO uint32_t*)0x40038400U) /**< (USBHS) Host General Control Register */
|
||||
#define REG_USBHS_HSTISR (*(__I uint32_t*)0x40038404U) /**< (USBHS) Host Global Interrupt Status Register */
|
||||
#define REG_USBHS_HSTICR (*(__O uint32_t*)0x40038408U) /**< (USBHS) Host Global Interrupt Clear Register */
|
||||
#define REG_USBHS_HSTIFR (*(__O uint32_t*)0x4003840CU) /**< (USBHS) Host Global Interrupt Set Register */
|
||||
#define REG_USBHS_HSTIMR (*(__I uint32_t*)0x40038410U) /**< (USBHS) Host Global Interrupt Mask Register */
|
||||
#define REG_USBHS_HSTIDR (*(__O uint32_t*)0x40038414U) /**< (USBHS) Host Global Interrupt Disable Register */
|
||||
#define REG_USBHS_HSTIER (*(__O uint32_t*)0x40038418U) /**< (USBHS) Host Global Interrupt Enable Register */
|
||||
#define REG_USBHS_HSTPIP (*(__IO uint32_t*)0x4003841CU) /**< (USBHS) Host Pipe Register */
|
||||
#define REG_USBHS_HSTFNUM (*(__IO uint32_t*)0x40038420U) /**< (USBHS) Host Frame Number Register */
|
||||
#define REG_USBHS_HSTADDR1 (*(__IO uint32_t*)0x40038424U) /**< (USBHS) Host Address 1 Register */
|
||||
#define REG_USBHS_HSTADDR2 (*(__IO uint32_t*)0x40038428U) /**< (USBHS) Host Address 2 Register */
|
||||
#define REG_USBHS_HSTADDR3 (*(__IO uint32_t*)0x4003842CU) /**< (USBHS) Host Address 3 Register */
|
||||
#define REG_USBHS_HSTPIPCFG (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register */
|
||||
#define REG_USBHS_HSTPIPCFG0 (*(__IO uint32_t*)0x40038500U) /**< (USBHS) Host Pipe Configuration Register 0 */
|
||||
#define REG_USBHS_HSTPIPCFG1 (*(__IO uint32_t*)0x40038504U) /**< (USBHS) Host Pipe Configuration Register 1 */
|
||||
#define REG_USBHS_HSTPIPCFG2 (*(__IO uint32_t*)0x40038508U) /**< (USBHS) Host Pipe Configuration Register 2 */
|
||||
#define REG_USBHS_HSTPIPCFG3 (*(__IO uint32_t*)0x4003850CU) /**< (USBHS) Host Pipe Configuration Register 3 */
|
||||
#define REG_USBHS_HSTPIPCFG4 (*(__IO uint32_t*)0x40038510U) /**< (USBHS) Host Pipe Configuration Register 4 */
|
||||
#define REG_USBHS_HSTPIPCFG5 (*(__IO uint32_t*)0x40038514U) /**< (USBHS) Host Pipe Configuration Register 5 */
|
||||
#define REG_USBHS_HSTPIPCFG6 (*(__IO uint32_t*)0x40038518U) /**< (USBHS) Host Pipe Configuration Register 6 */
|
||||
#define REG_USBHS_HSTPIPCFG7 (*(__IO uint32_t*)0x4003851CU) /**< (USBHS) Host Pipe Configuration Register 7 */
|
||||
#define REG_USBHS_HSTPIPCFG8 (*(__IO uint32_t*)0x40038520U) /**< (USBHS) Host Pipe Configuration Register 8 */
|
||||
#define REG_USBHS_HSTPIPCFG9 (*(__IO uint32_t*)0x40038524U) /**< (USBHS) Host Pipe Configuration Register 9 */
|
||||
#define REG_USBHS_HSTPIPISR (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register */
|
||||
#define REG_USBHS_HSTPIPISR0 (*(__I uint32_t*)0x40038530U) /**< (USBHS) Host Pipe Status Register 0 */
|
||||
#define REG_USBHS_HSTPIPISR1 (*(__I uint32_t*)0x40038534U) /**< (USBHS) Host Pipe Status Register 1 */
|
||||
#define REG_USBHS_HSTPIPISR2 (*(__I uint32_t*)0x40038538U) /**< (USBHS) Host Pipe Status Register 2 */
|
||||
#define REG_USBHS_HSTPIPISR3 (*(__I uint32_t*)0x4003853CU) /**< (USBHS) Host Pipe Status Register 3 */
|
||||
#define REG_USBHS_HSTPIPISR4 (*(__I uint32_t*)0x40038540U) /**< (USBHS) Host Pipe Status Register 4 */
|
||||
#define REG_USBHS_HSTPIPISR5 (*(__I uint32_t*)0x40038544U) /**< (USBHS) Host Pipe Status Register 5 */
|
||||
#define REG_USBHS_HSTPIPISR6 (*(__I uint32_t*)0x40038548U) /**< (USBHS) Host Pipe Status Register 6 */
|
||||
#define REG_USBHS_HSTPIPISR7 (*(__I uint32_t*)0x4003854CU) /**< (USBHS) Host Pipe Status Register 7 */
|
||||
#define REG_USBHS_HSTPIPISR8 (*(__I uint32_t*)0x40038550U) /**< (USBHS) Host Pipe Status Register 8 */
|
||||
#define REG_USBHS_HSTPIPISR9 (*(__I uint32_t*)0x40038554U) /**< (USBHS) Host Pipe Status Register 9 */
|
||||
#define REG_USBHS_HSTPIPICR (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register */
|
||||
#define REG_USBHS_HSTPIPICR0 (*(__O uint32_t*)0x40038560U) /**< (USBHS) Host Pipe Clear Register 0 */
|
||||
#define REG_USBHS_HSTPIPICR1 (*(__O uint32_t*)0x40038564U) /**< (USBHS) Host Pipe Clear Register 1 */
|
||||
#define REG_USBHS_HSTPIPICR2 (*(__O uint32_t*)0x40038568U) /**< (USBHS) Host Pipe Clear Register 2 */
|
||||
#define REG_USBHS_HSTPIPICR3 (*(__O uint32_t*)0x4003856CU) /**< (USBHS) Host Pipe Clear Register 3 */
|
||||
#define REG_USBHS_HSTPIPICR4 (*(__O uint32_t*)0x40038570U) /**< (USBHS) Host Pipe Clear Register 4 */
|
||||
#define REG_USBHS_HSTPIPICR5 (*(__O uint32_t*)0x40038574U) /**< (USBHS) Host Pipe Clear Register 5 */
|
||||
#define REG_USBHS_HSTPIPICR6 (*(__O uint32_t*)0x40038578U) /**< (USBHS) Host Pipe Clear Register 6 */
|
||||
#define REG_USBHS_HSTPIPICR7 (*(__O uint32_t*)0x4003857CU) /**< (USBHS) Host Pipe Clear Register 7 */
|
||||
#define REG_USBHS_HSTPIPICR8 (*(__O uint32_t*)0x40038580U) /**< (USBHS) Host Pipe Clear Register 8 */
|
||||
#define REG_USBHS_HSTPIPICR9 (*(__O uint32_t*)0x40038584U) /**< (USBHS) Host Pipe Clear Register 9 */
|
||||
#define REG_USBHS_HSTPIPIFR (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register */
|
||||
#define REG_USBHS_HSTPIPIFR0 (*(__O uint32_t*)0x40038590U) /**< (USBHS) Host Pipe Set Register 0 */
|
||||
#define REG_USBHS_HSTPIPIFR1 (*(__O uint32_t*)0x40038594U) /**< (USBHS) Host Pipe Set Register 1 */
|
||||
#define REG_USBHS_HSTPIPIFR2 (*(__O uint32_t*)0x40038598U) /**< (USBHS) Host Pipe Set Register 2 */
|
||||
#define REG_USBHS_HSTPIPIFR3 (*(__O uint32_t*)0x4003859CU) /**< (USBHS) Host Pipe Set Register 3 */
|
||||
#define REG_USBHS_HSTPIPIFR4 (*(__O uint32_t*)0x400385A0U) /**< (USBHS) Host Pipe Set Register 4 */
|
||||
#define REG_USBHS_HSTPIPIFR5 (*(__O uint32_t*)0x400385A4U) /**< (USBHS) Host Pipe Set Register 5 */
|
||||
#define REG_USBHS_HSTPIPIFR6 (*(__O uint32_t*)0x400385A8U) /**< (USBHS) Host Pipe Set Register 6 */
|
||||
#define REG_USBHS_HSTPIPIFR7 (*(__O uint32_t*)0x400385ACU) /**< (USBHS) Host Pipe Set Register 7 */
|
||||
#define REG_USBHS_HSTPIPIFR8 (*(__O uint32_t*)0x400385B0U) /**< (USBHS) Host Pipe Set Register 8 */
|
||||
#define REG_USBHS_HSTPIPIFR9 (*(__O uint32_t*)0x400385B4U) /**< (USBHS) Host Pipe Set Register 9 */
|
||||
#define REG_USBHS_HSTPIPIMR (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register */
|
||||
#define REG_USBHS_HSTPIPIMR0 (*(__I uint32_t*)0x400385C0U) /**< (USBHS) Host Pipe Mask Register 0 */
|
||||
#define REG_USBHS_HSTPIPIMR1 (*(__I uint32_t*)0x400385C4U) /**< (USBHS) Host Pipe Mask Register 1 */
|
||||
#define REG_USBHS_HSTPIPIMR2 (*(__I uint32_t*)0x400385C8U) /**< (USBHS) Host Pipe Mask Register 2 */
|
||||
#define REG_USBHS_HSTPIPIMR3 (*(__I uint32_t*)0x400385CCU) /**< (USBHS) Host Pipe Mask Register 3 */
|
||||
#define REG_USBHS_HSTPIPIMR4 (*(__I uint32_t*)0x400385D0U) /**< (USBHS) Host Pipe Mask Register 4 */
|
||||
#define REG_USBHS_HSTPIPIMR5 (*(__I uint32_t*)0x400385D4U) /**< (USBHS) Host Pipe Mask Register 5 */
|
||||
#define REG_USBHS_HSTPIPIMR6 (*(__I uint32_t*)0x400385D8U) /**< (USBHS) Host Pipe Mask Register 6 */
|
||||
#define REG_USBHS_HSTPIPIMR7 (*(__I uint32_t*)0x400385DCU) /**< (USBHS) Host Pipe Mask Register 7 */
|
||||
#define REG_USBHS_HSTPIPIMR8 (*(__I uint32_t*)0x400385E0U) /**< (USBHS) Host Pipe Mask Register 8 */
|
||||
#define REG_USBHS_HSTPIPIMR9 (*(__I uint32_t*)0x400385E4U) /**< (USBHS) Host Pipe Mask Register 9 */
|
||||
#define REG_USBHS_HSTPIPIER (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register */
|
||||
#define REG_USBHS_HSTPIPIER0 (*(__O uint32_t*)0x400385F0U) /**< (USBHS) Host Pipe Enable Register 0 */
|
||||
#define REG_USBHS_HSTPIPIER1 (*(__O uint32_t*)0x400385F4U) /**< (USBHS) Host Pipe Enable Register 1 */
|
||||
#define REG_USBHS_HSTPIPIER2 (*(__O uint32_t*)0x400385F8U) /**< (USBHS) Host Pipe Enable Register 2 */
|
||||
#define REG_USBHS_HSTPIPIER3 (*(__O uint32_t*)0x400385FCU) /**< (USBHS) Host Pipe Enable Register 3 */
|
||||
#define REG_USBHS_HSTPIPIER4 (*(__O uint32_t*)0x40038600U) /**< (USBHS) Host Pipe Enable Register 4 */
|
||||
#define REG_USBHS_HSTPIPIER5 (*(__O uint32_t*)0x40038604U) /**< (USBHS) Host Pipe Enable Register 5 */
|
||||
#define REG_USBHS_HSTPIPIER6 (*(__O uint32_t*)0x40038608U) /**< (USBHS) Host Pipe Enable Register 6 */
|
||||
#define REG_USBHS_HSTPIPIER7 (*(__O uint32_t*)0x4003860CU) /**< (USBHS) Host Pipe Enable Register 7 */
|
||||
#define REG_USBHS_HSTPIPIER8 (*(__O uint32_t*)0x40038610U) /**< (USBHS) Host Pipe Enable Register 8 */
|
||||
#define REG_USBHS_HSTPIPIER9 (*(__O uint32_t*)0x40038614U) /**< (USBHS) Host Pipe Enable Register 9 */
|
||||
#define REG_USBHS_HSTPIPIDR (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register */
|
||||
#define REG_USBHS_HSTPIPIDR0 (*(__O uint32_t*)0x40038620U) /**< (USBHS) Host Pipe Disable Register 0 */
|
||||
#define REG_USBHS_HSTPIPIDR1 (*(__O uint32_t*)0x40038624U) /**< (USBHS) Host Pipe Disable Register 1 */
|
||||
#define REG_USBHS_HSTPIPIDR2 (*(__O uint32_t*)0x40038628U) /**< (USBHS) Host Pipe Disable Register 2 */
|
||||
#define REG_USBHS_HSTPIPIDR3 (*(__O uint32_t*)0x4003862CU) /**< (USBHS) Host Pipe Disable Register 3 */
|
||||
#define REG_USBHS_HSTPIPIDR4 (*(__O uint32_t*)0x40038630U) /**< (USBHS) Host Pipe Disable Register 4 */
|
||||
#define REG_USBHS_HSTPIPIDR5 (*(__O uint32_t*)0x40038634U) /**< (USBHS) Host Pipe Disable Register 5 */
|
||||
#define REG_USBHS_HSTPIPIDR6 (*(__O uint32_t*)0x40038638U) /**< (USBHS) Host Pipe Disable Register 6 */
|
||||
#define REG_USBHS_HSTPIPIDR7 (*(__O uint32_t*)0x4003863CU) /**< (USBHS) Host Pipe Disable Register 7 */
|
||||
#define REG_USBHS_HSTPIPIDR8 (*(__O uint32_t*)0x40038640U) /**< (USBHS) Host Pipe Disable Register 8 */
|
||||
#define REG_USBHS_HSTPIPIDR9 (*(__O uint32_t*)0x40038644U) /**< (USBHS) Host Pipe Disable Register 9 */
|
||||
#define REG_USBHS_HSTPIPINRQ (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register */
|
||||
#define REG_USBHS_HSTPIPINRQ0 (*(__IO uint32_t*)0x40038650U) /**< (USBHS) Host Pipe IN Request Register 0 */
|
||||
#define REG_USBHS_HSTPIPINRQ1 (*(__IO uint32_t*)0x40038654U) /**< (USBHS) Host Pipe IN Request Register 1 */
|
||||
#define REG_USBHS_HSTPIPINRQ2 (*(__IO uint32_t*)0x40038658U) /**< (USBHS) Host Pipe IN Request Register 2 */
|
||||
#define REG_USBHS_HSTPIPINRQ3 (*(__IO uint32_t*)0x4003865CU) /**< (USBHS) Host Pipe IN Request Register 3 */
|
||||
#define REG_USBHS_HSTPIPINRQ4 (*(__IO uint32_t*)0x40038660U) /**< (USBHS) Host Pipe IN Request Register 4 */
|
||||
#define REG_USBHS_HSTPIPINRQ5 (*(__IO uint32_t*)0x40038664U) /**< (USBHS) Host Pipe IN Request Register 5 */
|
||||
#define REG_USBHS_HSTPIPINRQ6 (*(__IO uint32_t*)0x40038668U) /**< (USBHS) Host Pipe IN Request Register 6 */
|
||||
#define REG_USBHS_HSTPIPINRQ7 (*(__IO uint32_t*)0x4003866CU) /**< (USBHS) Host Pipe IN Request Register 7 */
|
||||
#define REG_USBHS_HSTPIPINRQ8 (*(__IO uint32_t*)0x40038670U) /**< (USBHS) Host Pipe IN Request Register 8 */
|
||||
#define REG_USBHS_HSTPIPINRQ9 (*(__IO uint32_t*)0x40038674U) /**< (USBHS) Host Pipe IN Request Register 9 */
|
||||
#define REG_USBHS_HSTPIPERR (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register */
|
||||
#define REG_USBHS_HSTPIPERR0 (*(__IO uint32_t*)0x40038680U) /**< (USBHS) Host Pipe Error Register 0 */
|
||||
#define REG_USBHS_HSTPIPERR1 (*(__IO uint32_t*)0x40038684U) /**< (USBHS) Host Pipe Error Register 1 */
|
||||
#define REG_USBHS_HSTPIPERR2 (*(__IO uint32_t*)0x40038688U) /**< (USBHS) Host Pipe Error Register 2 */
|
||||
#define REG_USBHS_HSTPIPERR3 (*(__IO uint32_t*)0x4003868CU) /**< (USBHS) Host Pipe Error Register 3 */
|
||||
#define REG_USBHS_HSTPIPERR4 (*(__IO uint32_t*)0x40038690U) /**< (USBHS) Host Pipe Error Register 4 */
|
||||
#define REG_USBHS_HSTPIPERR5 (*(__IO uint32_t*)0x40038694U) /**< (USBHS) Host Pipe Error Register 5 */
|
||||
#define REG_USBHS_HSTPIPERR6 (*(__IO uint32_t*)0x40038698U) /**< (USBHS) Host Pipe Error Register 6 */
|
||||
#define REG_USBHS_HSTPIPERR7 (*(__IO uint32_t*)0x4003869CU) /**< (USBHS) Host Pipe Error Register 7 */
|
||||
#define REG_USBHS_HSTPIPERR8 (*(__IO uint32_t*)0x400386A0U) /**< (USBHS) Host Pipe Error Register 8 */
|
||||
#define REG_USBHS_HSTPIPERR9 (*(__IO uint32_t*)0x400386A4U) /**< (USBHS) Host Pipe Error Register 9 */
|
||||
#define REG_USBHS_CTRL (*(__IO uint32_t*)0x40038800U) /**< (USBHS) General Control Register */
|
||||
#define REG_USBHS_SR (*(__I uint32_t*)0x40038804U) /**< (USBHS) General Status Register */
|
||||
#define REG_USBHS_SCR (*(__O uint32_t*)0x40038808U) /**< (USBHS) General Status Clear Register */
|
||||
#define REG_USBHS_SFR (*(__O uint32_t*)0x4003880CU) /**< (USBHS) General Status Set Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for USBHS peripheral ========== */
|
||||
#define USBHS_INSTANCE_ID 34
|
||||
#define USBHS_CLOCK_ID 34
|
||||
|
||||
#endif /* _SAME70_USBHS_INSTANCE_ */
|
||||
46
lib/same70b/include/instance/utmi.h
Normal file
46
lib/same70b/include/instance/utmi.h
Normal file
|
|
@ -0,0 +1,46 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for UTMI
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_UTMI_INSTANCE_H_
|
||||
#define _SAME70_UTMI_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for UTMI peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_UTMI_OHCIICR (0x400E0410) /**< (UTMI) OHCI Interrupt Configuration Register */
|
||||
#define REG_UTMI_CKTRIM (0x400E0430) /**< (UTMI) UTMI Clock Trimming Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_UTMI_OHCIICR (*(__IO uint32_t*)0x400E0410U) /**< (UTMI) OHCI Interrupt Configuration Register */
|
||||
#define REG_UTMI_CKTRIM (*(__IO uint32_t*)0x400E0430U) /**< (UTMI) UTMI Clock Trimming Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
#endif /* _SAME70_UTMI_INSTANCE_ */
|
||||
52
lib/same70b/include/instance/wdt.h
Normal file
52
lib/same70b/include/instance/wdt.h
Normal file
|
|
@ -0,0 +1,52 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for WDT
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_WDT_INSTANCE_H_
|
||||
#define _SAME70_WDT_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for WDT peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_WDT_CR (0x400E1850) /**< (WDT) Control Register */
|
||||
#define REG_WDT_MR (0x400E1854) /**< (WDT) Mode Register */
|
||||
#define REG_WDT_SR (0x400E1858) /**< (WDT) Status Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_WDT_CR (*(__O uint32_t*)0x400E1850U) /**< (WDT) Control Register */
|
||||
#define REG_WDT_MR (*(__IO uint32_t*)0x400E1854U) /**< (WDT) Mode Register */
|
||||
#define REG_WDT_SR (*(__I uint32_t*)0x400E1858U) /**< (WDT) Status Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for WDT peripheral ========== */
|
||||
#define WDT_INSTANCE_ID 4
|
||||
|
||||
#endif /* _SAME70_WDT_INSTANCE_ */
|
||||
753
lib/same70b/include/instance/xdmac.h
Normal file
753
lib/same70b/include/instance/xdmac.h
Normal file
|
|
@ -0,0 +1,753 @@
|
|||
/**
|
||||
* \file
|
||||
*
|
||||
* \brief Instance description for XDMAC
|
||||
*
|
||||
* Copyright (c) 2019 Microchip Technology Inc.
|
||||
*
|
||||
* \license_start
|
||||
*
|
||||
* \page License
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||
* you may not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*
|
||||
* \license_stop
|
||||
*
|
||||
*/
|
||||
|
||||
/* file generated from device description version 2019-01-18T21:19:59Z */
|
||||
#ifndef _SAME70_XDMAC_INSTANCE_H_
|
||||
#define _SAME70_XDMAC_INSTANCE_H_
|
||||
|
||||
/* ========== Register definition for XDMAC peripheral ========== */
|
||||
#if (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__))
|
||||
|
||||
#define REG_XDMAC_CIE0 (0x40078050) /**< (XDMAC) Channel Interrupt Enable Register 0 */
|
||||
#define REG_XDMAC_CID0 (0x40078054) /**< (XDMAC) Channel Interrupt Disable Register 0 */
|
||||
#define REG_XDMAC_CIM0 (0x40078058) /**< (XDMAC) Channel Interrupt Mask Register 0 */
|
||||
#define REG_XDMAC_CIS0 (0x4007805C) /**< (XDMAC) Channel Interrupt Status Register 0 */
|
||||
#define REG_XDMAC_CSA0 (0x40078060) /**< (XDMAC) Channel Source Address Register 0 */
|
||||
#define REG_XDMAC_CDA0 (0x40078064) /**< (XDMAC) Channel Destination Address Register 0 */
|
||||
#define REG_XDMAC_CNDA0 (0x40078068) /**< (XDMAC) Channel Next Descriptor Address Register 0 */
|
||||
#define REG_XDMAC_CNDC0 (0x4007806C) /**< (XDMAC) Channel Next Descriptor Control Register 0 */
|
||||
#define REG_XDMAC_CUBC0 (0x40078070) /**< (XDMAC) Channel Microblock Control Register 0 */
|
||||
#define REG_XDMAC_CBC0 (0x40078074) /**< (XDMAC) Channel Block Control Register 0 */
|
||||
#define REG_XDMAC_CC0 (0x40078078) /**< (XDMAC) Channel Configuration Register 0 */
|
||||
#define REG_XDMAC_CDS_MSP0 (0x4007807C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */
|
||||
#define REG_XDMAC_CSUS0 (0x40078080) /**< (XDMAC) Channel Source Microblock Stride 0 */
|
||||
#define REG_XDMAC_CDUS0 (0x40078084) /**< (XDMAC) Channel Destination Microblock Stride 0 */
|
||||
#define REG_XDMAC_CIE1 (0x40078090) /**< (XDMAC) Channel Interrupt Enable Register 1 */
|
||||
#define REG_XDMAC_CID1 (0x40078094) /**< (XDMAC) Channel Interrupt Disable Register 1 */
|
||||
#define REG_XDMAC_CIM1 (0x40078098) /**< (XDMAC) Channel Interrupt Mask Register 1 */
|
||||
#define REG_XDMAC_CIS1 (0x4007809C) /**< (XDMAC) Channel Interrupt Status Register 1 */
|
||||
#define REG_XDMAC_CSA1 (0x400780A0) /**< (XDMAC) Channel Source Address Register 1 */
|
||||
#define REG_XDMAC_CDA1 (0x400780A4) /**< (XDMAC) Channel Destination Address Register 1 */
|
||||
#define REG_XDMAC_CNDA1 (0x400780A8) /**< (XDMAC) Channel Next Descriptor Address Register 1 */
|
||||
#define REG_XDMAC_CNDC1 (0x400780AC) /**< (XDMAC) Channel Next Descriptor Control Register 1 */
|
||||
#define REG_XDMAC_CUBC1 (0x400780B0) /**< (XDMAC) Channel Microblock Control Register 1 */
|
||||
#define REG_XDMAC_CBC1 (0x400780B4) /**< (XDMAC) Channel Block Control Register 1 */
|
||||
#define REG_XDMAC_CC1 (0x400780B8) /**< (XDMAC) Channel Configuration Register 1 */
|
||||
#define REG_XDMAC_CDS_MSP1 (0x400780BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */
|
||||
#define REG_XDMAC_CSUS1 (0x400780C0) /**< (XDMAC) Channel Source Microblock Stride 1 */
|
||||
#define REG_XDMAC_CDUS1 (0x400780C4) /**< (XDMAC) Channel Destination Microblock Stride 1 */
|
||||
#define REG_XDMAC_CIE2 (0x400780D0) /**< (XDMAC) Channel Interrupt Enable Register 2 */
|
||||
#define REG_XDMAC_CID2 (0x400780D4) /**< (XDMAC) Channel Interrupt Disable Register 2 */
|
||||
#define REG_XDMAC_CIM2 (0x400780D8) /**< (XDMAC) Channel Interrupt Mask Register 2 */
|
||||
#define REG_XDMAC_CIS2 (0x400780DC) /**< (XDMAC) Channel Interrupt Status Register 2 */
|
||||
#define REG_XDMAC_CSA2 (0x400780E0) /**< (XDMAC) Channel Source Address Register 2 */
|
||||
#define REG_XDMAC_CDA2 (0x400780E4) /**< (XDMAC) Channel Destination Address Register 2 */
|
||||
#define REG_XDMAC_CNDA2 (0x400780E8) /**< (XDMAC) Channel Next Descriptor Address Register 2 */
|
||||
#define REG_XDMAC_CNDC2 (0x400780EC) /**< (XDMAC) Channel Next Descriptor Control Register 2 */
|
||||
#define REG_XDMAC_CUBC2 (0x400780F0) /**< (XDMAC) Channel Microblock Control Register 2 */
|
||||
#define REG_XDMAC_CBC2 (0x400780F4) /**< (XDMAC) Channel Block Control Register 2 */
|
||||
#define REG_XDMAC_CC2 (0x400780F8) /**< (XDMAC) Channel Configuration Register 2 */
|
||||
#define REG_XDMAC_CDS_MSP2 (0x400780FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */
|
||||
#define REG_XDMAC_CSUS2 (0x40078100) /**< (XDMAC) Channel Source Microblock Stride 2 */
|
||||
#define REG_XDMAC_CDUS2 (0x40078104) /**< (XDMAC) Channel Destination Microblock Stride 2 */
|
||||
#define REG_XDMAC_CIE3 (0x40078110) /**< (XDMAC) Channel Interrupt Enable Register 3 */
|
||||
#define REG_XDMAC_CID3 (0x40078114) /**< (XDMAC) Channel Interrupt Disable Register 3 */
|
||||
#define REG_XDMAC_CIM3 (0x40078118) /**< (XDMAC) Channel Interrupt Mask Register 3 */
|
||||
#define REG_XDMAC_CIS3 (0x4007811C) /**< (XDMAC) Channel Interrupt Status Register 3 */
|
||||
#define REG_XDMAC_CSA3 (0x40078120) /**< (XDMAC) Channel Source Address Register 3 */
|
||||
#define REG_XDMAC_CDA3 (0x40078124) /**< (XDMAC) Channel Destination Address Register 3 */
|
||||
#define REG_XDMAC_CNDA3 (0x40078128) /**< (XDMAC) Channel Next Descriptor Address Register 3 */
|
||||
#define REG_XDMAC_CNDC3 (0x4007812C) /**< (XDMAC) Channel Next Descriptor Control Register 3 */
|
||||
#define REG_XDMAC_CUBC3 (0x40078130) /**< (XDMAC) Channel Microblock Control Register 3 */
|
||||
#define REG_XDMAC_CBC3 (0x40078134) /**< (XDMAC) Channel Block Control Register 3 */
|
||||
#define REG_XDMAC_CC3 (0x40078138) /**< (XDMAC) Channel Configuration Register 3 */
|
||||
#define REG_XDMAC_CDS_MSP3 (0x4007813C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */
|
||||
#define REG_XDMAC_CSUS3 (0x40078140) /**< (XDMAC) Channel Source Microblock Stride 3 */
|
||||
#define REG_XDMAC_CDUS3 (0x40078144) /**< (XDMAC) Channel Destination Microblock Stride 3 */
|
||||
#define REG_XDMAC_CIE4 (0x40078150) /**< (XDMAC) Channel Interrupt Enable Register 4 */
|
||||
#define REG_XDMAC_CID4 (0x40078154) /**< (XDMAC) Channel Interrupt Disable Register 4 */
|
||||
#define REG_XDMAC_CIM4 (0x40078158) /**< (XDMAC) Channel Interrupt Mask Register 4 */
|
||||
#define REG_XDMAC_CIS4 (0x4007815C) /**< (XDMAC) Channel Interrupt Status Register 4 */
|
||||
#define REG_XDMAC_CSA4 (0x40078160) /**< (XDMAC) Channel Source Address Register 4 */
|
||||
#define REG_XDMAC_CDA4 (0x40078164) /**< (XDMAC) Channel Destination Address Register 4 */
|
||||
#define REG_XDMAC_CNDA4 (0x40078168) /**< (XDMAC) Channel Next Descriptor Address Register 4 */
|
||||
#define REG_XDMAC_CNDC4 (0x4007816C) /**< (XDMAC) Channel Next Descriptor Control Register 4 */
|
||||
#define REG_XDMAC_CUBC4 (0x40078170) /**< (XDMAC) Channel Microblock Control Register 4 */
|
||||
#define REG_XDMAC_CBC4 (0x40078174) /**< (XDMAC) Channel Block Control Register 4 */
|
||||
#define REG_XDMAC_CC4 (0x40078178) /**< (XDMAC) Channel Configuration Register 4 */
|
||||
#define REG_XDMAC_CDS_MSP4 (0x4007817C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */
|
||||
#define REG_XDMAC_CSUS4 (0x40078180) /**< (XDMAC) Channel Source Microblock Stride 4 */
|
||||
#define REG_XDMAC_CDUS4 (0x40078184) /**< (XDMAC) Channel Destination Microblock Stride 4 */
|
||||
#define REG_XDMAC_CIE5 (0x40078190) /**< (XDMAC) Channel Interrupt Enable Register 5 */
|
||||
#define REG_XDMAC_CID5 (0x40078194) /**< (XDMAC) Channel Interrupt Disable Register 5 */
|
||||
#define REG_XDMAC_CIM5 (0x40078198) /**< (XDMAC) Channel Interrupt Mask Register 5 */
|
||||
#define REG_XDMAC_CIS5 (0x4007819C) /**< (XDMAC) Channel Interrupt Status Register 5 */
|
||||
#define REG_XDMAC_CSA5 (0x400781A0) /**< (XDMAC) Channel Source Address Register 5 */
|
||||
#define REG_XDMAC_CDA5 (0x400781A4) /**< (XDMAC) Channel Destination Address Register 5 */
|
||||
#define REG_XDMAC_CNDA5 (0x400781A8) /**< (XDMAC) Channel Next Descriptor Address Register 5 */
|
||||
#define REG_XDMAC_CNDC5 (0x400781AC) /**< (XDMAC) Channel Next Descriptor Control Register 5 */
|
||||
#define REG_XDMAC_CUBC5 (0x400781B0) /**< (XDMAC) Channel Microblock Control Register 5 */
|
||||
#define REG_XDMAC_CBC5 (0x400781B4) /**< (XDMAC) Channel Block Control Register 5 */
|
||||
#define REG_XDMAC_CC5 (0x400781B8) /**< (XDMAC) Channel Configuration Register 5 */
|
||||
#define REG_XDMAC_CDS_MSP5 (0x400781BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */
|
||||
#define REG_XDMAC_CSUS5 (0x400781C0) /**< (XDMAC) Channel Source Microblock Stride 5 */
|
||||
#define REG_XDMAC_CDUS5 (0x400781C4) /**< (XDMAC) Channel Destination Microblock Stride 5 */
|
||||
#define REG_XDMAC_CIE6 (0x400781D0) /**< (XDMAC) Channel Interrupt Enable Register 6 */
|
||||
#define REG_XDMAC_CID6 (0x400781D4) /**< (XDMAC) Channel Interrupt Disable Register 6 */
|
||||
#define REG_XDMAC_CIM6 (0x400781D8) /**< (XDMAC) Channel Interrupt Mask Register 6 */
|
||||
#define REG_XDMAC_CIS6 (0x400781DC) /**< (XDMAC) Channel Interrupt Status Register 6 */
|
||||
#define REG_XDMAC_CSA6 (0x400781E0) /**< (XDMAC) Channel Source Address Register 6 */
|
||||
#define REG_XDMAC_CDA6 (0x400781E4) /**< (XDMAC) Channel Destination Address Register 6 */
|
||||
#define REG_XDMAC_CNDA6 (0x400781E8) /**< (XDMAC) Channel Next Descriptor Address Register 6 */
|
||||
#define REG_XDMAC_CNDC6 (0x400781EC) /**< (XDMAC) Channel Next Descriptor Control Register 6 */
|
||||
#define REG_XDMAC_CUBC6 (0x400781F0) /**< (XDMAC) Channel Microblock Control Register 6 */
|
||||
#define REG_XDMAC_CBC6 (0x400781F4) /**< (XDMAC) Channel Block Control Register 6 */
|
||||
#define REG_XDMAC_CC6 (0x400781F8) /**< (XDMAC) Channel Configuration Register 6 */
|
||||
#define REG_XDMAC_CDS_MSP6 (0x400781FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */
|
||||
#define REG_XDMAC_CSUS6 (0x40078200) /**< (XDMAC) Channel Source Microblock Stride 6 */
|
||||
#define REG_XDMAC_CDUS6 (0x40078204) /**< (XDMAC) Channel Destination Microblock Stride 6 */
|
||||
#define REG_XDMAC_CIE7 (0x40078210) /**< (XDMAC) Channel Interrupt Enable Register 7 */
|
||||
#define REG_XDMAC_CID7 (0x40078214) /**< (XDMAC) Channel Interrupt Disable Register 7 */
|
||||
#define REG_XDMAC_CIM7 (0x40078218) /**< (XDMAC) Channel Interrupt Mask Register 7 */
|
||||
#define REG_XDMAC_CIS7 (0x4007821C) /**< (XDMAC) Channel Interrupt Status Register 7 */
|
||||
#define REG_XDMAC_CSA7 (0x40078220) /**< (XDMAC) Channel Source Address Register 7 */
|
||||
#define REG_XDMAC_CDA7 (0x40078224) /**< (XDMAC) Channel Destination Address Register 7 */
|
||||
#define REG_XDMAC_CNDA7 (0x40078228) /**< (XDMAC) Channel Next Descriptor Address Register 7 */
|
||||
#define REG_XDMAC_CNDC7 (0x4007822C) /**< (XDMAC) Channel Next Descriptor Control Register 7 */
|
||||
#define REG_XDMAC_CUBC7 (0x40078230) /**< (XDMAC) Channel Microblock Control Register 7 */
|
||||
#define REG_XDMAC_CBC7 (0x40078234) /**< (XDMAC) Channel Block Control Register 7 */
|
||||
#define REG_XDMAC_CC7 (0x40078238) /**< (XDMAC) Channel Configuration Register 7 */
|
||||
#define REG_XDMAC_CDS_MSP7 (0x4007823C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */
|
||||
#define REG_XDMAC_CSUS7 (0x40078240) /**< (XDMAC) Channel Source Microblock Stride 7 */
|
||||
#define REG_XDMAC_CDUS7 (0x40078244) /**< (XDMAC) Channel Destination Microblock Stride 7 */
|
||||
#define REG_XDMAC_CIE8 (0x40078250) /**< (XDMAC) Channel Interrupt Enable Register 8 */
|
||||
#define REG_XDMAC_CID8 (0x40078254) /**< (XDMAC) Channel Interrupt Disable Register 8 */
|
||||
#define REG_XDMAC_CIM8 (0x40078258) /**< (XDMAC) Channel Interrupt Mask Register 8 */
|
||||
#define REG_XDMAC_CIS8 (0x4007825C) /**< (XDMAC) Channel Interrupt Status Register 8 */
|
||||
#define REG_XDMAC_CSA8 (0x40078260) /**< (XDMAC) Channel Source Address Register 8 */
|
||||
#define REG_XDMAC_CDA8 (0x40078264) /**< (XDMAC) Channel Destination Address Register 8 */
|
||||
#define REG_XDMAC_CNDA8 (0x40078268) /**< (XDMAC) Channel Next Descriptor Address Register 8 */
|
||||
#define REG_XDMAC_CNDC8 (0x4007826C) /**< (XDMAC) Channel Next Descriptor Control Register 8 */
|
||||
#define REG_XDMAC_CUBC8 (0x40078270) /**< (XDMAC) Channel Microblock Control Register 8 */
|
||||
#define REG_XDMAC_CBC8 (0x40078274) /**< (XDMAC) Channel Block Control Register 8 */
|
||||
#define REG_XDMAC_CC8 (0x40078278) /**< (XDMAC) Channel Configuration Register 8 */
|
||||
#define REG_XDMAC_CDS_MSP8 (0x4007827C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */
|
||||
#define REG_XDMAC_CSUS8 (0x40078280) /**< (XDMAC) Channel Source Microblock Stride 8 */
|
||||
#define REG_XDMAC_CDUS8 (0x40078284) /**< (XDMAC) Channel Destination Microblock Stride 8 */
|
||||
#define REG_XDMAC_CIE9 (0x40078290) /**< (XDMAC) Channel Interrupt Enable Register 9 */
|
||||
#define REG_XDMAC_CID9 (0x40078294) /**< (XDMAC) Channel Interrupt Disable Register 9 */
|
||||
#define REG_XDMAC_CIM9 (0x40078298) /**< (XDMAC) Channel Interrupt Mask Register 9 */
|
||||
#define REG_XDMAC_CIS9 (0x4007829C) /**< (XDMAC) Channel Interrupt Status Register 9 */
|
||||
#define REG_XDMAC_CSA9 (0x400782A0) /**< (XDMAC) Channel Source Address Register 9 */
|
||||
#define REG_XDMAC_CDA9 (0x400782A4) /**< (XDMAC) Channel Destination Address Register 9 */
|
||||
#define REG_XDMAC_CNDA9 (0x400782A8) /**< (XDMAC) Channel Next Descriptor Address Register 9 */
|
||||
#define REG_XDMAC_CNDC9 (0x400782AC) /**< (XDMAC) Channel Next Descriptor Control Register 9 */
|
||||
#define REG_XDMAC_CUBC9 (0x400782B0) /**< (XDMAC) Channel Microblock Control Register 9 */
|
||||
#define REG_XDMAC_CBC9 (0x400782B4) /**< (XDMAC) Channel Block Control Register 9 */
|
||||
#define REG_XDMAC_CC9 (0x400782B8) /**< (XDMAC) Channel Configuration Register 9 */
|
||||
#define REG_XDMAC_CDS_MSP9 (0x400782BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */
|
||||
#define REG_XDMAC_CSUS9 (0x400782C0) /**< (XDMAC) Channel Source Microblock Stride 9 */
|
||||
#define REG_XDMAC_CDUS9 (0x400782C4) /**< (XDMAC) Channel Destination Microblock Stride 9 */
|
||||
#define REG_XDMAC_CIE10 (0x400782D0) /**< (XDMAC) Channel Interrupt Enable Register 10 */
|
||||
#define REG_XDMAC_CID10 (0x400782D4) /**< (XDMAC) Channel Interrupt Disable Register 10 */
|
||||
#define REG_XDMAC_CIM10 (0x400782D8) /**< (XDMAC) Channel Interrupt Mask Register 10 */
|
||||
#define REG_XDMAC_CIS10 (0x400782DC) /**< (XDMAC) Channel Interrupt Status Register 10 */
|
||||
#define REG_XDMAC_CSA10 (0x400782E0) /**< (XDMAC) Channel Source Address Register 10 */
|
||||
#define REG_XDMAC_CDA10 (0x400782E4) /**< (XDMAC) Channel Destination Address Register 10 */
|
||||
#define REG_XDMAC_CNDA10 (0x400782E8) /**< (XDMAC) Channel Next Descriptor Address Register 10 */
|
||||
#define REG_XDMAC_CNDC10 (0x400782EC) /**< (XDMAC) Channel Next Descriptor Control Register 10 */
|
||||
#define REG_XDMAC_CUBC10 (0x400782F0) /**< (XDMAC) Channel Microblock Control Register 10 */
|
||||
#define REG_XDMAC_CBC10 (0x400782F4) /**< (XDMAC) Channel Block Control Register 10 */
|
||||
#define REG_XDMAC_CC10 (0x400782F8) /**< (XDMAC) Channel Configuration Register 10 */
|
||||
#define REG_XDMAC_CDS_MSP10 (0x400782FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */
|
||||
#define REG_XDMAC_CSUS10 (0x40078300) /**< (XDMAC) Channel Source Microblock Stride 10 */
|
||||
#define REG_XDMAC_CDUS10 (0x40078304) /**< (XDMAC) Channel Destination Microblock Stride 10 */
|
||||
#define REG_XDMAC_CIE11 (0x40078310) /**< (XDMAC) Channel Interrupt Enable Register 11 */
|
||||
#define REG_XDMAC_CID11 (0x40078314) /**< (XDMAC) Channel Interrupt Disable Register 11 */
|
||||
#define REG_XDMAC_CIM11 (0x40078318) /**< (XDMAC) Channel Interrupt Mask Register 11 */
|
||||
#define REG_XDMAC_CIS11 (0x4007831C) /**< (XDMAC) Channel Interrupt Status Register 11 */
|
||||
#define REG_XDMAC_CSA11 (0x40078320) /**< (XDMAC) Channel Source Address Register 11 */
|
||||
#define REG_XDMAC_CDA11 (0x40078324) /**< (XDMAC) Channel Destination Address Register 11 */
|
||||
#define REG_XDMAC_CNDA11 (0x40078328) /**< (XDMAC) Channel Next Descriptor Address Register 11 */
|
||||
#define REG_XDMAC_CNDC11 (0x4007832C) /**< (XDMAC) Channel Next Descriptor Control Register 11 */
|
||||
#define REG_XDMAC_CUBC11 (0x40078330) /**< (XDMAC) Channel Microblock Control Register 11 */
|
||||
#define REG_XDMAC_CBC11 (0x40078334) /**< (XDMAC) Channel Block Control Register 11 */
|
||||
#define REG_XDMAC_CC11 (0x40078338) /**< (XDMAC) Channel Configuration Register 11 */
|
||||
#define REG_XDMAC_CDS_MSP11 (0x4007833C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */
|
||||
#define REG_XDMAC_CSUS11 (0x40078340) /**< (XDMAC) Channel Source Microblock Stride 11 */
|
||||
#define REG_XDMAC_CDUS11 (0x40078344) /**< (XDMAC) Channel Destination Microblock Stride 11 */
|
||||
#define REG_XDMAC_CIE12 (0x40078350) /**< (XDMAC) Channel Interrupt Enable Register 12 */
|
||||
#define REG_XDMAC_CID12 (0x40078354) /**< (XDMAC) Channel Interrupt Disable Register 12 */
|
||||
#define REG_XDMAC_CIM12 (0x40078358) /**< (XDMAC) Channel Interrupt Mask Register 12 */
|
||||
#define REG_XDMAC_CIS12 (0x4007835C) /**< (XDMAC) Channel Interrupt Status Register 12 */
|
||||
#define REG_XDMAC_CSA12 (0x40078360) /**< (XDMAC) Channel Source Address Register 12 */
|
||||
#define REG_XDMAC_CDA12 (0x40078364) /**< (XDMAC) Channel Destination Address Register 12 */
|
||||
#define REG_XDMAC_CNDA12 (0x40078368) /**< (XDMAC) Channel Next Descriptor Address Register 12 */
|
||||
#define REG_XDMAC_CNDC12 (0x4007836C) /**< (XDMAC) Channel Next Descriptor Control Register 12 */
|
||||
#define REG_XDMAC_CUBC12 (0x40078370) /**< (XDMAC) Channel Microblock Control Register 12 */
|
||||
#define REG_XDMAC_CBC12 (0x40078374) /**< (XDMAC) Channel Block Control Register 12 */
|
||||
#define REG_XDMAC_CC12 (0x40078378) /**< (XDMAC) Channel Configuration Register 12 */
|
||||
#define REG_XDMAC_CDS_MSP12 (0x4007837C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */
|
||||
#define REG_XDMAC_CSUS12 (0x40078380) /**< (XDMAC) Channel Source Microblock Stride 12 */
|
||||
#define REG_XDMAC_CDUS12 (0x40078384) /**< (XDMAC) Channel Destination Microblock Stride 12 */
|
||||
#define REG_XDMAC_CIE13 (0x40078390) /**< (XDMAC) Channel Interrupt Enable Register 13 */
|
||||
#define REG_XDMAC_CID13 (0x40078394) /**< (XDMAC) Channel Interrupt Disable Register 13 */
|
||||
#define REG_XDMAC_CIM13 (0x40078398) /**< (XDMAC) Channel Interrupt Mask Register 13 */
|
||||
#define REG_XDMAC_CIS13 (0x4007839C) /**< (XDMAC) Channel Interrupt Status Register 13 */
|
||||
#define REG_XDMAC_CSA13 (0x400783A0) /**< (XDMAC) Channel Source Address Register 13 */
|
||||
#define REG_XDMAC_CDA13 (0x400783A4) /**< (XDMAC) Channel Destination Address Register 13 */
|
||||
#define REG_XDMAC_CNDA13 (0x400783A8) /**< (XDMAC) Channel Next Descriptor Address Register 13 */
|
||||
#define REG_XDMAC_CNDC13 (0x400783AC) /**< (XDMAC) Channel Next Descriptor Control Register 13 */
|
||||
#define REG_XDMAC_CUBC13 (0x400783B0) /**< (XDMAC) Channel Microblock Control Register 13 */
|
||||
#define REG_XDMAC_CBC13 (0x400783B4) /**< (XDMAC) Channel Block Control Register 13 */
|
||||
#define REG_XDMAC_CC13 (0x400783B8) /**< (XDMAC) Channel Configuration Register 13 */
|
||||
#define REG_XDMAC_CDS_MSP13 (0x400783BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */
|
||||
#define REG_XDMAC_CSUS13 (0x400783C0) /**< (XDMAC) Channel Source Microblock Stride 13 */
|
||||
#define REG_XDMAC_CDUS13 (0x400783C4) /**< (XDMAC) Channel Destination Microblock Stride 13 */
|
||||
#define REG_XDMAC_CIE14 (0x400783D0) /**< (XDMAC) Channel Interrupt Enable Register 14 */
|
||||
#define REG_XDMAC_CID14 (0x400783D4) /**< (XDMAC) Channel Interrupt Disable Register 14 */
|
||||
#define REG_XDMAC_CIM14 (0x400783D8) /**< (XDMAC) Channel Interrupt Mask Register 14 */
|
||||
#define REG_XDMAC_CIS14 (0x400783DC) /**< (XDMAC) Channel Interrupt Status Register 14 */
|
||||
#define REG_XDMAC_CSA14 (0x400783E0) /**< (XDMAC) Channel Source Address Register 14 */
|
||||
#define REG_XDMAC_CDA14 (0x400783E4) /**< (XDMAC) Channel Destination Address Register 14 */
|
||||
#define REG_XDMAC_CNDA14 (0x400783E8) /**< (XDMAC) Channel Next Descriptor Address Register 14 */
|
||||
#define REG_XDMAC_CNDC14 (0x400783EC) /**< (XDMAC) Channel Next Descriptor Control Register 14 */
|
||||
#define REG_XDMAC_CUBC14 (0x400783F0) /**< (XDMAC) Channel Microblock Control Register 14 */
|
||||
#define REG_XDMAC_CBC14 (0x400783F4) /**< (XDMAC) Channel Block Control Register 14 */
|
||||
#define REG_XDMAC_CC14 (0x400783F8) /**< (XDMAC) Channel Configuration Register 14 */
|
||||
#define REG_XDMAC_CDS_MSP14 (0x400783FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */
|
||||
#define REG_XDMAC_CSUS14 (0x40078400) /**< (XDMAC) Channel Source Microblock Stride 14 */
|
||||
#define REG_XDMAC_CDUS14 (0x40078404) /**< (XDMAC) Channel Destination Microblock Stride 14 */
|
||||
#define REG_XDMAC_CIE15 (0x40078410) /**< (XDMAC) Channel Interrupt Enable Register 15 */
|
||||
#define REG_XDMAC_CID15 (0x40078414) /**< (XDMAC) Channel Interrupt Disable Register 15 */
|
||||
#define REG_XDMAC_CIM15 (0x40078418) /**< (XDMAC) Channel Interrupt Mask Register 15 */
|
||||
#define REG_XDMAC_CIS15 (0x4007841C) /**< (XDMAC) Channel Interrupt Status Register 15 */
|
||||
#define REG_XDMAC_CSA15 (0x40078420) /**< (XDMAC) Channel Source Address Register 15 */
|
||||
#define REG_XDMAC_CDA15 (0x40078424) /**< (XDMAC) Channel Destination Address Register 15 */
|
||||
#define REG_XDMAC_CNDA15 (0x40078428) /**< (XDMAC) Channel Next Descriptor Address Register 15 */
|
||||
#define REG_XDMAC_CNDC15 (0x4007842C) /**< (XDMAC) Channel Next Descriptor Control Register 15 */
|
||||
#define REG_XDMAC_CUBC15 (0x40078430) /**< (XDMAC) Channel Microblock Control Register 15 */
|
||||
#define REG_XDMAC_CBC15 (0x40078434) /**< (XDMAC) Channel Block Control Register 15 */
|
||||
#define REG_XDMAC_CC15 (0x40078438) /**< (XDMAC) Channel Configuration Register 15 */
|
||||
#define REG_XDMAC_CDS_MSP15 (0x4007843C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */
|
||||
#define REG_XDMAC_CSUS15 (0x40078440) /**< (XDMAC) Channel Source Microblock Stride 15 */
|
||||
#define REG_XDMAC_CDUS15 (0x40078444) /**< (XDMAC) Channel Destination Microblock Stride 15 */
|
||||
#define REG_XDMAC_CIE16 (0x40078450) /**< (XDMAC) Channel Interrupt Enable Register 16 */
|
||||
#define REG_XDMAC_CID16 (0x40078454) /**< (XDMAC) Channel Interrupt Disable Register 16 */
|
||||
#define REG_XDMAC_CIM16 (0x40078458) /**< (XDMAC) Channel Interrupt Mask Register 16 */
|
||||
#define REG_XDMAC_CIS16 (0x4007845C) /**< (XDMAC) Channel Interrupt Status Register 16 */
|
||||
#define REG_XDMAC_CSA16 (0x40078460) /**< (XDMAC) Channel Source Address Register 16 */
|
||||
#define REG_XDMAC_CDA16 (0x40078464) /**< (XDMAC) Channel Destination Address Register 16 */
|
||||
#define REG_XDMAC_CNDA16 (0x40078468) /**< (XDMAC) Channel Next Descriptor Address Register 16 */
|
||||
#define REG_XDMAC_CNDC16 (0x4007846C) /**< (XDMAC) Channel Next Descriptor Control Register 16 */
|
||||
#define REG_XDMAC_CUBC16 (0x40078470) /**< (XDMAC) Channel Microblock Control Register 16 */
|
||||
#define REG_XDMAC_CBC16 (0x40078474) /**< (XDMAC) Channel Block Control Register 16 */
|
||||
#define REG_XDMAC_CC16 (0x40078478) /**< (XDMAC) Channel Configuration Register 16 */
|
||||
#define REG_XDMAC_CDS_MSP16 (0x4007847C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */
|
||||
#define REG_XDMAC_CSUS16 (0x40078480) /**< (XDMAC) Channel Source Microblock Stride 16 */
|
||||
#define REG_XDMAC_CDUS16 (0x40078484) /**< (XDMAC) Channel Destination Microblock Stride 16 */
|
||||
#define REG_XDMAC_CIE17 (0x40078490) /**< (XDMAC) Channel Interrupt Enable Register 17 */
|
||||
#define REG_XDMAC_CID17 (0x40078494) /**< (XDMAC) Channel Interrupt Disable Register 17 */
|
||||
#define REG_XDMAC_CIM17 (0x40078498) /**< (XDMAC) Channel Interrupt Mask Register 17 */
|
||||
#define REG_XDMAC_CIS17 (0x4007849C) /**< (XDMAC) Channel Interrupt Status Register 17 */
|
||||
#define REG_XDMAC_CSA17 (0x400784A0) /**< (XDMAC) Channel Source Address Register 17 */
|
||||
#define REG_XDMAC_CDA17 (0x400784A4) /**< (XDMAC) Channel Destination Address Register 17 */
|
||||
#define REG_XDMAC_CNDA17 (0x400784A8) /**< (XDMAC) Channel Next Descriptor Address Register 17 */
|
||||
#define REG_XDMAC_CNDC17 (0x400784AC) /**< (XDMAC) Channel Next Descriptor Control Register 17 */
|
||||
#define REG_XDMAC_CUBC17 (0x400784B0) /**< (XDMAC) Channel Microblock Control Register 17 */
|
||||
#define REG_XDMAC_CBC17 (0x400784B4) /**< (XDMAC) Channel Block Control Register 17 */
|
||||
#define REG_XDMAC_CC17 (0x400784B8) /**< (XDMAC) Channel Configuration Register 17 */
|
||||
#define REG_XDMAC_CDS_MSP17 (0x400784BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */
|
||||
#define REG_XDMAC_CSUS17 (0x400784C0) /**< (XDMAC) Channel Source Microblock Stride 17 */
|
||||
#define REG_XDMAC_CDUS17 (0x400784C4) /**< (XDMAC) Channel Destination Microblock Stride 17 */
|
||||
#define REG_XDMAC_CIE18 (0x400784D0) /**< (XDMAC) Channel Interrupt Enable Register 18 */
|
||||
#define REG_XDMAC_CID18 (0x400784D4) /**< (XDMAC) Channel Interrupt Disable Register 18 */
|
||||
#define REG_XDMAC_CIM18 (0x400784D8) /**< (XDMAC) Channel Interrupt Mask Register 18 */
|
||||
#define REG_XDMAC_CIS18 (0x400784DC) /**< (XDMAC) Channel Interrupt Status Register 18 */
|
||||
#define REG_XDMAC_CSA18 (0x400784E0) /**< (XDMAC) Channel Source Address Register 18 */
|
||||
#define REG_XDMAC_CDA18 (0x400784E4) /**< (XDMAC) Channel Destination Address Register 18 */
|
||||
#define REG_XDMAC_CNDA18 (0x400784E8) /**< (XDMAC) Channel Next Descriptor Address Register 18 */
|
||||
#define REG_XDMAC_CNDC18 (0x400784EC) /**< (XDMAC) Channel Next Descriptor Control Register 18 */
|
||||
#define REG_XDMAC_CUBC18 (0x400784F0) /**< (XDMAC) Channel Microblock Control Register 18 */
|
||||
#define REG_XDMAC_CBC18 (0x400784F4) /**< (XDMAC) Channel Block Control Register 18 */
|
||||
#define REG_XDMAC_CC18 (0x400784F8) /**< (XDMAC) Channel Configuration Register 18 */
|
||||
#define REG_XDMAC_CDS_MSP18 (0x400784FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */
|
||||
#define REG_XDMAC_CSUS18 (0x40078500) /**< (XDMAC) Channel Source Microblock Stride 18 */
|
||||
#define REG_XDMAC_CDUS18 (0x40078504) /**< (XDMAC) Channel Destination Microblock Stride 18 */
|
||||
#define REG_XDMAC_CIE19 (0x40078510) /**< (XDMAC) Channel Interrupt Enable Register 19 */
|
||||
#define REG_XDMAC_CID19 (0x40078514) /**< (XDMAC) Channel Interrupt Disable Register 19 */
|
||||
#define REG_XDMAC_CIM19 (0x40078518) /**< (XDMAC) Channel Interrupt Mask Register 19 */
|
||||
#define REG_XDMAC_CIS19 (0x4007851C) /**< (XDMAC) Channel Interrupt Status Register 19 */
|
||||
#define REG_XDMAC_CSA19 (0x40078520) /**< (XDMAC) Channel Source Address Register 19 */
|
||||
#define REG_XDMAC_CDA19 (0x40078524) /**< (XDMAC) Channel Destination Address Register 19 */
|
||||
#define REG_XDMAC_CNDA19 (0x40078528) /**< (XDMAC) Channel Next Descriptor Address Register 19 */
|
||||
#define REG_XDMAC_CNDC19 (0x4007852C) /**< (XDMAC) Channel Next Descriptor Control Register 19 */
|
||||
#define REG_XDMAC_CUBC19 (0x40078530) /**< (XDMAC) Channel Microblock Control Register 19 */
|
||||
#define REG_XDMAC_CBC19 (0x40078534) /**< (XDMAC) Channel Block Control Register 19 */
|
||||
#define REG_XDMAC_CC19 (0x40078538) /**< (XDMAC) Channel Configuration Register 19 */
|
||||
#define REG_XDMAC_CDS_MSP19 (0x4007853C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */
|
||||
#define REG_XDMAC_CSUS19 (0x40078540) /**< (XDMAC) Channel Source Microblock Stride 19 */
|
||||
#define REG_XDMAC_CDUS19 (0x40078544) /**< (XDMAC) Channel Destination Microblock Stride 19 */
|
||||
#define REG_XDMAC_CIE20 (0x40078550) /**< (XDMAC) Channel Interrupt Enable Register 20 */
|
||||
#define REG_XDMAC_CID20 (0x40078554) /**< (XDMAC) Channel Interrupt Disable Register 20 */
|
||||
#define REG_XDMAC_CIM20 (0x40078558) /**< (XDMAC) Channel Interrupt Mask Register 20 */
|
||||
#define REG_XDMAC_CIS20 (0x4007855C) /**< (XDMAC) Channel Interrupt Status Register 20 */
|
||||
#define REG_XDMAC_CSA20 (0x40078560) /**< (XDMAC) Channel Source Address Register 20 */
|
||||
#define REG_XDMAC_CDA20 (0x40078564) /**< (XDMAC) Channel Destination Address Register 20 */
|
||||
#define REG_XDMAC_CNDA20 (0x40078568) /**< (XDMAC) Channel Next Descriptor Address Register 20 */
|
||||
#define REG_XDMAC_CNDC20 (0x4007856C) /**< (XDMAC) Channel Next Descriptor Control Register 20 */
|
||||
#define REG_XDMAC_CUBC20 (0x40078570) /**< (XDMAC) Channel Microblock Control Register 20 */
|
||||
#define REG_XDMAC_CBC20 (0x40078574) /**< (XDMAC) Channel Block Control Register 20 */
|
||||
#define REG_XDMAC_CC20 (0x40078578) /**< (XDMAC) Channel Configuration Register 20 */
|
||||
#define REG_XDMAC_CDS_MSP20 (0x4007857C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */
|
||||
#define REG_XDMAC_CSUS20 (0x40078580) /**< (XDMAC) Channel Source Microblock Stride 20 */
|
||||
#define REG_XDMAC_CDUS20 (0x40078584) /**< (XDMAC) Channel Destination Microblock Stride 20 */
|
||||
#define REG_XDMAC_CIE21 (0x40078590) /**< (XDMAC) Channel Interrupt Enable Register 21 */
|
||||
#define REG_XDMAC_CID21 (0x40078594) /**< (XDMAC) Channel Interrupt Disable Register 21 */
|
||||
#define REG_XDMAC_CIM21 (0x40078598) /**< (XDMAC) Channel Interrupt Mask Register 21 */
|
||||
#define REG_XDMAC_CIS21 (0x4007859C) /**< (XDMAC) Channel Interrupt Status Register 21 */
|
||||
#define REG_XDMAC_CSA21 (0x400785A0) /**< (XDMAC) Channel Source Address Register 21 */
|
||||
#define REG_XDMAC_CDA21 (0x400785A4) /**< (XDMAC) Channel Destination Address Register 21 */
|
||||
#define REG_XDMAC_CNDA21 (0x400785A8) /**< (XDMAC) Channel Next Descriptor Address Register 21 */
|
||||
#define REG_XDMAC_CNDC21 (0x400785AC) /**< (XDMAC) Channel Next Descriptor Control Register 21 */
|
||||
#define REG_XDMAC_CUBC21 (0x400785B0) /**< (XDMAC) Channel Microblock Control Register 21 */
|
||||
#define REG_XDMAC_CBC21 (0x400785B4) /**< (XDMAC) Channel Block Control Register 21 */
|
||||
#define REG_XDMAC_CC21 (0x400785B8) /**< (XDMAC) Channel Configuration Register 21 */
|
||||
#define REG_XDMAC_CDS_MSP21 (0x400785BC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */
|
||||
#define REG_XDMAC_CSUS21 (0x400785C0) /**< (XDMAC) Channel Source Microblock Stride 21 */
|
||||
#define REG_XDMAC_CDUS21 (0x400785C4) /**< (XDMAC) Channel Destination Microblock Stride 21 */
|
||||
#define REG_XDMAC_CIE22 (0x400785D0) /**< (XDMAC) Channel Interrupt Enable Register 22 */
|
||||
#define REG_XDMAC_CID22 (0x400785D4) /**< (XDMAC) Channel Interrupt Disable Register 22 */
|
||||
#define REG_XDMAC_CIM22 (0x400785D8) /**< (XDMAC) Channel Interrupt Mask Register 22 */
|
||||
#define REG_XDMAC_CIS22 (0x400785DC) /**< (XDMAC) Channel Interrupt Status Register 22 */
|
||||
#define REG_XDMAC_CSA22 (0x400785E0) /**< (XDMAC) Channel Source Address Register 22 */
|
||||
#define REG_XDMAC_CDA22 (0x400785E4) /**< (XDMAC) Channel Destination Address Register 22 */
|
||||
#define REG_XDMAC_CNDA22 (0x400785E8) /**< (XDMAC) Channel Next Descriptor Address Register 22 */
|
||||
#define REG_XDMAC_CNDC22 (0x400785EC) /**< (XDMAC) Channel Next Descriptor Control Register 22 */
|
||||
#define REG_XDMAC_CUBC22 (0x400785F0) /**< (XDMAC) Channel Microblock Control Register 22 */
|
||||
#define REG_XDMAC_CBC22 (0x400785F4) /**< (XDMAC) Channel Block Control Register 22 */
|
||||
#define REG_XDMAC_CC22 (0x400785F8) /**< (XDMAC) Channel Configuration Register 22 */
|
||||
#define REG_XDMAC_CDS_MSP22 (0x400785FC) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */
|
||||
#define REG_XDMAC_CSUS22 (0x40078600) /**< (XDMAC) Channel Source Microblock Stride 22 */
|
||||
#define REG_XDMAC_CDUS22 (0x40078604) /**< (XDMAC) Channel Destination Microblock Stride 22 */
|
||||
#define REG_XDMAC_CIE23 (0x40078610) /**< (XDMAC) Channel Interrupt Enable Register 23 */
|
||||
#define REG_XDMAC_CID23 (0x40078614) /**< (XDMAC) Channel Interrupt Disable Register 23 */
|
||||
#define REG_XDMAC_CIM23 (0x40078618) /**< (XDMAC) Channel Interrupt Mask Register 23 */
|
||||
#define REG_XDMAC_CIS23 (0x4007861C) /**< (XDMAC) Channel Interrupt Status Register 23 */
|
||||
#define REG_XDMAC_CSA23 (0x40078620) /**< (XDMAC) Channel Source Address Register 23 */
|
||||
#define REG_XDMAC_CDA23 (0x40078624) /**< (XDMAC) Channel Destination Address Register 23 */
|
||||
#define REG_XDMAC_CNDA23 (0x40078628) /**< (XDMAC) Channel Next Descriptor Address Register 23 */
|
||||
#define REG_XDMAC_CNDC23 (0x4007862C) /**< (XDMAC) Channel Next Descriptor Control Register 23 */
|
||||
#define REG_XDMAC_CUBC23 (0x40078630) /**< (XDMAC) Channel Microblock Control Register 23 */
|
||||
#define REG_XDMAC_CBC23 (0x40078634) /**< (XDMAC) Channel Block Control Register 23 */
|
||||
#define REG_XDMAC_CC23 (0x40078638) /**< (XDMAC) Channel Configuration Register 23 */
|
||||
#define REG_XDMAC_CDS_MSP23 (0x4007863C) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */
|
||||
#define REG_XDMAC_CSUS23 (0x40078640) /**< (XDMAC) Channel Source Microblock Stride 23 */
|
||||
#define REG_XDMAC_CDUS23 (0x40078644) /**< (XDMAC) Channel Destination Microblock Stride 23 */
|
||||
#define REG_XDMAC_GTYPE (0x40078000) /**< (XDMAC) Global Type Register */
|
||||
#define REG_XDMAC_GCFG (0x40078004) /**< (XDMAC) Global Configuration Register */
|
||||
#define REG_XDMAC_GWAC (0x40078008) /**< (XDMAC) Global Weighted Arbiter Configuration Register */
|
||||
#define REG_XDMAC_GIE (0x4007800C) /**< (XDMAC) Global Interrupt Enable Register */
|
||||
#define REG_XDMAC_GID (0x40078010) /**< (XDMAC) Global Interrupt Disable Register */
|
||||
#define REG_XDMAC_GIM (0x40078014) /**< (XDMAC) Global Interrupt Mask Register */
|
||||
#define REG_XDMAC_GIS (0x40078018) /**< (XDMAC) Global Interrupt Status Register */
|
||||
#define REG_XDMAC_GE (0x4007801C) /**< (XDMAC) Global Channel Enable Register */
|
||||
#define REG_XDMAC_GD (0x40078020) /**< (XDMAC) Global Channel Disable Register */
|
||||
#define REG_XDMAC_GS (0x40078024) /**< (XDMAC) Global Channel Status Register */
|
||||
#define REG_XDMAC_GRS (0x40078028) /**< (XDMAC) Global Channel Read Suspend Register */
|
||||
#define REG_XDMAC_GWS (0x4007802C) /**< (XDMAC) Global Channel Write Suspend Register */
|
||||
#define REG_XDMAC_GRWS (0x40078030) /**< (XDMAC) Global Channel Read Write Suspend Register */
|
||||
#define REG_XDMAC_GRWR (0x40078034) /**< (XDMAC) Global Channel Read Write Resume Register */
|
||||
#define REG_XDMAC_GSWR (0x40078038) /**< (XDMAC) Global Channel Software Request Register */
|
||||
#define REG_XDMAC_GSWS (0x4007803C) /**< (XDMAC) Global Channel Software Request Status Register */
|
||||
#define REG_XDMAC_GSWF (0x40078040) /**< (XDMAC) Global Channel Software Flush Request Register */
|
||||
|
||||
#else
|
||||
|
||||
#define REG_XDMAC_CIE0 (*(__O uint32_t*)0x40078050U) /**< (XDMAC) Channel Interrupt Enable Register 0 */
|
||||
#define REG_XDMAC_CID0 (*(__O uint32_t*)0x40078054U) /**< (XDMAC) Channel Interrupt Disable Register 0 */
|
||||
#define REG_XDMAC_CIM0 (*(__I uint32_t*)0x40078058U) /**< (XDMAC) Channel Interrupt Mask Register 0 */
|
||||
#define REG_XDMAC_CIS0 (*(__I uint32_t*)0x4007805CU) /**< (XDMAC) Channel Interrupt Status Register 0 */
|
||||
#define REG_XDMAC_CSA0 (*(__IO uint32_t*)0x40078060U) /**< (XDMAC) Channel Source Address Register 0 */
|
||||
#define REG_XDMAC_CDA0 (*(__IO uint32_t*)0x40078064U) /**< (XDMAC) Channel Destination Address Register 0 */
|
||||
#define REG_XDMAC_CNDA0 (*(__IO uint32_t*)0x40078068U) /**< (XDMAC) Channel Next Descriptor Address Register 0 */
|
||||
#define REG_XDMAC_CNDC0 (*(__IO uint32_t*)0x4007806CU) /**< (XDMAC) Channel Next Descriptor Control Register 0 */
|
||||
#define REG_XDMAC_CUBC0 (*(__IO uint32_t*)0x40078070U) /**< (XDMAC) Channel Microblock Control Register 0 */
|
||||
#define REG_XDMAC_CBC0 (*(__IO uint32_t*)0x40078074U) /**< (XDMAC) Channel Block Control Register 0 */
|
||||
#define REG_XDMAC_CC0 (*(__IO uint32_t*)0x40078078U) /**< (XDMAC) Channel Configuration Register 0 */
|
||||
#define REG_XDMAC_CDS_MSP0 (*(__IO uint32_t*)0x4007807CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 0 */
|
||||
#define REG_XDMAC_CSUS0 (*(__IO uint32_t*)0x40078080U) /**< (XDMAC) Channel Source Microblock Stride 0 */
|
||||
#define REG_XDMAC_CDUS0 (*(__IO uint32_t*)0x40078084U) /**< (XDMAC) Channel Destination Microblock Stride 0 */
|
||||
#define REG_XDMAC_CIE1 (*(__O uint32_t*)0x40078090U) /**< (XDMAC) Channel Interrupt Enable Register 1 */
|
||||
#define REG_XDMAC_CID1 (*(__O uint32_t*)0x40078094U) /**< (XDMAC) Channel Interrupt Disable Register 1 */
|
||||
#define REG_XDMAC_CIM1 (*(__I uint32_t*)0x40078098U) /**< (XDMAC) Channel Interrupt Mask Register 1 */
|
||||
#define REG_XDMAC_CIS1 (*(__I uint32_t*)0x4007809CU) /**< (XDMAC) Channel Interrupt Status Register 1 */
|
||||
#define REG_XDMAC_CSA1 (*(__IO uint32_t*)0x400780A0U) /**< (XDMAC) Channel Source Address Register 1 */
|
||||
#define REG_XDMAC_CDA1 (*(__IO uint32_t*)0x400780A4U) /**< (XDMAC) Channel Destination Address Register 1 */
|
||||
#define REG_XDMAC_CNDA1 (*(__IO uint32_t*)0x400780A8U) /**< (XDMAC) Channel Next Descriptor Address Register 1 */
|
||||
#define REG_XDMAC_CNDC1 (*(__IO uint32_t*)0x400780ACU) /**< (XDMAC) Channel Next Descriptor Control Register 1 */
|
||||
#define REG_XDMAC_CUBC1 (*(__IO uint32_t*)0x400780B0U) /**< (XDMAC) Channel Microblock Control Register 1 */
|
||||
#define REG_XDMAC_CBC1 (*(__IO uint32_t*)0x400780B4U) /**< (XDMAC) Channel Block Control Register 1 */
|
||||
#define REG_XDMAC_CC1 (*(__IO uint32_t*)0x400780B8U) /**< (XDMAC) Channel Configuration Register 1 */
|
||||
#define REG_XDMAC_CDS_MSP1 (*(__IO uint32_t*)0x400780BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 1 */
|
||||
#define REG_XDMAC_CSUS1 (*(__IO uint32_t*)0x400780C0U) /**< (XDMAC) Channel Source Microblock Stride 1 */
|
||||
#define REG_XDMAC_CDUS1 (*(__IO uint32_t*)0x400780C4U) /**< (XDMAC) Channel Destination Microblock Stride 1 */
|
||||
#define REG_XDMAC_CIE2 (*(__O uint32_t*)0x400780D0U) /**< (XDMAC) Channel Interrupt Enable Register 2 */
|
||||
#define REG_XDMAC_CID2 (*(__O uint32_t*)0x400780D4U) /**< (XDMAC) Channel Interrupt Disable Register 2 */
|
||||
#define REG_XDMAC_CIM2 (*(__I uint32_t*)0x400780D8U) /**< (XDMAC) Channel Interrupt Mask Register 2 */
|
||||
#define REG_XDMAC_CIS2 (*(__I uint32_t*)0x400780DCU) /**< (XDMAC) Channel Interrupt Status Register 2 */
|
||||
#define REG_XDMAC_CSA2 (*(__IO uint32_t*)0x400780E0U) /**< (XDMAC) Channel Source Address Register 2 */
|
||||
#define REG_XDMAC_CDA2 (*(__IO uint32_t*)0x400780E4U) /**< (XDMAC) Channel Destination Address Register 2 */
|
||||
#define REG_XDMAC_CNDA2 (*(__IO uint32_t*)0x400780E8U) /**< (XDMAC) Channel Next Descriptor Address Register 2 */
|
||||
#define REG_XDMAC_CNDC2 (*(__IO uint32_t*)0x400780ECU) /**< (XDMAC) Channel Next Descriptor Control Register 2 */
|
||||
#define REG_XDMAC_CUBC2 (*(__IO uint32_t*)0x400780F0U) /**< (XDMAC) Channel Microblock Control Register 2 */
|
||||
#define REG_XDMAC_CBC2 (*(__IO uint32_t*)0x400780F4U) /**< (XDMAC) Channel Block Control Register 2 */
|
||||
#define REG_XDMAC_CC2 (*(__IO uint32_t*)0x400780F8U) /**< (XDMAC) Channel Configuration Register 2 */
|
||||
#define REG_XDMAC_CDS_MSP2 (*(__IO uint32_t*)0x400780FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 2 */
|
||||
#define REG_XDMAC_CSUS2 (*(__IO uint32_t*)0x40078100U) /**< (XDMAC) Channel Source Microblock Stride 2 */
|
||||
#define REG_XDMAC_CDUS2 (*(__IO uint32_t*)0x40078104U) /**< (XDMAC) Channel Destination Microblock Stride 2 */
|
||||
#define REG_XDMAC_CIE3 (*(__O uint32_t*)0x40078110U) /**< (XDMAC) Channel Interrupt Enable Register 3 */
|
||||
#define REG_XDMAC_CID3 (*(__O uint32_t*)0x40078114U) /**< (XDMAC) Channel Interrupt Disable Register 3 */
|
||||
#define REG_XDMAC_CIM3 (*(__I uint32_t*)0x40078118U) /**< (XDMAC) Channel Interrupt Mask Register 3 */
|
||||
#define REG_XDMAC_CIS3 (*(__I uint32_t*)0x4007811CU) /**< (XDMAC) Channel Interrupt Status Register 3 */
|
||||
#define REG_XDMAC_CSA3 (*(__IO uint32_t*)0x40078120U) /**< (XDMAC) Channel Source Address Register 3 */
|
||||
#define REG_XDMAC_CDA3 (*(__IO uint32_t*)0x40078124U) /**< (XDMAC) Channel Destination Address Register 3 */
|
||||
#define REG_XDMAC_CNDA3 (*(__IO uint32_t*)0x40078128U) /**< (XDMAC) Channel Next Descriptor Address Register 3 */
|
||||
#define REG_XDMAC_CNDC3 (*(__IO uint32_t*)0x4007812CU) /**< (XDMAC) Channel Next Descriptor Control Register 3 */
|
||||
#define REG_XDMAC_CUBC3 (*(__IO uint32_t*)0x40078130U) /**< (XDMAC) Channel Microblock Control Register 3 */
|
||||
#define REG_XDMAC_CBC3 (*(__IO uint32_t*)0x40078134U) /**< (XDMAC) Channel Block Control Register 3 */
|
||||
#define REG_XDMAC_CC3 (*(__IO uint32_t*)0x40078138U) /**< (XDMAC) Channel Configuration Register 3 */
|
||||
#define REG_XDMAC_CDS_MSP3 (*(__IO uint32_t*)0x4007813CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 3 */
|
||||
#define REG_XDMAC_CSUS3 (*(__IO uint32_t*)0x40078140U) /**< (XDMAC) Channel Source Microblock Stride 3 */
|
||||
#define REG_XDMAC_CDUS3 (*(__IO uint32_t*)0x40078144U) /**< (XDMAC) Channel Destination Microblock Stride 3 */
|
||||
#define REG_XDMAC_CIE4 (*(__O uint32_t*)0x40078150U) /**< (XDMAC) Channel Interrupt Enable Register 4 */
|
||||
#define REG_XDMAC_CID4 (*(__O uint32_t*)0x40078154U) /**< (XDMAC) Channel Interrupt Disable Register 4 */
|
||||
#define REG_XDMAC_CIM4 (*(__I uint32_t*)0x40078158U) /**< (XDMAC) Channel Interrupt Mask Register 4 */
|
||||
#define REG_XDMAC_CIS4 (*(__I uint32_t*)0x4007815CU) /**< (XDMAC) Channel Interrupt Status Register 4 */
|
||||
#define REG_XDMAC_CSA4 (*(__IO uint32_t*)0x40078160U) /**< (XDMAC) Channel Source Address Register 4 */
|
||||
#define REG_XDMAC_CDA4 (*(__IO uint32_t*)0x40078164U) /**< (XDMAC) Channel Destination Address Register 4 */
|
||||
#define REG_XDMAC_CNDA4 (*(__IO uint32_t*)0x40078168U) /**< (XDMAC) Channel Next Descriptor Address Register 4 */
|
||||
#define REG_XDMAC_CNDC4 (*(__IO uint32_t*)0x4007816CU) /**< (XDMAC) Channel Next Descriptor Control Register 4 */
|
||||
#define REG_XDMAC_CUBC4 (*(__IO uint32_t*)0x40078170U) /**< (XDMAC) Channel Microblock Control Register 4 */
|
||||
#define REG_XDMAC_CBC4 (*(__IO uint32_t*)0x40078174U) /**< (XDMAC) Channel Block Control Register 4 */
|
||||
#define REG_XDMAC_CC4 (*(__IO uint32_t*)0x40078178U) /**< (XDMAC) Channel Configuration Register 4 */
|
||||
#define REG_XDMAC_CDS_MSP4 (*(__IO uint32_t*)0x4007817CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 4 */
|
||||
#define REG_XDMAC_CSUS4 (*(__IO uint32_t*)0x40078180U) /**< (XDMAC) Channel Source Microblock Stride 4 */
|
||||
#define REG_XDMAC_CDUS4 (*(__IO uint32_t*)0x40078184U) /**< (XDMAC) Channel Destination Microblock Stride 4 */
|
||||
#define REG_XDMAC_CIE5 (*(__O uint32_t*)0x40078190U) /**< (XDMAC) Channel Interrupt Enable Register 5 */
|
||||
#define REG_XDMAC_CID5 (*(__O uint32_t*)0x40078194U) /**< (XDMAC) Channel Interrupt Disable Register 5 */
|
||||
#define REG_XDMAC_CIM5 (*(__I uint32_t*)0x40078198U) /**< (XDMAC) Channel Interrupt Mask Register 5 */
|
||||
#define REG_XDMAC_CIS5 (*(__I uint32_t*)0x4007819CU) /**< (XDMAC) Channel Interrupt Status Register 5 */
|
||||
#define REG_XDMAC_CSA5 (*(__IO uint32_t*)0x400781A0U) /**< (XDMAC) Channel Source Address Register 5 */
|
||||
#define REG_XDMAC_CDA5 (*(__IO uint32_t*)0x400781A4U) /**< (XDMAC) Channel Destination Address Register 5 */
|
||||
#define REG_XDMAC_CNDA5 (*(__IO uint32_t*)0x400781A8U) /**< (XDMAC) Channel Next Descriptor Address Register 5 */
|
||||
#define REG_XDMAC_CNDC5 (*(__IO uint32_t*)0x400781ACU) /**< (XDMAC) Channel Next Descriptor Control Register 5 */
|
||||
#define REG_XDMAC_CUBC5 (*(__IO uint32_t*)0x400781B0U) /**< (XDMAC) Channel Microblock Control Register 5 */
|
||||
#define REG_XDMAC_CBC5 (*(__IO uint32_t*)0x400781B4U) /**< (XDMAC) Channel Block Control Register 5 */
|
||||
#define REG_XDMAC_CC5 (*(__IO uint32_t*)0x400781B8U) /**< (XDMAC) Channel Configuration Register 5 */
|
||||
#define REG_XDMAC_CDS_MSP5 (*(__IO uint32_t*)0x400781BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 5 */
|
||||
#define REG_XDMAC_CSUS5 (*(__IO uint32_t*)0x400781C0U) /**< (XDMAC) Channel Source Microblock Stride 5 */
|
||||
#define REG_XDMAC_CDUS5 (*(__IO uint32_t*)0x400781C4U) /**< (XDMAC) Channel Destination Microblock Stride 5 */
|
||||
#define REG_XDMAC_CIE6 (*(__O uint32_t*)0x400781D0U) /**< (XDMAC) Channel Interrupt Enable Register 6 */
|
||||
#define REG_XDMAC_CID6 (*(__O uint32_t*)0x400781D4U) /**< (XDMAC) Channel Interrupt Disable Register 6 */
|
||||
#define REG_XDMAC_CIM6 (*(__I uint32_t*)0x400781D8U) /**< (XDMAC) Channel Interrupt Mask Register 6 */
|
||||
#define REG_XDMAC_CIS6 (*(__I uint32_t*)0x400781DCU) /**< (XDMAC) Channel Interrupt Status Register 6 */
|
||||
#define REG_XDMAC_CSA6 (*(__IO uint32_t*)0x400781E0U) /**< (XDMAC) Channel Source Address Register 6 */
|
||||
#define REG_XDMAC_CDA6 (*(__IO uint32_t*)0x400781E4U) /**< (XDMAC) Channel Destination Address Register 6 */
|
||||
#define REG_XDMAC_CNDA6 (*(__IO uint32_t*)0x400781E8U) /**< (XDMAC) Channel Next Descriptor Address Register 6 */
|
||||
#define REG_XDMAC_CNDC6 (*(__IO uint32_t*)0x400781ECU) /**< (XDMAC) Channel Next Descriptor Control Register 6 */
|
||||
#define REG_XDMAC_CUBC6 (*(__IO uint32_t*)0x400781F0U) /**< (XDMAC) Channel Microblock Control Register 6 */
|
||||
#define REG_XDMAC_CBC6 (*(__IO uint32_t*)0x400781F4U) /**< (XDMAC) Channel Block Control Register 6 */
|
||||
#define REG_XDMAC_CC6 (*(__IO uint32_t*)0x400781F8U) /**< (XDMAC) Channel Configuration Register 6 */
|
||||
#define REG_XDMAC_CDS_MSP6 (*(__IO uint32_t*)0x400781FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 6 */
|
||||
#define REG_XDMAC_CSUS6 (*(__IO uint32_t*)0x40078200U) /**< (XDMAC) Channel Source Microblock Stride 6 */
|
||||
#define REG_XDMAC_CDUS6 (*(__IO uint32_t*)0x40078204U) /**< (XDMAC) Channel Destination Microblock Stride 6 */
|
||||
#define REG_XDMAC_CIE7 (*(__O uint32_t*)0x40078210U) /**< (XDMAC) Channel Interrupt Enable Register 7 */
|
||||
#define REG_XDMAC_CID7 (*(__O uint32_t*)0x40078214U) /**< (XDMAC) Channel Interrupt Disable Register 7 */
|
||||
#define REG_XDMAC_CIM7 (*(__I uint32_t*)0x40078218U) /**< (XDMAC) Channel Interrupt Mask Register 7 */
|
||||
#define REG_XDMAC_CIS7 (*(__I uint32_t*)0x4007821CU) /**< (XDMAC) Channel Interrupt Status Register 7 */
|
||||
#define REG_XDMAC_CSA7 (*(__IO uint32_t*)0x40078220U) /**< (XDMAC) Channel Source Address Register 7 */
|
||||
#define REG_XDMAC_CDA7 (*(__IO uint32_t*)0x40078224U) /**< (XDMAC) Channel Destination Address Register 7 */
|
||||
#define REG_XDMAC_CNDA7 (*(__IO uint32_t*)0x40078228U) /**< (XDMAC) Channel Next Descriptor Address Register 7 */
|
||||
#define REG_XDMAC_CNDC7 (*(__IO uint32_t*)0x4007822CU) /**< (XDMAC) Channel Next Descriptor Control Register 7 */
|
||||
#define REG_XDMAC_CUBC7 (*(__IO uint32_t*)0x40078230U) /**< (XDMAC) Channel Microblock Control Register 7 */
|
||||
#define REG_XDMAC_CBC7 (*(__IO uint32_t*)0x40078234U) /**< (XDMAC) Channel Block Control Register 7 */
|
||||
#define REG_XDMAC_CC7 (*(__IO uint32_t*)0x40078238U) /**< (XDMAC) Channel Configuration Register 7 */
|
||||
#define REG_XDMAC_CDS_MSP7 (*(__IO uint32_t*)0x4007823CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 7 */
|
||||
#define REG_XDMAC_CSUS7 (*(__IO uint32_t*)0x40078240U) /**< (XDMAC) Channel Source Microblock Stride 7 */
|
||||
#define REG_XDMAC_CDUS7 (*(__IO uint32_t*)0x40078244U) /**< (XDMAC) Channel Destination Microblock Stride 7 */
|
||||
#define REG_XDMAC_CIE8 (*(__O uint32_t*)0x40078250U) /**< (XDMAC) Channel Interrupt Enable Register 8 */
|
||||
#define REG_XDMAC_CID8 (*(__O uint32_t*)0x40078254U) /**< (XDMAC) Channel Interrupt Disable Register 8 */
|
||||
#define REG_XDMAC_CIM8 (*(__I uint32_t*)0x40078258U) /**< (XDMAC) Channel Interrupt Mask Register 8 */
|
||||
#define REG_XDMAC_CIS8 (*(__I uint32_t*)0x4007825CU) /**< (XDMAC) Channel Interrupt Status Register 8 */
|
||||
#define REG_XDMAC_CSA8 (*(__IO uint32_t*)0x40078260U) /**< (XDMAC) Channel Source Address Register 8 */
|
||||
#define REG_XDMAC_CDA8 (*(__IO uint32_t*)0x40078264U) /**< (XDMAC) Channel Destination Address Register 8 */
|
||||
#define REG_XDMAC_CNDA8 (*(__IO uint32_t*)0x40078268U) /**< (XDMAC) Channel Next Descriptor Address Register 8 */
|
||||
#define REG_XDMAC_CNDC8 (*(__IO uint32_t*)0x4007826CU) /**< (XDMAC) Channel Next Descriptor Control Register 8 */
|
||||
#define REG_XDMAC_CUBC8 (*(__IO uint32_t*)0x40078270U) /**< (XDMAC) Channel Microblock Control Register 8 */
|
||||
#define REG_XDMAC_CBC8 (*(__IO uint32_t*)0x40078274U) /**< (XDMAC) Channel Block Control Register 8 */
|
||||
#define REG_XDMAC_CC8 (*(__IO uint32_t*)0x40078278U) /**< (XDMAC) Channel Configuration Register 8 */
|
||||
#define REG_XDMAC_CDS_MSP8 (*(__IO uint32_t*)0x4007827CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 8 */
|
||||
#define REG_XDMAC_CSUS8 (*(__IO uint32_t*)0x40078280U) /**< (XDMAC) Channel Source Microblock Stride 8 */
|
||||
#define REG_XDMAC_CDUS8 (*(__IO uint32_t*)0x40078284U) /**< (XDMAC) Channel Destination Microblock Stride 8 */
|
||||
#define REG_XDMAC_CIE9 (*(__O uint32_t*)0x40078290U) /**< (XDMAC) Channel Interrupt Enable Register 9 */
|
||||
#define REG_XDMAC_CID9 (*(__O uint32_t*)0x40078294U) /**< (XDMAC) Channel Interrupt Disable Register 9 */
|
||||
#define REG_XDMAC_CIM9 (*(__I uint32_t*)0x40078298U) /**< (XDMAC) Channel Interrupt Mask Register 9 */
|
||||
#define REG_XDMAC_CIS9 (*(__I uint32_t*)0x4007829CU) /**< (XDMAC) Channel Interrupt Status Register 9 */
|
||||
#define REG_XDMAC_CSA9 (*(__IO uint32_t*)0x400782A0U) /**< (XDMAC) Channel Source Address Register 9 */
|
||||
#define REG_XDMAC_CDA9 (*(__IO uint32_t*)0x400782A4U) /**< (XDMAC) Channel Destination Address Register 9 */
|
||||
#define REG_XDMAC_CNDA9 (*(__IO uint32_t*)0x400782A8U) /**< (XDMAC) Channel Next Descriptor Address Register 9 */
|
||||
#define REG_XDMAC_CNDC9 (*(__IO uint32_t*)0x400782ACU) /**< (XDMAC) Channel Next Descriptor Control Register 9 */
|
||||
#define REG_XDMAC_CUBC9 (*(__IO uint32_t*)0x400782B0U) /**< (XDMAC) Channel Microblock Control Register 9 */
|
||||
#define REG_XDMAC_CBC9 (*(__IO uint32_t*)0x400782B4U) /**< (XDMAC) Channel Block Control Register 9 */
|
||||
#define REG_XDMAC_CC9 (*(__IO uint32_t*)0x400782B8U) /**< (XDMAC) Channel Configuration Register 9 */
|
||||
#define REG_XDMAC_CDS_MSP9 (*(__IO uint32_t*)0x400782BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 9 */
|
||||
#define REG_XDMAC_CSUS9 (*(__IO uint32_t*)0x400782C0U) /**< (XDMAC) Channel Source Microblock Stride 9 */
|
||||
#define REG_XDMAC_CDUS9 (*(__IO uint32_t*)0x400782C4U) /**< (XDMAC) Channel Destination Microblock Stride 9 */
|
||||
#define REG_XDMAC_CIE10 (*(__O uint32_t*)0x400782D0U) /**< (XDMAC) Channel Interrupt Enable Register 10 */
|
||||
#define REG_XDMAC_CID10 (*(__O uint32_t*)0x400782D4U) /**< (XDMAC) Channel Interrupt Disable Register 10 */
|
||||
#define REG_XDMAC_CIM10 (*(__I uint32_t*)0x400782D8U) /**< (XDMAC) Channel Interrupt Mask Register 10 */
|
||||
#define REG_XDMAC_CIS10 (*(__I uint32_t*)0x400782DCU) /**< (XDMAC) Channel Interrupt Status Register 10 */
|
||||
#define REG_XDMAC_CSA10 (*(__IO uint32_t*)0x400782E0U) /**< (XDMAC) Channel Source Address Register 10 */
|
||||
#define REG_XDMAC_CDA10 (*(__IO uint32_t*)0x400782E4U) /**< (XDMAC) Channel Destination Address Register 10 */
|
||||
#define REG_XDMAC_CNDA10 (*(__IO uint32_t*)0x400782E8U) /**< (XDMAC) Channel Next Descriptor Address Register 10 */
|
||||
#define REG_XDMAC_CNDC10 (*(__IO uint32_t*)0x400782ECU) /**< (XDMAC) Channel Next Descriptor Control Register 10 */
|
||||
#define REG_XDMAC_CUBC10 (*(__IO uint32_t*)0x400782F0U) /**< (XDMAC) Channel Microblock Control Register 10 */
|
||||
#define REG_XDMAC_CBC10 (*(__IO uint32_t*)0x400782F4U) /**< (XDMAC) Channel Block Control Register 10 */
|
||||
#define REG_XDMAC_CC10 (*(__IO uint32_t*)0x400782F8U) /**< (XDMAC) Channel Configuration Register 10 */
|
||||
#define REG_XDMAC_CDS_MSP10 (*(__IO uint32_t*)0x400782FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 10 */
|
||||
#define REG_XDMAC_CSUS10 (*(__IO uint32_t*)0x40078300U) /**< (XDMAC) Channel Source Microblock Stride 10 */
|
||||
#define REG_XDMAC_CDUS10 (*(__IO uint32_t*)0x40078304U) /**< (XDMAC) Channel Destination Microblock Stride 10 */
|
||||
#define REG_XDMAC_CIE11 (*(__O uint32_t*)0x40078310U) /**< (XDMAC) Channel Interrupt Enable Register 11 */
|
||||
#define REG_XDMAC_CID11 (*(__O uint32_t*)0x40078314U) /**< (XDMAC) Channel Interrupt Disable Register 11 */
|
||||
#define REG_XDMAC_CIM11 (*(__I uint32_t*)0x40078318U) /**< (XDMAC) Channel Interrupt Mask Register 11 */
|
||||
#define REG_XDMAC_CIS11 (*(__I uint32_t*)0x4007831CU) /**< (XDMAC) Channel Interrupt Status Register 11 */
|
||||
#define REG_XDMAC_CSA11 (*(__IO uint32_t*)0x40078320U) /**< (XDMAC) Channel Source Address Register 11 */
|
||||
#define REG_XDMAC_CDA11 (*(__IO uint32_t*)0x40078324U) /**< (XDMAC) Channel Destination Address Register 11 */
|
||||
#define REG_XDMAC_CNDA11 (*(__IO uint32_t*)0x40078328U) /**< (XDMAC) Channel Next Descriptor Address Register 11 */
|
||||
#define REG_XDMAC_CNDC11 (*(__IO uint32_t*)0x4007832CU) /**< (XDMAC) Channel Next Descriptor Control Register 11 */
|
||||
#define REG_XDMAC_CUBC11 (*(__IO uint32_t*)0x40078330U) /**< (XDMAC) Channel Microblock Control Register 11 */
|
||||
#define REG_XDMAC_CBC11 (*(__IO uint32_t*)0x40078334U) /**< (XDMAC) Channel Block Control Register 11 */
|
||||
#define REG_XDMAC_CC11 (*(__IO uint32_t*)0x40078338U) /**< (XDMAC) Channel Configuration Register 11 */
|
||||
#define REG_XDMAC_CDS_MSP11 (*(__IO uint32_t*)0x4007833CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 11 */
|
||||
#define REG_XDMAC_CSUS11 (*(__IO uint32_t*)0x40078340U) /**< (XDMAC) Channel Source Microblock Stride 11 */
|
||||
#define REG_XDMAC_CDUS11 (*(__IO uint32_t*)0x40078344U) /**< (XDMAC) Channel Destination Microblock Stride 11 */
|
||||
#define REG_XDMAC_CIE12 (*(__O uint32_t*)0x40078350U) /**< (XDMAC) Channel Interrupt Enable Register 12 */
|
||||
#define REG_XDMAC_CID12 (*(__O uint32_t*)0x40078354U) /**< (XDMAC) Channel Interrupt Disable Register 12 */
|
||||
#define REG_XDMAC_CIM12 (*(__I uint32_t*)0x40078358U) /**< (XDMAC) Channel Interrupt Mask Register 12 */
|
||||
#define REG_XDMAC_CIS12 (*(__I uint32_t*)0x4007835CU) /**< (XDMAC) Channel Interrupt Status Register 12 */
|
||||
#define REG_XDMAC_CSA12 (*(__IO uint32_t*)0x40078360U) /**< (XDMAC) Channel Source Address Register 12 */
|
||||
#define REG_XDMAC_CDA12 (*(__IO uint32_t*)0x40078364U) /**< (XDMAC) Channel Destination Address Register 12 */
|
||||
#define REG_XDMAC_CNDA12 (*(__IO uint32_t*)0x40078368U) /**< (XDMAC) Channel Next Descriptor Address Register 12 */
|
||||
#define REG_XDMAC_CNDC12 (*(__IO uint32_t*)0x4007836CU) /**< (XDMAC) Channel Next Descriptor Control Register 12 */
|
||||
#define REG_XDMAC_CUBC12 (*(__IO uint32_t*)0x40078370U) /**< (XDMAC) Channel Microblock Control Register 12 */
|
||||
#define REG_XDMAC_CBC12 (*(__IO uint32_t*)0x40078374U) /**< (XDMAC) Channel Block Control Register 12 */
|
||||
#define REG_XDMAC_CC12 (*(__IO uint32_t*)0x40078378U) /**< (XDMAC) Channel Configuration Register 12 */
|
||||
#define REG_XDMAC_CDS_MSP12 (*(__IO uint32_t*)0x4007837CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 12 */
|
||||
#define REG_XDMAC_CSUS12 (*(__IO uint32_t*)0x40078380U) /**< (XDMAC) Channel Source Microblock Stride 12 */
|
||||
#define REG_XDMAC_CDUS12 (*(__IO uint32_t*)0x40078384U) /**< (XDMAC) Channel Destination Microblock Stride 12 */
|
||||
#define REG_XDMAC_CIE13 (*(__O uint32_t*)0x40078390U) /**< (XDMAC) Channel Interrupt Enable Register 13 */
|
||||
#define REG_XDMAC_CID13 (*(__O uint32_t*)0x40078394U) /**< (XDMAC) Channel Interrupt Disable Register 13 */
|
||||
#define REG_XDMAC_CIM13 (*(__I uint32_t*)0x40078398U) /**< (XDMAC) Channel Interrupt Mask Register 13 */
|
||||
#define REG_XDMAC_CIS13 (*(__I uint32_t*)0x4007839CU) /**< (XDMAC) Channel Interrupt Status Register 13 */
|
||||
#define REG_XDMAC_CSA13 (*(__IO uint32_t*)0x400783A0U) /**< (XDMAC) Channel Source Address Register 13 */
|
||||
#define REG_XDMAC_CDA13 (*(__IO uint32_t*)0x400783A4U) /**< (XDMAC) Channel Destination Address Register 13 */
|
||||
#define REG_XDMAC_CNDA13 (*(__IO uint32_t*)0x400783A8U) /**< (XDMAC) Channel Next Descriptor Address Register 13 */
|
||||
#define REG_XDMAC_CNDC13 (*(__IO uint32_t*)0x400783ACU) /**< (XDMAC) Channel Next Descriptor Control Register 13 */
|
||||
#define REG_XDMAC_CUBC13 (*(__IO uint32_t*)0x400783B0U) /**< (XDMAC) Channel Microblock Control Register 13 */
|
||||
#define REG_XDMAC_CBC13 (*(__IO uint32_t*)0x400783B4U) /**< (XDMAC) Channel Block Control Register 13 */
|
||||
#define REG_XDMAC_CC13 (*(__IO uint32_t*)0x400783B8U) /**< (XDMAC) Channel Configuration Register 13 */
|
||||
#define REG_XDMAC_CDS_MSP13 (*(__IO uint32_t*)0x400783BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 13 */
|
||||
#define REG_XDMAC_CSUS13 (*(__IO uint32_t*)0x400783C0U) /**< (XDMAC) Channel Source Microblock Stride 13 */
|
||||
#define REG_XDMAC_CDUS13 (*(__IO uint32_t*)0x400783C4U) /**< (XDMAC) Channel Destination Microblock Stride 13 */
|
||||
#define REG_XDMAC_CIE14 (*(__O uint32_t*)0x400783D0U) /**< (XDMAC) Channel Interrupt Enable Register 14 */
|
||||
#define REG_XDMAC_CID14 (*(__O uint32_t*)0x400783D4U) /**< (XDMAC) Channel Interrupt Disable Register 14 */
|
||||
#define REG_XDMAC_CIM14 (*(__I uint32_t*)0x400783D8U) /**< (XDMAC) Channel Interrupt Mask Register 14 */
|
||||
#define REG_XDMAC_CIS14 (*(__I uint32_t*)0x400783DCU) /**< (XDMAC) Channel Interrupt Status Register 14 */
|
||||
#define REG_XDMAC_CSA14 (*(__IO uint32_t*)0x400783E0U) /**< (XDMAC) Channel Source Address Register 14 */
|
||||
#define REG_XDMAC_CDA14 (*(__IO uint32_t*)0x400783E4U) /**< (XDMAC) Channel Destination Address Register 14 */
|
||||
#define REG_XDMAC_CNDA14 (*(__IO uint32_t*)0x400783E8U) /**< (XDMAC) Channel Next Descriptor Address Register 14 */
|
||||
#define REG_XDMAC_CNDC14 (*(__IO uint32_t*)0x400783ECU) /**< (XDMAC) Channel Next Descriptor Control Register 14 */
|
||||
#define REG_XDMAC_CUBC14 (*(__IO uint32_t*)0x400783F0U) /**< (XDMAC) Channel Microblock Control Register 14 */
|
||||
#define REG_XDMAC_CBC14 (*(__IO uint32_t*)0x400783F4U) /**< (XDMAC) Channel Block Control Register 14 */
|
||||
#define REG_XDMAC_CC14 (*(__IO uint32_t*)0x400783F8U) /**< (XDMAC) Channel Configuration Register 14 */
|
||||
#define REG_XDMAC_CDS_MSP14 (*(__IO uint32_t*)0x400783FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 14 */
|
||||
#define REG_XDMAC_CSUS14 (*(__IO uint32_t*)0x40078400U) /**< (XDMAC) Channel Source Microblock Stride 14 */
|
||||
#define REG_XDMAC_CDUS14 (*(__IO uint32_t*)0x40078404U) /**< (XDMAC) Channel Destination Microblock Stride 14 */
|
||||
#define REG_XDMAC_CIE15 (*(__O uint32_t*)0x40078410U) /**< (XDMAC) Channel Interrupt Enable Register 15 */
|
||||
#define REG_XDMAC_CID15 (*(__O uint32_t*)0x40078414U) /**< (XDMAC) Channel Interrupt Disable Register 15 */
|
||||
#define REG_XDMAC_CIM15 (*(__I uint32_t*)0x40078418U) /**< (XDMAC) Channel Interrupt Mask Register 15 */
|
||||
#define REG_XDMAC_CIS15 (*(__I uint32_t*)0x4007841CU) /**< (XDMAC) Channel Interrupt Status Register 15 */
|
||||
#define REG_XDMAC_CSA15 (*(__IO uint32_t*)0x40078420U) /**< (XDMAC) Channel Source Address Register 15 */
|
||||
#define REG_XDMAC_CDA15 (*(__IO uint32_t*)0x40078424U) /**< (XDMAC) Channel Destination Address Register 15 */
|
||||
#define REG_XDMAC_CNDA15 (*(__IO uint32_t*)0x40078428U) /**< (XDMAC) Channel Next Descriptor Address Register 15 */
|
||||
#define REG_XDMAC_CNDC15 (*(__IO uint32_t*)0x4007842CU) /**< (XDMAC) Channel Next Descriptor Control Register 15 */
|
||||
#define REG_XDMAC_CUBC15 (*(__IO uint32_t*)0x40078430U) /**< (XDMAC) Channel Microblock Control Register 15 */
|
||||
#define REG_XDMAC_CBC15 (*(__IO uint32_t*)0x40078434U) /**< (XDMAC) Channel Block Control Register 15 */
|
||||
#define REG_XDMAC_CC15 (*(__IO uint32_t*)0x40078438U) /**< (XDMAC) Channel Configuration Register 15 */
|
||||
#define REG_XDMAC_CDS_MSP15 (*(__IO uint32_t*)0x4007843CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 15 */
|
||||
#define REG_XDMAC_CSUS15 (*(__IO uint32_t*)0x40078440U) /**< (XDMAC) Channel Source Microblock Stride 15 */
|
||||
#define REG_XDMAC_CDUS15 (*(__IO uint32_t*)0x40078444U) /**< (XDMAC) Channel Destination Microblock Stride 15 */
|
||||
#define REG_XDMAC_CIE16 (*(__O uint32_t*)0x40078450U) /**< (XDMAC) Channel Interrupt Enable Register 16 */
|
||||
#define REG_XDMAC_CID16 (*(__O uint32_t*)0x40078454U) /**< (XDMAC) Channel Interrupt Disable Register 16 */
|
||||
#define REG_XDMAC_CIM16 (*(__I uint32_t*)0x40078458U) /**< (XDMAC) Channel Interrupt Mask Register 16 */
|
||||
#define REG_XDMAC_CIS16 (*(__I uint32_t*)0x4007845CU) /**< (XDMAC) Channel Interrupt Status Register 16 */
|
||||
#define REG_XDMAC_CSA16 (*(__IO uint32_t*)0x40078460U) /**< (XDMAC) Channel Source Address Register 16 */
|
||||
#define REG_XDMAC_CDA16 (*(__IO uint32_t*)0x40078464U) /**< (XDMAC) Channel Destination Address Register 16 */
|
||||
#define REG_XDMAC_CNDA16 (*(__IO uint32_t*)0x40078468U) /**< (XDMAC) Channel Next Descriptor Address Register 16 */
|
||||
#define REG_XDMAC_CNDC16 (*(__IO uint32_t*)0x4007846CU) /**< (XDMAC) Channel Next Descriptor Control Register 16 */
|
||||
#define REG_XDMAC_CUBC16 (*(__IO uint32_t*)0x40078470U) /**< (XDMAC) Channel Microblock Control Register 16 */
|
||||
#define REG_XDMAC_CBC16 (*(__IO uint32_t*)0x40078474U) /**< (XDMAC) Channel Block Control Register 16 */
|
||||
#define REG_XDMAC_CC16 (*(__IO uint32_t*)0x40078478U) /**< (XDMAC) Channel Configuration Register 16 */
|
||||
#define REG_XDMAC_CDS_MSP16 (*(__IO uint32_t*)0x4007847CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 16 */
|
||||
#define REG_XDMAC_CSUS16 (*(__IO uint32_t*)0x40078480U) /**< (XDMAC) Channel Source Microblock Stride 16 */
|
||||
#define REG_XDMAC_CDUS16 (*(__IO uint32_t*)0x40078484U) /**< (XDMAC) Channel Destination Microblock Stride 16 */
|
||||
#define REG_XDMAC_CIE17 (*(__O uint32_t*)0x40078490U) /**< (XDMAC) Channel Interrupt Enable Register 17 */
|
||||
#define REG_XDMAC_CID17 (*(__O uint32_t*)0x40078494U) /**< (XDMAC) Channel Interrupt Disable Register 17 */
|
||||
#define REG_XDMAC_CIM17 (*(__I uint32_t*)0x40078498U) /**< (XDMAC) Channel Interrupt Mask Register 17 */
|
||||
#define REG_XDMAC_CIS17 (*(__I uint32_t*)0x4007849CU) /**< (XDMAC) Channel Interrupt Status Register 17 */
|
||||
#define REG_XDMAC_CSA17 (*(__IO uint32_t*)0x400784A0U) /**< (XDMAC) Channel Source Address Register 17 */
|
||||
#define REG_XDMAC_CDA17 (*(__IO uint32_t*)0x400784A4U) /**< (XDMAC) Channel Destination Address Register 17 */
|
||||
#define REG_XDMAC_CNDA17 (*(__IO uint32_t*)0x400784A8U) /**< (XDMAC) Channel Next Descriptor Address Register 17 */
|
||||
#define REG_XDMAC_CNDC17 (*(__IO uint32_t*)0x400784ACU) /**< (XDMAC) Channel Next Descriptor Control Register 17 */
|
||||
#define REG_XDMAC_CUBC17 (*(__IO uint32_t*)0x400784B0U) /**< (XDMAC) Channel Microblock Control Register 17 */
|
||||
#define REG_XDMAC_CBC17 (*(__IO uint32_t*)0x400784B4U) /**< (XDMAC) Channel Block Control Register 17 */
|
||||
#define REG_XDMAC_CC17 (*(__IO uint32_t*)0x400784B8U) /**< (XDMAC) Channel Configuration Register 17 */
|
||||
#define REG_XDMAC_CDS_MSP17 (*(__IO uint32_t*)0x400784BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 17 */
|
||||
#define REG_XDMAC_CSUS17 (*(__IO uint32_t*)0x400784C0U) /**< (XDMAC) Channel Source Microblock Stride 17 */
|
||||
#define REG_XDMAC_CDUS17 (*(__IO uint32_t*)0x400784C4U) /**< (XDMAC) Channel Destination Microblock Stride 17 */
|
||||
#define REG_XDMAC_CIE18 (*(__O uint32_t*)0x400784D0U) /**< (XDMAC) Channel Interrupt Enable Register 18 */
|
||||
#define REG_XDMAC_CID18 (*(__O uint32_t*)0x400784D4U) /**< (XDMAC) Channel Interrupt Disable Register 18 */
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#define REG_XDMAC_CIM18 (*(__I uint32_t*)0x400784D8U) /**< (XDMAC) Channel Interrupt Mask Register 18 */
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||||
#define REG_XDMAC_CIS18 (*(__I uint32_t*)0x400784DCU) /**< (XDMAC) Channel Interrupt Status Register 18 */
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||||
#define REG_XDMAC_CSA18 (*(__IO uint32_t*)0x400784E0U) /**< (XDMAC) Channel Source Address Register 18 */
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||||
#define REG_XDMAC_CDA18 (*(__IO uint32_t*)0x400784E4U) /**< (XDMAC) Channel Destination Address Register 18 */
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||||
#define REG_XDMAC_CNDA18 (*(__IO uint32_t*)0x400784E8U) /**< (XDMAC) Channel Next Descriptor Address Register 18 */
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||||
#define REG_XDMAC_CNDC18 (*(__IO uint32_t*)0x400784ECU) /**< (XDMAC) Channel Next Descriptor Control Register 18 */
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||||
#define REG_XDMAC_CUBC18 (*(__IO uint32_t*)0x400784F0U) /**< (XDMAC) Channel Microblock Control Register 18 */
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||||
#define REG_XDMAC_CBC18 (*(__IO uint32_t*)0x400784F4U) /**< (XDMAC) Channel Block Control Register 18 */
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||||
#define REG_XDMAC_CC18 (*(__IO uint32_t*)0x400784F8U) /**< (XDMAC) Channel Configuration Register 18 */
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||||
#define REG_XDMAC_CDS_MSP18 (*(__IO uint32_t*)0x400784FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 18 */
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||||
#define REG_XDMAC_CSUS18 (*(__IO uint32_t*)0x40078500U) /**< (XDMAC) Channel Source Microblock Stride 18 */
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||||
#define REG_XDMAC_CDUS18 (*(__IO uint32_t*)0x40078504U) /**< (XDMAC) Channel Destination Microblock Stride 18 */
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#define REG_XDMAC_CIE19 (*(__O uint32_t*)0x40078510U) /**< (XDMAC) Channel Interrupt Enable Register 19 */
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||||
#define REG_XDMAC_CID19 (*(__O uint32_t*)0x40078514U) /**< (XDMAC) Channel Interrupt Disable Register 19 */
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||||
#define REG_XDMAC_CIM19 (*(__I uint32_t*)0x40078518U) /**< (XDMAC) Channel Interrupt Mask Register 19 */
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||||
#define REG_XDMAC_CIS19 (*(__I uint32_t*)0x4007851CU) /**< (XDMAC) Channel Interrupt Status Register 19 */
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||||
#define REG_XDMAC_CSA19 (*(__IO uint32_t*)0x40078520U) /**< (XDMAC) Channel Source Address Register 19 */
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||||
#define REG_XDMAC_CDA19 (*(__IO uint32_t*)0x40078524U) /**< (XDMAC) Channel Destination Address Register 19 */
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||||
#define REG_XDMAC_CNDA19 (*(__IO uint32_t*)0x40078528U) /**< (XDMAC) Channel Next Descriptor Address Register 19 */
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||||
#define REG_XDMAC_CNDC19 (*(__IO uint32_t*)0x4007852CU) /**< (XDMAC) Channel Next Descriptor Control Register 19 */
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||||
#define REG_XDMAC_CUBC19 (*(__IO uint32_t*)0x40078530U) /**< (XDMAC) Channel Microblock Control Register 19 */
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||||
#define REG_XDMAC_CBC19 (*(__IO uint32_t*)0x40078534U) /**< (XDMAC) Channel Block Control Register 19 */
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||||
#define REG_XDMAC_CC19 (*(__IO uint32_t*)0x40078538U) /**< (XDMAC) Channel Configuration Register 19 */
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||||
#define REG_XDMAC_CDS_MSP19 (*(__IO uint32_t*)0x4007853CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 19 */
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||||
#define REG_XDMAC_CSUS19 (*(__IO uint32_t*)0x40078540U) /**< (XDMAC) Channel Source Microblock Stride 19 */
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||||
#define REG_XDMAC_CDUS19 (*(__IO uint32_t*)0x40078544U) /**< (XDMAC) Channel Destination Microblock Stride 19 */
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||||
#define REG_XDMAC_CIE20 (*(__O uint32_t*)0x40078550U) /**< (XDMAC) Channel Interrupt Enable Register 20 */
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||||
#define REG_XDMAC_CID20 (*(__O uint32_t*)0x40078554U) /**< (XDMAC) Channel Interrupt Disable Register 20 */
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||||
#define REG_XDMAC_CIM20 (*(__I uint32_t*)0x40078558U) /**< (XDMAC) Channel Interrupt Mask Register 20 */
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||||
#define REG_XDMAC_CIS20 (*(__I uint32_t*)0x4007855CU) /**< (XDMAC) Channel Interrupt Status Register 20 */
|
||||
#define REG_XDMAC_CSA20 (*(__IO uint32_t*)0x40078560U) /**< (XDMAC) Channel Source Address Register 20 */
|
||||
#define REG_XDMAC_CDA20 (*(__IO uint32_t*)0x40078564U) /**< (XDMAC) Channel Destination Address Register 20 */
|
||||
#define REG_XDMAC_CNDA20 (*(__IO uint32_t*)0x40078568U) /**< (XDMAC) Channel Next Descriptor Address Register 20 */
|
||||
#define REG_XDMAC_CNDC20 (*(__IO uint32_t*)0x4007856CU) /**< (XDMAC) Channel Next Descriptor Control Register 20 */
|
||||
#define REG_XDMAC_CUBC20 (*(__IO uint32_t*)0x40078570U) /**< (XDMAC) Channel Microblock Control Register 20 */
|
||||
#define REG_XDMAC_CBC20 (*(__IO uint32_t*)0x40078574U) /**< (XDMAC) Channel Block Control Register 20 */
|
||||
#define REG_XDMAC_CC20 (*(__IO uint32_t*)0x40078578U) /**< (XDMAC) Channel Configuration Register 20 */
|
||||
#define REG_XDMAC_CDS_MSP20 (*(__IO uint32_t*)0x4007857CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 20 */
|
||||
#define REG_XDMAC_CSUS20 (*(__IO uint32_t*)0x40078580U) /**< (XDMAC) Channel Source Microblock Stride 20 */
|
||||
#define REG_XDMAC_CDUS20 (*(__IO uint32_t*)0x40078584U) /**< (XDMAC) Channel Destination Microblock Stride 20 */
|
||||
#define REG_XDMAC_CIE21 (*(__O uint32_t*)0x40078590U) /**< (XDMAC) Channel Interrupt Enable Register 21 */
|
||||
#define REG_XDMAC_CID21 (*(__O uint32_t*)0x40078594U) /**< (XDMAC) Channel Interrupt Disable Register 21 */
|
||||
#define REG_XDMAC_CIM21 (*(__I uint32_t*)0x40078598U) /**< (XDMAC) Channel Interrupt Mask Register 21 */
|
||||
#define REG_XDMAC_CIS21 (*(__I uint32_t*)0x4007859CU) /**< (XDMAC) Channel Interrupt Status Register 21 */
|
||||
#define REG_XDMAC_CSA21 (*(__IO uint32_t*)0x400785A0U) /**< (XDMAC) Channel Source Address Register 21 */
|
||||
#define REG_XDMAC_CDA21 (*(__IO uint32_t*)0x400785A4U) /**< (XDMAC) Channel Destination Address Register 21 */
|
||||
#define REG_XDMAC_CNDA21 (*(__IO uint32_t*)0x400785A8U) /**< (XDMAC) Channel Next Descriptor Address Register 21 */
|
||||
#define REG_XDMAC_CNDC21 (*(__IO uint32_t*)0x400785ACU) /**< (XDMAC) Channel Next Descriptor Control Register 21 */
|
||||
#define REG_XDMAC_CUBC21 (*(__IO uint32_t*)0x400785B0U) /**< (XDMAC) Channel Microblock Control Register 21 */
|
||||
#define REG_XDMAC_CBC21 (*(__IO uint32_t*)0x400785B4U) /**< (XDMAC) Channel Block Control Register 21 */
|
||||
#define REG_XDMAC_CC21 (*(__IO uint32_t*)0x400785B8U) /**< (XDMAC) Channel Configuration Register 21 */
|
||||
#define REG_XDMAC_CDS_MSP21 (*(__IO uint32_t*)0x400785BCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 21 */
|
||||
#define REG_XDMAC_CSUS21 (*(__IO uint32_t*)0x400785C0U) /**< (XDMAC) Channel Source Microblock Stride 21 */
|
||||
#define REG_XDMAC_CDUS21 (*(__IO uint32_t*)0x400785C4U) /**< (XDMAC) Channel Destination Microblock Stride 21 */
|
||||
#define REG_XDMAC_CIE22 (*(__O uint32_t*)0x400785D0U) /**< (XDMAC) Channel Interrupt Enable Register 22 */
|
||||
#define REG_XDMAC_CID22 (*(__O uint32_t*)0x400785D4U) /**< (XDMAC) Channel Interrupt Disable Register 22 */
|
||||
#define REG_XDMAC_CIM22 (*(__I uint32_t*)0x400785D8U) /**< (XDMAC) Channel Interrupt Mask Register 22 */
|
||||
#define REG_XDMAC_CIS22 (*(__I uint32_t*)0x400785DCU) /**< (XDMAC) Channel Interrupt Status Register 22 */
|
||||
#define REG_XDMAC_CSA22 (*(__IO uint32_t*)0x400785E0U) /**< (XDMAC) Channel Source Address Register 22 */
|
||||
#define REG_XDMAC_CDA22 (*(__IO uint32_t*)0x400785E4U) /**< (XDMAC) Channel Destination Address Register 22 */
|
||||
#define REG_XDMAC_CNDA22 (*(__IO uint32_t*)0x400785E8U) /**< (XDMAC) Channel Next Descriptor Address Register 22 */
|
||||
#define REG_XDMAC_CNDC22 (*(__IO uint32_t*)0x400785ECU) /**< (XDMAC) Channel Next Descriptor Control Register 22 */
|
||||
#define REG_XDMAC_CUBC22 (*(__IO uint32_t*)0x400785F0U) /**< (XDMAC) Channel Microblock Control Register 22 */
|
||||
#define REG_XDMAC_CBC22 (*(__IO uint32_t*)0x400785F4U) /**< (XDMAC) Channel Block Control Register 22 */
|
||||
#define REG_XDMAC_CC22 (*(__IO uint32_t*)0x400785F8U) /**< (XDMAC) Channel Configuration Register 22 */
|
||||
#define REG_XDMAC_CDS_MSP22 (*(__IO uint32_t*)0x400785FCU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 22 */
|
||||
#define REG_XDMAC_CSUS22 (*(__IO uint32_t*)0x40078600U) /**< (XDMAC) Channel Source Microblock Stride 22 */
|
||||
#define REG_XDMAC_CDUS22 (*(__IO uint32_t*)0x40078604U) /**< (XDMAC) Channel Destination Microblock Stride 22 */
|
||||
#define REG_XDMAC_CIE23 (*(__O uint32_t*)0x40078610U) /**< (XDMAC) Channel Interrupt Enable Register 23 */
|
||||
#define REG_XDMAC_CID23 (*(__O uint32_t*)0x40078614U) /**< (XDMAC) Channel Interrupt Disable Register 23 */
|
||||
#define REG_XDMAC_CIM23 (*(__I uint32_t*)0x40078618U) /**< (XDMAC) Channel Interrupt Mask Register 23 */
|
||||
#define REG_XDMAC_CIS23 (*(__I uint32_t*)0x4007861CU) /**< (XDMAC) Channel Interrupt Status Register 23 */
|
||||
#define REG_XDMAC_CSA23 (*(__IO uint32_t*)0x40078620U) /**< (XDMAC) Channel Source Address Register 23 */
|
||||
#define REG_XDMAC_CDA23 (*(__IO uint32_t*)0x40078624U) /**< (XDMAC) Channel Destination Address Register 23 */
|
||||
#define REG_XDMAC_CNDA23 (*(__IO uint32_t*)0x40078628U) /**< (XDMAC) Channel Next Descriptor Address Register 23 */
|
||||
#define REG_XDMAC_CNDC23 (*(__IO uint32_t*)0x4007862CU) /**< (XDMAC) Channel Next Descriptor Control Register 23 */
|
||||
#define REG_XDMAC_CUBC23 (*(__IO uint32_t*)0x40078630U) /**< (XDMAC) Channel Microblock Control Register 23 */
|
||||
#define REG_XDMAC_CBC23 (*(__IO uint32_t*)0x40078634U) /**< (XDMAC) Channel Block Control Register 23 */
|
||||
#define REG_XDMAC_CC23 (*(__IO uint32_t*)0x40078638U) /**< (XDMAC) Channel Configuration Register 23 */
|
||||
#define REG_XDMAC_CDS_MSP23 (*(__IO uint32_t*)0x4007863CU) /**< (XDMAC) Channel Data Stride Memory Set Pattern 23 */
|
||||
#define REG_XDMAC_CSUS23 (*(__IO uint32_t*)0x40078640U) /**< (XDMAC) Channel Source Microblock Stride 23 */
|
||||
#define REG_XDMAC_CDUS23 (*(__IO uint32_t*)0x40078644U) /**< (XDMAC) Channel Destination Microblock Stride 23 */
|
||||
#define REG_XDMAC_GTYPE (*(__I uint32_t*)0x40078000U) /**< (XDMAC) Global Type Register */
|
||||
#define REG_XDMAC_GCFG (*(__IO uint32_t*)0x40078004U) /**< (XDMAC) Global Configuration Register */
|
||||
#define REG_XDMAC_GWAC (*(__IO uint32_t*)0x40078008U) /**< (XDMAC) Global Weighted Arbiter Configuration Register */
|
||||
#define REG_XDMAC_GIE (*(__O uint32_t*)0x4007800CU) /**< (XDMAC) Global Interrupt Enable Register */
|
||||
#define REG_XDMAC_GID (*(__O uint32_t*)0x40078010U) /**< (XDMAC) Global Interrupt Disable Register */
|
||||
#define REG_XDMAC_GIM (*(__I uint32_t*)0x40078014U) /**< (XDMAC) Global Interrupt Mask Register */
|
||||
#define REG_XDMAC_GIS (*(__I uint32_t*)0x40078018U) /**< (XDMAC) Global Interrupt Status Register */
|
||||
#define REG_XDMAC_GE (*(__O uint32_t*)0x4007801CU) /**< (XDMAC) Global Channel Enable Register */
|
||||
#define REG_XDMAC_GD (*(__O uint32_t*)0x40078020U) /**< (XDMAC) Global Channel Disable Register */
|
||||
#define REG_XDMAC_GS (*(__I uint32_t*)0x40078024U) /**< (XDMAC) Global Channel Status Register */
|
||||
#define REG_XDMAC_GRS (*(__IO uint32_t*)0x40078028U) /**< (XDMAC) Global Channel Read Suspend Register */
|
||||
#define REG_XDMAC_GWS (*(__IO uint32_t*)0x4007802CU) /**< (XDMAC) Global Channel Write Suspend Register */
|
||||
#define REG_XDMAC_GRWS (*(__O uint32_t*)0x40078030U) /**< (XDMAC) Global Channel Read Write Suspend Register */
|
||||
#define REG_XDMAC_GRWR (*(__O uint32_t*)0x40078034U) /**< (XDMAC) Global Channel Read Write Resume Register */
|
||||
#define REG_XDMAC_GSWR (*(__O uint32_t*)0x40078038U) /**< (XDMAC) Global Channel Software Request Register */
|
||||
#define REG_XDMAC_GSWS (*(__I uint32_t*)0x4007803CU) /**< (XDMAC) Global Channel Software Request Status Register */
|
||||
#define REG_XDMAC_GSWF (*(__O uint32_t*)0x40078040U) /**< (XDMAC) Global Channel Software Flush Request Register */
|
||||
|
||||
#endif /* (defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */
|
||||
|
||||
/* ========== Instance Parameter definitions for XDMAC peripheral ========== */
|
||||
#define XDMAC_INSTANCE_ID 58
|
||||
#define XDMAC_CLOCK_ID 58
|
||||
|
||||
#endif /* _SAME70_XDMAC_INSTANCE_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue