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lib: Add hc32f460 definitions
Signed-off-by: Steven Gotthardt <gotthardt@gmail.com>
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Steven Gotthardt
Kevin O'Connor
parent
1e7057e917
commit
94cbf5ff48
87 changed files with 80723 additions and 0 deletions
268
lib/hc32f460/driver/inc/hc32f460_timer4_oco.h
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268
lib/hc32f460/driver/inc/hc32f460_timer4_oco.h
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/*******************************************************************************
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* Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved.
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*
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* This software component is licensed by HDSC under BSD 3-Clause license
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* (the "License"); You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*/
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/******************************************************************************/
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/** \file hc32f460_timer4_oco.h
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**
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** A detailed description is available at
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** @link Timer4OcoGroup Timer4OCO description @endlink
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**
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** - 2018-11-02 CDT First version for Device Driver Library of Timer4OCO.
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**
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******************************************************************************/
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#ifndef __HC32F460_TIMER4_OCO_H__
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#define __HC32F460_TIMER4_OCO_H__
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/*******************************************************************************
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* Include files
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******************************************************************************/
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#include "hc32_common.h"
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/* C binding of definitions if building with C++ compiler */
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/**
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*******************************************************************************
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** \defgroup Timer4OcoGroup Timer4 Output Compare(Timer4OCO)
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**
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******************************************************************************/
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//@{
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/*******************************************************************************
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* Global type definitions ('typedef')
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******************************************************************************/
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/**
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*******************************************************************************
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** \brief Timer4 OCO channel enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_oco_ch
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{
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Timer4OcoOuh = 0u, ///< Timer4 OCO channel:OUH
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Timer4OcoOul = 1u, ///< Timer4 OCO channel:OUL
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Timer4OcoOvh = 2u, ///< Timer4 OCO channel:OVH
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Timer4OcoOvl = 3u, ///< Timer4 OCO channel:OVL
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Timer4OcoOwh = 4u, ///< Timer4 OCO channel:OWH
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Timer4OcoOwl = 5u, ///< Timer4 OCO channel:OWL
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} en_timer4_oco_ch_t;
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/**
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*******************************************************************************
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** \brief output level of the OC port enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_oco_port_level
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{
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OcPortLevelLow = 0u, ///< Output low level to OC port
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OcPortLevelHigh = 1u, ///< Output high level to OC port
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} en_timer4_oco_port_level_t;
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/**
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*******************************************************************************
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** \brief buffer register function of OCCR
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**
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******************************************************************************/
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typedef enum en_timer4_oco_occr_buf
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{
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OccrBufDisable = 0u, ///< Disable the register buffer function
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OccrBufTrsfByCntZero = 1u, ///< Register buffer transfer when counter value is 0x0000
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OccrBufTrsfByCntPeak = 2u, ///< Register buffer transfer when counter value is CPSR
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OccrBufTrsfByCntZeroOrCntPeak = 3u, ///< Register buffer transfer when the value is both 0 and CPSR
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OccrBufTrsfByCntZeroZicZero = 4u, ///< Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0
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OccrBufTrsfByCntPeakPicZero = 5u, ///< Register buffer transfer when counter value is CPSR and peak value detection mask counter value is 0
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OccrBufTrsfByCntZeroZicZeroOrCntPeakPicZero = 6u, ///< Register buffer transfer when counter value is 0x0000 and zero value detection mask counter value is 0 or
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///< when counter value is CPSR and peak value detection mask counter value is 0
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} en_timer4_oco_occr_buf_t;
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/**
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*******************************************************************************
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** \brief buffer register function of OCMR
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**
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******************************************************************************/
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typedef enum en_timer4_oco_ocmr_buf
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{
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OcmrBufDisable = 0u, ///< Disable the register buffer function
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OcmrBufTrsfByCntZero = 1u, ///< Register buffer transfer when counter value is 0x0000
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OcmrBufTrsfByCntPeak = 2u, ///< Register buffer transfer when counter value is CPSR
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OcmrBufTrsfByCntZeroOrCntPeak = 3u, ///< Register buffer transfer when the value is both 0 and CPSR
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OcmrBufTrsfByCntZeroZicZero = 4u, ///< Register buffer transfer when CNT counter value is 0x0000 and zero value detection mask counter value is 0
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OcmrBufTrsfByCntPeakPicZero = 5u, ///< Register buffer transfer when CNT counter value is CPSR and peak value detection mask counter value is 0
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OcmrBufTrsfByCntZeroZicZeroOrCntPeakPicZero = 6u, ///< Register buffer transfer when CNT counter value is 0x0000 and zero value detection mask counter value is 0 or
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///< when CNT counter value is CPSR and peak value detection mask counter value is 0
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} en_timer4_oco_ocmr_buf_t;
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/**
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*******************************************************************************
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** \brief OP output status enumeration
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**
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******************************************************************************/
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typedef enum en_timer4_oco_op_state
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{
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OcoOpOutputHold = 0u, ///< OP output hold
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OcoOpOutputHigh = 1u, ///< OP output high
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OcoOpOutputLow = 2u, ///< OP output low
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OcoOpOutputReverse = 3u, ///< OP output reverse
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} en_timer4_oco_op_state_t;
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/**
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*******************************************************************************
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** \brief The condition for OCF set
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**
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******************************************************************************/
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typedef enum en_timer4_oco_ocf_state
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{
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OcoOcfHold = 0u, ///< OCF hold
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OcoOcfSet = 1u, ///< OCF set
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} en_timer4_oco_ocf_state_t;
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/**
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*******************************************************************************
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** \brief The configuration of OCO high channel(OUH/OVH/OWH)
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**
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******************************************************************************/
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typedef struct stc_oco_high_ch_compare_mode
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{
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en_timer4_oco_op_state_t enCntZeroMatchOpState; ///< b11~b10 High channel's OP output status when high channel match occurs at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntZeroNotMatchOpState; ///< b15~b14 High channel's OP output status when high channel match doesn't occur at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntUpCntMatchOpState; ///< b9~b8 High channel's OP output status when high channel match occurs at the condition of CNT is counting up
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en_timer4_oco_op_state_t enCntPeakMatchOpState; ///< b7~b6 High channel's OP output status when high channel match occurs at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntPeakNotMatchOpState; ///< b13~b12 High channel's OP output status when high channel match doesn't occur at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntDownCntMatchOpState; ///< b5~b4 High channel's OP output status when high channel match occurs at the condition of CNT is counting down
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en_timer4_oco_ocf_state_t enCntZeroMatchOcfState; ///< b3 High channel's OCF status when high channel match occurs at the condition of CNT count=0x0000
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en_timer4_oco_ocf_state_t enCntUpCntMatchOcfState; ///< b2 High channel's OCF status when high channel match occurs at the condition of CNT is counting up
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en_timer4_oco_ocf_state_t enCntPeakMatchOcfState; ///< b1 High channel's OCF status when high channel match occurs at the condition of CNT count=Peak
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en_timer4_oco_ocf_state_t enCntDownCntMatchOcfState; ///< b0 High channel's OCF status when high channel match occurs at the condition of CNT is counting down
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en_functional_state_t enMatchConditionExtendCmd; ///< Enable: Extend the match condition
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///< Disable: Don't extend the match conditio
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} stc_oco_high_ch_compare_mode_t;
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/**
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*******************************************************************************
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** \brief The configuration of OCO low channel(OUL/OVL/OWL)
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**
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******************************************************************************/
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typedef struct stc_oco_low_ch_compare_mode
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{
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en_timer4_oco_op_state_t enCntZeroLowMatchHighMatchLowChOpState; ///< b27~b26 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntZeroLowMatchHighNotMatchLowChOpState; ///< b11~b10 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntZeroLowNotMatchHighMatchLowChOpState; ///< b31~b30 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntZeroLowNotMatchHighNotMatchLowChOpState; ///< b15~b14 Low channel's OP output status when high channel not match and low channel not match occurs at the condition of CNT count=0x0000
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en_timer4_oco_op_state_t enCntUpCntLowMatchHighMatchLowChOpState; ///< b25~b24 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT is counting up
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en_timer4_oco_op_state_t enCntUpCntLowMatchHighNotMatchLowChOpState; ///< b9~b8 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT is counting up
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en_timer4_oco_op_state_t enCntUpCntLowNotMatchHighMatchLowChOpState; ///< b19~b18 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT is counting up
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en_timer4_oco_op_state_t enCntPeakLowMatchHighMatchLowChOpState; ///< b23~b22 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntPeakLowMatchHighNotMatchLowChOpState; ///< b7~b6 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntPeakLowNotMatchHighMatchLowChOpState; ///< b29~b28 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntPeakLowNotMatchHighNotMatchLowChOpState; ///< b13~b12 Low channel's OP output status when high channel not match and low channel not match occurs at the condition of CNT count=Peak
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en_timer4_oco_op_state_t enCntDownLowMatchHighMatchLowChOpState; ///< b21~b20 Low channel's OP output status when high channel and low channel match occurs at the condition of CNT is counting down
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en_timer4_oco_op_state_t enCntDownLowMatchHighNotMatchLowChOpState; ///< b5~b4 Low channel's OP output status when high channel not match and low channel match occurs at the condition of CNT is counting down
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en_timer4_oco_op_state_t enCntDownLowNotMatchHighMatchLowChOpState; ///< b17~b16 Low channel's OP output status when high channel match and low channel not match occurs at the condition of CNT is coutning down
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en_timer4_oco_ocf_state_t enCntZeroMatchOcfState; ///< b3 Low channel's OCF status when low channel match occurs at the condition of CNT count=0x0000
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en_timer4_oco_ocf_state_t enCntUpCntMatchOcfState; ///< b2 Low channel's OCF status when low channel match occurs at the condition of CNT is counting up
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en_timer4_oco_ocf_state_t enCntPeakMatchOcfState; ///< b1 Low channel's OCF status when low channel match occurs at the condition of CNT count=Peak
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en_timer4_oco_ocf_state_t enCntDownCntMatchOcfState; ///< b0 Low channel's OCF status when low channel match occurs at the condition of CNT is counting down
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en_functional_state_t enMatchConditionExtendCmd; ///< Enable: Extend the match condition
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///< Disable: Don't extend the match conditio
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} stc_oco_low_ch_compare_mode_t;
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/**
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*******************************************************************************
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** \brief Timer4 OCO initialization configuration
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**
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******************************************************************************/
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typedef struct stc_timer4_oco_init
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{
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en_timer4_oco_occr_buf_t enOccrBufMode; ///< buffer register function of OCCR
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en_timer4_oco_ocmr_buf_t enOcmrBufMode; ///< buffer register function of OCMR
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en_timer4_oco_port_level_t enPortLevel; ///< OP output level state
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en_functional_state_t enOcoIntCmd; ///< Disable: Disable interrupt; Enable:Enable interrupt
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} stc_timer4_oco_init_t;
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global pre-processor symbols/macros ('#define')
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******************************************************************************/
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/*******************************************************************************
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* Global variable definitions ('extern')
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******************************************************************************/
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/*******************************************************************************
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* Global function prototypes (definition in C source)
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******************************************************************************/
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en_result_t TIMER4_OCO_Init(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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const stc_timer4_oco_init_t* pstcInitCfg);
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en_result_t TIMER4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh);
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en_result_t TIMER4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_timer4_oco_occr_buf_t enOccrBufMode);
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en_result_t TIMER4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_timer4_oco_ocmr_buf_t enOcmrBufMode);
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en_result_t TIMER4_OCO_ExtMatchCondCmd(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_functional_state_t enCmd);
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en_result_t TIMER4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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const stc_oco_high_ch_compare_mode_t *pstcMode);
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en_result_t TIMER4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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const stc_oco_low_ch_compare_mode_t *pstcMode);
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en_result_t TIMER4_OCO_OutputCompareCmd(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_functional_state_t enCmd);
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en_result_t TIMER4_OCO_IrqCmd(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_functional_state_t enCmd);
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en_flag_status_t TIMER4_OCO_GetIrqFlag(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh);
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en_result_t TIMER4_OCO_ClearIrqFlag(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh);
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en_result_t TIMER4_OCO_SetOpPortLevel(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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en_timer4_oco_port_level_t enLevel);
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en_timer4_oco_port_level_t TIMER4_OCO_GetOpPinLevel(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh);
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en_result_t TIMER4_OCO_WriteOccr(M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh,
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uint16_t u16Occr);
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uint16_t TIMER4_OCO_ReadOccr(const M4_TMR4_TypeDef *TMR4x,
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en_timer4_oco_ch_t enCh);
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//@} // Timer4OcoGroup
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#ifdef __cplusplus
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}
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#endif
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#endif /* __HC32F460_TIMER4_OCO_H__ */
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/*******************************************************************************
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* EOF (not truncated)
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******************************************************************************/
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