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Add STM32F103 port
Add a fully functional STM32F1 port, currently mostly targeting STM32F103 microcontrollers. This requires an 8 MHz XTAL. The maximum possible step rate is around 282K steps per second. This uses stm32flash to burn the firmware. The bootloader needs to be started by setting BOOT0 to 1 and resetting the MCU. There is no automatic bootloader, unlike on Arduino. Signed-off-by: Grigori Goronzy <greg@kinoho.net>
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166
src/stm32f1/serial.c
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166
src/stm32f1/serial.c
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// STM32F1 serial port
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//
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// Copyright (C) 2018 Grigori Goronzy <greg@kinoho.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // memmove
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#include "autoconf.h" // CONFIG_SERIAL_BAUD
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#include "command.h" // DECL_CONSTANT
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#include "stm32f1xx.h" // UART
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#include "stm32f1xx_ll_bus.h"
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#include "stm32f1xx_ll_rcc.h"
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#include "stm32f1xx_ll_usart.h"
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#include "stm32f1xx_ll_gpio.h"
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#include "board/irq.h"
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#include "board/io.h"
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#include "sched.h" // DECL_INIT
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#define SERIAL_BUFFER_SIZE 96
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static char receive_buf[SERIAL_BUFFER_SIZE];
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static uint32_t receive_pos;
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static char transmit_buf[SERIAL_BUFFER_SIZE];
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static uint32_t transmit_pos, transmit_max;
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/****************************************************************
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* Serial hardware
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****************************************************************/
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DECL_CONSTANT(SERIAL_BAUD, CONFIG_SERIAL_BAUD);
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void
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serial_init(void)
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{
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const uint32_t pclk = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock, LL_RCC_GetAPB2Prescaler());
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LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
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LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
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LL_USART_SetBaudRate(USART1, pclk, CONFIG_SERIAL_BAUD);
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LL_USART_SetDataWidth(USART1, LL_USART_DATAWIDTH_8B);
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LL_USART_SetParity(USART1, LL_USART_PARITY_NONE);
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LL_USART_SetStopBitsLength(USART1, LL_USART_STOPBITS_1);
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LL_USART_SetHWFlowCtrl(USART1, LL_USART_HWCONTROL_NONE);
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LL_USART_SetTransferDirection(USART1, LL_USART_DIRECTION_TX_RX);
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LL_USART_EnableIT_RXNE(USART1);
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NVIC_EnableIRQ(USART1_IRQn);
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NVIC_SetPriority(USART1_IRQn, 1);
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LL_USART_Enable(USART1);
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
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LL_GPIO_AF_DisableRemap_USART1();
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LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_9, LL_GPIO_PULL_UP);
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LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_9, LL_GPIO_MODE_ALTERNATE);
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LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_10, LL_GPIO_PULL_UP);
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LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_10, LL_GPIO_MODE_INPUT);
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}
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DECL_INIT(serial_init);
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void __visible
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USART1_IRQHandler(void)
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{
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if (LL_USART_IsActiveFlag_RXNE(USART1) || LL_USART_IsActiveFlag_ORE(USART1)) {
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uint8_t data = LL_USART_ReceiveData8(USART1);
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if (data == MESSAGE_SYNC)
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sched_wake_tasks();
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if (receive_pos >= sizeof(receive_buf))
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// Serial overflow - ignore it as crc error will force retransmit
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return;
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receive_buf[receive_pos++] = data;
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return;
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}
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if (LL_USART_IsActiveFlag_TXE(USART1)) {
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if (transmit_pos >= transmit_max)
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LL_USART_DisableIT_TXE(USART1);
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else
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LL_USART_TransmitData8(USART1, transmit_buf[transmit_pos++]);
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}
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}
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// Enable tx interrupts
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static void
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enable_tx_irq(void)
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{
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LL_USART_EnableIT_TXE(USART1);
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}
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/****************************************************************
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* Console access functions
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****************************************************************/
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// Remove from the receive buffer the given number of bytes
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static void
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console_pop_input(uint32_t len)
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{
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uint32_t copied = 0;
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for (;;) {
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uint32_t rpos = readl(&receive_pos);
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uint32_t needcopy = rpos - len;
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if (needcopy) {
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memmove(&receive_buf[copied], &receive_buf[copied + len]
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, needcopy - copied);
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copied = needcopy;
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sched_wake_tasks();
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}
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irqstatus_t flag = irq_save();
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if (rpos != readl(&receive_pos)) {
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// Raced with irq handler - retry
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irq_restore(flag);
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continue;
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}
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receive_pos = needcopy;
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irq_restore(flag);
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break;
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}
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}
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// Process any incoming commands
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void
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console_task(void)
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{
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uint8_t pop_count;
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uint32_t rpos = readl(&receive_pos);
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int8_t ret = command_find_block(receive_buf, rpos, &pop_count);
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if (ret > 0)
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command_dispatch(receive_buf, pop_count);
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if (ret)
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console_pop_input(pop_count);
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}
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DECL_TASK(console_task);
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// Encode and transmit a "response" message
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void
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console_sendf(const struct command_encoder *ce, va_list args)
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{
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// Verify space for message
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uint32_t tpos = readl(&transmit_pos), tmax = readl(&transmit_max);
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if (tpos >= tmax) {
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tpos = tmax = 0;
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writel(&transmit_max, 0);
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writel(&transmit_pos, 0);
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}
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uint32_t max_size = ce->max_size;
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if (tmax + max_size > sizeof(transmit_buf)) {
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if (tmax + max_size - tpos > sizeof(transmit_buf))
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// Not enough space for message
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return;
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// Disable TX irq and move buffer
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writel(&transmit_max, 0);
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tpos = readl(&transmit_pos);
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tmax -= tpos;
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memmove(&transmit_buf[0], &transmit_buf[tpos], tmax);
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writel(&transmit_pos, 0);
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writel(&transmit_max, tmax);
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enable_tx_irq();
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}
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// Generate message
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char *buf = &transmit_buf[tmax];
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uint32_t msglen = command_encodef(buf, ce, args);
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command_add_frame(buf, msglen);
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// Start message transmit
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writel(&transmit_max, tmax + msglen);
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enable_tx_irq();
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}
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