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Add STM32F103 port

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Add a fully functional STM32F1 port, currently mostly targeting STM32F103
microcontrollers. This requires an 8 MHz XTAL. The maximum possible step rate
is around 282K steps per second.

This uses stm32flash to burn the firmware. The bootloader needs to be started
by setting BOOT0 to 1 and resetting the MCU. There is no automatic bootloader,
unlike on Arduino.

Signed-off-by: Grigori Goronzy <greg@kinoho.net>
This commit is contained in:
Grigori Goronzy 2018-03-31 15:34:59 +02:00 • committed by KevinOConnor
parent e097b08520
commit 75d5737211
173 changed files with 267435 additions and 0 deletions
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28
src/stm32f1/Kconfig Normal file
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# Kconfig settings for STM32F1 processors
if MACH_STM32F1
config STM32F1_SELECT
bool
default y
select HAVE_GPIO
select HAVE_GPIO_ADC
config BOARD_DIRECTORY
string
default "stm32f1"
config CLOCK_FREQ
int
default 8000000 # 72000000 / 9
config SERIAL
bool
default y
config SERIAL_BAUD
depends on SERIAL
int "Baud rate for serial port"
default 250000
endif

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src/stm32f1/Makefile Normal file
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# Additional STM32F1 build rules
# Setup the toolchain
CROSS_PREFIX=arm-none-eabi-
dirs-y += src/stm32f1 src/generic
dirs-y += lib/cmsis-stm32f1/source
dirs-y += lib/hal-stm32f1/source
CFLAGS += -mthumb -mcpu=cortex-m3
CFLAGS += -Ilib/cmsis-stm32f1/include -Ilib/cmsis-stm32f1/cmsis-include
CFLAGS += -Ilib/hal-stm32f1/include
CFLAGS += -DSTM32F103xB
CFLAGS += -O3
CFLAGS_klipper.elf += -Llib/cmsis-stm32f1/source/
CFLAGS_klipper.elf += -Tlib/cmsis-stm32f1/source/stm32f1.ld
CFLAGS_klipper.elf += --specs=nano.specs --specs=nosys.specs
# Extra build rules
$(OUT)%.o: %.s $(OUT)autoconf.h $(OUT)board-link
@echo " Assembling $@"
$(Q)$(AS) $< -o $@
# Add source files
src-y += stm32f1/main.c stm32f1/timer.c stm32f1/gpio.c
src-y += $(addprefix ../, $(wildcard lib/hal-stm32f1/source/stm32f1xx_ll_*.c))
src-y += generic/crc16_ccitt.c generic/armcm_irq.c generic/timer_irq.c
src-y += ../lib/cmsis-stm32f1/source/system_stm32f1xx.c
src-ys = ../lib/cmsis-stm32f1/source/startup_stm32f103xb.s
src-$(CONFIG_SERIAL) += stm32f1/serial.c
# Build the additional hex output file
target-y += $(OUT)klipper.bin
# Add assembler objects to prerequisites list
$(OUT)klipper.elf: $(patsubst %.s, $(OUT)src/%.o,$(src-ys))
$(OUT)klipper.bin: $(OUT)klipper.elf
@echo " Creating hex file $@"
$(Q)$(OBJCOPY) -O binary $< $@
flash: $(OUT)klipper.bin
@echo " Flashing $^ to $(FLASH_DEVICE) via stm32flash"
$(Q)stm32flash -w $(OUT)klipper.bin -v -g 0 $(FLASH_DEVICE)

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src/stm32f1/gpio.c Normal file
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// GPIO functions on STM32F1
//
// Copyright (C) 2018 Grigori Goronzy <greg@kinoho.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include <stdint.h> // uint32_t
#include <stdbool.h>
#include "autoconf.h" // CONFIG_CLOCK_FREQ
#include "command.h" // shutdown
#include "compiler.h" // ARRAY_SIZE
#include "gpio.h" // gpio_out_setup
#include "stm32f1xx.h"
#include "stm32f1xx_ll_gpio.h"
#include "stm32f1xx_ll_adc.h"
#include "sched.h" // sched_shutdown
#include "board/irq.h"
#include "board/io.h"
/****************************************************************
* Pin mappings
****************************************************************/
#define GPIO(PORT, NUM) (((PORT)-'A') * 16 + (NUM))
#define GPIO2PORT(PIN) ((PIN) / 16)
static GPIO_TypeDef *const digital_regs[] = {
GPIOA, GPIOB, GPIOC, GPIOD, GPIOE
};
static uint32_t const digital_pins[] = {
LL_GPIO_PIN_0,
LL_GPIO_PIN_1,
LL_GPIO_PIN_2,
LL_GPIO_PIN_3,
LL_GPIO_PIN_4,
LL_GPIO_PIN_5,
LL_GPIO_PIN_6,
LL_GPIO_PIN_7,
LL_GPIO_PIN_8,
LL_GPIO_PIN_9,
LL_GPIO_PIN_10,
LL_GPIO_PIN_11,
LL_GPIO_PIN_12,
LL_GPIO_PIN_13,
LL_GPIO_PIN_14,
LL_GPIO_PIN_15,
};
/****************************************************************
* General Purpose Input Output (GPIO) pins
****************************************************************/
struct gpio_out
gpio_out_setup(uint8_t pin, uint8_t val)
{
if (GPIO2PORT(pin) >= ARRAY_SIZE(digital_regs))
goto fail;
GPIO_TypeDef *regs = digital_regs[GPIO2PORT(pin)];
uint32_t bit = digital_pins[pin % 16];
irqstatus_t flag = irq_save();
if (val)
LL_GPIO_SetOutputPin(regs, bit);
else
LL_GPIO_ResetOutputPin(regs, bit);
LL_GPIO_SetPinMode(regs, bit, LL_GPIO_MODE_OUTPUT);
irq_restore(flag);
return (struct gpio_out){ .regs = regs, .bit = bit };
fail:
shutdown("Not an output pin");
}
void
gpio_out_toggle(struct gpio_out g)
{
LL_GPIO_TogglePin(g.regs, g.bit);
}
void
gpio_out_write(struct gpio_out g, uint8_t val)
{
if (val)
LL_GPIO_SetOutputPin(g.regs, g.bit);
else
LL_GPIO_ResetOutputPin(g.regs, g.bit);
}
struct gpio_in
gpio_in_setup(uint8_t pin, int8_t pull_up)
{
if (GPIO2PORT(pin) >= ARRAY_SIZE(digital_regs))
goto fail;
GPIO_TypeDef *regs = digital_regs[GPIO2PORT(pin)];
uint32_t bit = digital_pins[pin % 16];
irqstatus_t flag = irq_save();
if (pull_up) {
LL_GPIO_SetPinMode(regs, bit, LL_GPIO_MODE_INPUT);
LL_GPIO_SetPinPull(regs, bit, LL_GPIO_PULL_UP);
} else {
LL_GPIO_SetPinMode(regs, bit, LL_GPIO_MODE_FLOATING);
}
irq_restore(flag);
return (struct gpio_in){ .regs = regs, .bit = bit };
fail:
shutdown("Not an input pin");
}
uint8_t
gpio_in_read(struct gpio_in g)
{
return LL_GPIO_IsInputPinSet(g.regs, g.bit);
}
/****************************************************************
* Analog to Digital Converter (ADC) pins
****************************************************************/
DECL_CONSTANT(ADC_MAX, 4095);
#define ADC_DELAY (240 * 8)
static bool adc_busy;
static uint32_t adc_current_channel;
static const uint8_t adc_pins[] = {
GPIO('A', 0), GPIO('A', 1), GPIO('A', 2), GPIO('A', 3),
GPIO('A', 4), GPIO('A', 5), GPIO('A', 6), GPIO('A', 7),
GPIO('B', 0), GPIO('B', 1), GPIO('C', 0), GPIO('C', 1),
GPIO('C', 2), GPIO('C', 3)
};
static const uint32_t adc_channels[] = {
LL_ADC_CHANNEL_0,
LL_ADC_CHANNEL_1,
LL_ADC_CHANNEL_2,
LL_ADC_CHANNEL_3,
LL_ADC_CHANNEL_4,
LL_ADC_CHANNEL_5,
LL_ADC_CHANNEL_6,
LL_ADC_CHANNEL_7,
LL_ADC_CHANNEL_8,
LL_ADC_CHANNEL_9,
LL_ADC_CHANNEL_10,
LL_ADC_CHANNEL_11,
LL_ADC_CHANNEL_12,
LL_ADC_CHANNEL_13,
LL_ADC_CHANNEL_14,
LL_ADC_CHANNEL_15,
};
struct gpio_adc
gpio_adc_setup(uint8_t pin)
{
// Find pin in adc_pins table
int chan;
for (chan=0; ; chan++) {
if (chan >= ARRAY_SIZE(adc_pins))
shutdown("Not a valid ADC pin");
if (adc_pins[chan] == pin)
break;
}
GPIO_TypeDef *regs = digital_regs[GPIO2PORT(pin)];
uint32_t bit = digital_pins[pin % 16];
LL_GPIO_SetPinMode(regs, bit, LL_GPIO_MODE_ANALOG);
return (struct gpio_adc){ .bit = adc_channels[chan] };
}
// Try to sample a value. Returns zero if sample ready, otherwise
// returns the number of clock ticks the caller should wait before
// retrying this function.
uint32_t
gpio_adc_sample(struct gpio_adc g)
{
/* ADC not busy, start conversion */
if (!readb(&adc_busy)) {
LL_ADC_REG_SetSequencerRanks(ADC1, LL_ADC_REG_RANK_1, g.bit);
LL_ADC_SetChannelSamplingTime(ADC1, g.bit, LL_ADC_SAMPLINGTIME_239CYCLES_5);
LL_ADC_REG_StartConversionSWStart(ADC1);
adc_busy = true;
adc_current_channel = g.bit;
return ADC_DELAY;
/* ADC finished conversion for this channel */
} else if (LL_ADC_IsActiveFlag_EOS(ADC1) &&
readl(&adc_current_channel) == g.bit) {
LL_ADC_ClearFlag_EOS(ADC1);
adc_busy = false;
return 0;
}
/* Wants to sample another channel, or not finished yet */
return ADC_DELAY;
}
// Read a value; use only after gpio_adc_sample() returns zero
uint16_t
gpio_adc_read(struct gpio_adc g)
{
return LL_ADC_REG_ReadConversionData12(ADC1);
}
// Cancel a sample that may have been started with gpio_adc_sample()
void
gpio_adc_cancel_sample(struct gpio_adc g)
{
if (readb(&adc_busy) && readl(&adc_current_channel) == g.bit) {
adc_busy = false;
LL_ADC_ClearFlag_EOS(ADC1);
}
}

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src/stm32f1/gpio.h Normal file
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#ifndef __STM32F1_GPIO_H
#define __STM32F1_GPIO_H
#include <stdint.h>
#include "stm32f1xx.h"
void gpio_peripheral(char bank, uint32_t bit, char ptype, uint32_t pull_up);
struct gpio_out {
GPIO_TypeDef *regs;
uint32_t bit;
};
struct gpio_out gpio_out_setup(uint8_t pin, uint8_t val);
void gpio_out_toggle(struct gpio_out g);
void gpio_out_write(struct gpio_out g, uint8_t val);
struct gpio_in {
GPIO_TypeDef *regs;
uint32_t bit;
};
struct gpio_in gpio_in_setup(uint8_t pin, int8_t pull_up);
uint8_t gpio_in_read(struct gpio_in g);
struct gpio_adc {
uint32_t bit;
};
struct gpio_adc gpio_adc_setup(uint8_t pin);
uint32_t gpio_adc_sample(struct gpio_adc g);
uint16_t gpio_adc_read(struct gpio_adc g);
void gpio_adc_cancel_sample(struct gpio_adc g);
#endif // gpio.h

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// Main starting point for STM32F103 boards.
//
// Copyright (C) 2018 Grigori Goronzy <greg@kinoho.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h"
#include "command.h" // DECL_CONSTANT
#include "stm32f1xx.h"
#include "stm32f1xx_ll_system.h"
#include "stm32f1xx_ll_utils.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_iwdg.h"
#include "stm32f1xx_ll_gpio.h"
#include "stm32f1xx_ll_adc.h"
#include "sched.h" // sched_main
DECL_CONSTANT(MCU, "stm32f103");
/****************************************************************
* dynamic memory pool
****************************************************************/
static char dynmem_pool[15 * 1024];
// Return the start of memory available for dynamic allocations
void *
dynmem_start(void)
{
return dynmem_pool;
}
// Return the end of memory available for dynamic allocations
void *
dynmem_end(void)
{
return &dynmem_pool[sizeof(dynmem_pool)];
}
/****************************************************************
* watchdog handler
****************************************************************/
void
watchdog_reset(void)
{
LL_IWDG_ReloadCounter(IWDG);
}
DECL_TASK(watchdog_reset);
void
watchdog_init(void)
{
LL_IWDG_EnableWriteAccess(IWDG);
/* IWDG timer is 40 KHz, configure to trigger every seconds */
LL_IWDG_SetPrescaler(IWDG, LL_IWDG_PRESCALER_16);
LL_IWDG_SetReloadCounter(IWDG, 2500);
LL_IWDG_Enable(IWDG);
}
DECL_INIT(watchdog_init);
/****************************************************************
* misc functions
****************************************************************/
void
command_reset(uint32_t *args)
{
NVIC_SystemReset();
}
DECL_COMMAND_FLAGS(command_reset, HF_IN_SHUTDOWN, "reset");
void clock_config(void)
{
LL_RCC_HSE_Enable();
while (!LL_RCC_HSE_IsReady());
LL_RCC_PLL_ConfigDomain_SYS(LL_RCC_PLLSOURCE_HSE, LL_RCC_PLL_MUL_9);
LL_RCC_PLL_Disable();
LL_RCC_PLL_Enable();
while (!LL_RCC_PLL_IsReady());
LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1);
LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_2);
LL_RCC_SetAPB2Prescaler(LL_RCC_APB2_DIV_2);
LL_RCC_SetADCClockSource(LL_RCC_ADC_CLKSRC_PCLK2_DIV_4);
LL_FLASH_SetLatency(LL_FLASH_LATENCY_2);
LL_FLASH_EnablePrefetch();
LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
SystemCoreClockUpdate();
LL_Init1msTick(SystemCoreClock);
}
void adc_config(void)
{
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_ADC1);
/* ADC might be in deep sleep, needs to be woken up twice in that case */
LL_ADC_Enable(ADC1);
LL_mDelay(1);
LL_ADC_Enable(ADC1);
LL_mDelay(1);
LL_ADC_StartCalibration(ADC1);
while (LL_ADC_IsCalibrationOnGoing(ADC1));
LL_ADC_SetSequencersScanMode(ADC1, LL_ADC_SEQ_SCAN_DISABLE);
LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_SOFTWARE);
LL_ADC_REG_SetSequencerLength(ADC1, LL_ADC_REG_SEQ_SCAN_DISABLE);
}
void io_config(void)
{
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_AFIO);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOB);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOC);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOD);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOE);
/* JTAG is normally not needed, but blocks ports like PB3, PB4 */
LL_GPIO_AF_Remap_SWJ_NOJTAG();
/* Likewise, we don't need PB3 for TRACESWO output */
LL_DBGMCU_SetTracePinAssignment(LL_DBGMCU_TRACE_NONE);
}
// Main entry point
int
main(void)
{
SystemInit();
LL_Init1msTick(SystemCoreClock);
clock_config();
adc_config();
io_config();
sched_main();
return 0;
}

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// STM32F1 serial port
//
// Copyright (C) 2018 Grigori Goronzy <greg@kinoho.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include <string.h> // memmove
#include "autoconf.h" // CONFIG_SERIAL_BAUD
#include "command.h" // DECL_CONSTANT
#include "stm32f1xx.h" // UART
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_rcc.h"
#include "stm32f1xx_ll_usart.h"
#include "stm32f1xx_ll_gpio.h"
#include "board/irq.h"
#include "board/io.h"
#include "sched.h" // DECL_INIT
#define SERIAL_BUFFER_SIZE 96
static char receive_buf[SERIAL_BUFFER_SIZE];
static uint32_t receive_pos;
static char transmit_buf[SERIAL_BUFFER_SIZE];
static uint32_t transmit_pos, transmit_max;
/****************************************************************
* Serial hardware
****************************************************************/
DECL_CONSTANT(SERIAL_BAUD, CONFIG_SERIAL_BAUD);
void
serial_init(void)
{
const uint32_t pclk = __LL_RCC_CALC_PCLK2_FREQ(SystemCoreClock, LL_RCC_GetAPB2Prescaler());
LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_USART1);
LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_USART1);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_USART1);
LL_USART_SetBaudRate(USART1, pclk, CONFIG_SERIAL_BAUD);
LL_USART_SetDataWidth(USART1, LL_USART_DATAWIDTH_8B);
LL_USART_SetParity(USART1, LL_USART_PARITY_NONE);
LL_USART_SetStopBitsLength(USART1, LL_USART_STOPBITS_1);
LL_USART_SetHWFlowCtrl(USART1, LL_USART_HWCONTROL_NONE);
LL_USART_SetTransferDirection(USART1, LL_USART_DIRECTION_TX_RX);
LL_USART_EnableIT_RXNE(USART1);
NVIC_EnableIRQ(USART1_IRQn);
NVIC_SetPriority(USART1_IRQn, 1);
LL_USART_Enable(USART1);
LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_GPIOA);
LL_GPIO_AF_DisableRemap_USART1();
LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_9, LL_GPIO_PULL_UP);
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_9, LL_GPIO_MODE_ALTERNATE);
LL_GPIO_SetPinPull(GPIOA, LL_GPIO_PIN_10, LL_GPIO_PULL_UP);
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_10, LL_GPIO_MODE_INPUT);
}
DECL_INIT(serial_init);
void __visible
USART1_IRQHandler(void)
{
if (LL_USART_IsActiveFlag_RXNE(USART1) || LL_USART_IsActiveFlag_ORE(USART1)) {
uint8_t data = LL_USART_ReceiveData8(USART1);
if (data == MESSAGE_SYNC)
sched_wake_tasks();
if (receive_pos >= sizeof(receive_buf))
// Serial overflow - ignore it as crc error will force retransmit
return;
receive_buf[receive_pos++] = data;
return;
}
if (LL_USART_IsActiveFlag_TXE(USART1)) {
if (transmit_pos >= transmit_max)
LL_USART_DisableIT_TXE(USART1);
else
LL_USART_TransmitData8(USART1, transmit_buf[transmit_pos++]);
}
}
// Enable tx interrupts
static void
enable_tx_irq(void)
{
LL_USART_EnableIT_TXE(USART1);
}
/****************************************************************
* Console access functions
****************************************************************/
// Remove from the receive buffer the given number of bytes
static void
console_pop_input(uint32_t len)
{
uint32_t copied = 0;
for (;;) {
uint32_t rpos = readl(&receive_pos);
uint32_t needcopy = rpos - len;
if (needcopy) {
memmove(&receive_buf[copied], &receive_buf[copied + len]
, needcopy - copied);
copied = needcopy;
sched_wake_tasks();
}
irqstatus_t flag = irq_save();
if (rpos != readl(&receive_pos)) {
// Raced with irq handler - retry
irq_restore(flag);
continue;
}
receive_pos = needcopy;
irq_restore(flag);
break;
}
}
// Process any incoming commands
void
console_task(void)
{
uint8_t pop_count;
uint32_t rpos = readl(&receive_pos);
int8_t ret = command_find_block(receive_buf, rpos, &pop_count);
if (ret > 0)
command_dispatch(receive_buf, pop_count);
if (ret)
console_pop_input(pop_count);
}
DECL_TASK(console_task);
// Encode and transmit a "response" message
void
console_sendf(const struct command_encoder *ce, va_list args)
{
// Verify space for message
uint32_t tpos = readl(&transmit_pos), tmax = readl(&transmit_max);
if (tpos >= tmax) {
tpos = tmax = 0;
writel(&transmit_max, 0);
writel(&transmit_pos, 0);
}
uint32_t max_size = ce->max_size;
if (tmax + max_size > sizeof(transmit_buf)) {
if (tmax + max_size - tpos > sizeof(transmit_buf))
// Not enough space for message
return;
// Disable TX irq and move buffer
writel(&transmit_max, 0);
tpos = readl(&transmit_pos);
tmax -= tpos;
memmove(&transmit_buf[0], &transmit_buf[tpos], tmax);
writel(&transmit_pos, 0);
writel(&transmit_max, tmax);
enable_tx_irq();
}
// Generate message
char *buf = &transmit_buf[tmax];
uint32_t msglen = command_encodef(buf, ce, args);
command_add_frame(buf, msglen);
// Start message transmit
writel(&transmit_max, tmax + msglen);
enable_tx_irq();
}

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// STM32F1 timer interrupt scheduling code.
//
// Copyright (C) 2018 Grigori Goronzy <greg@kinoho.net>
//
// This file may be distributed under the terms of the GNU GPLv3 license.
#include "autoconf.h"
#include "board/misc.h" // timer_from_us
#include "stm32f1xx.h"
#include "stm32f1xx.h"
#include "stm32f1xx_ll_bus.h"
#include "stm32f1xx_ll_tim.h"
#include "command.h" // shutdown
#include "board/irq.h" // irq_save
#include "sched.h" // sched_timer_dispatch
/****************************************************************
* Low level timer code
****************************************************************/
DECL_CONSTANT(CLOCK_FREQ, CONFIG_CLOCK_FREQ);
union u32_u {
struct { uint8_t b0, b1, b2, b3; };
struct { uint16_t lo, hi; };
uint32_t val;
};
static inline uint16_t
timer_get(void)
{
return LL_TIM_GetCounter(TIM2);
}
static inline void
timer_set(uint16_t next)
{
LL_TIM_OC_SetCompareCH1(TIM2, next);
}
static inline void
timer_repeat_set(uint16_t next)
{
LL_TIM_OC_SetCompareCH2(TIM2, next);
LL_TIM_ClearFlag_CC2(TIM2);
}
// Activate timer dispatch as soon as possible
void
timer_kick(void)
{
timer_set(timer_get() + 50);
LL_TIM_ClearFlag_CC1(TIM2);
}
static struct timer wrap_timer;
void
timer_reset(void)
{
sched_add_timer(&wrap_timer);
}
DECL_SHUTDOWN(timer_reset);
void
timer_init(void)
{
irqstatus_t flag = irq_save();
LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_TIM2);
LL_TIM_SetPrescaler(TIM2, __LL_TIM_CALC_PSC(SystemCoreClock, CONFIG_CLOCK_FREQ));
LL_TIM_SetCounter(TIM2, 0);
LL_TIM_SetAutoReload(TIM2, 0xFFFF);
LL_TIM_EnableIT_CC1(TIM2);
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH1);
LL_TIM_CC_EnableChannel(TIM2, LL_TIM_CHANNEL_CH2);
NVIC_EnableIRQ(TIM2_IRQn);
NVIC_SetPriority(TIM2_IRQn, 0);
timer_kick();
timer_repeat_set(timer_get() + 50);
timer_reset();
LL_TIM_EnableCounter(TIM2);
irq_restore(flag);
}
DECL_INIT(timer_init);
/****************************************************************
* 32bit timer wrappers
****************************************************************/
static uint16_t timer_high;
// Return the current time (in absolute clock ticks).
uint32_t
timer_read_time(void)
{
irqstatus_t flag = irq_save();
union u32_u calc = { .val = timer_get() };
calc.hi = timer_high;
if (unlikely(LL_TIM_IsActiveFlag_UPDATE(TIM2))) {
irq_restore(flag);
if (calc.b1 < 0xff)
calc.hi++;
return calc.val;
}
irq_restore(flag);
return calc.val;
}
// Timer that runs every cycle - allows 16bit comparison optimizations
static uint_fast8_t
timer_event(struct timer *t)
{
union u32_u *nextwake = (void*)&wrap_timer.waketime;
if (LL_TIM_IsActiveFlag_UPDATE(TIM2)) {
// Hardware timer has overflowed - update overflow counter
LL_TIM_ClearFlag_UPDATE(TIM2);
timer_high++;
*nextwake = (union u32_u){ .hi = timer_high, .lo = 0x8000 };
} else {
*nextwake = (union u32_u){ .hi = timer_high + 1, .lo = 0x0000 };
}
return SF_RESCHEDULE;
}
static struct timer wrap_timer = {
.func = timer_event,
.waketime = 0x8000,
};
#define TIMER_IDLE_REPEAT_TICKS timer_from_us(500)
#define TIMER_REPEAT_TICKS timer_from_us(100)
#define TIMER_MIN_TRY_TICKS timer_from_us(1)
#define TIMER_DEFER_REPEAT_TICKS timer_from_us(5)
// Hardware timer IRQ handler - dispatch software timers
void __visible __aligned(16)
TIM2_IRQHandler(void)
{
irq_disable();
LL_TIM_ClearFlag_CC1(TIM2);
uint16_t next;
for (;;) {
// Run the next software timer
next = sched_timer_dispatch();
for (;;) {
int16_t diff = timer_get() - next;
if (likely(diff >= 0)) {
// Another timer is pending - briefly allow irqs and then run it
irq_enable();
if (unlikely(LL_TIM_IsActiveFlag_CC2(TIM2)))
goto check_defer;
irq_disable();
break;
}
if (likely(diff <= -TIMER_MIN_TRY_TICKS))
// Schedule next timer normally
goto done;
irq_enable();
if (unlikely(LL_TIM_IsActiveFlag_CC2(TIM2)))
goto check_defer;
irq_disable();
continue;
check_defer:
// Check if there are too many repeat timers
irq_disable();
uint16_t now = timer_get();
if ((int16_t)(next - now) < (int16_t)(-timer_from_us(1000)))
try_shutdown("Rescheduled timer in the past");
if (sched_tasks_busy()) {
timer_repeat_set(now + TIMER_REPEAT_TICKS);
next = now + TIMER_DEFER_REPEAT_TICKS;
goto done;
}
timer_repeat_set(now + TIMER_IDLE_REPEAT_TICKS);
timer_set(now);
}
}
done:
timer_set(next);
irq_enable();
}