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Add STM32F103 port
Add a fully functional STM32F1 port, currently mostly targeting STM32F103 microcontrollers. This requires an 8 MHz XTAL. The maximum possible step rate is around 282K steps per second. This uses stm32flash to burn the firmware. The bootloader needs to be started by setting BOOT0 to 1 and resetting the MCU. There is no automatic bootloader, unlike on Arduino. Signed-off-by: Grigori Goronzy <greg@kinoho.net>
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Grigori Goronzy
KevinOConnor
parent
e097b08520
commit
75d5737211
173 changed files with 267435 additions and 0 deletions
331
lib/hal-stm32f1/source/stm32f1xx_ll_dma.c
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331
lib/hal-stm32f1/source/stm32f1xx_ll_dma.c
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/**
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******************************************************************************
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* @file stm32f1xx_ll_dma.c
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* @author MCD Application Team
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* @version V1.1.1
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* @date 12-May-2017
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* @brief DMA LL module driver.
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of STMicroelectronics nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#if defined(USE_FULL_LL_DRIVER)
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/* Includes ------------------------------------------------------------------*/
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#include "stm32f1xx_ll_dma.h"
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#include "stm32f1xx_ll_bus.h"
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#ifdef USE_FULL_ASSERT
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#include "stm32_assert.h"
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#else
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#define assert_param(expr) ((void)0U)
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#endif
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/** @addtogroup STM32F1xx_LL_Driver
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* @{
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*/
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#if defined (DMA1) || defined (DMA2)
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/** @defgroup DMA_LL DMA
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/** @addtogroup DMA_LL_Private_Macros
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* @{
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*/
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#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
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((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
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#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
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((__VALUE__) == LL_DMA_MODE_CIRCULAR))
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#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
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((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
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#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
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((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
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#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
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#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
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((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
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#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
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#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
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((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
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((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
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((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
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#if defined (DMA2)
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#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
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(((CHANNEL) == LL_DMA_CHANNEL_1) || \
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((CHANNEL) == LL_DMA_CHANNEL_2) || \
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((CHANNEL) == LL_DMA_CHANNEL_3) || \
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((CHANNEL) == LL_DMA_CHANNEL_4) || \
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((CHANNEL) == LL_DMA_CHANNEL_5) || \
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((CHANNEL) == LL_DMA_CHANNEL_6) || \
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((CHANNEL) == LL_DMA_CHANNEL_7))) || \
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(((INSTANCE) == DMA2) && \
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(((CHANNEL) == LL_DMA_CHANNEL_1) || \
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((CHANNEL) == LL_DMA_CHANNEL_2) || \
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((CHANNEL) == LL_DMA_CHANNEL_3) || \
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((CHANNEL) == LL_DMA_CHANNEL_4) || \
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((CHANNEL) == LL_DMA_CHANNEL_5))))
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#else
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#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \
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(((CHANNEL) == LL_DMA_CHANNEL_1) || \
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((CHANNEL) == LL_DMA_CHANNEL_2) || \
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((CHANNEL) == LL_DMA_CHANNEL_3) || \
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((CHANNEL) == LL_DMA_CHANNEL_4) || \
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((CHANNEL) == LL_DMA_CHANNEL_5) || \
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((CHANNEL) == LL_DMA_CHANNEL_6) || \
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((CHANNEL) == LL_DMA_CHANNEL_7))))
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#endif
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/**
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* @}
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*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup DMA_LL_Exported_Functions
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* @{
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*/
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/** @addtogroup DMA_LL_EF_Init
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* @{
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*/
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/**
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* @brief De-initialize the DMA registers to their default reset values.
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* @param DMAx DMAx Instance
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* @param Channel This parameter can be one of the following values:
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* @arg @ref LL_DMA_CHANNEL_1
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* @arg @ref LL_DMA_CHANNEL_2
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* @arg @ref LL_DMA_CHANNEL_3
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* @arg @ref LL_DMA_CHANNEL_4
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* @arg @ref LL_DMA_CHANNEL_5
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* @arg @ref LL_DMA_CHANNEL_6
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* @arg @ref LL_DMA_CHANNEL_7
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: DMA registers are de-initialized
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* - ERROR: DMA registers are not de-initialized
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*/
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uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel)
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{
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DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1;
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ErrorStatus status = SUCCESS;
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/* Check the DMA Instance DMAx and Channel parameters*/
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assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
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tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel));
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/* Disable the selected DMAx_Channely */
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CLEAR_BIT(tmp->CCR, DMA_CCR_EN);
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/* Reset DMAx_Channely control register */
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LL_DMA_WriteReg(tmp, CCR, 0U);
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/* Reset DMAx_Channely remaining bytes register */
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LL_DMA_WriteReg(tmp, CNDTR, 0U);
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/* Reset DMAx_Channely peripheral address register */
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LL_DMA_WriteReg(tmp, CPAR, 0U);
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/* Reset DMAx_Channely memory address register */
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LL_DMA_WriteReg(tmp, CMAR, 0U);
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if (Channel == LL_DMA_CHANNEL_1)
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{
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/* Reset interrupt pending bits for DMAx Channel1 */
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LL_DMA_ClearFlag_GI1(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_2)
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{
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/* Reset interrupt pending bits for DMAx Channel2 */
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LL_DMA_ClearFlag_GI2(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_3)
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{
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/* Reset interrupt pending bits for DMAx Channel3 */
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LL_DMA_ClearFlag_GI3(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_4)
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{
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/* Reset interrupt pending bits for DMAx Channel4 */
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LL_DMA_ClearFlag_GI4(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_5)
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{
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/* Reset interrupt pending bits for DMAx Channel5 */
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LL_DMA_ClearFlag_GI5(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_6)
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{
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/* Reset interrupt pending bits for DMAx Channel6 */
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LL_DMA_ClearFlag_GI6(DMAx);
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}
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else if (Channel == LL_DMA_CHANNEL_7)
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{
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/* Reset interrupt pending bits for DMAx Channel7 */
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LL_DMA_ClearFlag_GI7(DMAx);
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}
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else
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{
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status = ERROR;
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}
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return status;
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}
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/**
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* @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
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* @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros :
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* @arg @ref __LL_DMA_GET_INSTANCE
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* @arg @ref __LL_DMA_GET_CHANNEL
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* @param DMAx DMAx Instance
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* @param Channel This parameter can be one of the following values:
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* @arg @ref LL_DMA_CHANNEL_1
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* @arg @ref LL_DMA_CHANNEL_2
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* @arg @ref LL_DMA_CHANNEL_3
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* @arg @ref LL_DMA_CHANNEL_4
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* @arg @ref LL_DMA_CHANNEL_5
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* @arg @ref LL_DMA_CHANNEL_6
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* @arg @ref LL_DMA_CHANNEL_7
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* @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
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* @retval An ErrorStatus enumeration value:
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* - SUCCESS: DMA registers are initialized
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* - ERROR: Not applicable
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*/
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uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct)
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{
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/* Check the DMA Instance DMAx and Channel parameters*/
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assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel));
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/* Check the DMA parameters from DMA_InitStruct */
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assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
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assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
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assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
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assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
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assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
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assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
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assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
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assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
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/*---------------------------- DMAx CCR Configuration ------------------------
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* Configure DMAx_Channely: data transfer direction, data transfer mode,
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* peripheral and memory increment mode,
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* data size alignment and priority level with parameters :
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* - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits
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* - Mode: DMA_CCR_CIRC bit
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* - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit
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* - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit
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* - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits
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* - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits
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* - Priority: DMA_CCR_PL[1:0] bits
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*/
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LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \
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DMA_InitStruct->Mode | \
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DMA_InitStruct->PeriphOrM2MSrcIncMode | \
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DMA_InitStruct->MemoryOrM2MDstIncMode | \
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DMA_InitStruct->PeriphOrM2MSrcDataSize | \
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DMA_InitStruct->MemoryOrM2MDstDataSize | \
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DMA_InitStruct->Priority);
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/*-------------------------- DMAx CMAR Configuration -------------------------
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* Configure the memory or destination base address with parameter :
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* - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits
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*/
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LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress);
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/*-------------------------- DMAx CPAR Configuration -------------------------
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* Configure the peripheral or source base address with parameter :
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* - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits
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*/
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LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress);
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/*--------------------------- DMAx CNDTR Configuration -----------------------
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* Configure the peripheral base address with parameter :
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* - NbData: DMA_CNDTR_NDT[15:0] bits
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*/
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LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData);
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return SUCCESS;
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}
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/**
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* @brief Set each @ref LL_DMA_InitTypeDef field to default value.
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* @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
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* @retval None
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*/
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void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
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{
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/* Set DMA_InitStruct fields to default values */
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DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
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DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
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DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
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DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
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DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
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DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
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DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
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DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
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DMA_InitStruct->NbData = 0x00000000U;
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DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* DMA1 || DMA2 */
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/**
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* @}
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*/
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#endif /* USE_FULL_LL_DRIVER */
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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