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https://github.com/Klipper3d/klipper.git
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lib: update lib/stm32h7 to v1.9.0 for stm32h723
Signed-off-by: Chen.BJ from BigTreeTech chenbj@biqu3d.com
This commit is contained in:
bigtreetech
Kevin O'Connor
parent
c5d56f4438
commit
50b2e2e67e
23 changed files with 149374 additions and 401 deletions
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@ -667,7 +667,7 @@ typedef struct
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__IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
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__IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
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__IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
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uint32_t RESERVED0; /*!< Reserved, 0x68 */
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uint32_t RESERVED0; /*!< Reserved, 0x6C */
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__IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
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__IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
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}MDMA_Channel_TypeDef;
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@ -930,6 +930,15 @@ __IO uint32_t C2PR3; /*!< EXTI Pending register,
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}EXTI_TypeDef;
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/**
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* @brief This structure registers corresponds to EXTI_Typdef CPU1/CPU2 registers subset (IMRx, EMRx and PRx), allowing to define EXTI_D1/EXTI_D2
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* with rapid/common access to these IMRx, EMRx, PRx registers for CPU1 and CPU2.
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* Note that EXTI_D1 and EXTI_D2 bases addresses are calculated to point to CPUx first register:
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* IMR1 in case of EXTI_D1 that is addressing CPU1 (Coretx-M7)
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* C2IMR1 in case of EXTI_D2 that is addressing CPU2 (Coretx-M4)
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* Note: EXTI_D2 and corresponding C2IMRx, C2EMRx and C2PRx registers are available for Dual Core devices only
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*/
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typedef struct
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{
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__IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
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@ -1803,7 +1812,7 @@ typedef struct
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{
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__IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
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__IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
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__IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
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__IO uint32_t MICR; /*!< HRTIM Master Timer interrupt clear register, Address offset: 0x08 */
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__IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
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__IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
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__IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
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@ -2108,6 +2117,94 @@ typedef struct
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*/
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/**
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* @brief Global Programmer View
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*/
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typedef struct
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{
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uint32_t RESERVED0[2036]; /*!< Reserved, Address offset: 0x00-0x1FCC */
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__IO uint32_t AXI_PERIPH_ID_4; /*!< AXI interconnect - peripheral ID4 register, Address offset: 0x1FD0 */
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uint32_t AXI_PERIPH_ID_5; /*!< Reserved, Address offset: 0x1FD4 */
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uint32_t AXI_PERIPH_ID_6; /*!< Reserved, Address offset: 0x1FD8 */
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uint32_t AXI_PERIPH_ID_7; /*!< Reserved, Address offset: 0x1FDC */
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__IO uint32_t AXI_PERIPH_ID_0; /*!< AXI interconnect - peripheral ID0 register, Address offset: 0x1FE0 */
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__IO uint32_t AXI_PERIPH_ID_1; /*!< AXI interconnect - peripheral ID1 register, Address offset: 0x1FE4 */
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__IO uint32_t AXI_PERIPH_ID_2; /*!< AXI interconnect - peripheral ID2 register, Address offset: 0x1FE8 */
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__IO uint32_t AXI_PERIPH_ID_3; /*!< AXI interconnect - peripheral ID3 register, Address offset: 0x1FEC */
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__IO uint32_t AXI_COMP_ID_0; /*!< AXI interconnect - component ID0 register, Address offset: 0x1FF0 */
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__IO uint32_t AXI_COMP_ID_1; /*!< AXI interconnect - component ID1 register, Address offset: 0x1FF4 */
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__IO uint32_t AXI_COMP_ID_2; /*!< AXI interconnect - component ID2 register, Address offset: 0x1FF8 */
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__IO uint32_t AXI_COMP_ID_3; /*!< AXI interconnect - component ID3 register, Address offset: 0x1FFC */
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uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x2000-0x2004 */
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__IO uint32_t AXI_TARG1_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 1 bus matrix issuing functionality register, Address offset: 0x2008 */
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uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x200C-0x2020 */
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__IO uint32_t AXI_TARG1_FN_MOD2; /*!< AXI interconnect - TARG 1 bus matrix functionality 2 register, Address offset: 0x2024 */
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uint32_t RESERVED3; /*!< Reserved, Address offset: 0x2028 */
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__IO uint32_t AXI_TARG1_FN_MOD_LB; /*!< AXI interconnect - TARG 1 long burst functionality modification register, Address offset: 0x202C */
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uint32_t RESERVED4[54]; /*!< Reserved, Address offset: 0x2030-0x2104 */
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__IO uint32_t AXI_TARG1_FN_MOD; /*!< AXI interconnect - TARG 1 issuing functionality modification register, Address offset: 0x2108 */
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uint32_t RESERVED5[959]; /*!< Reserved, Address offset: 0x210C-0x3004 */
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__IO uint32_t AXI_TARG2_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 2 bus matrix issuing functionality register, Address offset: 0x3008 */
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uint32_t RESERVED6[6]; /*!< Reserved, Address offset: 0x300C-0x3020 */
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__IO uint32_t AXI_TARG2_FN_MOD2; /*!< AXI interconnect - TARG 2 bus matrix functionality 2 register, Address offset: 0x3024 */
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uint32_t RESERVED7; /*!< Reserved, Address offset: 0x3028 */
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__IO uint32_t AXI_TARG2_FN_MOD_LB; /*!< AXI interconnect - TARG 2 long burst functionality modification register, Address offset: 0x302C */
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uint32_t RESERVED8[54]; /*!< Reserved, Address offset: 0x3030-0x3104 */
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__IO uint32_t AXI_TARG2_FN_MOD; /*!< AXI interconnect - TARG 2 issuing functionality modification register, Address offset: 0x3108 */
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uint32_t RESERVED9[959]; /*!< Reserved, Address offset: 0x310C-0x4004 */
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__IO uint32_t AXI_TARG3_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 3 bus matrix issuing functionality register, Address offset: 0x4008 */
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uint32_t RESERVED10[1023]; /*!< Reserved, Address offset: 0x400C-0x5004 */
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__IO uint32_t AXI_TARG4_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 4 bus matrix issuing functionality register, Address offset: 0x5008 */
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uint32_t RESERVED11[1023]; /*!< Reserved, Address offset: 0x500C-0x6004 */
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__IO uint32_t AXI_TARG5_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 5 bus matrix issuing functionality register, Address offset: 0x6008 */
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uint32_t RESERVED12[1023]; /*!< Reserved, Address offset: 0x600C-0x7004 */
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__IO uint32_t AXI_TARG6_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 6 bus matrix issuing functionality register, Address offset: 0x7008 */
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uint32_t RESERVED13[1023]; /*!< Reserved, Address offset: 0x700C-0x8004 */
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__IO uint32_t AXI_TARG7_FN_MOD_ISS_BM; /*!< AXI interconnect - TARG 7 bus matrix issuing functionality register, Address offset: 0x8008 */
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uint32_t RESERVED14[6]; /*!< Reserved, Address offset: 0x800C-0x8020 */
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__IO uint32_t AXI_TARG7_FN_MOD2; /*!< AXI interconnect - TARG 7 bus matrix functionality 2 register, Address offset: 0x8024 */
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uint32_t RESERVED15; /*!< Reserved, Address offset: 0x8028 */
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__IO uint32_t AXI_TARG7_FN_MOD_LB; /*!< AXI interconnect - TARG 7 long burst functionality modification register, Address offset: 0x802C */
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uint32_t RESERVED16[54]; /*!< Reserved, Address offset: 0x8030-0x8104 */
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__IO uint32_t AXI_TARG7_FN_MOD; /*!< AXI interconnect - TARG 7 issuing functionality modification register, Address offset: 0x8108 */
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uint32_t RESERVED17[59334]; /*!< Reserved, Address offset: 0x810C-0x42020 */
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__IO uint32_t AXI_INI1_FN_MOD2; /*!< AXI interconnect - INI 1 functionality modification 2 register, Address offset: 0x42024 */
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__IO uint32_t AXI_INI1_FN_MOD_AHB; /*!< AXI interconnect - INI 1 AHB functionality modification register, Address offset: 0x42028 */
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uint32_t RESERVED18[53]; /*!< Reserved, Address offset: 0x4202C-0x420FC */
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__IO uint32_t AXI_INI1_READ_QOS; /*!< AXI interconnect - INI 1 read QoS register, Address offset: 0x42100 */
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__IO uint32_t AXI_INI1_WRITE_QOS; /*!< AXI interconnect - INI 1 write QoS register, Address offset: 0x42104 */
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__IO uint32_t AXI_INI1_FN_MOD; /*!< AXI interconnect - INI 1 issuing functionality modification register, Address offset: 0x42108 */
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uint32_t RESERVED19[1021]; /*!< Reserved, Address offset: 0x4210C-0x430FC */
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__IO uint32_t AXI_INI2_READ_QOS; /*!< AXI interconnect - INI 2 read QoS register, Address offset: 0x43100 */
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__IO uint32_t AXI_INI2_WRITE_QOS; /*!< AXI interconnect - INI 2 write QoS register, Address offset: 0x43104 */
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__IO uint32_t AXI_INI2_FN_MOD; /*!< AXI interconnect - INI 2 issuing functionality modification register, Address offset: 0x43108 */
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uint32_t RESERVED20[966]; /*!< Reserved, Address offset: 0x4310C-0x44020 */
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__IO uint32_t AXI_INI3_FN_MOD2; /*!< AXI interconnect - INI 3 functionality modification 2 register, Address offset: 0x44024 */
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__IO uint32_t AXI_INI3_FN_MOD_AHB; /*!< AXI interconnect - INI 3 AHB functionality modification register, Address offset: 0x44028 */
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uint32_t RESERVED21[53]; /*!< Reserved, Address offset: 0x4402C-0x440FC */
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__IO uint32_t AXI_INI3_READ_QOS; /*!< AXI interconnect - INI 3 read QoS register, Address offset: 0x44100 */
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__IO uint32_t AXI_INI3_WRITE_QOS; /*!< AXI interconnect - INI 3 write QoS register, Address offset: 0x44104 */
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__IO uint32_t AXI_INI3_FN_MOD; /*!< AXI interconnect - INI 3 issuing functionality modification register, Address offset: 0x44108 */
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uint32_t RESERVED22[1021]; /*!< Reserved, Address offset: 0x4410C-0x450FC */
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__IO uint32_t AXI_INI4_READ_QOS; /*!< AXI interconnect - INI 4 read QoS register, Address offset: 0x45100 */
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__IO uint32_t AXI_INI4_WRITE_QOS; /*!< AXI interconnect - INI 4 write QoS register, Address offset: 0x45104 */
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__IO uint32_t AXI_INI4_FN_MOD; /*!< AXI interconnect - INI 4 issuing functionality modification register, Address offset: 0x45108 */
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uint32_t RESERVED23[1021]; /*!< Reserved, Address offset: 0x4510C-0x460FC */
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__IO uint32_t AXI_INI5_READ_QOS; /*!< AXI interconnect - INI 5 read QoS register, Address offset: 0x46100 */
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__IO uint32_t AXI_INI5_WRITE_QOS; /*!< AXI interconnect - INI 5 write QoS register, Address offset: 0x46104 */
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__IO uint32_t AXI_INI5_FN_MOD; /*!< AXI interconnect - INI 5 issuing functionality modification register, Address offset: 0x46108 */
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uint32_t RESERVED24[1021]; /*!< Reserved, Address offset: 0x4610C-0x470FC */
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__IO uint32_t AXI_INI6_READ_QOS; /*!< AXI interconnect - INI 6 read QoS register, Address offset: 0x47100 */
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__IO uint32_t AXI_INI6_WRITE_QOS; /*!< AXI interconnect - INI 6 write QoS register, Address offset: 0x47104 */
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__IO uint32_t AXI_INI6_FN_MOD; /*!< AXI interconnect - INI 6 issuing functionality modification register, Address offset: 0x47108 */
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uint32_t RESERVED25[1021]; /*!< Reserved, Address offset: 0x4710C-0x480FC */
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__IO uint32_t AXI_INI7_READ_QOS; /*!< AXI interconnect - INI 7 read QoS register, Address offset: 0x48100 */
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__IO uint32_t AXI_INI7_WRITE_QOS; /*!< AXI interconnect - INI 7 write QoS register, Address offset: 0x48104 */
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__IO uint32_t AXI_INI7_FN_MOD; /*!< AXI interconnect - INI 7 issuing functionality modification register, Address offset: 0x48108 */
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} GPV_TypeDef;
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/** @addtogroup Peripheral_memory_map
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* @{
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*/
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@ -2470,6 +2567,9 @@ typedef struct
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#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
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#define GPV_BASE (PERIPH_BASE + 0x11000000UL) /*!< GPV_BASE (PERIPH_BASE + 0x11000000UL) */
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/**
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* @}
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*/
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@ -2773,6 +2873,8 @@ typedef struct
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#define USB_OTG_FS USB2_OTG_FS
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#define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
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#define GPV ((GPV_TypeDef *) GPV_BASE)
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/**
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* @}
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*/
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@ -3245,7 +3347,7 @@ typedef struct
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/******************** Bit definition for ADC_SQR1 register ********************/
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#define ADC_SQR1_L_Pos (0U)
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#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
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#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
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#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */
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#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
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#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
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#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
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@ -4138,7 +4240,7 @@ typedef struct
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/***************** Bit definition for FDCAN_ENDN register *******************/
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#define FDCAN_ENDN_ETV_Pos (0U)
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#define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
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#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
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#define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endianness Test Value */
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/***************** Bit definition for FDCAN_DBTP register *******************/
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#define FDCAN_DBTP_DSJW_Pos (0U)
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@ -4265,7 +4367,7 @@ typedef struct
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/***************** Bit definition for FDCAN_ECR register *********************/
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#define FDCAN_ECR_TEC_Pos (0U)
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#define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
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#define FDCAN_ECR_TEC_Msk (0xFFUL << FDCAN_ECR_TEC_Pos) /*!< 0x000000FF */
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#define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
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#define FDCAN_ECR_REC_Pos (8U)
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#define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
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@ -10848,8 +10950,11 @@ typedef struct
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/*
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* @brief FLASH Global Defines
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*/
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#define FLASH_SIZE_DATA_REGISTER 0x1FF1E880U
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#define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
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#define FLASH_SIZE 0x200000UL /* 2 MB */
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#define FLASH_SIZE ((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0xFFFFU)) ? 0x200000U : \
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((((*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) == 0x0000U)) ? 0x200000U : \
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(((uint32_t)(*((uint16_t *)FLASH_SIZE_DATA_REGISTER)) & (0x0FFFU)) << 10U))) /* 2 MB */
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#define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
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#define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
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#define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
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@ -11221,7 +11326,7 @@ typedef struct
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/****************** Bit definition for FMC_BCR1 register *******************/
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#define FMC_BCR1_CCLKEN_Pos (20U)
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#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
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#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
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#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continuous clock enable */
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#define FMC_BCR1_WFDIS_Pos (21U)
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#define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
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#define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
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@ -11701,7 +11806,7 @@ typedef struct
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#define FMC_SDRTR_REIE_Pos (14U)
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#define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
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#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
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#define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interrupt enable */
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/****************** Bit definition for FMC_SDSR register ******************/
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#define FMC_SDSR_RE_Pos (0U)
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@ -13948,7 +14053,7 @@ typedef struct
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#define LTDC_AWCR_AAH_Pos (0U)
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#define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
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#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
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#define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active height */
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#define LTDC_AWCR_AAW_Pos (16U)
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#define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
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#define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
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@ -13957,7 +14062,7 @@ typedef struct
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#define LTDC_TWCR_TOTALH_Pos (0U)
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#define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
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#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
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#define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total height */
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#define LTDC_TWCR_TOTALW_Pos (16U)
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#define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
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#define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
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@ -14276,7 +14381,7 @@ typedef struct
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#define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
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#define MDMA_CISR_CRQA_Pos (16U)
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#define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
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#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
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#define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x request Active flag */
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/******************** Bit definition for MDMA_CxIFCR register ****************/
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#define MDMA_CIFCR_CTEIF_Pos (0U)
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@ -14341,13 +14446,13 @@ typedef struct
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#define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
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#define MDMA_CCR_BEX_Pos (12U)
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#define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
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#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
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#define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianness eXchange */
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#define MDMA_CCR_HEX_Pos (13U)
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#define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
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#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
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#define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianness eXchange */
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#define MDMA_CCR_WEX_Pos (14U)
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#define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
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#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
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#define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianness eXchange */
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#define MDMA_CCR_SWRQ_Pos (16U)
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#define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
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#define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
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@ -14403,7 +14508,7 @@ typedef struct
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#define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
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#define MDMA_CTCR_PAM_Pos (26U)
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#define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
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#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
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||||
#define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignment Mode */
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||||
#define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
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||||
#define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
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#define MDMA_CTCR_TRGM_Pos (28U)
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|
|
@ -19309,7 +19414,7 @@ typedef struct
|
|||
#define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
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||||
#define QUADSPI_CR_DMAEN_Pos (2U)
|
||||
#define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
|
||||
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
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||||
#define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< Reserved: needed for softawre compatibility (DMA Enable) */
|
||||
#define QUADSPI_CR_TCEN_Pos (3U)
|
||||
#define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
|
||||
#define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
|
||||
|
|
@ -21877,7 +21982,7 @@ typedef struct
|
|||
/******************* Bit definition for SWPMI_RDR register ********************/
|
||||
#define SWPMI_RDR_RD_Pos (0U)
|
||||
#define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
|
||||
#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
|
||||
#define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Receive Data Register */
|
||||
|
||||
|
||||
/******************* Bit definition for SWPMI_OR register ********************/
|
||||
|
|
@ -21973,12 +22078,6 @@ typedef struct
|
|||
#define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
|
||||
#define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
|
||||
#define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
|
||||
#define DBGMCU_CR_DBG_STOPD3_Pos (7U)
|
||||
#define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
|
||||
#define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
|
||||
#define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
|
||||
#define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
|
||||
#define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
|
||||
#define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
|
||||
#define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
|
||||
#define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
|
||||
|
|
@ -23943,7 +24042,7 @@ typedef struct
|
|||
/**** Bit definition for Common HRTIM Timer Burst mode control register ********/
|
||||
#define HRTIM_BMCR_BME_Pos (0U)
|
||||
#define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
|
||||
#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
|
||||
#define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enable */
|
||||
#define HRTIM_BMCR_BMOM_Pos (1U)
|
||||
#define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
|
||||
#define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
|
||||
|
|
@ -26691,14 +26790,16 @@ typedef struct
|
|||
((INSTANCE) == I2C2) || \
|
||||
((INSTANCE) == I2C3) || \
|
||||
((INSTANCE) == I2C4))
|
||||
/************** I2C Instances : wakeup capability from stop modes *************/
|
||||
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
|
||||
|
||||
/****************************** SMBUS Instances *******************************/
|
||||
#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
|
||||
((INSTANCE) == I2C2) || \
|
||||
((INSTANCE) == I2C3) || \
|
||||
((INSTANCE) == I2C4))
|
||||
|
||||
/************** I2C Instances : wakeup capability from stop modes *************/
|
||||
#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
|
||||
|
||||
/******************************** I2S Instances *******************************/
|
||||
#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
||||
((INSTANCE) == SPI2) || \
|
||||
|
|
@ -26717,9 +26818,6 @@ typedef struct
|
|||
#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
|
||||
((_INSTANCE_) == SDMMC2))
|
||||
|
||||
/******************************** SMBUS Instances *****************************/
|
||||
#define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
|
||||
|
||||
/******************************** SPI Instances *******************************/
|
||||
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
|
||||
((INSTANCE) == SPI2) || \
|
||||
|
|
@ -26898,6 +26996,7 @@ typedef struct
|
|||
((INSTANCE) == TIM6) || \
|
||||
((INSTANCE) == TIM7) || \
|
||||
((INSTANCE) == TIM8) || \
|
||||
((INSTANCE) == TIM12) || \
|
||||
((INSTANCE) == TIM15))
|
||||
|
||||
/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue