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stm32: Fix pll_base on stm32h7 when using a clock other than 25Mhz

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2025-04-18 21:23:21 -04:00
parent 73e27aee4f
commit 5001983d34
1 changed files with 1 additions and 1 deletions
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2
src/stm32/stm32h7.c
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@ -100,7 +100,7 @@ clock_setup(void)
;
// (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
// /DIVP1(2) (SYSCLK 480Mhz)
uint32_t pll_base = 5000000;
uint32_t pll_base = CONFIG_STM32_CLOCK_REF_25M ? 5000000 : 4000000;
// Only even dividers (DIVP1) are allowed
uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {