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stm32: Update code to use armcm_boot mechanism
Replace the stm32 provided assembler with the src/generic/armcm_boot.c mechanism. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
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7 changed files with 24 additions and 111 deletions
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@ -5,6 +5,7 @@
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_SERIAL_BAUD
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#include "board/armcm_boot.h" // armcm_enable_irq
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#include "board/serial_irq.h" // serial_rx_byte
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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@ -17,34 +18,30 @@ DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA10,PA9");
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#define GPIO_Tx GPIO('A', 9)
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#define USARTx USART1
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#define USARTx_IRQn USART1_IRQn
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#define USARTx_IRQHandler USART1_IRQHandler
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#elif CONFIG_SERIAL_PORT == 2
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PA3,PA2");
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#define GPIO_Rx GPIO('A', 3)
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#define GPIO_Tx GPIO('A', 2)
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#define USARTx USART2
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#define USARTx_IRQn USART2_IRQn
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#define USARTx_IRQHandler USART2_IRQHandler
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#elif CONFIG_SERIAL_PORT == 103
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PD9,PD8");
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#define GPIO_Rx GPIO('D', 9)
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#define GPIO_Tx GPIO('D', 8)
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#define USARTx USART3
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#define USARTx_IRQn USART3_IRQn
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#define USARTx_IRQHandler USART3_IRQHandler
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#else
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DECL_CONSTANT_STR("RESERVE_PINS_serial", "PB11,PB10");
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#define GPIO_Rx GPIO('B', 11)
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#define GPIO_Tx GPIO('B', 10)
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#define USARTx USART3
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#define USARTx_IRQn USART3_IRQn
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#define USARTx_IRQHandler USART3_IRQHandler
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#endif
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#define CR1_FLAGS (USART_CR1_UE | USART_CR1_RE | USART_CR1_TE \
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| USART_CR1_RXNEIE)
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void __visible
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void
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USARTx_IRQHandler(void)
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{
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uint32_t sr = USARTx->SR;
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@ -76,8 +73,7 @@ serial_init(void)
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USARTx->BRR = (((div / 16) << USART_BRR_DIV_Mantissa_Pos)
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| ((div % 16) << USART_BRR_DIV_Fraction_Pos));
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USARTx->CR1 = CR1_FLAGS;
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NVIC_SetPriority(USARTx_IRQn, 0);
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NVIC_EnableIRQ(USARTx_IRQn);
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armcm_enable_irq(USARTx_IRQHandler, USARTx_IRQn, 0);
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gpio_peripheral(GPIO_Rx, GPIO_FUNCTION(7), 1);
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gpio_peripheral(GPIO_Tx, GPIO_FUNCTION(7), 0);
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