mirror of
https://github.com/Klipper3d/klipper.git
synced 2025-08-06 13:34:06 -06:00
stm32f7: add support for stm32f7 and remram board
Signed-off-by: Frederic Morin <frederic.morin.8@gmail.com>
This commit is contained in:
Frederic Morin
KevinOConnor
parent
a3eebab4f2
commit
33b18fd62b
31 changed files with 247955 additions and 11 deletions
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@ -10,7 +10,7 @@ config STM32_SELECT
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select HAVE_GPIO_I2C if !(MACH_STM32F031)
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select HAVE_GPIO_SPI if !MACH_STM32F031
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select HAVE_GPIO_SDIO if MACH_STM32F4
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select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32G0 || MACH_STM32H7
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select HAVE_GPIO_HARD_PWM if MACH_STM32F1 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32H7
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select HAVE_GPIO_BITBANGING if !MACH_STM32F031
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select HAVE_STRICT_TIMING
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select HAVE_CHIPID
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@ -52,6 +52,9 @@ choice
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config MACH_STM32F446
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bool "STM32F446"
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select MACH_STM32F4
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config MACH_STM32F765
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bool "STM32F765"
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select MACH_STM32F7
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config MACH_STM32F031
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bool "STM32F031"
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select MACH_STM32F0
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@ -119,6 +122,8 @@ config MACH_STM32F2
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bool
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config MACH_STM32F4
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bool
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config MACH_STM32F7
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bool
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config MACH_STM32G0
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bool
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config MACH_STM32G07x
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@ -143,7 +148,7 @@ config HAVE_STM32_USBFS
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default y if (MACH_STM32F1 || MACH_STM32F070) && !STM32_CLOCK_REF_INTERNAL
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config HAVE_STM32_USBOTG
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bool
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default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32H7
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default y if MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32H7
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config HAVE_STM32_CANBUS
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bool
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default y if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4x5 || MACH_STM32F446 || MACH_STM32F0x2
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@ -170,6 +175,7 @@ config MCU
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default "stm32f407xx" if MACH_STM32F407
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default "stm32f429xx" if MACH_STM32F429
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default "stm32f446xx" if MACH_STM32F446
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default "stm32f765xx" if MACH_STM32F765
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default "stm32g070xx" if MACH_STM32G070
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default "stm32g071xx" if MACH_STM32G071
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default "stm32g0b0xx" if MACH_STM32G0B0
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@ -190,6 +196,7 @@ config CLOCK_FREQ
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default 84000000 if MACH_STM32F401
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default 168000000 if MACH_STM32F4x5
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default 180000000 if MACH_STM32F446
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default 216000000 if MACH_STM32F765
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default 64000000 if MACH_STM32G0
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default 150000000 if MACH_STM32G431
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default 400000000 if MACH_STM32H7 # 400Mhz is max Klipper currently supports
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@ -207,7 +214,7 @@ config FLASH_SIZE
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default 0x80000 if MACH_STM32F4x5 || MACH_STM32F446
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default 0x20000 if MACH_STM32G0 || MACH_STM32G431
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default 0x20000 if MACH_STM32H750
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default 0x200000 if MACH_STM32H743
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default 0x200000 if MACH_STM32H743 || MACH_STM32F765
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default 0x20000 if MACH_N32G45x
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config FLASH_BOOT_ADDRESS
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@ -230,6 +237,7 @@ config RAM_SIZE
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default 0x20000 if MACH_STM32F207
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default 0x10000 if MACH_STM32F401
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default 0x20000 if MACH_STM32F4x5 || MACH_STM32F446
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default 0x80000 if MACH_STM32F765
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default 0x9000 if MACH_STM32G07x
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default 0x24000 if MACH_STM32G0Bx
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default 0x20000 if MACH_STM32H7
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@ -254,7 +262,7 @@ config STM32_DFU_ROM_ADDRESS
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default 0 if !USB
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default 0x1fffc400 if MACH_STM32F042
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default 0x1fffc800 if MACH_STM32F072
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default 0x1fff0000 if MACH_STM32F4 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
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default 0x1fff0000 if MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32G4 || MACH_STM32L4
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default 0x1ff09800 if MACH_STM32H7
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default 0
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@ -272,7 +280,7 @@ choice
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config STM32_FLASH_START_7000
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bool "28KiB bootloader" if MACH_STM32F1
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config STM32_FLASH_START_8000
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bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4
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bool "32KiB bootloader" if MACH_STM32F1 || MACH_STM32F2 || MACH_STM32F4 || MACH_STM32F7
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config STM32_FLASH_START_8800
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bool "34KiB bootloader (Chitu v6 Bootloader)" if MACH_STM32F103
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config STM32_FLASH_START_20200
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@ -289,7 +297,7 @@ choice
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config STM32_FLASH_START_4000
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bool "16KiB bootloader (HID Bootloader)" if MACH_STM32F207 || MACH_STM32F401 || MACH_STM32F4x5 || MACH_STM32F103 || MACH_STM32F072
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config STM32_FLASH_START_20000
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bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723
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bool "128KiB bootloader (SKR SE BX v2.0)" if MACH_STM32H743 || MACH_STM32H723 || MACH_STM32F7
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config STM32_FLASH_START_0000
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bool "No bootloader"
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@ -330,6 +338,8 @@ choice
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bool "16 MHz crystal"
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config STM32_CLOCK_REF_20M
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bool "20 MHz crystal"
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config STM32_CLOCK_REF_24M
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bool "24 MHz crystal"
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config STM32_CLOCK_REF_25M
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bool "25 MHz crystal"
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config STM32_CLOCK_REF_INTERNAL
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@ -338,6 +348,7 @@ endchoice
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config CLOCK_REF_FREQ
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int
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default 25000000 if STM32_CLOCK_REF_25M
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default 24000000 if STM32_CLOCK_REF_24M
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default 20000000 if STM32_CLOCK_REF_20M
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default 16000000 if STM32_CLOCK_REF_16M
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default 12000000 if STM32_CLOCK_REF_12M
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@ -9,6 +9,7 @@ dirs-$(CONFIG_MACH_STM32F1) += lib/stm32f1
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dirs-$(CONFIG_MACH_N32G45x) += lib/n32g45x
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dirs-$(CONFIG_MACH_STM32F2) += lib/stm32f2
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dirs-$(CONFIG_MACH_STM32F4) += lib/stm32f4
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dirs-$(CONFIG_MACH_STM32F7) += lib/stm32f7
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dirs-$(CONFIG_MACH_STM32G0) += lib/stm32g0
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dirs-$(CONFIG_MACH_STM32G4) += lib/stm32g4
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dirs-$(CONFIG_MACH_STM32H7) += lib/stm32h7
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@ -23,6 +24,7 @@ CFLAGS-$(CONFIG_MACH_N32G45x) += -mcpu=cortex-m4 -Ilib/n32g45x/include
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CFLAGS-$(CONFIG_MACH_STM32F1) += -Ilib/stm32f1/include
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CFLAGS-$(CONFIG_MACH_STM32F2) += -mcpu=cortex-m3 -Ilib/stm32f2/include
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CFLAGS-$(CONFIG_MACH_STM32F4) += -mcpu=cortex-m4 -Ilib/stm32f4/include
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CFLAGS-$(CONFIG_MACH_STM32F7) += -mcpu=cortex-m7 -Ilib/stm32f7/include
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CFLAGS-$(CONFIG_MACH_STM32G0) += -mcpu=cortex-m0plus -Ilib/stm32g0/include
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CFLAGS-$(CONFIG_MACH_STM32G4) += -mcpu=cortex-m4 -Ilib/stm32g4/include
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CFLAGS-$(CONFIG_MACH_STM32H7) += -mcpu=cortex-m7 -Ilib/stm32h7/include
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@ -52,6 +54,9 @@ src-$(CONFIG_MACH_STM32F2) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F4) += ../lib/stm32f4/system_stm32f4xx.c
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src-$(CONFIG_MACH_STM32F4) += stm32/stm32f4.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F4) += stm32/gpioperiph.c stm32/adc.c stm32/i2c.c
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src-$(CONFIG_MACH_STM32F7) += ../lib/stm32f7/system_stm32f7xx.c
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src-$(CONFIG_MACH_STM32F7) += stm32/stm32f7.c generic/armcm_timer.c
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src-$(CONFIG_MACH_STM32F7) += stm32/gpioperiph.c stm32/adc.c stm32/stm32f0_i2c.c
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src-$(CONFIG_MACH_STM32G0) += generic/timer_irq.c stm32/stm32f0_timer.c
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src-$(CONFIG_MACH_STM32G0) += stm32/stm32g0.c stm32/gpioperiph.c
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src-$(CONFIG_MACH_STM32G0) += stm32/stm32f0_adc.c stm32/stm32f0_i2c.c
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@ -36,7 +36,7 @@ dfu_reboot(void)
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irq_disable();
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uint64_t *bflag = (void*)USB_BOOT_FLAG_ADDR;
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*bflag = USB_BOOT_FLAG;
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#if CONFIG_MACH_STM32H7
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#if __CORTEX_M >= 7
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SCB_CleanDCache_by_Addr((void*)bflag, sizeof(*bflag));
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#endif
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NVIC_SystemReset();
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@ -32,6 +32,7 @@ gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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// stm32f0 is ~10Mhz at 50pF
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// stm32f2 is ~25Mhz at 40pF
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// stm32f4 is ~50Mhz at 40pF
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// stm32f7 is ~50Mhz at 40pF
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// stm32g0 is ~30Mhz at 50pF
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// stm32h7 is ~85Mhz at 50pF
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uint32_t ospeed = hs ? 0x03 : (CONFIG_MACH_STM32F0 ? 0x01 : 0x02);
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@ -102,6 +102,19 @@ static const struct gpio_pwm_info pwm_regs[] = {
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{TIM9, GPIO('E', 6), 2, GPIO_FUNCTION(3)},
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{TIM10, GPIO('B', 8), 1, GPIO_FUNCTION(3)},
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{TIM11, GPIO('B', 9), 1, GPIO_FUNCTION(3)}
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#elif CONFIG_MACH_STM32F7
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{TIM2, GPIO('A', 15), 1, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 3), 2, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 10), 3, GPIO_FUNCTION(1)},
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{TIM2, GPIO('B', 11), 4, GPIO_FUNCTION(1)},
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{TIM3, GPIO('B', 4), 1, GPIO_FUNCTION(1)},
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{TIM3, GPIO('B', 5), 1, GPIO_FUNCTION(1)},
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{TIM3, GPIO('C', 8), 2, GPIO_FUNCTION(1)},
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{TIM3, GPIO('C', 9), 2, GPIO_FUNCTION(1)},
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{TIM5, GPIO('A', 10), 3, GPIO_FUNCTION(1)},
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{TIM5, GPIO('E', 13), 3, GPIO_FUNCTION(1)},
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{TIM5, GPIO('A', 11), 4, GPIO_FUNCTION(1)},
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{TIM5, GPIO('E', 14), 4, GPIO_FUNCTION(1)},
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#elif CONFIG_MACH_STM32G0
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{TIM15, GPIO('A', 2), 1, GPIO_FUNCTION(5)},
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{TIM15, GPIO('A', 3), 2, GPIO_FUNCTION(5)},
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@ -12,6 +12,8 @@
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#include "stm32f2xx.h"
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#elif CONFIG_MACH_STM32F4
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#include "stm32f4xx.h"
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#elif CONFIG_MACH_STM32F7
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#include "stm32f7xx.h"
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#elif CONFIG_MACH_STM32G0
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#include "stm32g0xx.h"
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#elif CONFIG_MACH_STM32G4
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@ -86,9 +86,10 @@ spi_setup(uint32_t bus, uint8_t mode, uint32_t rate)
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gpio_peripheral(spi_bus[bus].mosi_pin, spi_bus[bus].function, 0);
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gpio_peripheral(spi_bus[bus].sck_pin, spi_bus[bus].function, 0);
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// Configure CR2 on stm32 f0/g0/l4/g4
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#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32L4 \
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|| CONFIG_MACH_STM32G4
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// Configure CR2 on stm32 f0/f7/g0/l4/g4
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#if CONFIG_MACH_STM32F0 || CONFIG_MACH_STM32F7 || \
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CONFIG_MACH_STM32G0 || CONFIG_MACH_STM32G4 || \
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CONFIG_MACH_STM32L4
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spi->CR2 = SPI_CR2_FRXTH | (7 << SPI_CR2_DS_Pos);
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#endif
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}
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@ -27,6 +27,9 @@ struct i2c_info {
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DECL_CONSTANT_STR("BUS_PINS_i2c1", "PB6,PB7");
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DECL_ENUMERATION("i2c_bus", "i2c1a", 1);
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DECL_CONSTANT_STR("BUS_PINS_i2c1a", "PF1,PF0");
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#elif CONFIG_MACH_STM32F7
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DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
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DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
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#elif CONFIG_MACH_STM32G0
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DECL_ENUMERATION("i2c_bus", "i2c1_PB6_PB7", 0);
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DECL_CONSTANT_STR("BUS_PINS_i2c1_PB6_PB7", "PB6,PB7");
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@ -86,6 +89,8 @@ static const struct i2c_info i2c_bus[] = {
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{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
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{ I2C1, GPIO('F', 1), GPIO('F', 0), GPIO_FUNCTION(1) },
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{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(1) },
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#elif CONFIG_MACH_STM32F7
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{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(1) },
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#elif CONFIG_MACH_STM32G0
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{ I2C1, GPIO('B', 6), GPIO('B', 7), GPIO_FUNCTION(6) },
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{ I2C1, GPIO('B', 8), GPIO('B', 9), GPIO_FUNCTION(6) },
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168
src/stm32/stm32f7.c
Normal file
168
src/stm32/stm32f7.c
Normal file
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@ -0,0 +1,168 @@
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// Code to setup clocks on stm32f7
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//
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// Copyright (C) 2023 Frederic Morin <frederic.morin.8@gmail.com>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/armcm_reset.h" // try_request_canboot
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#include "board/irq.h" // irq_disable
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#include "board/misc.h" // bootloader_request
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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/****************************************************************
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* Clock setup
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****************************************************************/
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#define FREQ_PERIPH_DIV 4
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / FREQ_PERIPH_DIV)
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#define FREQ_USB 48000000
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// Map a peripheral address to its enable bits
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struct cline
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lookup_clock_line(uint32_t periph_base)
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{
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if (periph_base >= AHB1PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - AHB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->AHB1ENR, .rst=&RCC->AHB1RSTR, .bit=bit};
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} else if (periph_base >= APB2PERIPH_BASE) {
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uint32_t bit = 1 << ((periph_base - APB2PERIPH_BASE) / 0x400);
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if (bit & 0x700)
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// Skip ADC peripheral reset as they share a bit
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return (struct cline){.en=&RCC->APB2ENR, .bit=bit};
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return (struct cline){.en=&RCC->APB2ENR, .rst=&RCC->APB2RSTR, .bit=bit};
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} else {
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uint32_t bit = 1 << ((periph_base - APB1PERIPH_BASE) / 0x400);
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return (struct cline){.en=&RCC->APB1ENR, .rst=&RCC->APB1RSTR, .bit=bit};
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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uint32_t rcc_pos = ((uint32_t)regs - AHB1PERIPH_BASE) / 0x400;
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RCC->AHB1ENR |= 1 << rcc_pos;
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RCC->AHB1ENR;
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Main clock setup called at chip startup
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static void
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clock_setup(void)
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{
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// Configure and enable PLL
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const uint32_t pll_base = 2000000, pll_freq = CONFIG_CLOCK_FREQ * 2;
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uint32_t pllcfgr;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure 216Mhz PLL from external crystal (HSE)
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const uint32_t div = CONFIG_CLOCK_REF_FREQ / pll_base;
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RCC->CR |= RCC_CR_HSEON;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSE | (div << RCC_PLLCFGR_PLLM_Pos);
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} else {
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// Configure 216Mhz PLL from internal 16Mhz oscillator (HSI)
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const uint32_t div = 16000000 / pll_base;
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pllcfgr = RCC_PLLCFGR_PLLSRC_HSI | (div << RCC_PLLCFGR_PLLM_Pos);
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}
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RCC->PLLCFGR = (pllcfgr | ((pll_freq/pll_base) << RCC_PLLCFGR_PLLN_Pos)
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| (0 << RCC_PLLCFGR_PLLP_Pos) // /2
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| ((pll_freq/FREQ_USB) << RCC_PLLCFGR_PLLQ_Pos)
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| (2 << RCC_PLLCFGR_PLLR_Pos));
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RCC->CR |= RCC_CR_PLLON;
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// Enable "over drive"
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enable_pclock(PWR_BASE);
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PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN;
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while (!(PWR->CSR1 & PWR_CSR1_ODRDY))
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;
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PWR->CR1 = (3 << PWR_CR1_VOS_Pos) | PWR_CR1_ODEN | PWR_CR1_ODSWEN;
|
||||
while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY))
|
||||
;
|
||||
|
||||
// Enable 48Mhz USB clock
|
||||
if (CONFIG_USB) {
|
||||
// setup PLLSAI
|
||||
const uint32_t plls_base = 2000000, plls_freq = FREQ_USB * 4;
|
||||
RCC->PLLSAICFGR = (
|
||||
((plls_freq/plls_base) << RCC_PLLSAICFGR_PLLSAIN_Pos) // *96
|
||||
| (((plls_freq/FREQ_USB)/2 - 1) << RCC_PLLSAICFGR_PLLSAIP_Pos)// /4
|
||||
| ((plls_freq/FREQ_USB) << RCC_PLLSAICFGR_PLLSAIQ_Pos));
|
||||
// enable PLLSAI and wait for PLLSAI lock
|
||||
RCC->CR |= RCC_CR_PLLSAION;
|
||||
while (!(RCC->CR & RCC_CR_PLLSAIRDY))
|
||||
;
|
||||
// set CLK48 source to PLLSAI
|
||||
RCC->DCKCFGR2 = RCC_DCKCFGR2_CK48MSEL; // RCC_CLK48SOURCE_PLLSAIP
|
||||
}
|
||||
|
||||
// Set flash latency
|
||||
MODIFY_REG(
|
||||
FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_ACR_LATENCY_7WS));
|
||||
|
||||
// Wait for PLL lock
|
||||
while (!(RCC->CR & RCC_CR_PLLRDY))
|
||||
;
|
||||
|
||||
// Switch system clock to PLL
|
||||
RCC->CFGR = RCC_CFGR_PPRE1_DIV4 | RCC_CFGR_PPRE2_DIV4 | RCC_CFGR_SW_PLL;
|
||||
while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL)
|
||||
;
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Bootloader
|
||||
****************************************************************/
|
||||
|
||||
// Handle reboot requests
|
||||
void
|
||||
bootloader_request(void)
|
||||
{
|
||||
try_request_canboot();
|
||||
dfu_reboot();
|
||||
}
|
||||
|
||||
|
||||
/****************************************************************
|
||||
* Startup
|
||||
****************************************************************/
|
||||
|
||||
// Main entry point - called from armcm_boot.c:ResetHandler()
|
||||
void
|
||||
armcm_main(void)
|
||||
{
|
||||
// Run SystemInit() and then restore VTOR
|
||||
SystemInit();
|
||||
SCB->VTOR = (uint32_t)VectorTable;
|
||||
|
||||
// Reset peripheral clocks (for some bootloaders that don't)
|
||||
RCC->AHB1ENR = 0x00100000;
|
||||
RCC->AHB2ENR = 0x00000000;
|
||||
RCC->AHB3ENR = 0x00000000;
|
||||
RCC->APB1ENR = 0x00000400;
|
||||
RCC->APB2ENR = 0x00000000;
|
||||
|
||||
dfu_reboot_check();
|
||||
|
||||
// STM32F7 specific DWT unlock required prior to timer_init() DWT setup.
|
||||
CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
|
||||
DWT->LAR = 0xC5ACCE55;
|
||||
|
||||
clock_setup();
|
||||
|
||||
sched_main();
|
||||
}
|
||||
|
|
@ -426,7 +426,7 @@ usb_init(void)
|
|||
OTG->GUSBCFG = (USB_OTG_GUSBCFG_FDMOD | USB_OTG_GUSBCFG_PHYSEL
|
||||
| (6 << USB_OTG_GUSBCFG_TRDT_Pos));
|
||||
OTGD->DCFG |= (3 << USB_OTG_DCFG_DSPD_Pos);
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7
|
||||
#if CONFIG_MACH_STM32F446 || CONFIG_MACH_STM32H7 || CONFIG_MACH_STM32F7
|
||||
OTG->GOTGCTL = USB_OTG_GOTGCTL_BVALOEN | USB_OTG_GOTGCTL_BVALOVAL;
|
||||
#else
|
||||
OTG->GCCFG |= USB_OTG_GCCFG_NOVBUSSENS;
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue