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lib: Updated existing cmsis-core for stm32h7 support
Signed-off-by: Konstantin Vogel <konstantin.vogel@gmx.net> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
D4SK
Kevin O'Connor
parent
c7b65f50e3
commit
309fbbc104
11 changed files with 3368 additions and 262 deletions
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@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file core_cm0.h
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* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
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* @version V5.0.3
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* @date 10. January 2018
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* @version V5.0.8
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* @date 21. August 2019
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******************************************************************************/
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/*
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* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
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* Copyright (c) 2009-2019 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -81,7 +81,7 @@
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#endif
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#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
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#if defined __ARM_PCS_VFP
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#if defined __ARM_FP
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#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
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#endif
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@ -316,7 +316,7 @@ typedef struct
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__IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[31U];
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__IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[31U];
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uint32_t RESERVED1[31U];
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__IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[31U];
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__IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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@ -572,8 +572,8 @@ typedef struct
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#endif
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#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
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#else
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/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M0 */
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/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M0 */
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#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping
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#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping
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#define NVIC_EnableIRQ __NVIC_EnableIRQ
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#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
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#define NVIC_DisableIRQ __NVIC_DisableIRQ
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@ -599,12 +599,20 @@ typedef struct
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#define NVIC_USER_IRQ_OFFSET 16
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/* The following EXC_RETURN values are saved the LR on exception entry */
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#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */
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#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */
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#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */
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/* Interrupt Priorities are WORD accessible only under Armv6-M */
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/* The following MACROS handle generation of the register offset and byte masks */
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#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
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#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
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#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
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#define __NVIC_SetPriorityGrouping(X) (void)(X)
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#define __NVIC_GetPriorityGrouping() (0U)
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/**
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\brief Enable Interrupt
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@ -616,7 +624,9 @@ __STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
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{
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if ((int32_t)(IRQn) >= 0)
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{
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__COMPILER_BARRIER();
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NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
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__COMPILER_BARRIER();
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}
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}
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@ -757,6 +767,59 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
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}
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/**
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\brief Encode Priority
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\details Encodes the priority for an interrupt with the given priority group,
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preemptive priority value, and subpriority value.
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In case of a conflict between priority grouping and available
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priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
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\param [in] PriorityGroup Used priority group.
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\param [in] PreemptPriority Preemptive priority value (starting from 0).
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\param [in] SubPriority Subpriority value (starting from 0).
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\return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
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*/
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__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
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{
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uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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uint32_t PreemptPriorityBits;
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uint32_t SubPriorityBits;
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PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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return (
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((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
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((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
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);
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}
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/**
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\brief Decode Priority
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\details Decodes an interrupt priority value with a given priority group to
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preemptive priority value and subpriority value.
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In case of a conflict between priority grouping and available
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priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
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\param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
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\param [in] PriorityGroup Used priority group.
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\param [out] pPreemptPriority Preemptive priority value (starting from 0).
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\param [out] pSubPriority Subpriority value (starting from 0).
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*/
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__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority)
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{
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uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
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uint32_t PreemptPriorityBits;
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uint32_t SubPriorityBits;
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PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
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SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
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*pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
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*pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
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}
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/**
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\brief Set Interrupt Vector
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\details Sets an interrupt vector in SRAM based interrupt vector table.
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@ -768,8 +831,9 @@ __STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
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*/
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__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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{
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uint32_t *vectors = (uint32_t *)0x0U;
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vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
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uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
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*(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */
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/* ARM Application Note 321 states that the M0 does not require the architectural barrier */
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}
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@ -783,8 +847,8 @@ __STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
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*/
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__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
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{
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uint32_t *vectors = (uint32_t *)0x0U;
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return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
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uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */
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return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */
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}
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@ -792,7 +856,7 @@ __STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
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\brief System Reset
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\details Initiates a system reset request to reset the MCU.
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*/
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__STATIC_INLINE void __NVIC_SystemReset(void)
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__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void)
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{
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__DSB(); /* Ensure all outstanding memory accesses included
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buffered write are completed before reset */
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