mirror of
https://github.com/Klipper3d/klipper.git
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lib: Updated existing cmsis-core for stm32h7 support
Signed-off-by: Konstantin Vogel <konstantin.vogel@gmx.net> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
D4SK
Kevin O'Connor
parent
c7b65f50e3
commit
309fbbc104
11 changed files with 3368 additions and 262 deletions
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@ -1,11 +1,11 @@
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/**************************************************************************//**
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* @file cmsis_gcc.h
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* @brief CMSIS compiler GCC header file
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* @version V5.0.3
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* @date 16. January 2018
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* @version V5.3.0
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* @date 26. March 2020
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******************************************************************************/
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/*
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* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
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* Copyright (c) 2009-2020 Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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@ -113,7 +113,74 @@
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#ifndef __RESTRICT
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#define __RESTRICT __restrict
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#endif
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#ifndef __COMPILER_BARRIER
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#define __COMPILER_BARRIER() __ASM volatile("":::"memory")
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#endif
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/* ######################### Startup and Lowlevel Init ######################## */
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#ifndef __PROGRAM_START
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/**
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\brief Initializes data and bss sections
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\details This default implementations initialized all data and additional bss
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sections relying on .copy.table and .zero.table specified properly
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in the used linker script.
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*/
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__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void)
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{
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extern void _start(void) __NO_RETURN;
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typedef struct {
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uint32_t const* src;
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uint32_t* dest;
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uint32_t wlen;
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} __copy_table_t;
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typedef struct {
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uint32_t* dest;
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uint32_t wlen;
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} __zero_table_t;
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extern const __copy_table_t __copy_table_start__;
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extern const __copy_table_t __copy_table_end__;
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extern const __zero_table_t __zero_table_start__;
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extern const __zero_table_t __zero_table_end__;
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for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) {
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for(uint32_t i=0u; i<pTable->wlen; ++i) {
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pTable->dest[i] = pTable->src[i];
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}
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}
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for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) {
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for(uint32_t i=0u; i<pTable->wlen; ++i) {
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pTable->dest[i] = 0u;
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}
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}
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_start();
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}
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#define __PROGRAM_START __cmsis_start
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#endif
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#ifndef __INITIAL_SP
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#define __INITIAL_SP __StackTop
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#endif
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#ifndef __STACK_LIMIT
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#define __STACK_LIMIT __StackLimit
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#endif
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#ifndef __VECTOR_TABLE
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#define __VECTOR_TABLE __Vectors
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#endif
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#ifndef __VECTOR_TABLE_ATTRIBUTE
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#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors")))
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#endif
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/* ########################### Core Function Access ########################### */
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/** \ingroup CMSIS_Core_FunctionInterface
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@ -246,7 +313,7 @@ __STATIC_FORCEINLINE uint32_t __get_xPSR(void)
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*/
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__STATIC_FORCEINLINE uint32_t __get_PSP(void)
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{
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, psp" : "=r" (result) );
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return(result);
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@ -261,7 +328,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSP(void)
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void)
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{
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, psp_ns" : "=r" (result) );
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return(result);
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@ -300,7 +367,7 @@ __STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack)
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*/
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__STATIC_FORCEINLINE uint32_t __get_MSP(void)
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{
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, msp" : "=r" (result) );
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return(result);
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@ -315,7 +382,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSP(void)
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void)
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{
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, msp_ns" : "=r" (result) );
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return(result);
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@ -355,7 +422,7 @@ __STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack)
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*/
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__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void)
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{
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, sp_ns" : "=r" (result) );
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return(result);
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@ -383,7 +450,7 @@ __STATIC_FORCEINLINE uint32_t __get_PRIMASK(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory");
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__ASM volatile ("MRS %0, primask" : "=r" (result) );
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return(result);
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}
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@ -398,7 +465,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void)
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{
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uint32_t result;
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__ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory");
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__ASM volatile ("MRS %0, primask_ns" : "=r" (result) );
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return(result);
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}
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#endif
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@ -596,7 +663,7 @@ __STATIC_FORCEINLINE uint32_t __get_PSPLIM(void)
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// without main extensions, the non-secure PSPLIM is RAZ/WI
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return 0U;
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#else
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, psplim" : "=r" (result) );
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return result;
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#endif
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@ -617,7 +684,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void)
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// without main extensions, the non-secure PSPLIM is RAZ/WI
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return 0U;
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#else
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, psplim_ns" : "=r" (result) );
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return result;
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#endif
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@ -683,7 +750,7 @@ __STATIC_FORCEINLINE uint32_t __get_MSPLIM(void)
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// without main extensions, the non-secure MSPLIM is RAZ/WI
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return 0U;
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#else
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, msplim" : "=r" (result) );
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return result;
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#endif
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@ -705,7 +772,7 @@ __STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void)
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// without main extensions, the non-secure MSPLIM is RAZ/WI
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return 0U;
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#else
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register uint32_t result;
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uint32_t result;
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__ASM volatile ("MRS %0, msplim_ns" : "=r" (result) );
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return result;
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#endif
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@ -758,9 +825,6 @@ __STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit)
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(defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */
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#if ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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/**
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\brief Get FPSCR
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\details Returns the current value of the Floating Point Status/Control register.
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@ -770,7 +834,9 @@ __STATIC_FORCEINLINE uint32_t __get_FPSCR(void)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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#if __has_builtin(__builtin_arm_get_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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#if __has_builtin(__builtin_arm_get_fpscr)
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// Re-enable using built-in when GCC has been fixed
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// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
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return __builtin_arm_get_fpscr();
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#else
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@ -794,7 +860,9 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
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{
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#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \
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(defined (__FPU_USED ) && (__FPU_USED == 1U)) )
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#if __has_builtin(__builtin_arm_set_fpscr) || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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#if __has_builtin(__builtin_arm_set_fpscr)
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// Re-enable using built-in when GCC has been fixed
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// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2)
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/* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */
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__builtin_arm_set_fpscr(fpscr);
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#else
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@ -805,10 +873,6 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
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#endif
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}
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#endif /* ((defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */
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/*@} end of CMSIS_Core_RegAccFunctions */
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@ -842,7 +906,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
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\brief Wait For Interrupt
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\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
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*/
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#define __WFI() __ASM volatile ("wfi")
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#define __WFI() __ASM volatile ("wfi":::"memory")
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/**
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@ -850,7 +914,7 @@ __STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr)
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\details Wait For Event is a hint instruction that permits the processor to enter
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a low-power state until one of a number of events occurs.
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*/
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#define __WFE() __ASM volatile ("wfe")
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#define __WFE() __ASM volatile ("wfe":::"memory")
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/**
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@ -907,7 +971,7 @@ __STATIC_FORCEINLINE uint32_t __REV(uint32_t value)
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#else
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uint32_t result;
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__ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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__ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return result;
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#endif
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}
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@ -923,7 +987,7 @@ __STATIC_FORCEINLINE uint32_t __REV16(uint32_t value)
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{
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uint32_t result;
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__ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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__ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return result;
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}
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@ -941,7 +1005,7 @@ __STATIC_FORCEINLINE int16_t __REVSH(int16_t value)
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#else
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int16_t result;
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__ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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__ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
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return result;
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#endif
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}
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@ -988,7 +1052,7 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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(defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \
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(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) )
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__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
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__ASM ("rbit %0, %1" : "=r" (result) : "r" (value) );
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#else
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uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */
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@ -1011,7 +1075,23 @@ __STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value)
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\param [in] value Value to count the leading zeros
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\return number of leading zeros in value
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*/
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#define __CLZ (uint8_t)__builtin_clz
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__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
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{
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/* Even though __builtin_clz produces a CLZ instruction on ARM, formally
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__builtin_clz(0) is undefined behaviour, so handle this case specially.
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This guarantees ARM-compatible results if happening to compile on a non-ARM
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target, and ensures the compiler doesn't decide to activate any
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optimisations using the logic "value was passed to __builtin_clz, so it
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is non-zero".
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ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a
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single CLZ instruction.
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*/
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if (value == 0U)
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{
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return 32U;
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}
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return __builtin_clz(value);
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}
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#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \
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@ -1153,11 +1233,11 @@ __STATIC_FORCEINLINE void __CLREX(void)
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\param [in] ARG2 Bit position to saturate to (1..32)
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\return Saturated value
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*/
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#define __SSAT(ARG1,ARG2) \
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#define __SSAT(ARG1, ARG2) \
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__extension__ \
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({ \
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int32_t __RES, __ARG1 = (ARG1); \
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__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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__ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
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__RES; \
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})
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@ -1169,11 +1249,11 @@ __extension__ \
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\param [in] ARG2 Bit position to saturate to (0..31)
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\return Saturated value
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*/
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#define __USAT(ARG1,ARG2) \
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#define __USAT(ARG1, ARG2) \
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__extension__ \
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({ \
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uint32_t __RES, __ARG1 = (ARG1); \
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__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
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__ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
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__RES; \
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})
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@ -1358,7 +1438,7 @@ __STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr)
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{
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uint32_t result;
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__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) );
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__ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
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return ((uint8_t) result);
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}
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@ -1373,7 +1453,7 @@ __STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr)
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{
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uint32_t result;
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__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) );
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__ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
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return ((uint16_t) result);
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}
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@ -1388,7 +1468,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
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{
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uint32_t result;
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__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) );
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__ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
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return(result);
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}
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@ -1401,7 +1481,7 @@ __STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr)
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*/
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__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
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{
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__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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__ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
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}
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@ -1413,7 +1493,7 @@ __STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr)
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*/
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__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
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{
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__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
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__ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
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}
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@ -1425,7 +1505,7 @@ __STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr)
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*/
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__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr)
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{
|
||||
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -1439,7 +1519,7 @@ __STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
__ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return ((uint8_t) result);
|
||||
}
|
||||
|
||||
|
|
@ -1454,7 +1534,7 @@ __STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
__ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return ((uint16_t) result);
|
||||
}
|
||||
|
||||
|
|
@ -1469,7 +1549,7 @@ __STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) );
|
||||
__ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1486,7 +1566,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1503,7 +1583,7 @@ __STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1520,7 +1600,7 @@ __STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) );
|
||||
__ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1550,7 +1630,7 @@ __STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1558,7 +1638,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1574,7 +1654,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1582,7 +1662,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1599,7 +1679,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1607,7 +1687,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1623,7 +1703,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1631,7 +1711,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1648,7 +1728,7 @@ __STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1656,7 +1736,7 @@ __STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1672,7 +1752,7 @@ __STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1680,7 +1760,7 @@ __STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1696,7 +1776,7 @@ __STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1704,7 +1784,7 @@ __STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1720,7 +1800,7 @@ __STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1728,7 +1808,7 @@ __STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1744,7 +1824,7 @@ __STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1752,7 +1832,7 @@ __STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1768,7 +1848,7 @@ __STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1776,7 +1856,7 @@ __STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1792,7 +1872,7 @@ __STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1800,7 +1880,7 @@ __STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1816,7 +1896,7 @@ __STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1824,7 +1904,7 @@ __STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1832,7 +1912,7 @@ __STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1840,21 +1920,21 @@ __STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
__ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
#define __SSAT16(ARG1,ARG2) \
|
||||
#define __SSAT16(ARG1, ARG2) \
|
||||
({ \
|
||||
int32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
#define __USAT16(ARG1,ARG2) \
|
||||
#define __USAT16(ARG1, ARG2) \
|
||||
({ \
|
||||
uint32_t __RES, __ARG1 = (ARG1); \
|
||||
__ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
|
||||
__ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \
|
||||
__RES; \
|
||||
})
|
||||
|
||||
|
|
@ -1862,7 +1942,7 @@ __STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
__ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1870,7 +1950,7 @@ __STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -1878,15 +1958,24 @@ __STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1)
|
|||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
__ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
|
||||
return(result);
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) );
|
||||
|
||||
return result;
|
||||
}
|
||||
|
||||
__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
__ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
@ -2075,7 +2164,7 @@ __STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3)
|
|||
{
|
||||
int32_t result;
|
||||
|
||||
__ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
__ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) );
|
||||
return(result);
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue