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stm32: Support setting the stm32f0 internal clock trim value

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Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor 2021-01-18 12:47:59 -05:00
parent 611b76369f
commit 28bca7da77
2 changed files with 11 additions and 1 deletions
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3
src/stm32/stm32f0.c
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@ -127,7 +127,8 @@ pll_setup(void)
if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
// Configure 48Mhz PLL from external crystal (HSE)
uint32_t div = CONFIG_CLOCK_FREQ / CONFIG_CLOCK_REF_FREQ;
RCC->CR |= RCC_CR_HSEON;
RCC->CR = ((RCC->CR & ~RCC_CR_HSITRIM) | RCC_CR_HSEON
| (CONFIG_STM32F0_TRIM << RCC_CR_HSITRIM_Pos));
cfgr = RCC_CFGR_PLLSRC_HSE_PREDIV | ((div - 2) << RCC_CFGR_PLLMUL_Pos);
} else {
// Configure 48Mhz PLL from internal 8Mhz oscillator (HSI)