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https://github.com/Klipper3d/klipper.git
synced 2025-07-26 16:14:00 -06:00
stm32: Add optimized stm32h7_gpio.c
Add optimized gpio functions for stm32h7 - caching the ODR register can notably improve the performance of the gpio_out_toggle() code. Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
Kevin O'Connor
parent
1f5783a250
commit
0d27195fd4
4 changed files with 176 additions and 5 deletions
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@ -13,7 +13,7 @@ config STM32_SELECT
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select HAVE_GPIO_HARD_PWM if MACH_STM32F070 || MACH_STM32F072 || MACH_STM32F1 || MACH_STM32F4 || MACH_STM32F7 || MACH_STM32G0 || MACH_STM32H7
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select HAVE_STRICT_TIMING
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select HAVE_CHIPID
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select HAVE_STEPPER_OPTIMIZED_BOTH_EDGE
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select HAVE_STEPPER_OPTIMIZED_BOTH_EDGE if !MACH_STM32H7
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select HAVE_BOOTLOADER_REQUEST
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select HAVE_LIMITED_CODE_SIZE if FLASH_SIZE < 0x10000
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@ -37,7 +37,7 @@ CFLAGS_klipper.elf += -T $(OUT)src/generic/armcm_link.ld
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$(OUT)klipper.elf: $(OUT)src/generic/armcm_link.ld
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# Add source files
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src-y += stm32/watchdog.c stm32/gpio.c stm32/clockline.c stm32/dfu_reboot.c
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src-y += stm32/watchdog.c stm32/clockline.c stm32/dfu_reboot.c
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src-y += generic/crc16_ccitt.c
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src-y += generic/armcm_boot.c generic/armcm_irq.c generic/armcm_reset.c
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src-$(CONFIG_MACH_STM32F0) += stm32/stm32f0.c ../lib/stm32f0/system_stm32f0xx.c
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@ -52,8 +52,9 @@ src-$(CONFIG_MACH_STM32L4) += stm32/stm32l4.c ../lib/stm32l4/system_stm32l4xx.c
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timer-src-y := generic/armcm_timer.c
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timer-src-$(CONFIG_MACH_STM32F0) := generic/timer_irq.c stm32/stm32f0_timer.c
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timer-src-$(CONFIG_MACH_STM32G0) := generic/timer_irq.c stm32/stm32f0_timer.c
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gpio-src-y := stm32/gpioperiph.c
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gpio-src-$(CONFIG_MACH_STM32F1) :=
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gpio-src-y := stm32/gpio.c stm32/gpioperiph.c
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gpio-src-$(CONFIG_MACH_STM32F1) := stm32/gpio.c
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gpio-src-$(CONFIG_MACH_STM32H7) := stm32/stm32h7_gpio.c stm32/gpioperiph.c
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src-y += $(timer-src-y) $(gpio-src-y)
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adc-src-y := stm32/adc.c
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adc-src-$(CONFIG_MACH_STM32F0) := stm32/stm32f0_adc.c
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@ -5,7 +5,10 @@
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struct gpio_out {
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void *regs;
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union {
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struct odr_cache *oc; // stm32h7 uses 'oc'; all others use 'bit'
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uint32_t bit;
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};
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};
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struct gpio_out gpio_out_setup(uint32_t pin, uint32_t val);
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void gpio_out_reset(struct gpio_out g, uint32_t val);
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167
src/stm32/stm32h7_gpio.c
Normal file
167
src/stm32/stm32h7_gpio.c
Normal file
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@ -0,0 +1,167 @@
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// GPIO functions optimized for stm32h7
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//
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// Copyright (C) 2019-2025 Kevin O'Connor <kevin@koconnor.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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#include <string.h> // ffs
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#include "board/irq.h" // irq_save
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#include "command.h" // DECL_ENUMERATION_RANGE
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#include "gpio.h" // gpio_out_setup
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#include "internal.h" // gpio_peripheral
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#include "sched.h" // sched_shutdown
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DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 16);
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DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 16);
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#ifdef GPIOD
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DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 16);
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#endif
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#ifdef GPIOE
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DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 16);
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#endif
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#ifdef GPIOF
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DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 16);
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#endif
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#ifdef GPIOG
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DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 16);
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#endif
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#ifdef GPIOH
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DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 16);
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#endif
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#ifdef GPIOI
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DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 16);
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#endif
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GPIO_TypeDef * const digital_regs[] = {
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['A' - 'A'] = GPIOA, GPIOB, GPIOC,
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#ifdef GPIOD
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['D' - 'A'] = GPIOD,
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#endif
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#ifdef GPIOE
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['E' - 'A'] = GPIOE,
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#endif
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#ifdef GPIOF
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['F' - 'A'] = GPIOF,
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#endif
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#ifdef GPIOG
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['G' - 'A'] = GPIOG,
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#endif
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#ifdef GPIOH
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['H' - 'A'] = GPIOH,
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#endif
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#ifdef GPIOI
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['I' - 'A'] = GPIOI,
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#endif
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};
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// Convert a register and bit location back to an integer pin identifier
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static int
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regs_to_pin(GPIO_TypeDef *regs, uint32_t bit)
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{
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int i;
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for (i=0; i<ARRAY_SIZE(digital_regs); i++)
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if (digital_regs[i] == regs)
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return GPIO('A' + i, ffs(bit)-1);
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return 0;
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}
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// Verify that a gpio is a valid pin
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static int
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gpio_valid(uint32_t pin)
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{
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uint32_t port = GPIO2PORT(pin);
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return port < ARRAY_SIZE(digital_regs) && digital_regs[port];
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}
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// The stm32h7 has very slow read access to the gpio registers. Cache
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// the ODR register in memory to speed up toggle operations.
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static struct odr_cache {
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uint32_t bsrr;
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} ODR_CACHE[ARRAY_SIZE(digital_regs) * 16] __aligned(64);
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struct gpio_out
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gpio_out_setup(uint32_t pin, uint32_t val)
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{
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if (!gpio_valid(pin))
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shutdown("Not an output pin");
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uint32_t port = GPIO2PORT(pin);
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GPIO_TypeDef *regs = digital_regs[port];
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gpio_clock_enable(regs);
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struct gpio_out g = { .regs=regs, .oc=&ODR_CACHE[pin] };
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gpio_out_reset(g, val);
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return g;
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}
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void
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gpio_out_reset(struct gpio_out g, uint32_t val)
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{
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GPIO_TypeDef *regs = g.regs;
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uint32_t pin = g.oc - ODR_CACHE;
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uint32_t bit_num = ((uint32_t)g.oc / sizeof(*g.oc)) % 16;
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uint32_t bsrr = 1 << (val ? bit_num : bit_num + 16);
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irqstatus_t flag = irq_save();
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g.oc->bsrr = bsrr;
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regs->BSRR = bsrr;
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gpio_peripheral(pin, GPIO_OUTPUT, 0);
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irq_restore(flag);
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}
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void
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gpio_out_toggle_noirq(struct gpio_out g)
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{
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GPIO_TypeDef *regs = g.regs;
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uint32_t bsrr = (g.oc->bsrr << 16) | (g.oc->bsrr >> 16);
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g.oc->bsrr = bsrr;
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regs->BSRR = bsrr;
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}
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void
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gpio_out_toggle(struct gpio_out g)
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{
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irqstatus_t flag = irq_save();
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gpio_out_toggle_noirq(g);
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irq_restore(flag);
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}
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void
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gpio_out_write(struct gpio_out g, uint32_t val)
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{
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GPIO_TypeDef *regs = g.regs;
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uint32_t bit_num = ((uint32_t)g.oc / sizeof(*g.oc)) % 16;
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uint32_t bsrr = 1 << (val ? bit_num : bit_num + 16);
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irqstatus_t flag = irq_save();
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g.oc->bsrr = bsrr;
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regs->BSRR = bsrr;
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irq_restore(flag);
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}
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struct gpio_in
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gpio_in_setup(uint32_t pin, int32_t pull_up)
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{
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if (!gpio_valid(pin))
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shutdown("Not a valid input pin");
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(pin)];
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struct gpio_in g = { .regs=regs, .bit=GPIO2BIT(pin) };
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gpio_in_reset(g, pull_up);
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return g;
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}
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void
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gpio_in_reset(struct gpio_in g, int32_t pull_up)
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{
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GPIO_TypeDef *regs = g.regs;
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int pin = regs_to_pin(regs, g.bit);
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irqstatus_t flag = irq_save();
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gpio_peripheral(pin, GPIO_INPUT, pull_up);
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irq_restore(flag);
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}
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uint8_t
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gpio_in_read(struct gpio_in g)
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{
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GPIO_TypeDef *regs = g.regs;
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return !!(regs->IDR & g.bit);
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}
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