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stm32: Add initial support for stm32h7
Signed-off-by: Konstantin Vogel <konstantin.vogel@gmx.net> Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
This commit is contained in:
D4SK
Kevin O'Connor
parent
28b3c9e88c
commit
0a55489e2c
7 changed files with 583 additions and 2 deletions
231
src/stm32/stm32h7.c
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231
src/stm32/stm32h7.c
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// Code to setup clocks and gpio on stm32h7
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//
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// Copyright (C) 2020 Konstantin Vogel <konstantin.vogel@gmx.net>
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//
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// This file may be distributed under the terms of the GNU GPLv3 license.
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// USB and I2C is not supported, SPI is untested!
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#include "autoconf.h" // CONFIG_CLOCK_REF_FREQ
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#include "board/armcm_boot.h" // VectorTable
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#include "board/irq.h" // irq_disable
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#include "command.h" // DECL_CONSTANT_STR
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#include "internal.h" // enable_pclock
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#include "sched.h" // sched_main
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#define FREQ_PERIPH (CONFIG_CLOCK_FREQ / 4)
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// Enable a peripheral clock
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void
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enable_pclock(uint32_t periph_base)
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{
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// periph_base determines in which bitfield at wich position to set a bit
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// E.g. D2_AHB1PERIPH_BASE is the adress offset of the given bitfield
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if (periph_base < D2_APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_APB1PERIPH_BASE) / 0x400;
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RCC->APB1LENR |= (1<<pos); // we assume it is not in APB1HENR
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RCC->APB1LENR;
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} else if (periph_base < D2_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_APB2PERIPH_BASE) / 0x400;
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RCC->APB2ENR |= (1<<pos);
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RCC->APB2ENR;
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} else if (periph_base < D2_AHB2PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB1ENR |= (1<<pos);
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RCC->AHB1ENR;
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} else if (periph_base < D1_APB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_AHB2PERIPH_BASE) / 0x400;
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RCC->AHB2ENR |= (1<<pos);
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RCC->AHB2ENR;
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} else if (periph_base < D1_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D1_APB1PERIPH_BASE) / 0x400;
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RCC->APB3ENR |= (1<<pos);
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RCC->APB3ENR;
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} else if (periph_base < D3_APB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D1_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB3ENR |= (1<<pos);
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RCC->AHB3ENR;
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} else if (periph_base < D3_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D3_APB1PERIPH_BASE) / 0x400;
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RCC->APB4ENR |= (1<<pos);
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RCC->APB4ENR;
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} else {
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uint32_t pos = (periph_base - D3_AHB1PERIPH_BASE) / 0x400;
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RCC->AHB4ENR |= (1<<pos);
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RCC->AHB4ENR;
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}
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}
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// Check if a peripheral clock has been enabled
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int
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is_enabled_pclock(uint32_t periph_base)
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{
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if (periph_base < D2_APB2PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_APB1PERIPH_BASE) / 0x400;
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return RCC->APB1LENR & (1<<pos); // we assume it is not in APB1HENR
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} else if (periph_base < D2_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_APB2PERIPH_BASE) / 0x400;
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return RCC->APB2ENR & (1<<pos);
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} else if (periph_base < D2_AHB2PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_AHB1PERIPH_BASE) / 0x400;
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return RCC->AHB1ENR & (1<<pos);
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} else if (periph_base < D1_APB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D2_AHB2PERIPH_BASE) / 0x400;
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return RCC->AHB2ENR & (1<<pos);
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} else if (periph_base < D1_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D1_APB1PERIPH_BASE) / 0x400;
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return RCC->APB3ENR & (1<<pos);
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} else if (periph_base < D3_APB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D1_AHB1PERIPH_BASE) / 0x400;
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return RCC->AHB3ENR & (1<<pos);
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} else if (periph_base < D3_AHB1PERIPH_BASE) {
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uint32_t pos = (periph_base - D3_APB1PERIPH_BASE) / 0x400;
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return RCC->APB4ENR & (1<<pos);
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} else {
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uint32_t pos = (periph_base - D3_AHB1PERIPH_BASE) / 0x400;
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return RCC->AHB4ENR & (1<<pos);
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}
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}
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// Return the frequency of the given peripheral clock
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uint32_t
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get_pclock_frequency(uint32_t periph_base)
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{
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return FREQ_PERIPH;
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}
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// Enable a GPIO peripheral clock
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void
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gpio_clock_enable(GPIO_TypeDef *regs)
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{
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enable_pclock((uint32_t)regs);
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}
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// Set the mode and extended function of a pin
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void
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gpio_peripheral(uint32_t gpio, uint32_t mode, int pullup)
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{
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GPIO_TypeDef *regs = digital_regs[GPIO2PORT(gpio)];
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// Enable GPIO clock
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gpio_clock_enable(regs);
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// Configure GPIO
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uint32_t mode_bits = mode & 0xf, func = (mode >> 4) & 0xf, od = mode >> 8;
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uint32_t pup = pullup ? (pullup > 0 ? 1 : 2) : 0;
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uint32_t pos = gpio % 16, af_reg = pos / 8;
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uint32_t af_shift = (pos % 8) * 4, af_msk = 0x0f << af_shift;
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uint32_t m_shift = pos * 2, m_msk = 0x03 << m_shift;
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regs->AFR[af_reg] = (regs->AFR[af_reg] & ~af_msk) | (func << af_shift);
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regs->MODER = (regs->MODER & ~m_msk) | (mode_bits << m_shift);
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regs->PUPDR = (regs->PUPDR & ~m_msk) | (pup << m_shift);
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regs->OTYPER = (regs->OTYPER & ~(1 << pos)) | (od << pos);
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regs->OSPEEDR = (regs->OSPEEDR & ~m_msk) | (0x02 << m_shift);
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}
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#if !CONFIG_STM32_CLOCK_REF_INTERNAL
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DECL_CONSTANT_STR("RESERVE_PINS_crystal", "PH0,PH1");
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#endif
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// Main clock and power setup called at chip startup
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static void
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clock_setup(void)
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{
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// Set this despite correct defaults.
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// "The software has to program the supply configuration in PWR control
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// register 3" (pg. 259)
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// Only a single write is allowed (pg. 304)
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PWR->CR3 = (PWR->CR3 | PWR_CR3_LDOEN) & ~(PWR_CR3_BYPASS | PWR_CR3_SCUEN);
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while (!(PWR->CSR1 & PWR_CSR1_ACTVOSRDY))
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;
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// (HSE 25mhz) /DIVM1(5) (pll_base 5Mhz) *DIVN1(192) (pll_freq 960Mhz)
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// /DIVP1(2) (SYSCLK 480Mhz)
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uint32_t pll_base = 5000000;
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// Only even dividers (DIVP1) are allowed
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uint32_t pll_freq = CONFIG_CLOCK_FREQ * 2;
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if (!CONFIG_STM32_CLOCK_REF_INTERNAL) {
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// Configure PLL from external crystal (HSE)
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RCC->CR |= RCC_CR_HSEON;
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while(!(RCC->CR & RCC_CR_HSERDY))
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;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSE);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(CONFIG_CLOCK_REF_FREQ/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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} else {
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// Configure PLL from internal 64Mhz oscillator (HSI)
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// HSI frequency of 64Mhz is integer divisible with 4Mhz
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pll_base = 4000000;
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC_Msk,
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RCC_PLLCKSELR_PLLSRC_HSI);
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MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1_Msk,
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(64000000/pll_base) << RCC_PLLCKSELR_DIVM1_Pos);
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}
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// Set input frequency range of PLL1 according to pll_base
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// 3 = 8-16Mhz, 2 = 4-8Mhz
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE_Msk, RCC_PLLCFGR_PLL1RGE_2);
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// Disable unused PLL1 outputs
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN_Msk, 0);
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN_Msk, 0);
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// This is necessary, default is not 1!
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MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN_Msk, RCC_PLLCFGR_DIVP1EN);
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// Set multiplier DIVN1 and post divider DIVP1
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// 001 = /2, 010 = not allowed, 0011 = /4 ...
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1_Msk,
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(pll_freq/pll_base - 1) << RCC_PLL1DIVR_N1_Pos);
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MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1_Msk,
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(pll_freq/CONFIG_CLOCK_FREQ - 1) << RCC_PLL1DIVR_P1_Pos);
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// Pwr
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MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS_Msk, PWR_D3CR_VOS);
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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// Enable VOS0 (overdrive)
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if (CONFIG_CLOCK_FREQ > 400000000) {
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RCC->APB4ENR |= RCC_APB4ENR_SYSCFGEN;
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SYSCFG->PWRCR |= SYSCFG_PWRCR_ODEN;
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while (!(PWR->D3CR & PWR_D3CR_VOSRDY))
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;
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}
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// Set flash latency according to clock frequency (pg.159)
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uint32_t flash_acr_latency = (CONFIG_CLOCK_FREQ > 450000000) ?
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FLASH_ACR_LATENCY_4WS : FLASH_ACR_LATENCY_2WS;
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY_Msk, flash_acr_latency);
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MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ_Msk, FLASH_ACR_WRHIGHFREQ_1);
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while (!(FLASH->ACR & flash_acr_latency))
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;
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// Set HPRE, D1PPRE, D2PPRE, D2PPRE2, D3PPRE dividers
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE_Msk, RCC_D1CFGR_HPRE_DIV2);
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MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE_Msk, RCC_D1CFGR_D1PPRE_DIV2);
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1_Msk, RCC_D2CFGR_D2PPRE1_DIV2);
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MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2_Msk, RCC_D2CFGR_D2PPRE2_DIV2);
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MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE_Msk, RCC_D3CFGR_D3PPRE_DIV2);
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// Switch on PLL1
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RCC->CR |= RCC_CR_PLL1ON;
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while (!(RCC->CR & RCC_CR_PLL1RDY))
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;
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// Switch system clock source (SYSCLK) to PLL1
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MODIFY_REG(RCC->CFGR, RCC_CFGR_SW_Msk, RCC_CFGR_SW_PLL1);
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while ((RCC->CFGR & RCC_CFGR_SWS_Msk) != RCC_CFGR_SWS_PLL1)
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;
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}
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// Main entry point - called from armcm_boot.c:ResetHandler()
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void
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armcm_main(void)
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{
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// Run SystemInit() and then restore VTOR
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SystemInit();
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SCB->VTOR = (uint32_t)VectorTable;
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clock_setup();
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sched_main();
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}
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