From 017a4d8321cb89c21aecc946b375bead17ee023e Mon Sep 17 00:00:00 2001
From: Kevin O'Connor <kevin@koconnor.net>
Date: Sat, 31 Aug 2019 18:35:01 -0400
Subject: [PATCH] stm32: Fix gpio enumerations (each bank has 16 pins, not 32)

Signed-off-by: Kevin O'Connor <kevin@koconnor.net>
---
 src/stm32/gpio.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/src/stm32/gpio.c b/src/stm32/gpio.c
index 8db0b7c49..cadb33968 100644
--- a/src/stm32/gpio.c
+++ b/src/stm32/gpio.c
@@ -11,18 +11,18 @@
 #include "internal.h" // gpio_peripheral
 #include "sched.h" // sched_shutdown
 
-DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 32);
+DECL_ENUMERATION_RANGE("pin", "PA0", GPIO('A', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PB0", GPIO('B', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PC0", GPIO('C', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PD0", GPIO('D', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PE0", GPIO('E', 0), 16);
 #ifdef GPIOH
-DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 32);
-DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 32);
+DECL_ENUMERATION_RANGE("pin", "PF0", GPIO('F', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PG0", GPIO('G', 0), 16);
+DECL_ENUMERATION_RANGE("pin", "PH0", GPIO('H', 0), 16);
 #endif
 #ifdef GPIOI
-DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 32);
+DECL_ENUMERATION_RANGE("pin", "PI0", GPIO('I', 0), 16);
 #endif
 
 GPIO_TypeDef * const digital_regs[] = {