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📝 Clean up variant labels

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This commit is contained in:
Scott Lahteine 2023-12-22 17:47:29 -06:00
parent 56ac5d03ed
commit ec060f979f
11 changed files with 539 additions and 655 deletions
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224
buildroot/share/PlatformIO/variants/MARLIN_BIGTREE_OCTOPUS_PRO_V1_F429/variant.h
View file

@ -27,118 +27,118 @@ extern "C" {
* Pins * Pins
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#define PA0 0 //D0 #define PA0 0
#define PA1 1 //D1 #define PA1 1
#define PA2 2 //D2 #define PA2 2
#define PA3 3 //D3 #define PA3 3
#define PA4 4 //D4 #define PA4 4
#define PA5 5 //D5 #define PA5 5
#define PA6 6 //D6 #define PA6 6
#define PA7 7 //D7 #define PA7 7
#define PA8 8 //D8 #define PA8 8
#define PA9 9 //D9 #define PA9 9
#define PA10 10 //D10 #define PA10 10
#define PA11 11 //D11 #define PA11 11
#define PA12 12 //D12 #define PA12 12
#define PA13 13 //D13 #define PA13 13
#define PA14 14 //D14 #define PA14 14
#define PA15 15 //D15 #define PA15 15
#define PB0 16 //D16 #define PB0 16
#define PB1 17 //D17 #define PB1 17
#define PB2 18 //D18 #define PB2 18
#define PB3 19 //D19 #define PB3 19
#define PB4 20 //D20 #define PB4 20
#define PB5 21 //D21 #define PB5 21
#define PB6 22 //D22 #define PB6 22
#define PB7 23 //D23 #define PB7 23
#define PB8 24 //D24 #define PB8 24
#define PB9 25 //D25 #define PB9 25
#define PB10 26 //D26 #define PB10 26
#define PB11 27 //D27 #define PB11 27
#define PB12 28 //D28 #define PB12 28
#define PB13 29 //D29 #define PB13 29
#define PB14 30 //D30 #define PB14 30
#define PB15 31 //D31 #define PB15 31
#define PC0 32 //D32 #define PC0 32
#define PC1 33 //D33 #define PC1 33
#define PC2 34 //D34 #define PC2 34
#define PC3 35 //D35 #define PC3 35
#define PC4 36 //D36 #define PC4 36
#define PC5 37 //D37 #define PC5 37
#define PC6 38 //D38 #define PC6 38
#define PC7 39 //D39 #define PC7 39
#define PC8 40 //D40 #define PC8 40
#define PC9 41 //D41 #define PC9 41
#define PC10 42 //D42 #define PC10 42
#define PC11 43 //D43 #define PC11 43
#define PC12 44 //D44 #define PC12 44
#define PC13 45 //D45 #define PC13 45
#define PC14 46 //D46 #define PC14 46
#define PC15 47 //D47 #define PC15 47
#define PD0 48 //D48 #define PD0 48
#define PD1 49 //D49 #define PD1 49
#define PD2 50 //D50 #define PD2 50
#define PD3 51 //D51 #define PD3 51
#define PD4 52 //D52 #define PD4 52
#define PD5 53 //D53 #define PD5 53
#define PD6 54 //D54 #define PD6 54
#define PD7 55 //D55 #define PD7 55
#define PD8 56 //D56 #define PD8 56
#define PD9 57 //D57 #define PD9 57
#define PD10 58 //D58 #define PD10 58
#define PD11 59 //D59 #define PD11 59
#define PD12 60 //D60 #define PD12 60
#define PD13 61 //D61 #define PD13 61
#define PD14 62 //D62 #define PD14 62
#define PD15 63 //D63 #define PD15 63
#define PE0 64 //D64 #define PE0 64
#define PE1 65 //D65 #define PE1 65
#define PE2 66 //D66 #define PE2 66
#define PE3 67 //D67 #define PE3 67
#define PE4 68 //D68 #define PE4 68
#define PE5 69 //D69 #define PE5 69
#define PE6 70 //D70 #define PE6 70
#define PE7 71 //D71 #define PE7 71
#define PE8 72 //D72 #define PE8 72
#define PE9 73 //D73 #define PE9 73
#define PE10 74 //D74 #define PE10 74
#define PE11 75 //D75 #define PE11 75
#define PE12 76 //D76 #define PE12 76
#define PE13 77 //D77 #define PE13 77
#define PE14 78 //D78 #define PE14 78
#define PE15 79 //D79 #define PE15 79
#define PF0 80 //D64 #define PF0 80
#define PF1 81 //D65 #define PF1 81
#define PF2 82 //D66 #define PF2 82
#define PF3 83 //D67 #define PF3 83
#define PF4 84 //D68 #define PF4 84
#define PF5 85 //D69 #define PF5 85
#define PF6 86 //D70 #define PF6 86
#define PF7 87 //D71 #define PF7 87
#define PF8 88 //D72 #define PF8 88
#define PF9 89 //D73 #define PF9 89
#define PF10 90 //D74 #define PF10 90
#define PF11 91 //D75 #define PF11 91
#define PF12 92 //D76 #define PF12 92
#define PF13 93 //D77 #define PF13 93
#define PF14 94 //D78 #define PF14 94
#define PF15 95 //D79 #define PF15 95
#define PG0 96 //D64 #define PG0 96
#define PG1 97 //D65 #define PG1 97
#define PG2 98 //D66 #define PG2 98
#define PG3 99 //D67 #define PG3 99
#define PG4 100 //D68 #define PG4 100
#define PG5 101 //D69 #define PG5 101
#define PG6 102 //D70 #define PG6 102
#define PG7 103 //D71 #define PG7 103
#define PG8 104 //D72 #define PG8 104
#define PG9 105 //D73 #define PG9 105
#define PG10 106 //D74 #define PG10 106
#define PG11 107 //D75 #define PG11 107
#define PG12 108 //D76 #define PG12 108
#define PG13 109 //D77 #define PG13 109
#define PG14 110 //D78 #define PG14 110
#define PG15 111 //D79 #define PG15 111
// This must be a literal with the same value as PEND // This must be a literal with the same value as PEND
#define NUM_DIGITAL_PINS 112 #define NUM_DIGITAL_PINS 112

224
buildroot/share/PlatformIO/variants/MARLIN_BIGTREE_OCTOPUS_V1/variant.h
View file

@ -27,118 +27,118 @@ extern "C" {
* Pins * Pins
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#define PA0 0 //D0 #define PA0 0
#define PA1 1 //D1 #define PA1 1
#define PA2 2 //D2 #define PA2 2
#define PA3 3 //D3 #define PA3 3
#define PA4 4 //D4 #define PA4 4
#define PA5 5 //D5 #define PA5 5
#define PA6 6 //D6 #define PA6 6
#define PA7 7 //D7 #define PA7 7
#define PA8 8 //D8 #define PA8 8
#define PA9 9 //D9 #define PA9 9
#define PA10 10 //D10 #define PA10 10
#define PA11 11 //D11 #define PA11 11
#define PA12 12 //D12 #define PA12 12
#define PA13 13 //D13 #define PA13 13
#define PA14 14 //D14 #define PA14 14
#define PA15 15 //D15 #define PA15 15
#define PB0 16 //D16 #define PB0 16
#define PB1 17 //D17 #define PB1 17
#define PB2 18 //D18 #define PB2 18
#define PB3 19 //D19 #define PB3 19
#define PB4 20 //D20 #define PB4 20
#define PB5 21 //D21 #define PB5 21
#define PB6 22 //D22 #define PB6 22
#define PB7 23 //D23 #define PB7 23
#define PB8 24 //D24 #define PB8 24
#define PB9 25 //D25 #define PB9 25
#define PB10 26 //D26 #define PB10 26
#define PB11 27 //D27 #define PB11 27
#define PB12 28 //D28 #define PB12 28
#define PB13 29 //D29 #define PB13 29
#define PB14 30 //D30 #define PB14 30
#define PB15 31 //D31 #define PB15 31
#define PC0 32 //D32 #define PC0 32
#define PC1 33 //D33 #define PC1 33
#define PC2 34 //D34 #define PC2 34
#define PC3 35 //D35 #define PC3 35
#define PC4 36 //D36 #define PC4 36
#define PC5 37 //D37 #define PC5 37
#define PC6 38 //D38 #define PC6 38
#define PC7 39 //D39 #define PC7 39
#define PC8 40 //D40 #define PC8 40
#define PC9 41 //D41 #define PC9 41
#define PC10 42 //D42 #define PC10 42
#define PC11 43 //D43 #define PC11 43
#define PC12 44 //D44 #define PC12 44
#define PC13 45 //D45 #define PC13 45
#define PC14 46 //D46 #define PC14 46
#define PC15 47 //D47 #define PC15 47
#define PD0 48 //D48 #define PD0 48
#define PD1 49 //D49 #define PD1 49
#define PD2 50 //D50 #define PD2 50
#define PD3 51 //D51 #define PD3 51
#define PD4 52 //D52 #define PD4 52
#define PD5 53 //D53 #define PD5 53
#define PD6 54 //D54 #define PD6 54
#define PD7 55 //D55 #define PD7 55
#define PD8 56 //D56 #define PD8 56
#define PD9 57 //D57 #define PD9 57
#define PD10 58 //D58 #define PD10 58
#define PD11 59 //D59 #define PD11 59
#define PD12 60 //D60 #define PD12 60
#define PD13 61 //D61 #define PD13 61
#define PD14 62 //D62 #define PD14 62
#define PD15 63 //D63 #define PD15 63
#define PE0 64 //D64 #define PE0 64
#define PE1 65 //D65 #define PE1 65
#define PE2 66 //D66 #define PE2 66
#define PE3 67 //D67 #define PE3 67
#define PE4 68 //D68 #define PE4 68
#define PE5 69 //D69 #define PE5 69
#define PE6 70 //D70 #define PE6 70
#define PE7 71 //D71 #define PE7 71
#define PE8 72 //D72 #define PE8 72
#define PE9 73 //D73 #define PE9 73
#define PE10 74 //D74 #define PE10 74
#define PE11 75 //D75 #define PE11 75
#define PE12 76 //D76 #define PE12 76
#define PE13 77 //D77 #define PE13 77
#define PE14 78 //D78 #define PE14 78
#define PE15 79 //D79 #define PE15 79
#define PF0 80 //D64 #define PF0 80
#define PF1 81 //D65 #define PF1 81
#define PF2 82 //D66 #define PF2 82
#define PF3 83 //D67 #define PF3 83
#define PF4 84 //D68 #define PF4 84
#define PF5 85 //D69 #define PF5 85
#define PF6 86 //D70 #define PF6 86
#define PF7 87 //D71 #define PF7 87
#define PF8 88 //D72 #define PF8 88
#define PF9 89 //D73 #define PF9 89
#define PF10 90 //D74 #define PF10 90
#define PF11 91 //D75 #define PF11 91
#define PF12 92 //D76 #define PF12 92
#define PF13 93 //D77 #define PF13 93
#define PF14 94 //D78 #define PF14 94
#define PF15 95 //D79 #define PF15 95
#define PG0 96 //D64 #define PG0 96
#define PG1 97 //D65 #define PG1 97
#define PG2 98 //D66 #define PG2 98
#define PG3 99 //D67 #define PG3 99
#define PG4 100 //D68 #define PG4 100
#define PG5 101 //D69 #define PG5 101
#define PG6 102 //D70 #define PG6 102
#define PG7 103 //D71 #define PG7 103
#define PG8 104 //D72 #define PG8 104
#define PG9 105 //D73 #define PG9 105
#define PG10 106 //D74 #define PG10 106
#define PG11 107 //D75 #define PG11 107
#define PG12 108 //D76 #define PG12 108
#define PG13 109 //D77 #define PG13 109
#define PG14 110 //D78 #define PG14 110
#define PG15 111 //D79 #define PG15 111
// This must be a literal with the same value as PEND // This must be a literal with the same value as PEND
#define NUM_DIGITAL_PINS 112 #define NUM_DIGITAL_PINS 112

15
buildroot/share/PlatformIO/variants/MARLIN_CREALITY_STM32F401RC/variant.h
View file

@ -23,9 +23,8 @@
extern "C" { extern "C" {
#endif // __cplusplus #endif // __cplusplus
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL |
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL | // |---------|--------|-----------|----------|------------------------|-----------|
// |---------|--------|-----------|----------|------------------------|-----------|
#define PA0 0 // | 0 | A0 | | | | | #define PA0 0 // | 0 | A0 | | | | |
#define PA1 1 // | 1 | A1 | | | | | #define PA1 1 // | 1 | A1 | | | | |
#define PA2 2 // | 2 | A2 | USART2_TX | | | | #define PA2 2 // | 2 | A2 | USART2_TX | | | |
@ -42,7 +41,7 @@ extern "C" {
#define PA13 13 // | 13 | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | | #define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PB0 16 // | 16 | A8 | | | | | #define PB0 16 // | 16 | A8 | | | | |
#define PB1 17 // | 17 | A9 | | | | | #define PB1 17 // | 17 | A9 | | | | |
#define PB2 18 // | 18 | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | BOOT1 |
@ -58,7 +57,7 @@ extern "C" {
#define PB13 28 // | 28 | | | | SPI2_SCK | | #define PB13 28 // | 28 | | | | SPI2_SCK | |
#define PB14 29 // | 29 | | | | SPI2_MISO | | #define PB14 29 // | 29 | | | | SPI2_MISO | |
#define PB15 30 // | 30 | | | | SPI2_MOSI | | #define PB15 30 // | 30 | | | | SPI2_MOSI | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PC0 31 // | 31 | A10 | | | | | #define PC0 31 // | 31 | A10 | | | | |
#define PC1 32 // | 32 | A11 | | | | | #define PC1 32 // | 32 | A11 | | | | |
#define PC2 33 // | 33 | A12 | | | SPI2_MISO | | #define PC2 33 // | 33 | A12 | | | SPI2_MISO | |
@ -75,12 +74,12 @@ extern "C" {
#define PC13 44 // | 44 | | | | | | #define PC13 44 // | 44 | | | | | |
#define PC14 45 // | 45 | | | | | OSC32_IN | #define PC14 45 // | 45 | | | | | OSC32_IN |
#define PC15 46 // | 46 | | | | | OSC32_OUT | #define PC15 46 // | 46 | | | | | OSC32_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PD2 47 // | 47 | | | | | | #define PD2 47 // | 47 | | | | | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PH0 48 // | 48 | | | | | OSC_IN | #define PH0 48 // | 48 | | | | | OSC_IN |
#define PH1 49 // | 49 | | | | | OSC_OUT | #define PH1 49 // | 49 | | | | | OSC_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
// This must be a literal // This must be a literal
#define NUM_DIGITAL_PINS 50 #define NUM_DIGITAL_PINS 50

35
buildroot/share/PlatformIO/variants/MARLIN_CREALITY_STM32F401RE/variant.h
View file

@ -23,26 +23,25 @@
extern "C" { extern "C" {
#endif // __cplusplus #endif // __cplusplus
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL |
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL | // |---------|--------|-----------|----------|------------------------|-----------|
// |---------|--------|-----------|----------|------------------------|-----------| #define PA0 0 // | 0 | A0 | | | | |
#define PA0 0 // | 0 | A0 | | | | | #define PA1 1 // | 1 | A1 | | | | |
#define PA1 1 // | 1 | A1 | | | | | #define PA2 2 // | 2 | A2 | USART2_TX | | | |
#define PA2 2 // | 2 | A2 | USART2_TX | | | | #define PA3 3 // | 3 | A3 | USART2_RX | | | |
#define PA3 3 // | 3 | A3 | USART2_RX | | | | #define PA4 4 // | 4 | A4 | | | SPI1_SS, (SPI3_SS) | |
#define PA4 4 // | 4 | A4 | | | SPI1_SS, (SPI3_SS) | | #define PA5 5 // | 5 | A5 | | | SPI1_SCK | |
#define PA5 5 // | 5 | A5 | | | SPI1_SCK | | #define PA6 6 // | 6 | A6 | | | SPI1_MISO | |
#define PA6 6 // | 6 | A6 | | | SPI1_MISO | | #define PA7 7 // | 7 | A7 | | | SPI1_MOSI | |
#define PA7 7 // | 7 | A7 | | | SPI1_MOSI | | #define PA8 8 // | 8 | | | TWI3_SCL | | |
#define PA8 8 // | 8 | | | TWI3_SCL | | | #define PA9 9 // | 9 | | USART1_TX | | | |
#define PA9 9 // | 9 | | USART1_TX | | | |
#define PA10 10 // | 10 | | USART1_RX | | | | #define PA10 10 // | 10 | | USART1_RX | | | |
#define PA11 11 // | 11 | | USART6_TX | | | | #define PA11 11 // | 11 | | USART6_TX | | | |
#define PA12 12 // | 12 | | USART6_RX | | | | #define PA12 12 // | 12 | | USART6_RX | | | |
#define PA13 13 // | 13 | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | | #define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PB0 16 // | 16 | A8 | | | | | #define PB0 16 // | 16 | A8 | | | | |
#define PB1 17 // | 17 | A9 | | | | | #define PB1 17 // | 17 | A9 | | | | |
#define PB2 18 // | 18 | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | BOOT1 |
@ -58,7 +57,7 @@ extern "C" {
#define PB13 28 // | 28 | | | | SPI2_SCK | | #define PB13 28 // | 28 | | | | SPI2_SCK | |
#define PB14 29 // | 29 | | | | SPI2_MISO | | #define PB14 29 // | 29 | | | | SPI2_MISO | |
#define PB15 30 // | 30 | | | | SPI2_MOSI | | #define PB15 30 // | 30 | | | | SPI2_MOSI | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PC0 31 // | 31 | A10 | | | | | #define PC0 31 // | 31 | A10 | | | | |
#define PC1 32 // | 32 | A11 | | | | | #define PC1 32 // | 32 | A11 | | | | |
#define PC2 33 // | 33 | A12 | | | SPI2_MISO | | #define PC2 33 // | 33 | A12 | | | SPI2_MISO | |
@ -75,12 +74,12 @@ extern "C" {
#define PC13 44 // | 44 | | | | | | #define PC13 44 // | 44 | | | | | |
#define PC14 45 // | 45 | | | | | OSC32_IN | #define PC14 45 // | 45 | | | | | OSC32_IN |
#define PC15 46 // | 46 | | | | | OSC32_OUT | #define PC15 46 // | 46 | | | | | OSC32_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PD2 47 // | 47 | | | | | | #define PD2 47 // | 47 | | | | | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PH0 48 // | 48 | | | | | OSC_IN | #define PH0 48 // | 48 | | | | | OSC_IN |
#define PH1 49 // | 49 | | | | | OSC_OUT | #define PH1 49 // | 49 | | | | | OSC_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
// This must be a literal // This must be a literal
#define NUM_DIGITAL_PINS 50 #define NUM_DIGITAL_PINS 50

82
buildroot/share/PlatformIO/variants/MARLIN_F103Rx/variant.h
View file

@ -26,8 +26,8 @@ extern "C" {
// * = F103R8-B-C-D-E-F-G // * = F103R8-B-C-D-E-F-G
// ** = F103RC-D-E-F-G // ** = F103RC-D-E-F-G
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL | // | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL |
// |---------|----------------|--------------------------|-----------|-----------------------|-----------| // |---------|----------------|--------------------------|-----------|-----------------------|-----------|
#define PA0 PIN_A0 // | 0 | A0 | | | | | #define PA0 PIN_A0 // | 0 | A0 | | | | |
#define PA1 PIN_A1 // | 1 | A1 | | | | | #define PA1 PIN_A1 // | 1 | A1 | | | | |
#define PA2 PIN_A2 // | 2 | A2 | USART2_TX | | | | #define PA2 PIN_A2 // | 2 | A2 | USART2_TX | | | |
@ -36,53 +36,53 @@ extern "C" {
#define PA5 PIN_A5 // | 5 | A5 | | | SPI1_SCK | | #define PA5 PIN_A5 // | 5 | A5 | | | SPI1_SCK | |
#define PA6 PIN_A6 // | 6 | A6 | | | SPI1_MISO | | #define PA6 PIN_A6 // | 6 | A6 | | | SPI1_MISO | |
#define PA7 PIN_A7 // | 7 | A7 | | | SPI1_MOSI | | #define PA7 PIN_A7 // | 7 | A7 | | | SPI1_MOSI | |
#define PA8 8 // | 8 | | | | | | #define PA8 8 // | 8 | | | | | |
#define PA9 9 // | 9 | | USART1_TX | | | | #define PA9 9 // | 9 | | USART1_TX | | | |
#define PA10 10 // | 10 | | USART1_RX | | | | #define PA10 10 // | 10 | | USART1_RX | | | |
#define PA11 11 // | 11 | | | | | USB_DM | #define PA11 11 // | 11 | | | | | USB_DM |
#define PA12 12 // | 12 | | | | | USB_DP | #define PA12 12 // | 12 | | | | | USB_DP |
#define PA13 13 // | 13 | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | SPI1_SS/SPI3_SS** | | #define PA15 15 // | 15 | | | | SPI1_SS/SPI3_SS** | |
// |---------|----------------|--------------------------|-----------|-----------------------|-----------| // |---------|----------------|--------------------------|-----------|-----------------------|-----------|
#define PB0 PIN_A8 // | 16 | A8 | | | | | #define PB0 PIN_A8 // | 16 | A8 | | | | |
#define PB1 PIN_A9 // | 17 | A9 | | | | | #define PB1 PIN_A9 // | 17 | A9 | | | | |
#define PB2 18 // | 18 | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | BOOT1 |
#define PB3 19 // | 19 | | | | SPI1_SCK/SPI3_SCK** | | #define PB3 19 // | 19 | | | | SPI1_SCK/SPI3_SCK** | |
#define PB4 20 // | 20 | | | | SPI1_MISO/SPI3_MISO** | | #define PB4 20 // | 20 | | | | SPI1_MISO/SPI3_MISO** | |
#define PB5 21 // | 21 | | | | SPI1_MOSI/SPI3_MOSI** | | #define PB5 21 // | 21 | | | | SPI1_MOSI/SPI3_MOSI** | |
#define PB6 22 // | 22 | | USART1_TX | TWI1_SCL | | | #define PB6 22 // | 22 | | USART1_TX | TWI1_SCL | | |
#define PB7 23 // | 23 | | USART1_RX | TWI1_SDA | | | #define PB7 23 // | 23 | | USART1_RX | TWI1_SDA | | |
#define PB8 24 // | 24 | | | TWI1_SCL | | | #define PB8 24 // | 24 | | | TWI1_SCL | | |
#define PB9 25 // | 25 | | | TWI1_SDA | | | #define PB9 25 // | 25 | | | TWI1_SDA | | |
#define PB10 26 // | 26 | | USART3_TX* | TWI2_SCL* | | | #define PB10 26 // | 26 | | USART3_TX* | TWI2_SCL* | | |
#define PB11 27 // | 27 | | USART3_RX* | TWI2_SDA* | | | #define PB11 27 // | 27 | | USART3_RX* | TWI2_SDA* | | |
#define PB12 28 // | 28 | | | | SPI2_SS* | | #define PB12 28 // | 28 | | | | SPI2_SS* | |
#define PB13 29 // | 29 | | | | SPI2_SCK* | | #define PB13 29 // | 29 | | | | SPI2_SCK* | |
#define PB14 30 // | 30 | | | | SPI2_MISO* | | #define PB14 30 // | 30 | | | | SPI2_MISO* | |
#define PB15 31 // | 31 | | | | SPI2_MOSI* | | #define PB15 31 // | 31 | | | | SPI2_MOSI* | |
// |---------|----------------|--------------------------|-----------|-----------------------|-----------| // |---------|----------------|--------------------------|-----------|-----------------------|-----------|
#define PC0 PIN_A10 // | 32 | A10 | | | | | #define PC0 PIN_A10 // | 32 | A10 | | | | |
#define PC1 PIN_A11 // | 33 | A11 | | | | | #define PC1 PIN_A11 // | 33 | A11 | | | | |
#define PC2 PIN_A12 // | 34 | A12 | | | | | #define PC2 PIN_A12 // | 34 | A12 | | | | |
#define PC3 PIN_A13 // | 35 | A13 | | | | | #define PC3 PIN_A13 // | 35 | A13 | | | | |
#define PC4 PIN_A14 // | 36 | A14 | | | | | #define PC4 PIN_A14 // | 36 | A14 | | | | |
#define PC5 PIN_A15 // | 37 | A15 | | | | | #define PC5 PIN_A15 // | 37 | A15 | | | | |
#define PC6 38 // | 38 | | | | | | #define PC6 38 // | 38 | | | | | |
#define PC7 39 // | 39 | | | | | | #define PC7 39 // | 39 | | | | | |
#define PC8 40 // | 40 | | | | | | #define PC8 40 // | 40 | | | | | |
#define PC9 41 // | 41 | | | | | | #define PC9 41 // | 41 | | | | | |
#define PC10 42 // | 42 | | USART3_TX*/UART4_TX** | | | | #define PC10 42 // | 42 | | USART3_TX*/UART4_TX** | | | |
#define PC11 43 // | 43 | | USART3_RX*/UART4_RX** | | | | #define PC11 43 // | 43 | | USART3_RX*/UART4_RX** | | | |
#define PC12 44 // | 44 | | UART5_TX** | | | | #define PC12 44 // | 44 | | UART5_TX** | | | |
#define PC13 45 // | 45 | | | | | | #define PC13 45 // | 45 | | | | | |
#define PC14 46 // | 46 | | | | | OSC32_IN | #define PC14 46 // | 46 | | | | | OSC32_IN |
#define PC15 47 // | 47 | | | | | OSC32_OUT | #define PC15 47 // | 47 | | | | | OSC32_OUT |
// |---------|----------------|--------------------------|-----------|-----------------------|-----------| // |---------|----------------|--------------------------|-----------|-----------------------|-----------|
#define PD0 48 // | 48 | | | | | OSC_IN | #define PD0 48 // | 48 | | | | | OSC_IN |
#define PD1 49 // | 48 | | | | | OSC_OUT | #define PD1 49 // | 48 | | | | | OSC_OUT |
#define PD2 50 // | 50 | | UART5_RX** | | | | #define PD2 50 // | 50 | | UART5_RX** | | | |
// |---------|----------------|--------------------------|-----------|-----------------------|-----------| // |---------|----------------|--------------------------|-----------|-----------------------|-----------|
// This must be a literal // This must be a literal
#define NUM_DIGITAL_PINS 51 #define NUM_DIGITAL_PINS 51

224
buildroot/share/PlatformIO/variants/MARLIN_F407ZE/variant.h
View file

@ -27,118 +27,118 @@ extern "C" {
* Pins * Pins
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#define PA0 0 //D0 #define PA0 0
#define PA1 1 //D1 #define PA1 1
#define PA2 2 //D2 #define PA2 2
#define PA3 3 //D3 #define PA3 3
#define PA4 4 //D4 #define PA4 4
#define PA5 5 //D5 #define PA5 5
#define PA6 6 //D6 #define PA6 6
#define PA7 7 //D7 #define PA7 7
#define PA8 8 //D8 #define PA8 8
#define PA9 9 //D9 #define PA9 9
#define PA10 10 //D10 #define PA10 10
#define PA11 11 //D11 #define PA11 11
#define PA12 12 //D12 #define PA12 12
#define PA13 13 //D13 #define PA13 13
#define PA14 14 //D14 #define PA14 14
#define PA15 15 //D15 #define PA15 15
#define PB0 16 //D16 #define PB0 16
#define PB1 17 //D17 #define PB1 17
#define PB2 18 //D18 #define PB2 18
#define PB3 19 //D19 #define PB3 19
#define PB4 20 //D20 #define PB4 20
#define PB5 21 //D21 #define PB5 21
#define PB6 22 //D22 #define PB6 22
#define PB7 23 //D23 #define PB7 23
#define PB8 24 //D24 #define PB8 24
#define PB9 25 //D25 #define PB9 25
#define PB10 26 //D26 #define PB10 26
#define PB11 27 //D27 #define PB11 27
#define PB12 28 //D28 #define PB12 28
#define PB13 29 //D29 #define PB13 29
#define PB14 30 //D30 #define PB14 30
#define PB15 31 //D31 #define PB15 31
#define PC0 32 //D32 #define PC0 32
#define PC1 33 //D33 #define PC1 33
#define PC2 34 //D34 #define PC2 34
#define PC3 35 //D35 #define PC3 35
#define PC4 36 //D36 #define PC4 36
#define PC5 37 //D37 #define PC5 37
#define PC6 38 //D38 #define PC6 38
#define PC7 39 //D39 #define PC7 39
#define PC8 40 //D40 #define PC8 40
#define PC9 41 //D41 #define PC9 41
#define PC10 42 //D42 #define PC10 42
#define PC11 43 //D43 #define PC11 43
#define PC12 44 //D44 #define PC12 44
#define PC13 45 //D45 #define PC13 45
#define PC14 46 //D46 #define PC14 46
#define PC15 47 //D47 #define PC15 47
#define PD0 48 //D48 #define PD0 48
#define PD1 49 //D49 #define PD1 49
#define PD2 50 //D50 #define PD2 50
#define PD3 51 //D51 #define PD3 51
#define PD4 52 //D52 #define PD4 52
#define PD5 53 //D53 #define PD5 53
#define PD6 54 //D54 #define PD6 54
#define PD7 55 //D55 #define PD7 55
#define PD8 56 //D56 #define PD8 56
#define PD9 57 //D57 #define PD9 57
#define PD10 58 //D58 #define PD10 58
#define PD11 59 //D59 #define PD11 59
#define PD12 60 //D60 #define PD12 60
#define PD13 61 //D61 #define PD13 61
#define PD14 62 //D62 #define PD14 62
#define PD15 63 //D63 #define PD15 63
#define PE0 64 //D64 #define PE0 64
#define PE1 65 //D65 #define PE1 65
#define PE2 66 //D66 #define PE2 66
#define PE3 67 //D67 #define PE3 67
#define PE4 68 //D68 #define PE4 68
#define PE5 69 //D69 #define PE5 69
#define PE6 70 //D70 #define PE6 70
#define PE7 71 //D71 #define PE7 71
#define PE8 72 //D72 #define PE8 72
#define PE9 73 //D73 #define PE9 73
#define PE10 74 //D74 #define PE10 74
#define PE11 75 //D75 #define PE11 75
#define PE12 76 //D76 #define PE12 76
#define PE13 77 //D77 #define PE13 77
#define PE14 78 //D78 #define PE14 78
#define PE15 79 //D79 #define PE15 79
#define PF0 80 //D64 #define PF0 80
#define PF1 81 //D65 #define PF1 81
#define PF2 82 //D66 #define PF2 82
#define PF3 83 //D67 #define PF3 83
#define PF4 84 //D68 #define PF4 84
#define PF5 85 //D69 #define PF5 85
#define PF6 86 //D70 #define PF6 86
#define PF7 87 //D71 #define PF7 87
#define PF8 88 //D72 #define PF8 88
#define PF9 89 //D73 #define PF9 89
#define PF10 90 //D74 #define PF10 90
#define PF11 91 //D75 #define PF11 91
#define PF12 92 //D76 #define PF12 92
#define PF13 93 //D77 #define PF13 93
#define PF14 94 //D78 #define PF14 94
#define PF15 95 //D79 #define PF15 95
#define PG0 96 //D64 #define PG0 96
#define PG1 97 //D65 #define PG1 97
#define PG2 98 //D66 #define PG2 98
#define PG3 99 //D67 #define PG3 99
#define PG4 100 //D68 #define PG4 100
#define PG5 101 //D69 #define PG5 101
#define PG6 102 //D70 #define PG6 102
#define PG7 103 //D71 #define PG7 103
#define PG8 104 //D72 #define PG8 104
#define PG9 105 //D73 #define PG9 105
#define PG10 106 //D74 #define PG10 106
#define PG11 107 //D75 #define PG11 107
#define PG12 108 //D76 #define PG12 108
#define PG13 109 //D77 #define PG13 109
#define PG14 110 //D78 #define PG14 110
#define PG15 111 //D79 #define PG15 111
// This must be a literal with the same value as PEND // This must be a literal with the same value as PEND
#define NUM_DIGITAL_PINS 112 #define NUM_DIGITAL_PINS 112

15
buildroot/share/PlatformIO/variants/MARLIN_FYSETC_CHEETAH_V20/variant.h
View file

@ -23,9 +23,8 @@
extern "C" { extern "C" {
#endif // __cplusplus #endif // __cplusplus
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL |
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL | // |---------|--------|-----------|----------|------------------------|-----------|
// |---------|--------|-----------|----------|------------------------|-----------|
#define PA0 A0 // | 0 | A0 | | | | | #define PA0 A0 // | 0 | A0 | | | | |
#define PA1 A1 // | 1 | A1 | | | | | #define PA1 A1 // | 1 | A1 | | | | |
#define PA2 A2 // | 2 | A2 | USART2_TX | | | | #define PA2 A2 // | 2 | A2 | USART2_TX | | | |
@ -42,7 +41,7 @@ extern "C" {
#define PA13 13 // | 13 | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | | #define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PB0 A8 // | 16 | A8 | | | | | #define PB0 A8 // | 16 | A8 | | | | |
#define PB1 A9 // | 17 | A9 | | | | | #define PB1 A9 // | 17 | A9 | | | | |
#define PB2 18 // | 18 | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | BOOT1 |
@ -58,7 +57,7 @@ extern "C" {
#define PB13 28 // | 28 | | | | SPI2_SCK | | #define PB13 28 // | 28 | | | | SPI2_SCK | |
#define PB14 29 // | 29 | | | | SPI2_MISO | | #define PB14 29 // | 29 | | | | SPI2_MISO | |
#define PB15 30 // | 30 | | | | SPI2_MOSI | | #define PB15 30 // | 30 | | | | SPI2_MOSI | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PC0 A10 // | 31 | A10 | | | | | #define PC0 A10 // | 31 | A10 | | | | |
#define PC1 A11 // | 32 | A11 | | | | | #define PC1 A11 // | 32 | A11 | | | | |
#define PC2 A12 // | 33 | A12 | | | SPI2_MISO | | #define PC2 A12 // | 33 | A12 | | | SPI2_MISO | |
@ -75,12 +74,12 @@ extern "C" {
#define PC13 44 // | 44 | | | | | | #define PC13 44 // | 44 | | | | | |
#define PC14 45 // | 45 | | | | | OSC32_IN | #define PC14 45 // | 45 | | | | | OSC32_IN |
#define PC15 46 // | 46 | | | | | OSC32_OUT | #define PC15 46 // | 46 | | | | | OSC32_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PD2 47 // | 47 | | | | | | #define PD2 47 // | 47 | | | | | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PH0 48 // | 48 | | | | | OSC_IN | #define PH0 48 // | 48 | | | | | OSC_IN |
#define PH1 49 // | 49 | | | | | OSC_OUT | #define PH1 49 // | 49 | | | | | OSC_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
// This must be a literal // This must be a literal
#define NUM_DIGITAL_PINS 50 #define NUM_DIGITAL_PINS 50

160
buildroot/share/PlatformIO/variants/MARLIN_FYSETC_S6/variant.h
View file

@ -27,86 +27,86 @@ extern "C" {
* Pins * Pins
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
#define PA0 0 //D0 #define PA0 0
#define PA1 1 //D1 #define PA1 1
#define PA2 2 //D2 #define PA2 2
#define PA3 3 //D3 #define PA3 3
#define PA4 4 //D4 #define PA4 4
#define PA5 5 //D5 #define PA5 5
#define PA6 6 //D6 #define PA6 6
#define PA7 7 //D7 #define PA7 7
#define PA8 8 //D8 #define PA8 8
#define PA9 9 //D9 #define PA9 9
#define PA10 10 //D10 #define PA10 10
#define PA11 11 //D11 #define PA11 11
#define PA12 12 //D12 #define PA12 12
#define PA13 13 //D13 #define PA13 13
#define PA14 14 //D14 #define PA14 14
#define PA15 15 //D15 #define PA15 15
#define PB0 16 //D16 #define PB0 16
#define PB1 17 //D17 #define PB1 17
#define PB2 18 //D18 #define PB2 18
#define PB3 19 //D19 #define PB3 19
#define PB4 20 //D20 #define PB4 20
#define PB5 21 //D21 #define PB5 21
#define PB6 22 //D22 #define PB6 22
#define PB7 23 //D23 #define PB7 23
#define PB8 24 //D24 #define PB8 24
#define PB9 25 //D25 #define PB9 25
#define PB10 26 //D26 #define PB10 26
#define PB11 27 //D27 #define PB11 27
#define PB12 28 //D28 #define PB12 28
#define PB13 29 //D29 #define PB13 29
#define PB14 30 //D30 #define PB14 30
#define PB15 31 //D31 #define PB15 31
#define PC0 32 //D32 #define PC0 32
#define PC1 33 //D33 #define PC1 33
#define PC2 34 //D34 #define PC2 34
#define PC3 35 //D35 #define PC3 35
#define PC4 36 //D36 #define PC4 36
#define PC5 37 //D37 #define PC5 37
#define PC6 38 //D38 #define PC6 38
#define PC7 39 //D39 #define PC7 39
#define PC8 40 //D40 #define PC8 40
#define PC9 41 //D41 #define PC9 41
#define PC10 42 //D42 #define PC10 42
#define PC11 43 //D43 #define PC11 43
#define PC12 44 //D44 #define PC12 44
#define PC13 45 //D45 #define PC13 45
#define PC14 46 //D46 #define PC14 46
#define PC15 47 //D47 #define PC15 47
#define PD0 48 //D48 #define PD0 48
#define PD1 49 //D49 #define PD1 49
#define PD2 50 //D50 #define PD2 50
#define PD3 51 //D51 #define PD3 51
#define PD4 52 //D52 #define PD4 52
#define PD5 53 //D53 #define PD5 53
#define PD6 54 //D54 #define PD6 54
#define PD7 55 //D55 #define PD7 55
#define PD8 56 //D56 #define PD8 56
#define PD9 57 //D57 #define PD9 57
#define PD10 58 //D58 #define PD10 58
#define PD11 59 //D59 #define PD11 59
#define PD12 60 //D60 #define PD12 60
#define PD13 61 //D61 #define PD13 61
#define PD14 62 //D62 #define PD14 62
#define PD15 63 //D63 #define PD15 63
#define PE0 64 //D64 #define PE0 64
#define PE1 65 //D65 #define PE1 65
#define PE2 66 //D66 #define PE2 66
#define PE3 67 //D67 #define PE3 67
#define PE4 68 //D68 #define PE4 68
#define PE5 69 //D69 #define PE5 69
#define PE6 70 //D70 #define PE6 70
#define PE7 71 //D71 #define PE7 71
#define PE8 72 //D72 #define PE8 72
#define PE9 73 //D73 #define PE9 73
#define PE10 74 //D74 #define PE10 74
#define PE11 75 //D75 #define PE11 75
#define PE12 76 //D76 #define PE12 76
#define PE13 77 //D77 #define PE13 77
#define PE14 78 //D78 #define PE14 78
#define PE15 79 //D79 #define PE15 79
// This must be a literal with the same value as PEND // This must be a literal with the same value as PEND
#define NUM_DIGITAL_PINS 87 #define NUM_DIGITAL_PINS 87

15
buildroot/share/PlatformIO/variants/MARLIN_STM32F401RE_FREERUNS/variant.h
View file

@ -23,9 +23,8 @@
extern "C" { extern "C" {
#endif // __cplusplus #endif // __cplusplus
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL |
// | DIGITAL | ANALOG | USART | TWI | SPI | SPECIAL | // |---------|--------|-----------|----------|------------------------|-----------|
// |---------|--------|-----------|----------|------------------------|-----------|
#define PA0 0 // | 0 | A0 | | | | | #define PA0 0 // | 0 | A0 | | | | |
#define PA1 1 // | 1 | A1 | | | | | #define PA1 1 // | 1 | A1 | | | | |
#define PA2 2 // | 2 | A2 | USART2_TX | | | | #define PA2 2 // | 2 | A2 | USART2_TX | | | |
@ -42,7 +41,7 @@ extern "C" {
#define PA13 13 // | 13 | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | | #define PA15 15 // | 15 | | | | SPI3_SS, (SPI1_SS) | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PB0 16 // | 16 | A8 | | | | | #define PB0 16 // | 16 | A8 | | | | |
#define PB1 17 // | 17 | A9 | | | | | #define PB1 17 // | 17 | A9 | | | | |
#define PB2 18 // | 18 | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | BOOT1 |
@ -58,7 +57,7 @@ extern "C" {
#define PB13 28 // | 28 | | | | SPI2_SCK | | #define PB13 28 // | 28 | | | | SPI2_SCK | |
#define PB14 29 // | 29 | | | | SPI2_MISO | | #define PB14 29 // | 29 | | | | SPI2_MISO | |
#define PB15 30 // | 30 | | | | SPI2_MOSI | | #define PB15 30 // | 30 | | | | SPI2_MOSI | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PC0 31 // | 31 | A10 | | | | | #define PC0 31 // | 31 | A10 | | | | |
#define PC1 32 // | 32 | A11 | | | | | #define PC1 32 // | 32 | A11 | | | | |
#define PC2 33 // | 33 | A12 | | | SPI2_MISO | | #define PC2 33 // | 33 | A12 | | | SPI2_MISO | |
@ -75,12 +74,12 @@ extern "C" {
#define PC13 44 // | 44 | | | | | | #define PC13 44 // | 44 | | | | | |
#define PC14 45 // | 45 | | | | | OSC32_IN | #define PC14 45 // | 45 | | | | | OSC32_IN |
#define PC15 46 // | 46 | | | | | OSC32_OUT | #define PC15 46 // | 46 | | | | | OSC32_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PD2 47 // | 47 | | | | | | #define PD2 47 // | 47 | | | | | |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
#define PH0 48 // | 48 | | | | | OSC_IN | #define PH0 48 // | 48 | | | | | OSC_IN |
#define PH1 49 // | 49 | | | | | OSC_OUT | #define PH1 49 // | 49 | | | | | OSC_OUT |
// |---------|--------|-----------|----------|------------------------|-----------| // |---------|--------|-----------|----------|------------------------|-----------|
// This must be a literal // This must be a literal
#define NUM_DIGITAL_PINS 50 #define NUM_DIGITAL_PINS 50

84
buildroot/share/PlatformIO/variants/MARLIN_TH3D_EZBOARD_V2/variant.h
View file

@ -27,8 +27,8 @@ extern "C" {
* Pins (STM32F405RG and STM32F415RG) * Pins (STM32F405RG and STM32F415RG)
*----------------------------------------------------------------------------*/ *----------------------------------------------------------------------------*/
// | DIGITAL | ANALOG IN | ANALOG OUT | UART/USART | TWI | SPI | SPECIAL | // | DIGITAL | ANALOG IN | ANALOG OUT | UART/USART | TWI | SPI | SPECIAL |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
#define PA0 PIN_A0 // | 0 | A0 (ADC1) | | UART4_TX | | | | #define PA0 PIN_A0 // | 0 | A0 (ADC1) | | UART4_TX | | | |
#define PA1 PIN_A1 // | 1 | A1 (ADC1) | | UART4_RX | | | | #define PA1 PIN_A1 // | 1 | A1 (ADC1) | | UART4_RX | | | |
#define PA2 PIN_A2 // | 2 | A2 (ADC1) | | USART2_TX | | | | #define PA2 PIN_A2 // | 2 | A2 (ADC1) | | USART2_TX | | | |
@ -37,54 +37,54 @@ extern "C" {
#define PA5 PIN_A5 // | 5 | A5 (ADC1) | DAC_OUT2 | | | SPI1_SCK | | #define PA5 PIN_A5 // | 5 | A5 (ADC1) | DAC_OUT2 | | | SPI1_SCK | |
#define PA6 PIN_A6 // | 6 | A6 (ADC1) | | | | SPI1_MISO | | #define PA6 PIN_A6 // | 6 | A6 (ADC1) | | | | SPI1_MISO | |
#define PA7 PIN_A7 // | 7 | A7 (ADC1) | | | | SPI1_MOSI | | #define PA7 PIN_A7 // | 7 | A7 (ADC1) | | | | SPI1_MOSI | |
#define PA8 8 // | 8 | | | | TWI3_SCL | | | #define PA8 8 // | 8 | | | | TWI3_SCL | | |
#define PA9 9 // | 9 | | | USART1_TX | | SPI2_SCK | | #define PA9 9 // | 9 | | | USART1_TX | | SPI2_SCK | |
#define PA10 10 // | 10 | | | USART1_RX | | | | #define PA10 10 // | 10 | | | USART1_RX | | | |
#define PA11 11 // | 11 | | | | | | | #define PA11 11 // | 11 | | | | | | |
#define PA12 12 // | 12 | | | | | | | #define PA12 12 // | 12 | | | | | | |
#define PA13 13 // | 13 | | | | | | SWD_SWDIO | #define PA13 13 // | 13 | | | | | | SWD_SWDIO |
#define PA14 14 // | 14 | | | | | | SWD_SWCLK | #define PA14 14 // | 14 | | | | | | SWD_SWCLK |
#define PA15 15 // | 15 | | | | | SPI3_SS, (SPI1_SS) | | #define PA15 15 // | 15 | | | | | SPI3_SS, (SPI1_SS) | |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
#define PB0 PIN_A8 // | 16 | A8 (ADC1) | | | | | | #define PB0 PIN_A8 // | 16 | A8 (ADC1) | | | | | |
#define PB1 PIN_A9 // | 17 | A9 (ADC1) | | | | | | #define PB1 PIN_A9 // | 17 | A9 (ADC1) | | | | | |
#define PB2 18 // | 18 | | | | | | BOOT1 | #define PB2 18 // | 18 | | | | | | BOOT1 |
#define PB3 19 // | 19 | | | | | SPI3_SCK, (SPI1_SCK) | | #define PB3 19 // | 19 | | | | | SPI3_SCK, (SPI1_SCK) | |
#define PB4 20 // | 20 | | | | | SPI3_MISO, (SPI1_MISO) | | #define PB4 20 // | 20 | | | | | SPI3_MISO, (SPI1_MISO) | |
#define PB5 21 // | 21 | | | | | SPI3_MOSI, (SPI1_MOSI) | | #define PB5 21 // | 21 | | | | | SPI3_MOSI, (SPI1_MOSI) | |
#define PB6 22 // | 22 | | | USART1_TX | TWI1_SCL | | | #define PB6 22 // | 22 | | | USART1_TX | TWI1_SCL | | |
#define PB7 23 // | 23 | | | USART1_RX | TWI1_SDA | | | #define PB7 23 // | 23 | | | USART1_RX | TWI1_SDA | | |
#define PB8 24 // | 24 | | | | TWI1_SCL | | | #define PB8 24 // | 24 | | | | TWI1_SCL | | |
#define PB9 25 // | 25 | | | | TWI1_SDA | SPI2_SS | | #define PB9 25 // | 25 | | | | TWI1_SDA | SPI2_SS | |
#define PB10 26 // | 26 | | | USART3_TX | TWI2_SCL | SPI2_SCK | | #define PB10 26 // | 26 | | | USART3_TX | TWI2_SCL | SPI2_SCK | |
#define PB11 27 // | 27 | | | USART3_RX | TWI2_SDA | | | #define PB11 27 // | 27 | | | USART3_RX | TWI2_SDA | | |
#define PB12 28 // | 28 | | | | | SPI2_SS | | #define PB12 28 // | 28 | | | | | SPI2_SS | |
#define PB13 29 // | 29 | | | | | SPI2_SCK | | #define PB13 29 // | 29 | | | | | SPI2_SCK | |
#define PB14 30 // | 30 | | | | | SPI2_MISO | | #define PB14 30 // | 30 | | | | | SPI2_MISO | |
#define PB15 31 // | 31 | | | | | SPI2_MOSI | | #define PB15 31 // | 31 | | | | | SPI2_MOSI | |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
#define PC0 PIN_A10 // | 32 | A10 (ADC1) | | | | | | #define PC0 PIN_A10 // | 32 | A10 (ADC1) | | | | | |
#define PC1 PIN_A11 // | 33 | A11 (ADC1) | | | | | | #define PC1 PIN_A11 // | 33 | A11 (ADC1) | | | | | |
#define PC2 PIN_A12 // | 34 | A12 (ADC1) | | | | SPI2_MISO | | #define PC2 PIN_A12 // | 34 | A12 (ADC1) | | | | SPI2_MISO | |
#define PC3 PIN_A13 // | 35 | A13 (ADC1) | | | | SPI2_MOSI | | #define PC3 PIN_A13 // | 35 | A13 (ADC1) | | | | SPI2_MOSI | |
#define PC4 PIN_A14 // | 36 | A14 (ADC1) | | | | | | #define PC4 PIN_A14 // | 36 | A14 (ADC1) | | | | | |
#define PC5 PIN_A15 // | 37 | A15 (ADC1) | | | | | | #define PC5 PIN_A15 // | 37 | A15 (ADC1) | | | | | |
#define PC6 38 // | 38 | | | USART6_TX | | | | #define PC6 38 // | 38 | | | USART6_TX | | | |
#define PC7 39 // | 39 | | | USART3_RX | | SPI2_SCK | | #define PC7 39 // | 39 | | | USART3_RX | | SPI2_SCK | |
#define PC8 40 // | 40 | | | | | | | #define PC8 40 // | 40 | | | | | | |
#define PC9 41 // | 41 | | | | TWI3_SDA | | | #define PC9 41 // | 41 | | | | TWI3_SDA | | |
#define PC10 42 // | 42 | | | USART3_TX, (UART4_TX) | | SPI3_SCK | | #define PC10 42 // | 42 | | | USART3_TX, (UART4_TX) | | SPI3_SCK | |
#define PC11 43 // | 43 | | | USART3_RX, (UART4_RX) | | SPI3_MISO | | #define PC11 43 // | 43 | | | USART3_RX, (UART4_RX) | | SPI3_MISO | |
#define PC12 44 // | 44 | | | UART5_TX | | SPI3_MOSI | | #define PC12 44 // | 44 | | | UART5_TX | | SPI3_MOSI | |
#define PC13 45 // | 45 | | | | | | | #define PC13 45 // | 45 | | | | | | |
#define PC14 46 // | 46 | | | | | | OSC32_IN | #define PC14 46 // | 46 | | | | | | OSC32_IN |
#define PC15 47 // | 47 | | | | | | OSC32_OUT | #define PC15 47 // | 47 | | | | | | OSC32_OUT |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
#define PD2 48 // | 48 | | | UART5_RX | | | | #define PD2 48 // | 48 | | | UART5_RX | | | |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
#define PH0 49 // | 49 | | | | | | OSC_IN | #define PH0 49 // | 49 | | | | | | OSC_IN |
#define PH1 50 // | 50 | | | | | | OSC_OUT | #define PH1 50 // | 50 | | | | | | OSC_OUT |
// |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------| // |---------|------------|------------|-----------------------|----------------------|-----------------------------------|-----------|
/// This must be a literal /// This must be a literal
#define NUM_DIGITAL_PINS 51 #define NUM_DIGITAL_PINS 51

116
buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/board/board.h
View file

@ -119,117 +119,5 @@ PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15, PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15 PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
};/* Note PB2 is skipped as this is Boot1 and is not going to be much use as its likely to be pulled permanently low */ };/* Note PB2 is skipped as this is Boot1 and is not going to be much use as its likely to be pulled permanently low */
/*
#define PA0 0 #endif // _BOARDS_GENERIC_STM32F103Z_H_
#define PA1 1
#define PA2 2
#define PA3 3
#define PA4 4
#define PA5 5
#define PA6 6
#define PA7 7
#define PA8 8
#define PA9 9
#define PA10 10
#define PA11 11
#define PA12 12
#define PA13 13
#define PA14 14
#define PA15 15
#define PB0 16
#define PB1 17
#define PB2 18
#define PB3 19
#define PB4 20
#define PB5 21
#define PB6 22
#define PB7 23
#define PB8 24
#define PB9 25
#define PB10 26
#define PB11 27
#define PB12 28
#define PB13 29
#define PB14 30
#define PB15 31
#define PC0 32
#define PC1 33
#define PC2 34
#define PC3 35
#define PC4 36
#define PC5 37
#define PC6 38
#define PC7 39
#define PC8 40
#define PC9 41
#define PC10 42
#define PC11 43
#define PC12 44
#define PC13 45
#define PC14 46
#define PC15 47
#define PD0 48
#define PD1 49
#define PD2 50
#define PD3 51
#define PD4 52
#define PD5 53
#define PD6 54
#define PD7 55
#define PD8 56
#define PD9 57
#define PD10 58
#define PD11 59
#define PD12 60
#define PD13 61
#define PD14 62
#define PD15 63
#define PE0 64
#define PE1 65
#define PE2 66
#define PE3 67
#define PE4 68
#define PE5 69
#define PE6 70
#define PE7 71
#define PE8 72
#define PE9 73
#define PE10 74
#define PE11 75
#define PE12 76
#define PE13 77
#define PE14 78
#define PE15 79
#define PF0 80
#define PF1 81
#define PF2 82
#define PF3 83
#define PF4 84
#define PF5 85
#define PF6 86
#define PF7 87
#define PF8 88
#define PF9 89
#define PF10 90
#define PF11 91
#define PF12 92
#define PF13 93
#define PF14 94
#define PF15 95
#define PG0 96
#define PG1 97
#define PG2 98
#define PG3 99
#define PG4 100
#define PG5 101
#define PG6 102
#define PG7 103
#define PG8 104
#define PG9 105
#define PG10 106
#define PG11 107
#define PG12 108
#define PG13 109
#define PG14 110
#define PG15 111 */
#endif