From 89557f3f532f8c522e66f91c4b4ef299648e4f4b Mon Sep 17 00:00:00 2001
From: Andrew <andrewleduc88@yahoo.com>
Date: Fri, 17 Oct 2025 04:23:17 -0400
Subject: [PATCH] proper calling

---
 .../variants/MARLIN_F103VE_LONGER/variant.cpp         | 11 +++++++----
 .../marlin_maple_CHITU_F103/wirish/syscalls.c         |  9 +++------
 .../variants/marlin_maple_MEEB_3DP/wirish/syscalls.c  |  9 +++------
 3 files changed, 13 insertions(+), 16 deletions(-)

diff --git a/buildroot/share/PlatformIO/variants/MARLIN_F103VE_LONGER/variant.cpp b/buildroot/share/PlatformIO/variants/MARLIN_F103VE_LONGER/variant.cpp
index 007ef81065..c1f0985de7 100644
--- a/buildroot/share/PlatformIO/variants/MARLIN_F103VE_LONGER/variant.cpp
+++ b/buildroot/share/PlatformIO/variants/MARLIN_F103VE_LONGER/variant.cpp
@@ -158,11 +158,12 @@ static bool SetSysClock_PLL_HSE(bool bypass)
     RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK) {
-      PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
       PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;
       PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5; // 72/1.5 = 48MHz
       #ifndef USBCON
         PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
+      #else
+        PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
       #endif
       if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) == HAL_OK) {
         ret = true;
@@ -189,11 +190,12 @@ bool SetSysClock_PLL_HSI(void)
   RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
   RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
   RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI_DIV2; // 4 MHz
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL12; // 48 MHz
   #ifndef USBCON
     // When the HSI is used as a PLL clock input, the maximum
     // system clock frequency that can be achieved is 64 MHz.
     RCC_OscInitStruct.PLL.PLLMUL        = RCC_PLL_MUL16; // 64 MHz, stay close to 72 for delay()
+  #else
+    RCC_OscInitStruct.PLL.PLLMUL        = RCC_PLL_MUL12; // 48 MHz
   #endif
   if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
     // Initializes the CPU, AHB and APB busses clocks
@@ -206,12 +208,13 @@ bool SetSysClock_PLL_HSI(void)
 
     // FLASH_LATENCY_1 may cause boot loops
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK) {
-      PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
-      PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;
       PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLL;  // requires 48 MHz
       #ifndef USBCON
         PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;// No USB, RTC nor I2S
         PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV6;   // 2 4 6 8
+      #else
+        PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_USB;
+        PeriphClkInit.AdcClockSelection = RCC_ADCPCLK2_DIV4;   // Use DIV4 for USB-enabled configuration
       #endif
       if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) == HAL_OK) {
         ret = true;
diff --git a/buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/wirish/syscalls.c b/buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/wirish/syscalls.c
index ec1c34dbad..5267f8b013 100755
--- a/buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/wirish/syscalls.c
+++ b/buildroot/share/PlatformIO/variants/marlin_maple_CHITU_F103/wirish/syscalls.c
@@ -116,8 +116,7 @@ __weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
-    char *p;
-    int c;
+    char *p = s;
     int i;
 
     for (i = 0; i < bufsize; i++) {
@@ -125,10 +124,8 @@ __weak void cgets(char *s, int bufsize) {
     }
 //    memset(s, 0, bufsize);
 
-    p = s;
-
-    for (p = s; p < s + bufsize-1;) {
-        c = getch();
+    for (p = s; p < s + bufsize - 1;) {
+        int c = getch();
         switch (c) {
         case '\r' :
         case '\n' :
diff --git a/buildroot/share/PlatformIO/variants/marlin_maple_MEEB_3DP/wirish/syscalls.c b/buildroot/share/PlatformIO/variants/marlin_maple_MEEB_3DP/wirish/syscalls.c
index d5f2d9fac3..e56c2ac285 100644
--- a/buildroot/share/PlatformIO/variants/marlin_maple_MEEB_3DP/wirish/syscalls.c
+++ b/buildroot/share/PlatformIO/variants/marlin_maple_MEEB_3DP/wirish/syscalls.c
@@ -116,8 +116,7 @@ __weak void putch(unsigned char c) {
 }
 
 __weak void cgets(char *s, int bufsize) {
-    char *p;
-    int c;
+    char *p = s;
     int i;
 
     for (i = 0; i < bufsize; i++) {
@@ -125,10 +124,8 @@ __weak void cgets(char *s, int bufsize) {
     }
 //    memset(s, 0, bufsize);
 
-    p = s;
-
-    for (p = s; p < s + bufsize-1;) {
-        c = getch();
+    for (p = s; p < s + bufsize - 1;) {
+        int c = getch();
         switch (c) {
         case '\r' :
         case '\n' :